Lines Matching refs:CLK_SET_RATE_PARENT
956 CLK_SET_RATE_PARENT, 1, 2); in tegra114_fixed_clk_init()
961 CLK_SET_RATE_PARENT, 1, 4); in tegra114_fixed_clk_init()
1065 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
1090 CLK_SET_RATE_PARENT, 0, NULL); in tegra114_pll_init()
1095 CLK_SET_RATE_PARENT, 1, 1); in tegra114_pll_init()
1110 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra114_pll_init()
1116 CLK_SET_RATE_PARENT, 1, 8); in tegra114_pll_init()
1121 CLK_SET_RATE_PARENT, 1, 10); in tegra114_pll_init()
1126 CLK_SET_RATE_PARENT, 1, 40); in tegra114_pll_init()
1136 CLK_SET_RATE_PARENT, 1, 2); in tegra114_pll_init()
1146 CLK_SET_RATE_PARENT, 1, 2); in tegra114_pll_init()