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Searched refs:nv_wr32 (Results 1 – 143 of 143) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgm204.c268 nv_wr32(priv, 0x418880, 0x00001000 | (tmp & 0x00000fff)); in gm204_gr_init()
269 nv_wr32(priv, 0x418890, 0x00000000); in gm204_gr_init()
270 nv_wr32(priv, 0x418894, 0x00000000); in gm204_gr_init()
271 nv_wr32(priv, 0x4188b4, priv->unk4188b4->addr >> 8); in gm204_gr_init()
272 nv_wr32(priv, 0x4188b8, priv->unk4188b8->addr >> 8); in gm204_gr_init()
276 nv_wr32(priv, 0x100cc8, priv->unk4188b4->addr >> 8); in gm204_gr_init()
277 nv_wr32(priv, 0x100ccc, priv->unk4188b8->addr >> 8); in gm204_gr_init()
284 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); in gm204_gr_init()
297 nv_wr32(priv, GPC_BCAST(0x0980), data[0]); in gm204_gr_init()
298 nv_wr32(priv, GPC_BCAST(0x0984), data[1]); in gm204_gr_init()
[all …]
Dgk104.c214 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); in gk104_gr_init()
215 nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); in gk104_gr_init()
216 nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); in gk104_gr_init()
217 nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); in gk104_gr_init()
218 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); in gk104_gr_init()
219 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); in gk104_gr_init()
220 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); in gk104_gr_init()
221 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); in gk104_gr_init()
225 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); in gk104_gr_init()
238 nv_wr32(priv, GPC_BCAST(0x0980), data[0]); in gk104_gr_init()
[all …]
Dgm107.c315 nv_wr32(priv, regs[E].ctrl, infoE.data); in gm107_gr_init_bios()
317 nv_wr32(priv, regs[E].data, infoX.data); in gm107_gr_init_bios()
337 nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); in gm107_gr_init()
338 nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); in gm107_gr_init()
339 nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); in gm107_gr_init()
340 nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); in gm107_gr_init()
341 nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); in gm107_gr_init()
347 nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); in gm107_gr_init()
360 nv_wr32(priv, GPC_BCAST(0x0980), data[0]); in gm107_gr_init()
361 nv_wr32(priv, GPC_BCAST(0x0984), data[1]); in gm107_gr_init()
[all …]
Dnv40.c167 nv_wr32(priv, 0x400720, 0x00000000); in nv40_gr_context_fini()
168 nv_wr32(priv, 0x400784, inst); in nv40_gr_context_fini()
223 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile_prog()
224 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile_prog()
225 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile_prog()
226 nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile_prog()
227 nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile_prog()
228 nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile_prog()
232 nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile_prog()
233 nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile_prog()
[all …]
Dnv20.c128 nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4); in nv20_gr_context_fini()
129 nv_wr32(priv, 0x400788, 0x00000002); in nv20_gr_context_fini()
131 nv_wr32(priv, 0x400144, 0x10000000); in nv20_gr_context_fini()
168 nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile_prog()
169 nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile_prog()
170 nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile_prog()
172 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); in nv20_gr_tile_prog()
173 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile_prog()
174 nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); in nv20_gr_tile_prog()
175 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile_prog()
[all …]
Dnv30.c164 nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); in nv30_gr_init()
166 nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv30_gr_init()
167 nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv30_gr_init()
169 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv30_gr_init()
170 nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv30_gr_init()
171 nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv30_gr_init()
172 nv_wr32(priv, 0x400890, 0x01b463ff); in nv30_gr_init()
173 nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475); in nv30_gr_init()
174 nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv30_gr_init()
175 nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); in nv30_gr_init()
[all …]
Dgf100.c48 nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
49 nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
50 nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
51 nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
53 nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
54 nv_wr32(priv, 0x405820, zbc); in gf100_gr_zbc_clear_color()
55 nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
98 nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
99 nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
100 nv_wr32(priv, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
[all …]
Dnv50.c289 nv_wr32(priv, 0x100c80, 0x00000001); in g84_gr_tlb_flush()
498 nv_wr32(priv, addr + 0x10, mp10); in nv50_priv_mp_trap()
499 nv_wr32(priv, addr + 0x14, 0); in nv50_priv_mp_trap()
565 nv_wr32(priv, ustatus_addr, 0xc0000000); in nv50_priv_tp_trap()
593 nv_wr32(priv, 0x400500, 0x00000000); in nv50_gr_trap_handler()
617 nv_wr32(priv, 0x400808, 0); in nv50_gr_trap_handler()
618 nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); in nv50_gr_trap_handler()
619 nv_wr32(priv, 0x400848, 0); in nv50_gr_trap_handler()
642 nv_wr32(priv, 0x40084c, 0); in nv50_gr_trap_handler()
651 nv_wr32(priv, 0x400804, 0xc0000000); in nv50_gr_trap_handler()
[all …]
Dnv10.c418 nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \
426 nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \
428 nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \
513 nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); in nv17_gr_mthd_lma_window()
514 nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); in nv17_gr_mthd_lma_window()
515 nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv17_gr_mthd_lma_window()
517 nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
519 nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
521 nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv17_gr_mthd_lma_window()
523 nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
[all …]
Dctxgf100.c1024 nv_wr32(info->priv, addr, data); in gf100_grctx_mmio_item()
1093 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); in gf100_grctx_generate_tpcid()
1094 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id); in gf100_grctx_generate_tpcid()
1095 nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); in gf100_grctx_generate_tpcid()
1096 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); in gf100_grctx_generate_tpcid()
1100 nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); in gf100_grctx_generate_tpcid()
1101 nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); in gf100_grctx_generate_tpcid()
1113 nv_wr32(priv, 0x406028 + (i * 4), tmp[i]); in gf100_grctx_generate_r406028()
1114 nv_wr32(priv, 0x405870 + (i * 4), tmp[i]); in gf100_grctx_generate_r406028()
1137 nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); in gf100_grctx_generate_r4060a8()
[all …]
Dctxgm204.c929 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); in gm204_grctx_generate_tpcid()
930 nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); in gm204_grctx_generate_tpcid()
931 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); in gm204_grctx_generate_tpcid()
972 nv_wr32(priv, 0x405b60 + (i * 4), dist[i]); in gm204_grctx_generate_405b60()
974 nv_wr32(priv, 0x405ba0 + (i * 4), gpcs[i]); in gm204_grctx_generate_405b60()
990 nv_wr32(priv, 0x404154, 0x00000000); in gm204_grctx_generate_main()
1002 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); in gm204_grctx_generate_main()
1003 nv_wr32(priv, 0x406500, 0x00000000); in gm204_grctx_generate_main()
1005 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); in gm204_grctx_generate_main()
1011 nv_wr32(priv, 0x4041c4, tmp); in gm204_grctx_generate_main()
[all …]
Dctxgk104.c924 nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
927 nv_wr32(priv, 0x418b08 + (i * 4), data[i]); in gk104_grctx_generate_r418bb8()
930 nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
932 nv_wr32(priv, 0x41bfe4, data2[1]); in gk104_grctx_generate_r418bb8()
934 nv_wr32(priv, 0x41bf00 + (i * 4), data[i]); in gk104_grctx_generate_r418bb8()
937 nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
940 nv_wr32(priv, 0x40780c + (i * 4), data[i]); in gk104_grctx_generate_r418bb8()
965 nv_wr32(priv, 0x404154, 0x00000000); in gk104_grctx_generate_main()
978 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); in gk104_grctx_generate_main()
980 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); in gk104_grctx_generate_main()
[all …]
Dctxgm107.c942 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); in gm107_grctx_generate_tpcid()
943 nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); in gm107_grctx_generate_tpcid()
944 nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); in gm107_grctx_generate_tpcid()
948 nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); in gm107_grctx_generate_tpcid()
949 nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); in gm107_grctx_generate_tpcid()
966 nv_wr32(priv, 0x404154, 0x00000000); in gm107_grctx_generate_main()
978 nv_wr32(priv, 0x4064d0, 0x00000001); in gm107_grctx_generate_main()
980 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); in gm107_grctx_generate_main()
981 nv_wr32(priv, 0x406500, 0x00000001); in gm107_grctx_generate_main()
983 nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); in gm107_grctx_generate_main()
[all …]
Dnv04.c458 nv_wr32(priv, NV04_PGRAPH_CTX_SWITCH1, tmp); in nv04_gr_set_ctx1()
459 nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); in nv04_gr_set_ctx1()
543 nv_wr32(priv, 0x40053c, min); in nv04_gr_mthd_surf3d_clip_h()
544 nv_wr32(priv, 0x400544, max); in nv04_gr_mthd_surf3d_clip_h()
564 nv_wr32(priv, 0x400540, min); in nv04_gr_mthd_surf3d_clip_v()
565 nv_wr32(priv, 0x400548, max); in nv04_gr_mthd_surf3d_clip_v()
1053 nv_wr32(priv, nv04_gr_ctx_regs[i], chan->nv04[i]); in nv04_gr_load_context()
1055 nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100); in nv04_gr_load_context()
1070 nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000); in nv04_gr_unload_context()
1284 nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); in nv04_gr_intr()
[all …]
Dctxgf117.c233 nv_wr32(priv, 0x404154, 0x00000000); in gf117_grctx_generate_main()
247 nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); in gf117_grctx_generate_main()
250 nv_wr32(priv, 0x404154, 0x00000400); in gf117_grctx_generate_main()
Dctxnv40.c687 nv_wr32(device, 0x400324, 0); in nv40_grctx_init()
689 nv_wr32(device, 0x400328, ctxprog[i]); in nv40_grctx_init()
Dctxnv50.c280 nv_wr32(device, 0x400324, 0); in nv50_grctx_init()
282 nv_wr32(device, 0x400328, ctxprog[i]); in nv50_grctx_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dbase.c60 nv_wr32(pmu, 0x10a580, 0x00000001); in nvkm_pmu_send()
64 nv_wr32(pmu, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + in nvkm_pmu_send()
66 nv_wr32(pmu, 0x10a1c4, process); in nvkm_pmu_send()
67 nv_wr32(pmu, 0x10a1c4, message); in nvkm_pmu_send()
68 nv_wr32(pmu, 0x10a1c4, data0); in nvkm_pmu_send()
69 nv_wr32(pmu, 0x10a1c4, data1); in nvkm_pmu_send()
70 nv_wr32(pmu, 0x10a4a0, (addr + 1) & 0x0f); in nvkm_pmu_send()
73 nv_wr32(pmu, 0x10a580, 0x00000000); in nvkm_pmu_send()
99 nv_wr32(pmu, 0x10a580, 0x00000002); in nvkm_pmu_recv()
103 nv_wr32(pmu, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + in nvkm_pmu_recv()
[all …]
Dmemx.c25 nv_wr32(pmu, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); in memx_out()
27 nv_wr32(pmu, 0x10a1c4, memx->c.data[i]); in memx_out()
65 nv_wr32(pmu, 0x10a580, 0x00000003); in nvkm_memx_init()
67 nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base); in nvkm_memx_init()
83 nv_wr32(pmu, 0x10a580, 0x00000000); in nvkm_memx_fini()
179 nv_wr32(pmu, 0x10a1c0, 0x02000000 | base); in nvkm_memx_train_result()
Dgk20a.c109 nv_wr32(priv, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
110 nv_wr32(priv, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
187 nv_wr32(pmu, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); in gk20a_pmu_init()
188 nv_wr32(pmu, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); in gk20a_pmu_init()
189 nv_wr32(pmu, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); in gk20a_pmu_init()
Dgk110.c68 nv_wr32(pmu, magic[i].addr, magic[i].data); in gk110_pmu_pgob()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv04.c205 nv_wr32(priv, NV03_PFIFO_CACHES, 0); in nv04_fifo_chan_fini()
211 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 0); in nv04_fifo_chan_fini()
225 nv_wr32(priv, c->regp, 0x00000000); in nv04_fifo_chan_fini()
228 nv_wr32(priv, NV03_PFIFO_CACHE1_GET, 0); in nv04_fifo_chan_fini()
229 nv_wr32(priv, NV03_PFIFO_CACHE1_PUT, 0); in nv04_fifo_chan_fini()
230 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); in nv04_fifo_chan_fini()
231 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); in nv04_fifo_chan_fini()
232 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_chan_fini()
237 nv_wr32(priv, NV03_PFIFO_CACHES, 1); in nv04_fifo_chan_fini()
310 nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000000); in nv04_fifo_pause()
[all …]
Dnv40.c132 nv_wr32(priv, reg, nv_engctx(engctx)->addr); in nv40_fifo_context_attach()
168 nv_wr32(priv, reg, 0x00000000); in nv40_fifo_context_detach()
306 nv_wr32(priv, 0x002040, 0x000000ff); in nv40_fifo_init()
307 nv_wr32(priv, 0x002044, 0x2101ffff); in nv40_fifo_init()
308 nv_wr32(priv, 0x002058, 0x00000001); in nv40_fifo_init()
310 nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv40_fifo_init()
313 nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); in nv40_fifo_init()
319 nv_wr32(priv, 0x002230, 0x00000001); in nv40_fifo_init()
326 nv_wr32(priv, 0x002220, 0x00030002); in nv40_fifo_init()
329 nv_wr32(priv, 0x002230, 0x00000000); in nv40_fifo_init()
[all …]
Dnv17.c186 nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); in nv17_fifo_init()
187 nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); in nv17_fifo_init()
189 nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv17_fifo_init()
192 nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); in nv17_fifo_init()
193 nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); in nv17_fifo_init()
195 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); in nv17_fifo_init()
197 nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); in nv17_fifo_init()
198 nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); in nv17_fifo_init()
200 nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); in nv17_fifo_init()
201 nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
[all …]
Dgf100.c97 nv_wr32(priv, 0x002270, cur->addr >> 12); in gf100_fifo_runlist_update()
98 nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3)); in gf100_fifo_runlist_update()
166 nv_wr32(priv, 0x002634, chan->base.chid); in gf100_fifo_context_detach()
263 nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); in gf100_fifo_chan_init()
266 nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); in gf100_fifo_chan_init()
289 nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); in gf100_fifo_chan_fini()
433 nv_wr32(priv, 0x00262c, engm); in gf100_fifo_recover_work()
707 nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); in gf100_fifo_intr_pbdma()
708 nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); in gf100_fifo_intr_pbdma()
718 nv_wr32(priv, 0x002a00, 0x10000000); in gf100_fifo_intr_runlist()
[all …]
Dgk104.c117 nv_wr32(priv, 0x002270, cur->addr >> 12); in gk104_fifo_runlist_update()
118 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); in gk104_fifo_runlist_update()
191 nv_wr32(priv, 0x002634, chan->base.chid); in gk104_fifo_context_detach()
299 nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); in gk104_fifo_chan_init()
322 nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); in gk104_fifo_chan_fini()
458 nv_wr32(priv, 0x00262c, engm); in gk104_fifo_recover_work()
595 nv_wr32(priv, 0x00256c, stat); in gk104_fifo_intr_chsw()
836 nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); in gk104_fifo_intr_pbdma_0()
850 nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); in gk104_fifo_intr_pbdma_0()
878 nv_wr32(priv, 0x040148 + (unit * 0x2000), stat); in gk104_fifo_intr_pbdma_1()
[all …]
Dnv50.c58 nv_wr32(priv, 0x0032f4, cur->addr >> 12); in nv50_fifo_playlist_update_locked()
59 nv_wr32(priv, 0x0032ec, p); in nv50_fifo_playlist_update_locked()
60 nv_wr32(priv, 0x002500, 0x00000101); in nv50_fifo_playlist_update_locked()
135 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); in nv50_fifo_context_detach()
142 nv_wr32(priv, 0x00b860, me); in nv50_fifo_context_detach()
334 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); in nv50_fifo_chan_init()
349 nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000); in nv50_fifo_chan_fini()
509 nv_wr32(priv, 0x00250c, 0x6f3cfc34); in nv50_fifo_init()
510 nv_wr32(priv, 0x002044, 0x01003fff); in nv50_fifo_init()
512 nv_wr32(priv, 0x002100, 0xffffffff); in nv50_fifo_init()
[all …]
Dg84.c107 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); in g84_fifo_context_detach()
109 nv_wr32(priv, 0x002520, save); in g84_fifo_context_detach()
323 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); in g84_fifo_chan_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c157 nv_wr32(devinit, 0x001584, in setPLL_single()
164 nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff)); in setPLL_single()
167 nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1); in setPLL_single()
176 nv_wr32(devinit, reg, pll); in setPLL_single()
179 nv_wr32(devinit, 0x001584, saved_powerctrl_1); in setPLL_single()
235 nv_wr32(devinit, 0x001584, in setPLL_double_highregs()
256 nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040)); in setPLL_double_highregs()
260 nv_wr32(devinit, 0x680580, ramdac580); in setPLL_double_highregs()
263 nv_wr32(devinit, reg2, pll2); in setPLL_double_highregs()
264 nv_wr32(devinit, reg1, pll1); in setPLL_double_highregs()
[all …]
Dgm204.c36 nv_wr32(priv, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu); in pmu_code()
39 nv_wr32(priv, 0x10a188, (pmu + i) >> 8); in pmu_code()
40 nv_wr32(priv, 0x10a184, nv_ro32(bios, img + i)); in pmu_code()
44 nv_wr32(priv, 0x10a184, 0x00000000); in pmu_code()
55 nv_wr32(priv, 0x10a1c0, 0x01000000 | pmu); in pmu_data()
57 nv_wr32(priv, 0x10a1c4, nv_ro32(bios, img + i)); in pmu_data()
63 nv_wr32(priv, 0x10a1c0, argp); in pmu_args()
64 nv_wr32(priv, 0x10a1c0, nv_rd32(priv, 0x10a1c4) + argi); in pmu_args()
71 nv_wr32(priv, 0x10a104, init_addr); in pmu_exec()
72 nv_wr32(priv, 0x10a10c, 0x00000000); in pmu_exec()
[all …]
Dnv50.c59 nv_wr32(priv, info.reg + 0, 0x10000611); in nv50_devinit_pll_set()
68 nv_wr32(priv, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
72 nv_wr32(priv, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
Dgt215.c51 nv_wr32(priv, info.reg + 0, 0x50000610); in gt215_devinit_pll_set()
54 nv_wr32(priv, info.reg + 8, fN); in gt215_devinit_pll_set()
Dgf100.c54 nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M); in gf100_devinit_pll_set()
55 nv_wr32(priv, info.reg + 0x10, fN << 16); in gf100_devinit_pll_set()
Dnv20.c48 nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); in nv20_devinit_meminit()
Dnv10.c55 nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); in nv10_devinit_meminit()
Dnv05.c83 nv_wr32(priv, NV04_PFB_SCRAMBLE(i), scramble); in nv05_devinit_meminit()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv31.c78 nv_wr32(priv, 0x00b334, base); in nv31_mpeg_mthd_dma()
79 nv_wr32(priv, 0x00b324, size); in nv31_mpeg_mthd_dma()
84 nv_wr32(priv, 0x00b360, base); in nv31_mpeg_mthd_dma()
85 nv_wr32(priv, 0x00b364, size); in nv31_mpeg_mthd_dma()
91 nv_wr32(priv, 0x00b370, base); in nv31_mpeg_mthd_dma()
92 nv_wr32(priv, 0x00b374, size); in nv31_mpeg_mthd_dma()
188 nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile_prog()
189 nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile_prog()
190 nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile_prog()
225 nv_wr32(priv, 0x00b100, stat); in nv31_mpeg_intr()
[all …]
Dnv50.c135 nv_wr32(priv, 0x00b308, 0x00000100); in nv50_mpeg_intr()
145 nv_wr32(priv, 0x00b100, stat); in nv50_mpeg_intr()
146 nv_wr32(priv, 0x00b230, 0x00000001); in nv50_mpeg_intr()
160 nv_wr32(priv, 0xb800, stat); in nv50_vpe_intr()
194 nv_wr32(priv, 0x00b32c, 0x00000000); in nv50_mpeg_init()
195 nv_wr32(priv, 0x00b314, 0x00000100); in nv50_mpeg_init()
196 nv_wr32(priv, 0x00b0e0, 0x0000001a); in nv50_mpeg_init()
198 nv_wr32(priv, 0x00b220, 0x00000044); in nv50_mpeg_init()
199 nv_wr32(priv, 0x00b300, 0x00801ec1); in nv50_mpeg_init()
200 nv_wr32(priv, 0x00b390, 0x00000000); in nv50_mpeg_init()
[all …]
Dnv40.c51 nv_wr32(priv, 0x00b334, base); in nv40_mpeg_mthd_dma()
52 nv_wr32(priv, 0x00b324, size); in nv40_mpeg_mthd_dma()
57 nv_wr32(priv, 0x00b360, base); in nv40_mpeg_mthd_dma()
58 nv_wr32(priv, 0x00b364, size); in nv40_mpeg_mthd_dma()
64 nv_wr32(priv, 0x00b370, base); in nv40_mpeg_mthd_dma()
65 nv_wr32(priv, 0x00b374, size); in nv40_mpeg_mthd_dma()
100 nv_wr32(priv, 0x00b800, stat); in nv40_mpeg_intr()
Dnv44.c127 nv_wr32(priv, 0x00b100, stat); in nv44_mpeg_intr()
128 nv_wr32(priv, 0x00b230, 0x00000001); in nv44_mpeg_intr()
151 nv_wr32(priv, 0x00b800, stat); in nv44_mpeg_me_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dhdmig84.c65 nv_wr32(priv, 0x616528 + hoff, 0x000d0282); in g84_hdmi_ctrl()
66 nv_wr32(priv, 0x61652c + hoff, 0x0000006f); in g84_hdmi_ctrl()
67 nv_wr32(priv, 0x616530 + hoff, 0x00000000); in g84_hdmi_ctrl()
68 nv_wr32(priv, 0x616534 + hoff, 0x00000000); in g84_hdmi_ctrl()
69 nv_wr32(priv, 0x616538 + hoff, 0x00000000); in g84_hdmi_ctrl()
74 nv_wr32(priv, 0x616508 + hoff, 0x000a0184); in g84_hdmi_ctrl()
75 nv_wr32(priv, 0x61650c + hoff, 0x00000071); in g84_hdmi_ctrl()
76 nv_wr32(priv, 0x616510 + hoff, 0x00000000); in g84_hdmi_ctrl()
Dhdmigt215.c66 nv_wr32(priv, 0x61c528 + soff, 0x000d0282); in gt215_hdmi_ctrl()
67 nv_wr32(priv, 0x61c52c + soff, 0x0000006f); in gt215_hdmi_ctrl()
68 nv_wr32(priv, 0x61c530 + soff, 0x00000000); in gt215_hdmi_ctrl()
69 nv_wr32(priv, 0x61c534 + soff, 0x00000000); in gt215_hdmi_ctrl()
70 nv_wr32(priv, 0x61c538 + soff, 0x00000000); in gt215_hdmi_ctrl()
75 nv_wr32(priv, 0x61c508 + soff, 0x000a0184); in gt215_hdmi_ctrl()
76 nv_wr32(priv, 0x61c50c + soff, 0x00000071); in gt215_hdmi_ctrl()
77 nv_wr32(priv, 0x61c510 + soff, 0x00000000); in gt215_hdmi_ctrl()
Dhdmigk104.c65 nv_wr32(priv, 0x690008 + hdmi, 0x000d0282); in gk104_hdmi_ctrl()
66 nv_wr32(priv, 0x69000c + hdmi, 0x0000006f); in gk104_hdmi_ctrl()
67 nv_wr32(priv, 0x690010 + hdmi, 0x00000000); in gk104_hdmi_ctrl()
68 nv_wr32(priv, 0x690014 + hdmi, 0x00000000); in gk104_hdmi_ctrl()
69 nv_wr32(priv, 0x690018 + hdmi, 0x00000000); in gk104_hdmi_ctrl()
74 nv_wr32(priv, 0x6900cc + hdmi, 0x00000010); in gk104_hdmi_ctrl()
78 nv_wr32(priv, 0x690080 + hdmi, 0x82000000); in gk104_hdmi_ctrl()
Dhdmigf110.c64 nv_wr32(priv, 0x61671c + hoff, 0x000d0282); in gf110_hdmi_ctrl()
65 nv_wr32(priv, 0x616720 + hoff, 0x0000006f); in gf110_hdmi_ctrl()
66 nv_wr32(priv, 0x616724 + hoff, 0x00000000); in gf110_hdmi_ctrl()
67 nv_wr32(priv, 0x616728 + hoff, 0x00000000); in gf110_hdmi_ctrl()
68 nv_wr32(priv, 0x61672c + hoff, 0x00000000); in gf110_hdmi_ctrl()
73 nv_wr32(priv, 0x6167ac + hoff, 0x00000010); in gf110_hdmi_ctrl()
Dgf110.c51 nv_wr32(priv, 0x61008c, 0x00000001 << index); in gf110_disp_chan_uevent_fini()
58 nv_wr32(priv, 0x61008c, 0x00000001 << index); in gf110_disp_chan_uevent_init()
107 nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push); in gf110_disp_dmac_init()
108 nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000); in gf110_disp_dmac_init()
109 nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001); in gf110_disp_dmac_init()
111 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); in gf110_disp_dmac_init()
112 nv_wr32(priv, 0x610490 + (chid * 0x0010), 0x00000013); in gf110_disp_dmac_init()
307 nv_wr32(priv, 0x610494, mast->push); in gf110_disp_core_init()
308 nv_wr32(priv, 0x610498, 0x00010000); in gf110_disp_core_init()
309 nv_wr32(priv, 0x61049c, 0x00000001); in gf110_disp_core_init()
[all …]
Dnv50.c94 nv_wr32(priv, 0x610020, 0x00000001 << index); in nv50_disp_chan_uevent_fini()
101 nv_wr32(priv, 0x610020, 0x00000001 << index); in nv50_disp_chan_uevent_init()
179 nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data); in nv50_disp_chan_wr32()
272 nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push); in nv50_disp_dmac_init()
273 nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000); in nv50_disp_dmac_init()
274 nv_wr32(priv, 0x61020c + (chid * 0x0010), chid); in nv50_disp_dmac_init()
276 nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); in nv50_disp_dmac_init()
277 nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013); in nv50_disp_dmac_init()
537 nv_wr32(priv, 0x610204, mast->push); in nv50_disp_core_init()
538 nv_wr32(priv, 0x610208, 0x00010000); in nv50_disp_core_init()
[all …]
Dnv04.c132 nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001); in nv04_disp_vblank_init()
139 nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000); in nv04_disp_vblank_fini()
159 nv_wr32(priv, 0x600100, 0x00000001); in nv04_disp_intr()
164 nv_wr32(priv, 0x602100, 0x00000001); in nv04_disp_intr()
172 nv_wr32(priv, 0x8100, pvideo); in nv04_disp_intr()
Dsorgf110.c103 nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); in gf110_sor_dp_drv_ctl()
104 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); in gf110_sor_dp_drv_ctl()
105 nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); in gf110_sor_dp_drv_ctl()
107 nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); in gf110_sor_dp_drv_ctl()
Dsorgm204.c118 nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); in gm204_sor_dp_drv_ctl()
119 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); in gm204_sor_dp_drv_ctl()
120 nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); in gm204_sor_dp_drv_ctl()
122 nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); in gm204_sor_dp_drv_ctl()
Dhdagt215.c56 nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]); in gt215_hda_eld()
58 nv_wr32(priv, 0x61c440 + soff, (i << 8)); in gt215_hda_eld()
Dhdagf110.c60 nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]); in gf110_hda_eld()
62 nv_wr32(priv, 0x10ec00 + soff, (i << 8)); in gf110_hda_eld()
Dsorg94.c126 nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); in g94_sor_dp_drv_ctl()
127 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); in g94_sor_dp_drv_ctl()
128 nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); in g94_sor_dp_drv_ctl()
Ddacnv50.c85 nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval); in nv50_dac_sense()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dgm107.c32 nv_wr32(priv, 0x17e270, start); in gm107_ltc_cbc_clear()
33 nv_wr32(priv, 0x17e274, limit); in gm107_ltc_cbc_clear()
34 nv_wr32(priv, 0x17e26c, 0x00000004); in gm107_ltc_cbc_clear()
51 nv_wr32(priv, 0x17e33c, color[0]); in gm107_ltc_zbc_clear_color()
52 nv_wr32(priv, 0x17e340, color[1]); in gm107_ltc_zbc_clear_color()
53 nv_wr32(priv, 0x17e344, color[2]); in gm107_ltc_zbc_clear_color()
54 nv_wr32(priv, 0x17e348, color[3]); in gm107_ltc_zbc_clear_color()
61 nv_wr32(priv, 0x17e34c, depth); in gm107_ltc_zbc_clear_depth()
72 nv_wr32(priv, base + 0x00c, stat); in gm107_ltc_lts_isr()
102 nv_wr32(priv, 0x17e27c, priv->ltc_nr); in gm107_ltc_init()
[all …]
Dgf100.c33 nv_wr32(priv, 0x17e8cc, start); in gf100_ltc_cbc_clear()
34 nv_wr32(priv, 0x17e8d0, limit); in gf100_ltc_cbc_clear()
35 nv_wr32(priv, 0x17e8c8, 0x00000004); in gf100_ltc_cbc_clear()
52 nv_wr32(priv, 0x17ea48, color[0]); in gf100_ltc_zbc_clear_color()
53 nv_wr32(priv, 0x17ea4c, color[1]); in gf100_ltc_zbc_clear_color()
54 nv_wr32(priv, 0x17ea50, color[2]); in gf100_ltc_zbc_clear_color()
55 nv_wr32(priv, 0x17ea54, color[3]); in gf100_ltc_zbc_clear_color()
62 nv_wr32(priv, 0x17ea58, depth); in gf100_ltc_zbc_clear_depth()
96 nv_wr32(priv, base + 0x020, intr); in gf100_ltc_lts_intr()
126 nv_wr32(priv, 0x17e8d8, priv->ltc_nr); in gf100_ltc_init()
[all …]
Dgk104.c37 nv_wr32(priv, 0x17e8d8, priv->ltc_nr); in gk104_ltc_init()
38 nv_wr32(priv, 0x17e000, priv->ltc_nr); in gk104_ltc_init()
39 nv_wr32(priv, 0x17e8d4, priv->tag_base); in gk104_ltc_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
Dnv04.c60 nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp); in nv04_timer_alarm_trigger()
61 nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001); in nv04_timer_alarm_trigger()
63 nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); in nv04_timer_alarm_trigger()
119 nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001); in nv04_timer_intr()
125 nv_wr32(priv, NV04_PTIMER_INTR_0, stat); in nv04_timer_intr()
135 nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); in nv04_timer_fini()
172 nv_wr32(priv, 0x009220, m - 1); in nv04_timer_init()
179 nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1); in nv04_timer_init()
180 nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1); in nv04_timer_init()
213 nv_wr32(priv, NV04_PTIMER_NUMERATOR, n); in nv04_timer_init()
[all …]
Dgk20a.c42 nv_wr32(priv, NV04_PTIMER_TIME_1, hi); in gk20a_timer_init()
43 nv_wr32(priv, NV04_PTIMER_TIME_0, lo); in gk20a_timer_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dg84.c67 nv_wr32(therm, 0x20000, 0x000003ff); in g84_therm_program_alarms()
70 nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
71 nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
74 nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
77 nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp); in g84_therm_program_alarms()
80 nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp); in g84_therm_program_alarms()
109 nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis); in g84_therm_threshold_hyst_emulation()
112 nv_wr32(therm, thrs_reg, thrs->temp); in g84_therm_threshold_hyst_emulation()
186 nv_wr32(therm, 0x20100, 0xffffffff); in g84_therm_intr()
187 nv_wr32(therm, 0x1100, 0x10000); /* PBUS */ in g84_therm_intr()
[all …]
Dnv40.c69 nv_wr32(therm, 0x15b0, 0x80003fff); in nv40_sensor_setup()
73 nv_wr32(therm, 0x15b0, 0xff); in nv40_sensor_setup()
89 nv_wr32(therm, 0x15b0, 0x80003fff); in nv40_temp_get()
92 nv_wr32(therm, 0x15b0, 0xff); in nv40_temp_get()
159 nv_wr32(therm, 0x0015f8, divs); in nv40_fan_pwm_set()
178 nv_wr32(therm, 0x1100, 0x70000); in nv40_therm_intr()
Dgf110.c97 nv_wr32(therm, 0x00e114 + (indx * 8), divs); in gf110_fan_pwm_set()
98 nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000); in gf110_fan_pwm_set()
101 nv_wr32(therm, 0x0200dc, duty | 0x40000000); in gf110_fan_pwm_set()
132 nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000); in gf110_therm_init()
Dnv50.c91 nv_wr32(therm, 0x00e114 + (id * 8), divs); in nv50_fan_pwm_set()
92 nv_wr32(therm, 0x00e118 + (id * 8), duty | 0x80000000); in nv50_fan_pwm_set()
Dgm107.c51 nv_wr32(therm, 0x10eb14, duty | 0x80000000); in gm107_fan_pwm_set()
Dgt215.c59 nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000); in gt215_therm_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dnv50.c36 nv_wr32(pbus, 0x001304, 0x00000000); in nv50_bus_hwsq_exec()
38 nv_wr32(priv, 0x001400 + (i * 4), data[i]); in nv50_bus_hwsq_exec()
40 nv_wr32(pbus, 0x00130c, 0x00000003); in nv50_bus_hwsq_exec()
60 nv_wr32(pbus, 0x001100, 0x00000008); in nv50_bus_intr()
68 nv_wr32(pbus, 0x001100, 0x00010000); in nv50_bus_intr()
87 nv_wr32(priv, 0x001100, 0xffffffff); in nv50_bus_init()
88 nv_wr32(priv, 0x001140, 0x00010008); in nv50_bus_init()
Dg94.c36 nv_wr32(pbus, 0x001304, 0x00000000); in g94_bus_hwsq_exec()
37 nv_wr32(pbus, 0x001318, 0x00000000); in g94_bus_hwsq_exec()
39 nv_wr32(priv, 0x080000 + (i * 4), data[i]); in g94_bus_hwsq_exec()
41 nv_wr32(pbus, 0x00130c, 0x00000001); in g94_bus_hwsq_exec()
Dgf100.c44 nv_wr32(pbus, 0x009084, 0x00000000); in gf100_bus_intr()
45 nv_wr32(pbus, 0x001100, (stat & 0x0000000e)); in gf100_bus_intr()
65 nv_wr32(priv, 0x001100, 0xffffffff); in gf100_bus_init()
66 nv_wr32(priv, 0x001140, 0x0000000e); in gf100_bus_init()
Dnv31.c49 nv_wr32(pbus, 0x001100, 0x00000008); in nv31_bus_intr()
57 nv_wr32(pbus, 0x001100, 0x00070000); in nv31_bus_intr()
76 nv_wr32(priv, 0x001100, 0xffffffff); in nv31_bus_init()
77 nv_wr32(priv, 0x001140, 0x00070008); in nv31_bus_init()
Dnv04.c36 nv_wr32(pbus, 0x001100, 0x00000001); in nv04_bus_intr()
44 nv_wr32(pbus, 0x001100, 0x00000110); in nv04_bus_intr()
58 nv_wr32(priv, 0x001100, 0xffffffff); in nv04_bus_init()
59 nv_wr32(priv, 0x001140, 0x00000111); in nv04_bus_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
Dnv44.c32 nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ in nv44_mc_init()
34 nv_wr32(priv, 0x001700, tmp); in nv44_mc_init()
35 nv_wr32(priv, 0x001704, 0); in nv44_mc_init()
36 nv_wr32(priv, 0x001708, 0); in nv44_mc_init()
37 nv_wr32(priv, 0x00170c, tmp); in nv44_mc_init()
Dbase.c55 nv_wr32(pmc, 0x000140, 0x00000000); in nvkm_mc_intr()
77 nv_wr32(pmc, 0x000140, 0x00000001); in nvkm_mc_intr()
85 nv_wr32(pmc, 0x000140, 0x00000000); in _nvkm_mc_fini()
96 nv_wr32(pmc, 0x000140, 0x00000001); in _nvkm_mc_init()
Dgf100.c55 nv_wr32(priv, 0x088704, 0x00000000); in gf100_mc_msi_rearm()
61 nv_wr32(pmc, 0x000260, data); in gf100_mc_unk260()
Dnv04.c46 nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ in nv04_mc_init()
47 nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */ in nv04_mc_init()
Dnv50.c57 nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */ in nv50_mc_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sw/
Dgf100.c58 nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */ in gf100_sw_mthd_mp_control()
63 nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */ in gf100_sw_mthd_mp_control()
66 nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */ in gf100_sw_mthd_mp_control()
105 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); in gf100_sw_vblsem_release()
107 nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset)); in gf100_sw_vblsem_release()
108 nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset)); in gf100_sw_vblsem_release()
109 nv_wr32(priv, 0x060014, chan->vblank.value); in gf100_sw_vblsem_release()
Dnv50.c128 nv_wr32(priv, 0x001704, chan->vblank.channel); in nv50_sw_vblsem_release()
129 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); in nv50_sw_vblsem_release()
133 nv_wr32(priv, 0x001570, chan->vblank.offset); in nv50_sw_vblsem_release()
134 nv_wr32(priv, 0x001574, chan->vblank.value); in nv50_sw_vblsem_release()
136 nv_wr32(priv, 0x060010, chan->vblank.offset); in nv50_sw_vblsem_release()
137 nv_wr32(priv, 0x060014, chan->vblank.value); in nv50_sw_vblsem_release()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dnv41.c31 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
32 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
33 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
35 nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
48 nv_wr32(priv, 0x100800, 0x00000001); in nv41_fb_init()
Dramnv40.c104 nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */ in nv40_ram_prog()
105 nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */ in nv40_ram_prog()
106 nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */ in nv40_ram_prog()
108 nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */ in nv40_ram_prog()
120 nv_wr32(pfb, 0x004048, ram->coef); in nv40_ram_prog()
121 nv_wr32(pfb, 0x004030, ram->coef); in nv40_ram_prog()
126 nv_wr32(pfb, 0x00403c, ram->coef); in nv40_ram_prog()
129 nv_wr32(pfb, 0x004024, ram->coef); in nv40_ram_prog()
136 nv_wr32(pfb, 0x1002dc, 0x00000000); in nv40_ram_prog()
Dnv44.c41 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
42 nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
43 nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
57 nv_wr32(priv, 0x100850, 0x80000000); in nv44_fb_init()
58 nv_wr32(priv, 0x100800, 0x00000001); in nv44_fb_init()
Dnv20.c71 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); in nv20_fb_tile_prog()
72 nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); in nv20_fb_tile_prog()
73 nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); in nv20_fb_tile_prog()
75 nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp); in nv20_fb_tile_prog()
Dnv10.c49 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); in nv10_fb_tile_prog()
50 nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); in nv10_fb_tile_prog()
51 nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); in nv10_fb_tile_prog()
Drammcp77.c84 nv_wr32(pfb, 0x100c18, dniso); in mcp77_ram_init()
86 nv_wr32(pfb, 0x100c1c, hostnb); in mcp77_ram_init()
88 nv_wr32(pfb, 0x100c24, flush); in mcp77_ram_init()
Dramgf100.c605 nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8)); in gf100_ram_init()
606 nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8)); in gf100_ram_init()
607 nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]); in gf100_ram_init()
608 nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]); in gf100_ram_init()
609 nv_wr32(pfb, 0x10f918, train1[i % 12]); in gf100_ram_init()
610 nv_wr32(pfb, 0x10f91c, train1[i % 12]); in gf100_ram_init()
611 nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]); in gf100_ram_init()
612 nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]); in gf100_ram_init()
613 nv_wr32(pfb, 0x10f918, train1[i % 12]); in gf100_ram_init()
614 nv_wr32(pfb, 0x10f91c, train1[i % 12]); in gf100_ram_init()
Dnv50.c163 nv_wr32(priv, 0x100c90, idx | i << 24); in nv50_fb_intr()
166 nv_wr32(priv, 0x100c90, idx | 0x80000000); in nv50_fb_intr()
300 nv_wr32(priv, 0x100c08, priv->r100c08 >> 8); in nv50_fb_init()
304 nv_wr32(priv, 0x100c90, impl->trap); in nv50_fb_init()
Dramgt215.c200 nv_wr32(pfb, 0x111400, 0x00000000); in gt215_link_train()
205 nv_wr32(pfb, 0x100c04, 0x00000400); in gt215_link_train()
307 nv_wr32(pfb, 0x100538, 0x10000000 | (mem->offset >> 16)); in gt215_link_train_init()
308 nv_wr32(pfb, 0x1005a8, 0x0000ffff); in gt215_link_train_init()
312 nv_wr32(pfb, 0x10f8c0, (i << 8) | i); in gt215_link_train_init()
313 nv_wr32(pfb, 0x10f900, pattern[i % 16]); in gt215_link_train_init()
317 nv_wr32(pfb, 0x10f8e0, (i << 8) | i); in gt215_link_train_init()
318 nv_wr32(pfb, 0x10f920, pattern[i % 16]); in gt215_link_train_init()
323 nv_wr32(pfb, 0x1700, mem->offset >> 16); in gt215_link_train_init()
325 nv_wr32(pfb, 0x700000 + (i << 2), pattern[i]); in gt215_link_train_init()
[all …]
Dnv30.c112 nv_wr32(priv, 0x10037c + 0xc * i + 0x4 * j, in nv30_fb_init()
116 nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j, in nv30_fb_init()
Dnv04.c50 nv_wr32(priv, NV04_PFB_CFG0, 0x1114); in nv04_fb_init()
Dgf100.c63 nv_wr32(priv, 0x100c10, priv->r100c10 >> 8); in gf100_fb_init()
Dramgk104.c1258 nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8)); in gk104_ram_train_init_0()
1259 nv_wr32(pfb, 0x10f920 + j, 0x00000000 | in gk104_ram_train_init_0()
1262 nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]); in gk104_ram_train_init_0()
1263 nv_wr32(pfb, 0x10f920 + j, 0x00000100 | in gk104_ram_train_init_0()
1266 nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]); in gk104_ram_train_init_0()
1272 nv_wr32(pfb, 0x10f968 + j, i); in gk104_ram_train_init_0()
1273 nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]); in gk104_ram_train_init_0()
1353 nv_wr32(pfb, 0x10ecc0, 0xffffffff); in gk104_ram_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv44.c144 nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); in nv44_vm_flush()
145 nv_wr32(priv, 0x100808, 0x00000020); in nv44_vm_flush()
148 nv_wr32(priv, 0x100808, 0x00000000); in nv44_vm_flush()
227 nv_wr32(priv, 0x100850, 0x80000000); in nv44_mmu_init()
228 nv_wr32(priv, 0x100818, priv->null); in nv44_mmu_init()
229 nv_wr32(priv, 0x100804, NV44_GART_SIZE); in nv44_mmu_init()
230 nv_wr32(priv, 0x100850, 0x00008000); in nv44_mmu_init()
232 nv_wr32(priv, 0x100820, 0x00000000); in nv44_mmu_init()
233 nv_wr32(priv, 0x10082c, 0x00000001); in nv44_mmu_init()
234 nv_wr32(priv, 0x100800, addr | 0x00000010); in nv44_mmu_init()
Dnv41.c71 nv_wr32(priv, 0x100810, 0x00000022); in nv41_vm_flush()
76 nv_wr32(priv, 0x100810, 0x00000000); in nv41_vm_flush()
142 nv_wr32(priv, 0x100800, dma->addr | 0x00000002); in nv41_mmu_init()
144 nv_wr32(priv, 0x100820, 0x00000000); in nv41_mmu_init()
Dgf100.c182 nv_wr32(priv, 0x100cb8, vpgd->obj->addr >> 8); in gf100_vm_flush()
183 nv_wr32(priv, 0x100cbc, 0x80000000 | type); in gf100_vm_flush()
Dnv50.c187 nv_wr32(priv, 0x100c80, (vme << 16) | 1); in nv50_vm_flush()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/pm/
Ddaemon.c37 nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask); in pwr_perfctr_init()
38 nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl); in pwr_perfctr_init()
39 nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003); in pwr_perfctr_init()
57 nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000); in pwr_perfctr_next()
Dgf100.c54 nv_wr32(priv, dom->addr + 0x09c, 0x00040002); in gf100_perfctr_init()
55 nv_wr32(priv, dom->addr + 0x100, 0x00000000); in gf100_perfctr_init()
56 nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src); in gf100_perfctr_init()
57 nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log); in gf100_perfctr_init()
80 nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27); in gf100_perfctr_next()
81 nv_wr32(priv, dom->addr + 0x0ec, 0x00000011); in gf100_perfctr_next()
Dnv40.c39 nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001); in nv40_perfctr_init()
40 nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src); in nv40_perfctr_init()
41 nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log); in nv40_perfctr_init()
65 nv_wr32(priv, 0x400084, 0x00000020); in nv40_perfctr_next()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dgk104.c35 nv_wr32(gpio, 0x00dc00, intr0); in gk104_gpio_intr_stat()
36 nv_wr32(gpio, 0x00dc80, intr1); in gk104_gpio_intr_stat()
54 nv_wr32(gpio, 0x00dc08, inte0); in gk104_gpio_intr_mask()
55 nv_wr32(gpio, 0x00dc88, inte1); in gk104_gpio_intr_mask()
Dg94.c35 nv_wr32(gpio, 0x00e054, intr0); in g94_gpio_intr_stat()
36 nv_wr32(gpio, 0x00e074, intr1); in g94_gpio_intr_stat()
54 nv_wr32(gpio, 0x00e050, inte0); in g94_gpio_intr_mask()
55 nv_wr32(gpio, 0x00e070, inte1); in g94_gpio_intr_mask()
Dnv10.c87 nv_wr32(gpio, 0x001104, intr); in nv10_gpio_intr_stat()
98 nv_wr32(gpio, 0x001144, inte); in nv10_gpio_intr_mask()
Dnv50.c99 nv_wr32(gpio, 0x00e054, intr); in nv50_gpio_intr_stat()
110 nv_wr32(gpio, 0x00e050, inte); in nv50_gpio_intr_mask()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c132 nv_wr32(priv, 0x102130, stat); in g84_cipher_intr()
133 nv_wr32(priv, 0x10200c, 0x10); in g84_cipher_intr()
169 nv_wr32(priv, 0x102130, 0xffffffff); in g84_cipher_init()
170 nv_wr32(priv, 0x102140, 0xffffffbf); in g84_cipher_init()
171 nv_wr32(priv, 0x10200c, 0x00000010); in g84_cipher_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Dmemx.fuc91 nv_wr32($r8, $r7)
97 nv_wr32($r6, $r8)
102 nv_wr32($r6, $r8)
107 nv_wr32($r6, $r8)
143 nv_wr32($r8, $r7)
149 nv_wr32($r6, $r8)
154 nv_wr32($r6, $r8)
159 nv_wr32($r6, $r8)
227 nv_wr32($r6, $r5)
289 nv_wr32($r9, $r8)
[all …]
Dmacros.fuc240 #define nv_wr32(addr,reg) /*
247 #define nv_wr32(addr,reg) /*
Dkernel.fuc519 // used by the nv_rd32/nv_wr32 macros to work
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dnv50.c87 nv_wr32(priv, 0x00330c, 0x00000001); in nv50_bar_flush()
99 nv_wr32(bar, 0x070000, 0x00000001); in g84_bar_flush()
240 nv_wr32(priv, 0x100c80, 0x00060001); in nv50_bar_init()
246 nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12); in nv50_bar_init()
247 nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12); in nv50_bar_init()
248 nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4); in nv50_bar_init()
249 nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4); in nv50_bar_init()
251 nv_wr32(priv, 0x001900 + (i * 4), 0x00000000); in nv50_bar_init()
Dgf100.c203 nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); in gf100_bar_init()
205 nv_wr32(priv, 0x001714, in gf100_bar_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dmcp77.c318 nv_wr32(clk, 0x402c, priv->ccoef); in mcp77_clk_prog()
319 nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl); in mcp77_clk_prog()
320 nv_wr32(clk, 0x4040, priv->cpost); in mcp77_clk_prog()
339 nv_wr32(clk, 0x4024, priv->scoef); in mcp77_clk_prog()
340 nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl); in mcp77_clk_prog()
341 nv_wr32(clk, 0x4070, priv->spost); in mcp77_clk_prog()
359 nv_wr32(clk, 0x4600, priv->vdiv); in mcp77_clk_prog()
362 nv_wr32(clk, 0xc054, mast); in mcp77_clk_prog()
367 nv_wr32(clk, 0x4040, 0x00000000); in mcp77_clk_prog()
372 nv_wr32(clk, 0x4070, 0x00000000); in mcp77_clk_prog()
Dgt215.c359 nv_wr32(priv, coef, info->pll); in prog_pll()
395 nv_wr32(priv, 0xc040, hsrc | 0x20000000); in prog_host()
402 nv_wr32(priv, 0xc040, hsrc & ~0x30000000); in prog_host()
410 nv_wr32(priv, 0xc044, 0x3e); in prog_host()
420 nv_wr32(priv, 0x10002c, info->fb_delay); in prog_core()
425 nv_wr32(priv, 0x10002c, info->fb_delay); in prog_core()
Dgk20a.c295 nv_wr32(priv, GPCPLL_COEFF, val); in gk20a_pllg_slide()
301 nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val); in gk20a_pllg_slide()
374 nv_wr32(priv, SEL_VCO, val); in _gk20a_pllg_program_mnp()
380 nv_wr32(priv, GPCPLL_CFG, val); in _gk20a_pllg_program_mnp()
395 nv_wr32(priv, GPCPLL_COEFF, val); in _gk20a_pllg_program_mnp()
402 nv_wr32(priv, GPCPLL_CFG, val); in _gk20a_pllg_program_mnp()
418 nv_wr32(priv, GPC2CLK_OUT, val); in _gk20a_pllg_program_mnp()
Dgf100.c338 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); in gf100_clk_prog_0()
358 nv_wr32(priv, addr + 0x04, info->coef); in gf100_clk_prog_2()
Dgk104.c355 nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); in gk104_clk_prog_0()
380 nv_wr32(priv, addr + 0x04, info->coef); in gk104_clk_prog_2()
Dnv40.c196 nv_wr32(priv, 0x004004, priv->npll_coef); in nv40_clk_prog()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dg94.c37 nv_wr32(i2c, 0x00e06c, intr); in g94_aux_stat()
53 nv_wr32(i2c, 0x00e068, temp); in g94_aux_mask()
128 nv_wr32(aux, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]); in g94_aux()
136 nv_wr32(aux, 0x00e4e0 + (ch * 0x50), addr); in g94_aux()
141 nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl); in g94_aux()
142 nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl); in g94_aux()
147 nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl); in g94_aux()
Dgm204.c98 nv_wr32(aux, 0x00d930 + (ch * 0x50) + i, xbuf[i / 4]); in gm204_aux()
106 nv_wr32(aux, 0x00d950 + (ch * 0x50), addr); in gm204_aux()
111 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x80000000 | ctrl); in gm204_aux()
112 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00000000 | ctrl); in gm204_aux()
117 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00010000 | ctrl); in gm204_aux()
Dnv50.c33 nv_wr32(priv, port->addr, port->state); in nv50_i2c_drive_scl()
43 nv_wr32(priv, port->addr, port->state); in nv50_i2c_drive_sda()
105 nv_wr32(priv, port->addr, port->state); in nv50_i2c_port_init()
Dgk104.c37 nv_wr32(i2c, 0x00dc60, intr); in gk104_aux_stat()
53 nv_wr32(i2c, 0x00dc68, temp); in gk104_aux_mask()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
Dgf100.c44 nv_wr32(priv, 0x21000, unk); in gf100_fuse_rd32()
45 nv_wr32(priv, 0x22400, fuse_enable); in gf100_fuse_rd32()
Dnv50.c43 nv_wr32(priv, 0x1084, fuse_enable); in nv50_fuse_rd32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
Dg98.c74 nv_wr32(priv, 0x084010, 0x0000ffd2); in g98_msvld_init()
75 nv_wr32(priv, 0x08401c, 0x0000fff2); in g98_msvld_init()
Dgk104.c72 nv_wr32(priv, 0x084010, 0x0000fff2); in gk104_msvld_init()
73 nv_wr32(priv, 0x08401c, 0x0000fff2); in gk104_msvld_init()
Dgf100.c72 nv_wr32(priv, 0x084010, 0x0000fff2); in gf100_msvld_init()
73 nv_wr32(priv, 0x08401c, 0x0000fff2); in gf100_msvld_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
Dgk104.c72 nv_wr32(priv, 0x085010, 0x0000fff2); in gk104_mspdec_init()
73 nv_wr32(priv, 0x08501c, 0x0000fff2); in gk104_mspdec_init()
Dg98.c73 nv_wr32(priv, 0x085010, 0x0000ffd2); in g98_mspdec_init()
74 nv_wr32(priv, 0x08501c, 0x0000fff2); in g98_mspdec_init()
Dgf100.c72 nv_wr32(priv, 0x085010, 0x0000fff2); in gf100_mspdec_init()
73 nv_wr32(priv, 0x08501c, 0x0000fff2); in gf100_mspdec_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
Dg98.c73 nv_wr32(priv, 0x086010, 0x0000ffd2); in g98_msppp_init()
74 nv_wr32(priv, 0x08601c, 0x0000fff2); in g98_msppp_init()
Dgf100.c72 nv_wr32(priv, 0x086010, 0x0000fff2); in gf100_msppp_init()
73 nv_wr32(priv, 0x08601c, 0x0000fff2); in gf100_msppp_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgk20a.c38 nv_wr32(priv, 0x12004c, 0x4); in gk20a_ibus_init_priv_ring()
39 nv_wr32(priv, 0x122204, 0x2); in gk20a_ibus_init_priv_ring()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv50.c55 nv_wr32(priv, 0x001700, base >> 16); in nv50_instobj_rd32()
74 nv_wr32(priv, 0x001700, base >> 16); in nv50_instobj_wr32()
77 nv_wr32(priv, 0x700000 + addr, data); in nv50_instobj_wr32()
Dgk20a.c118 nv_wr32(priv, 0x001700, base >> 16); in gk20a_instobj_rd32()
137 nv_wr32(priv, 0x001700, base >> 16); in gk20a_instobj_wr32()
140 nv_wr32(priv, 0x700000 + addr, data); in gk20a_instobj_wr32()
Dnv04.c118 return nv_wr32(object, 0x700000 + addr, data); in nv04_instmem_wr32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dshadowramin.c49 nv_wr32(priv->bios, 0x001700, priv->bar0); in pramin_fini()
104 nv_wr32(bios, 0x001700, addr >> 16); in pramin_init()
Dinit.c195 nv_wr32(init->subdev, reg, val); in init_wr32()
204 nv_wr32(init->subdev, reg, (tmp & ~mask) | val); in init_mask()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dhub.fuc181 call(nv_wr32) // CC_SCRATCH[1] = ctx offset
184 call(nv_wr32)
186 call(nv_wr32) // ENTRY
189 call(nv_wr32) // CTRL
360 nv_wr32(0x400144, $r11)
390 nv_wr32(0x404160, $r15)
402 nv_wr32(0x404160, $r15)
412 nv_wr32(0x404170, $r15)
451 nv_wr32(0x408a14, $r15)
452 nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15)
[all …]
Dgpc.fuc59 */ call(nv_wr32)
67 nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15)
69 nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15)
260 call(nv_wr32)
263 call(nv_wr32)
266 call(nv_wr32)
372 nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET
Dmacros.fuc248 #define nv_wr32(addr,reg) /*
251 */ call(nv_wr32)
Dcom.fuc107 // nv_wr32 - write 32-bit value to nv register
112 nv_wr32:
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
Dg98.c101 nv_wr32(priv, 0x087004, 0x00000040); in g98_sec_intr()
107 nv_wr32(priv, 0x087004, stat); in g98_sec_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dsubdev.h105 nv_wr32(void *obj, u32 addr, u32 data) in nv_wr32() function
116 nv_wr32(obj, addr, (temp & ~mask) | data); in nv_mask()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
Dgk104.c75 nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); in gk104_ce_intr()
Dgm204.c75 nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); in gm204_ce_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
Dxtensa.c38 nv_wr32(xtensa, xtensa->addr + addr, data); in _nvkm_xtensa_wr32()
Dfalcon.c57 nv_wr32(falcon, falcon->addr + addr, data); in _nvkm_falcon_wr32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dbase.c197 nv_wr32(object->engine, addr, data); in nvkm_devobj_wr32()