1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "nv50.h"
25 #include "outpdp.h"
26
27 static inline u32
gf110_sor_soff(struct nvkm_output_dp * outp)28 gf110_sor_soff(struct nvkm_output_dp *outp)
29 {
30 return (ffs(outp->base.info.or) - 1) * 0x800;
31 }
32
33 static inline u32
gf110_sor_loff(struct nvkm_output_dp * outp)34 gf110_sor_loff(struct nvkm_output_dp *outp)
35 {
36 return gf110_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
37 }
38
39 static inline u32
gf110_sor_dp_lane_map(struct nv50_disp_priv * priv,u8 lane)40 gf110_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
41 {
42 static const u8 gf110[] = { 16, 8, 0, 24 };
43 return gf110[lane];
44 }
45
46 static int
gf110_sor_dp_pattern(struct nvkm_output_dp * outp,int pattern)47 gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
48 {
49 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
50 const u32 loff = gf110_sor_loff(outp);
51 nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
52 return 0;
53 }
54
55 int
gf110_sor_dp_lnk_ctl(struct nvkm_output_dp * outp,int nr,int bw,bool ef)56 gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
57 {
58 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
59 const u32 soff = gf110_sor_soff(outp);
60 const u32 loff = gf110_sor_loff(outp);
61 u32 dpctrl = 0x00000000;
62 u32 clksor = 0x00000000;
63
64 clksor |= bw << 18;
65 dpctrl |= ((1 << nr) - 1) << 16;
66 if (ef)
67 dpctrl |= 0x00004000;
68
69 nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor);
70 nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl);
71 return 0;
72 }
73
74 static int
gf110_sor_dp_drv_ctl(struct nvkm_output_dp * outp,int ln,int vs,int pe,int pc)75 gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
76 int ln, int vs, int pe, int pc)
77 {
78 struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
79 struct nvkm_bios *bios = nvkm_bios(priv);
80 const u32 shift = gf110_sor_dp_lane_map(priv, ln);
81 const u32 loff = gf110_sor_loff(outp);
82 u32 addr, data[4];
83 u8 ver, hdr, cnt, len;
84 struct nvbios_dpout info;
85 struct nvbios_dpcfg ocfg;
86
87 addr = nvbios_dpout_match(bios, outp->base.info.hasht,
88 outp->base.info.hashm,
89 &ver, &hdr, &cnt, &len, &info);
90 if (!addr)
91 return -ENODEV;
92
93 addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
94 &ver, &hdr, &cnt, &len, &ocfg);
95 if (!addr)
96 return -EINVAL;
97
98 data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
99 data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
100 data[2] = nv_rd32(priv, 0x61c130 + loff);
101 if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0)
102 data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8);
103 nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift));
104 nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift));
105 nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8));
106 data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift);
107 nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift));
108 return 0;
109 }
110
111 struct nvkm_output_dp_impl
112 gf110_sor_dp_impl = {
113 .base.base.handle = DCB_OUTPUT_DP,
114 .base.base.ofuncs = &(struct nvkm_ofuncs) {
115 .ctor = _nvkm_output_dp_ctor,
116 .dtor = _nvkm_output_dp_dtor,
117 .init = _nvkm_output_dp_init,
118 .fini = _nvkm_output_dp_fini,
119 },
120 .pattern = gf110_sor_dp_pattern,
121 .lnk_pwr = g94_sor_dp_lnk_pwr,
122 .lnk_ctl = gf110_sor_dp_lnk_ctl,
123 .drv_ctl = gf110_sor_dp_drv_ctl,
124 };
125