1/*
2 * Copyright 2012 Nouveau Community
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Martin Peres <martin.peres@labri.fr>
23 *          Ben Skeggs
24 */
25#include "nv04.h"
26
27static void
28gf100_bus_intr(struct nvkm_subdev *subdev)
29{
30	struct nvkm_bus *pbus = nvkm_bus(subdev);
31	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
32
33	if (stat & 0x0000000e) {
34		u32 addr = nv_rd32(pbus, 0x009084);
35		u32 data = nv_rd32(pbus, 0x009088);
36
37		nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
38			 (addr & 0x00000002) ? "write" : "read", data,
39			 (addr & 0x00fffffc),
40			 (stat & 0x00000002) ? "!ENGINE " : "",
41			 (stat & 0x00000004) ? "IBUS " : "",
42			 (stat & 0x00000008) ? "TIMEOUT " : "");
43
44		nv_wr32(pbus, 0x009084, 0x00000000);
45		nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
46		stat &= ~0x0000000e;
47	}
48
49	if (stat) {
50		nv_error(pbus, "unknown intr 0x%08x\n", stat);
51		nv_mask(pbus, 0x001140, stat, 0x00000000);
52	}
53}
54
55static int
56gf100_bus_init(struct nvkm_object *object)
57{
58	struct nv04_bus_priv *priv = (void *)object;
59	int ret;
60
61	ret = nvkm_bus_init(&priv->base);
62	if (ret)
63		return ret;
64
65	nv_wr32(priv, 0x001100, 0xffffffff);
66	nv_wr32(priv, 0x001140, 0x0000000e);
67	return 0;
68}
69
70struct nvkm_oclass *
71gf100_bus_oclass = &(struct nv04_bus_impl) {
72	.base.handle = NV_SUBDEV(BUS, 0xc0),
73	.base.ofuncs = &(struct nvkm_ofuncs) {
74		.ctor = nv04_bus_ctor,
75		.dtor = _nvkm_bus_dtor,
76		.init = gf100_bus_init,
77		.fini = _nvkm_bus_fini,
78	},
79	.intr = gf100_bus_intr,
80}.base;
81