1/* 2 * Copyright 2009 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 25/* NVIDIA context programs handle a number of other conditions which are 26 * not implemented in our versions. It's not clear why NVIDIA context 27 * programs have this code, nor whether it's strictly necessary for 28 * correct operation. We'll implement additional handling if/when we 29 * discover it's necessary. 30 * 31 * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" 32 * flag is set, this gets saved into the context. 33 * - On context save, the context program for all cards load nsource 34 * into a flag register and check for ILLEGAL_MTHD. If it's set, 35 * opcode 0x60000d is called before resuming normal operation. 36 * - Some context programs check more conditions than the above. NV44 37 * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) 38 * and calls 0x60000d before resuming normal operation. 39 * - At the very beginning of NVIDIA's context programs, flag 9 is checked 40 * and if true 0x800001 is called with count=0, pos=0, the flag is cleared 41 * and then the ctxprog is aborted. It looks like a complicated NOP, 42 * its purpose is unknown. 43 * - In the section of code that loads the per-vs state, NVIDIA check 44 * flag 10. If it's set, they only transfer the small 0x300 byte block 45 * of state + the state for a single vs as opposed to the state for 46 * all vs units. It doesn't seem likely that it'll occur in normal 47 * operation, especially seeing as it appears NVIDIA may have screwed 48 * up the ctxprogs for some cards and have an invalid instruction 49 * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. 50 * - There's a number of places where context offset 0 (where we place 51 * the PRAMIN offset of the context) is loaded into either 0x408000, 52 * 0x408004 or 0x408008. Not sure what's up there either. 53 * - The ctxprogs for some cards save 0x400a00 again during the cleanup 54 * path for auto-loadctx. 55 */ 56 57#define CP_FLAG_CLEAR 0 58#define CP_FLAG_SET 1 59#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) 60#define CP_FLAG_SWAP_DIRECTION_LOAD 0 61#define CP_FLAG_SWAP_DIRECTION_SAVE 1 62#define CP_FLAG_USER_SAVE ((0 * 32) + 5) 63#define CP_FLAG_USER_SAVE_NOT_PENDING 0 64#define CP_FLAG_USER_SAVE_PENDING 1 65#define CP_FLAG_USER_LOAD ((0 * 32) + 6) 66#define CP_FLAG_USER_LOAD_NOT_PENDING 0 67#define CP_FLAG_USER_LOAD_PENDING 1 68#define CP_FLAG_STATUS ((3 * 32) + 0) 69#define CP_FLAG_STATUS_IDLE 0 70#define CP_FLAG_STATUS_BUSY 1 71#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) 72#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 73#define CP_FLAG_AUTO_SAVE_PENDING 1 74#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) 75#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 76#define CP_FLAG_AUTO_LOAD_PENDING 1 77#define CP_FLAG_UNK54 ((3 * 32) + 6) 78#define CP_FLAG_UNK54_CLEAR 0 79#define CP_FLAG_UNK54_SET 1 80#define CP_FLAG_ALWAYS ((3 * 32) + 8) 81#define CP_FLAG_ALWAYS_FALSE 0 82#define CP_FLAG_ALWAYS_TRUE 1 83#define CP_FLAG_UNK57 ((3 * 32) + 9) 84#define CP_FLAG_UNK57_CLEAR 0 85#define CP_FLAG_UNK57_SET 1 86 87#define CP_CTX 0x00100000 88#define CP_CTX_COUNT 0x000fc000 89#define CP_CTX_COUNT_SHIFT 14 90#define CP_CTX_REG 0x00003fff 91#define CP_LOAD_SR 0x00200000 92#define CP_LOAD_SR_VALUE 0x000fffff 93#define CP_BRA 0x00400000 94#define CP_BRA_IP 0x0000ff00 95#define CP_BRA_IP_SHIFT 8 96#define CP_BRA_IF_CLEAR 0x00000080 97#define CP_BRA_FLAG 0x0000007f 98#define CP_WAIT 0x00500000 99#define CP_WAIT_SET 0x00000080 100#define CP_WAIT_FLAG 0x0000007f 101#define CP_SET 0x00700000 102#define CP_SET_1 0x00000080 103#define CP_SET_FLAG 0x0000007f 104#define CP_NEXT_TO_SWAP 0x00600007 105#define CP_NEXT_TO_CURRENT 0x00600009 106#define CP_SET_CONTEXT_POINTER 0x0060000a 107#define CP_END 0x0060000e 108#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ 109#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ 110#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ 111 112#include "ctxnv40.h" 113#include "nv40.h" 114#include <core/device.h> 115 116/* TODO: 117 * - get vs count from 0x1540 118 */ 119 120static int 121nv40_gr_vs_count(struct nvkm_device *device) 122{ 123 124 switch (device->chipset) { 125 case 0x47: 126 case 0x49: 127 case 0x4b: 128 return 8; 129 case 0x40: 130 return 6; 131 case 0x41: 132 case 0x42: 133 return 5; 134 case 0x43: 135 case 0x44: 136 case 0x46: 137 case 0x4a: 138 return 3; 139 case 0x4c: 140 case 0x4e: 141 case 0x67: 142 default: 143 return 1; 144 } 145} 146 147 148enum cp_label { 149 cp_check_load = 1, 150 cp_setup_auto_load, 151 cp_setup_load, 152 cp_setup_save, 153 cp_swap_state, 154 cp_swap_state3d_3_is_save, 155 cp_prepare_exit, 156 cp_exit, 157}; 158 159static void 160nv40_gr_construct_general(struct nvkm_grctx *ctx) 161{ 162 struct nvkm_device *device = ctx->device; 163 int i; 164 165 cp_ctx(ctx, 0x4000a4, 1); 166 gr_def(ctx, 0x4000a4, 0x00000008); 167 cp_ctx(ctx, 0x400144, 58); 168 gr_def(ctx, 0x400144, 0x00000001); 169 cp_ctx(ctx, 0x400314, 1); 170 gr_def(ctx, 0x400314, 0x00000000); 171 cp_ctx(ctx, 0x400400, 10); 172 cp_ctx(ctx, 0x400480, 10); 173 cp_ctx(ctx, 0x400500, 19); 174 gr_def(ctx, 0x400514, 0x00040000); 175 gr_def(ctx, 0x400524, 0x55555555); 176 gr_def(ctx, 0x400528, 0x55555555); 177 gr_def(ctx, 0x40052c, 0x55555555); 178 gr_def(ctx, 0x400530, 0x55555555); 179 cp_ctx(ctx, 0x400560, 6); 180 gr_def(ctx, 0x400568, 0x0000ffff); 181 gr_def(ctx, 0x40056c, 0x0000ffff); 182 cp_ctx(ctx, 0x40057c, 5); 183 cp_ctx(ctx, 0x400710, 3); 184 gr_def(ctx, 0x400710, 0x20010001); 185 gr_def(ctx, 0x400714, 0x0f73ef00); 186 cp_ctx(ctx, 0x400724, 1); 187 gr_def(ctx, 0x400724, 0x02008821); 188 cp_ctx(ctx, 0x400770, 3); 189 if (device->chipset == 0x40) { 190 cp_ctx(ctx, 0x400814, 4); 191 cp_ctx(ctx, 0x400828, 5); 192 cp_ctx(ctx, 0x400840, 5); 193 gr_def(ctx, 0x400850, 0x00000040); 194 cp_ctx(ctx, 0x400858, 4); 195 gr_def(ctx, 0x400858, 0x00000040); 196 gr_def(ctx, 0x40085c, 0x00000040); 197 gr_def(ctx, 0x400864, 0x80000000); 198 cp_ctx(ctx, 0x40086c, 9); 199 gr_def(ctx, 0x40086c, 0x80000000); 200 gr_def(ctx, 0x400870, 0x80000000); 201 gr_def(ctx, 0x400874, 0x80000000); 202 gr_def(ctx, 0x400878, 0x80000000); 203 gr_def(ctx, 0x400888, 0x00000040); 204 gr_def(ctx, 0x40088c, 0x80000000); 205 cp_ctx(ctx, 0x4009c0, 8); 206 gr_def(ctx, 0x4009cc, 0x80000000); 207 gr_def(ctx, 0x4009dc, 0x80000000); 208 } else { 209 cp_ctx(ctx, 0x400840, 20); 210 if (nv44_gr_class(ctx->device)) { 211 for (i = 0; i < 8; i++) 212 gr_def(ctx, 0x400860 + (i * 4), 0x00000001); 213 } 214 gr_def(ctx, 0x400880, 0x00000040); 215 gr_def(ctx, 0x400884, 0x00000040); 216 gr_def(ctx, 0x400888, 0x00000040); 217 cp_ctx(ctx, 0x400894, 11); 218 gr_def(ctx, 0x400894, 0x00000040); 219 if (!nv44_gr_class(ctx->device)) { 220 for (i = 0; i < 8; i++) 221 gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); 222 } 223 cp_ctx(ctx, 0x4008e0, 2); 224 cp_ctx(ctx, 0x4008f8, 2); 225 if (device->chipset == 0x4c || 226 (device->chipset & 0xf0) == 0x60) 227 cp_ctx(ctx, 0x4009f8, 1); 228 } 229 cp_ctx(ctx, 0x400a00, 73); 230 gr_def(ctx, 0x400b0c, 0x0b0b0b0c); 231 cp_ctx(ctx, 0x401000, 4); 232 cp_ctx(ctx, 0x405004, 1); 233 switch (device->chipset) { 234 case 0x47: 235 case 0x49: 236 case 0x4b: 237 cp_ctx(ctx, 0x403448, 1); 238 gr_def(ctx, 0x403448, 0x00001010); 239 break; 240 default: 241 cp_ctx(ctx, 0x403440, 1); 242 switch (device->chipset) { 243 case 0x40: 244 gr_def(ctx, 0x403440, 0x00000010); 245 break; 246 case 0x44: 247 case 0x46: 248 case 0x4a: 249 gr_def(ctx, 0x403440, 0x00003010); 250 break; 251 case 0x41: 252 case 0x42: 253 case 0x43: 254 case 0x4c: 255 case 0x4e: 256 case 0x67: 257 default: 258 gr_def(ctx, 0x403440, 0x00001010); 259 break; 260 } 261 break; 262 } 263} 264 265static void 266nv40_gr_construct_state3d(struct nvkm_grctx *ctx) 267{ 268 struct nvkm_device *device = ctx->device; 269 int i; 270 271 if (device->chipset == 0x40) { 272 cp_ctx(ctx, 0x401880, 51); 273 gr_def(ctx, 0x401940, 0x00000100); 274 } else 275 if (device->chipset == 0x46 || device->chipset == 0x47 || 276 device->chipset == 0x49 || device->chipset == 0x4b) { 277 cp_ctx(ctx, 0x401880, 32); 278 for (i = 0; i < 16; i++) 279 gr_def(ctx, 0x401880 + (i * 4), 0x00000111); 280 if (device->chipset == 0x46) 281 cp_ctx(ctx, 0x401900, 16); 282 cp_ctx(ctx, 0x401940, 3); 283 } 284 cp_ctx(ctx, 0x40194c, 18); 285 gr_def(ctx, 0x401954, 0x00000111); 286 gr_def(ctx, 0x401958, 0x00080060); 287 gr_def(ctx, 0x401974, 0x00000080); 288 gr_def(ctx, 0x401978, 0xffff0000); 289 gr_def(ctx, 0x40197c, 0x00000001); 290 gr_def(ctx, 0x401990, 0x46400000); 291 if (device->chipset == 0x40) { 292 cp_ctx(ctx, 0x4019a0, 2); 293 cp_ctx(ctx, 0x4019ac, 5); 294 } else { 295 cp_ctx(ctx, 0x4019a0, 1); 296 cp_ctx(ctx, 0x4019b4, 3); 297 } 298 gr_def(ctx, 0x4019bc, 0xffff0000); 299 switch (device->chipset) { 300 case 0x46: 301 case 0x47: 302 case 0x49: 303 case 0x4b: 304 cp_ctx(ctx, 0x4019c0, 18); 305 for (i = 0; i < 16; i++) 306 gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); 307 break; 308 } 309 cp_ctx(ctx, 0x401a08, 8); 310 gr_def(ctx, 0x401a10, 0x0fff0000); 311 gr_def(ctx, 0x401a14, 0x0fff0000); 312 gr_def(ctx, 0x401a1c, 0x00011100); 313 cp_ctx(ctx, 0x401a2c, 4); 314 cp_ctx(ctx, 0x401a44, 26); 315 for (i = 0; i < 16; i++) 316 gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); 317 gr_def(ctx, 0x401a8c, 0x4b7fffff); 318 if (device->chipset == 0x40) { 319 cp_ctx(ctx, 0x401ab8, 3); 320 } else { 321 cp_ctx(ctx, 0x401ab8, 1); 322 cp_ctx(ctx, 0x401ac0, 1); 323 } 324 cp_ctx(ctx, 0x401ad0, 8); 325 gr_def(ctx, 0x401ad0, 0x30201000); 326 gr_def(ctx, 0x401ad4, 0x70605040); 327 gr_def(ctx, 0x401ad8, 0xb8a89888); 328 gr_def(ctx, 0x401adc, 0xf8e8d8c8); 329 cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); 330 gr_def(ctx, 0x401b10, 0x40100000); 331 cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); 332 gr_def(ctx, 0x401b28, device->chipset == 0x40 ? 333 0x00000004 : 0x00000000); 334 cp_ctx(ctx, 0x401b30, 25); 335 gr_def(ctx, 0x401b34, 0x0000ffff); 336 gr_def(ctx, 0x401b68, 0x435185d6); 337 gr_def(ctx, 0x401b6c, 0x2155b699); 338 gr_def(ctx, 0x401b70, 0xfedcba98); 339 gr_def(ctx, 0x401b74, 0x00000098); 340 gr_def(ctx, 0x401b84, 0xffffffff); 341 gr_def(ctx, 0x401b88, 0x00ff7000); 342 gr_def(ctx, 0x401b8c, 0x0000ffff); 343 if (device->chipset != 0x44 && device->chipset != 0x4a && 344 device->chipset != 0x4e) 345 cp_ctx(ctx, 0x401b94, 1); 346 cp_ctx(ctx, 0x401b98, 8); 347 gr_def(ctx, 0x401b9c, 0x00ff0000); 348 cp_ctx(ctx, 0x401bc0, 9); 349 gr_def(ctx, 0x401be0, 0x00ffff00); 350 cp_ctx(ctx, 0x401c00, 192); 351 for (i = 0; i < 16; i++) { /* fragment texture units */ 352 gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); 353 gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); 354 gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); 355 gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); 356 gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); 357 gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); 358 } 359 for (i = 0; i < 4; i++) { /* vertex texture units */ 360 gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); 361 gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); 362 gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); 363 gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); 364 } 365 cp_ctx(ctx, 0x400f5c, 3); 366 gr_def(ctx, 0x400f5c, 0x00000002); 367 cp_ctx(ctx, 0x400f84, 1); 368} 369 370static void 371nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx) 372{ 373 struct nvkm_device *device = ctx->device; 374 int i; 375 376 cp_ctx(ctx, 0x402000, 1); 377 cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); 378 switch (device->chipset) { 379 case 0x40: 380 gr_def(ctx, 0x402404, 0x00000001); 381 break; 382 case 0x4c: 383 case 0x4e: 384 case 0x67: 385 gr_def(ctx, 0x402404, 0x00000020); 386 break; 387 case 0x46: 388 case 0x49: 389 case 0x4b: 390 gr_def(ctx, 0x402404, 0x00000421); 391 break; 392 default: 393 gr_def(ctx, 0x402404, 0x00000021); 394 } 395 if (device->chipset != 0x40) 396 gr_def(ctx, 0x402408, 0x030c30c3); 397 switch (device->chipset) { 398 case 0x44: 399 case 0x46: 400 case 0x4a: 401 case 0x4c: 402 case 0x4e: 403 case 0x67: 404 cp_ctx(ctx, 0x402440, 1); 405 gr_def(ctx, 0x402440, 0x00011001); 406 break; 407 default: 408 break; 409 } 410 cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); 411 gr_def(ctx, 0x402488, 0x3e020200); 412 gr_def(ctx, 0x40248c, 0x00ffffff); 413 switch (device->chipset) { 414 case 0x40: 415 gr_def(ctx, 0x402490, 0x60103f00); 416 break; 417 case 0x47: 418 gr_def(ctx, 0x402490, 0x40103f00); 419 break; 420 case 0x41: 421 case 0x42: 422 case 0x49: 423 case 0x4b: 424 gr_def(ctx, 0x402490, 0x20103f00); 425 break; 426 default: 427 gr_def(ctx, 0x402490, 0x0c103f00); 428 break; 429 } 430 gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? 431 0x00020000 : 0x00040000); 432 cp_ctx(ctx, 0x402500, 31); 433 gr_def(ctx, 0x402530, 0x00008100); 434 if (device->chipset == 0x40) 435 cp_ctx(ctx, 0x40257c, 6); 436 cp_ctx(ctx, 0x402594, 16); 437 cp_ctx(ctx, 0x402800, 17); 438 gr_def(ctx, 0x402800, 0x00000001); 439 switch (device->chipset) { 440 case 0x47: 441 case 0x49: 442 case 0x4b: 443 cp_ctx(ctx, 0x402864, 1); 444 gr_def(ctx, 0x402864, 0x00001001); 445 cp_ctx(ctx, 0x402870, 3); 446 gr_def(ctx, 0x402878, 0x00000003); 447 if (device->chipset != 0x47) { /* belong at end!! */ 448 cp_ctx(ctx, 0x402900, 1); 449 cp_ctx(ctx, 0x402940, 1); 450 cp_ctx(ctx, 0x402980, 1); 451 cp_ctx(ctx, 0x4029c0, 1); 452 cp_ctx(ctx, 0x402a00, 1); 453 cp_ctx(ctx, 0x402a40, 1); 454 cp_ctx(ctx, 0x402a80, 1); 455 cp_ctx(ctx, 0x402ac0, 1); 456 } 457 break; 458 case 0x40: 459 cp_ctx(ctx, 0x402844, 1); 460 gr_def(ctx, 0x402844, 0x00000001); 461 cp_ctx(ctx, 0x402850, 1); 462 break; 463 default: 464 cp_ctx(ctx, 0x402844, 1); 465 gr_def(ctx, 0x402844, 0x00001001); 466 cp_ctx(ctx, 0x402850, 2); 467 gr_def(ctx, 0x402854, 0x00000003); 468 break; 469 } 470 471 cp_ctx(ctx, 0x402c00, 4); 472 gr_def(ctx, 0x402c00, device->chipset == 0x40 ? 473 0x80800001 : 0x00888001); 474 switch (device->chipset) { 475 case 0x47: 476 case 0x49: 477 case 0x4b: 478 cp_ctx(ctx, 0x402c20, 40); 479 for (i = 0; i < 32; i++) 480 gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); 481 cp_ctx(ctx, 0x4030b8, 13); 482 gr_def(ctx, 0x4030dc, 0x00000005); 483 gr_def(ctx, 0x4030e8, 0x0000ffff); 484 break; 485 default: 486 cp_ctx(ctx, 0x402c10, 4); 487 if (device->chipset == 0x40) 488 cp_ctx(ctx, 0x402c20, 36); 489 else 490 if (device->chipset <= 0x42) 491 cp_ctx(ctx, 0x402c20, 24); 492 else 493 if (device->chipset <= 0x4a) 494 cp_ctx(ctx, 0x402c20, 16); 495 else 496 cp_ctx(ctx, 0x402c20, 8); 497 cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); 498 gr_def(ctx, 0x402cd4, 0x00000005); 499 if (device->chipset != 0x40) 500 gr_def(ctx, 0x402ce0, 0x0000ffff); 501 break; 502 } 503 504 cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); 505 cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); 506 cp_ctx(ctx, 0x403420, nv40_gr_vs_count(ctx->device)); 507 for (i = 0; i < nv40_gr_vs_count(ctx->device); i++) 508 gr_def(ctx, 0x403420 + (i * 4), 0x00005555); 509 510 if (device->chipset != 0x40) { 511 cp_ctx(ctx, 0x403600, 1); 512 gr_def(ctx, 0x403600, 0x00000001); 513 } 514 cp_ctx(ctx, 0x403800, 1); 515 516 cp_ctx(ctx, 0x403c18, 1); 517 gr_def(ctx, 0x403c18, 0x00000001); 518 switch (device->chipset) { 519 case 0x46: 520 case 0x47: 521 case 0x49: 522 case 0x4b: 523 cp_ctx(ctx, 0x405018, 1); 524 gr_def(ctx, 0x405018, 0x08e00001); 525 cp_ctx(ctx, 0x405c24, 1); 526 gr_def(ctx, 0x405c24, 0x000e3000); 527 break; 528 } 529 if (device->chipset != 0x4e) 530 cp_ctx(ctx, 0x405800, 11); 531 cp_ctx(ctx, 0x407000, 1); 532} 533 534static void 535nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx) 536{ 537 int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684; 538 539 cp_out (ctx, 0x300000); 540 cp_lsr (ctx, len - 4); 541 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); 542 cp_lsr (ctx, len); 543 cp_name(ctx, cp_swap_state3d_3_is_save); 544 cp_out (ctx, 0x800001); 545 546 ctx->ctxvals_pos += len; 547} 548 549static void 550nv40_gr_construct_shader(struct nvkm_grctx *ctx) 551{ 552 struct nvkm_device *device = ctx->device; 553 struct nvkm_gpuobj *obj = ctx->data; 554 int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; 555 int offset, i; 556 557 vs_nr = nv40_gr_vs_count(ctx->device); 558 vs_nr_b0 = 363; 559 vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; 560 if (device->chipset == 0x40) { 561 b0_offset = 0x2200/4; /* 33a0 */ 562 b1_offset = 0x55a0/4; /* 1500 */ 563 vs_len = 0x6aa0/4; 564 } else 565 if (device->chipset == 0x41 || device->chipset == 0x42) { 566 b0_offset = 0x2200/4; /* 2200 */ 567 b1_offset = 0x4400/4; /* 0b00 */ 568 vs_len = 0x4f00/4; 569 } else { 570 b0_offset = 0x1d40/4; /* 2200 */ 571 b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ 572 vs_len = nv44_gr_class(device) ? 0x4980/4 : 0x4a40/4; 573 } 574 575 cp_lsr(ctx, vs_len * vs_nr + 0x300/4); 576 cp_out(ctx, nv44_gr_class(device) ? 0x800029 : 0x800041); 577 578 offset = ctx->ctxvals_pos; 579 ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); 580 581 if (ctx->mode != NVKM_GRCTX_VALS) 582 return; 583 584 offset += 0x0280/4; 585 for (i = 0; i < 16; i++, offset += 2) 586 nv_wo32(obj, offset * 4, 0x3f800000); 587 588 for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { 589 for (i = 0; i < vs_nr_b0 * 6; i += 6) 590 nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); 591 for (i = 0; i < vs_nr_b1 * 4; i += 4) 592 nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); 593 } 594} 595 596static void 597nv40_grctx_generate(struct nvkm_grctx *ctx) 598{ 599 /* decide whether we're loading/unloading the context */ 600 cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); 601 cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); 602 603 cp_name(ctx, cp_check_load); 604 cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); 605 cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); 606 cp_bra (ctx, ALWAYS, TRUE, cp_exit); 607 608 /* setup for context load */ 609 cp_name(ctx, cp_setup_auto_load); 610 cp_wait(ctx, STATUS, IDLE); 611 cp_out (ctx, CP_NEXT_TO_SWAP); 612 cp_name(ctx, cp_setup_load); 613 cp_wait(ctx, STATUS, IDLE); 614 cp_set (ctx, SWAP_DIRECTION, LOAD); 615 cp_out (ctx, 0x00910880); /* ?? */ 616 cp_out (ctx, 0x00901ffe); /* ?? */ 617 cp_out (ctx, 0x01940000); /* ?? */ 618 cp_lsr (ctx, 0x20); 619 cp_out (ctx, 0x0060000b); /* ?? */ 620 cp_wait(ctx, UNK57, CLEAR); 621 cp_out (ctx, 0x0060000c); /* ?? */ 622 cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); 623 624 /* setup for context save */ 625 cp_name(ctx, cp_setup_save); 626 cp_set (ctx, SWAP_DIRECTION, SAVE); 627 628 /* general PGRAPH state */ 629 cp_name(ctx, cp_swap_state); 630 cp_pos (ctx, 0x00020/4); 631 nv40_gr_construct_general(ctx); 632 cp_wait(ctx, STATUS, IDLE); 633 634 /* 3D state, block 1 */ 635 cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); 636 nv40_gr_construct_state3d(ctx); 637 cp_wait(ctx, STATUS, IDLE); 638 639 /* 3D state, block 2 */ 640 nv40_gr_construct_state3d_2(ctx); 641 642 /* Some other block of "random" state */ 643 nv40_gr_construct_state3d_3(ctx); 644 645 /* Per-vertex shader state */ 646 cp_pos (ctx, ctx->ctxvals_pos); 647 nv40_gr_construct_shader(ctx); 648 649 /* pre-exit state updates */ 650 cp_name(ctx, cp_prepare_exit); 651 cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); 652 cp_bra (ctx, USER_SAVE, PENDING, cp_exit); 653 cp_out (ctx, CP_NEXT_TO_CURRENT); 654 655 cp_name(ctx, cp_exit); 656 cp_set (ctx, USER_SAVE, NOT_PENDING); 657 cp_set (ctx, USER_LOAD, NOT_PENDING); 658 cp_out (ctx, CP_END); 659} 660 661void 662nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem) 663{ 664 nv40_grctx_generate(&(struct nvkm_grctx) { 665 .device = device, 666 .mode = NVKM_GRCTX_VALS, 667 .data = mem, 668 }); 669} 670 671int 672nv40_grctx_init(struct nvkm_device *device, u32 *size) 673{ 674 u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; 675 struct nvkm_grctx ctx = { 676 .device = device, 677 .mode = NVKM_GRCTX_PROG, 678 .data = ctxprog, 679 .ctxprog_max = 256, 680 }; 681 682 if (!ctxprog) 683 return -ENOMEM; 684 685 nv40_grctx_generate(&ctx); 686 687 nv_wr32(device, 0x400324, 0); 688 for (i = 0; i < ctx.ctxprog_len; i++) 689 nv_wr32(device, 0x400328, ctxprog[i]); 690 *size = ctx.ctxvals_pos * 4; 691 692 kfree(ctxprog); 693 return 0; 694} 695