Searched refs:mcr (Results 1 - 200 of 228) sorted by relevance

12

/linux-4.1.27/arch/arm/mm/
H A D	proc-arm946.S	50 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 111 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 187 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 192 mcr p15, 0, r0, c7, c10, 4 @ drain WB 208 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 213 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 214 mcr p15, 0, r0, c7, c10, 4 @ drain WB 237 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 241 mcr p15, 0, r0, c7, c10, 4 @ drain WB 257 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 262 mcr p15, 0, r0, c7, c10, 4 @ drain WB 279 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 281 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 286 mcr p15, 0, r0, c7, c10, 4 @ drain WB 321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 326 mcr p15, 0, r0, c7, c10, 4 @ drain WB 332 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 333 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache 334 mcr p15, 0, r0, c7, c10, 4 @ drain WB 336 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7 337 mcr p15, 0, r0, c6, c4, 0 338 mcr p15, 0, r0, c6, c5, 0 339 mcr p15, 0, r0, c6, c6, 0 340 mcr p15, 0, r0, c6, c7, 0 343 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default 348 mcr p15, 0, r3, c6, c1, 0 353 mcr p15, 0, r3, c6, c2, 0 356 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable 357 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable 363 mcr p15, 0, r0, c3, c0, 0 376 mcr p15, 0, r0, c5, c0, 2 @ set data access permission 377 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
H A D	proc-arm940.S	43 mcr p15, 0, r0, c1, c0, 0 @ disable caches 54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 56 mcr p15, 0, ip, c7, c10, 4 @ drain WB 60 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 116 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 166 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 172 mcr p15, 0, r0, c7, c10, 4 @ drain WB 188 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry 193 mcr p15, 0, ip, c7, c10, 4 @ drain WB 211 2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry 217 mcr p15, 0, ip, c7, c10, 4 @ drain WB 235 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry 237 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry 243 mcr p15, 0, ip, c7, c10, 4 @ drain WB 279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 280 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache 281 mcr p15, 0, r0, c7, c10, 4 @ drain WB 283 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7 284 mcr p15, 0, r0, c6, c4, 0 285 mcr p15, 0, r0, c6, c5, 0 286 mcr p15, 0, r0, c6, c6, 0 287 mcr p15, 0, r0, c6, c7, 0 289 mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7 290 mcr p15, 0, r0, c6, c4, 1 291 mcr p15, 0, r0, c6, c5, 1 292 mcr p15, 0, r0, c6, c6, 1 293 mcr p15, 0, r0, c6, c7, 1 296 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default 297 mcr p15, 0, r0, c6, c0, 1 302 mcr p15, 0, r3, c6, c1, 0 @ set area 1, RAM 303 mcr p15, 0, r3, c6, c1, 1 308 mcr p15, 0, r3, c6, c2, 0 @ set area 2, ROM/FLASH 309 mcr p15, 0, r3, c6, c2, 1 312 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable 313 mcr p15, 0, r0, c2, c0, 1 319 mcr p15, 0, r0, c3, c0, 0 323 mcr p15, 0, r0, c5, c0, 0 @ all read/write access 324 mcr p15, 0, r0, c5, c0, 1
H A D	proc-sa110.S	40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 52 mcr p15, 0, r0, c1, c0, 0 @ disable caches 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching 101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned 105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching 120 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 140 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 157 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 158 mcr p15, 0, r0, c7, c10, 4 @ drain WB 165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 166 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
H A D	proc-sa1100.S	44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt 115 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching 130 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 151 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 169 mcr p15, 0, r0, c7, c10, 4 @ drain WB 188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs 189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache 190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 191 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB 193 mcr p15, 0, r4, c3, c0, 0 @ domain ID 194 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr 195 mcr p15, 0, r5, c13, c0, 0 @ PID 204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 205 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A D	proc-mohawk.S	57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 76 mcr p15, 0, ip, c7, c10, 4 @ drain WB 77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 190 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 195 mcr p15, 0, r0, c7, c10, 4 @ drain WB 210 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 216 mcr p15, 0, r0, c7, c10, 4 @ drain WB 238 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 242 mcr p15, 0, r0, c7, c10, 4 @ drain WB 257 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 261 mcr p15, 0, r0, c7, c10, 4 @ drain WB 275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 279 mcr p15, 0, r0, c7, c10, 4 @ drain WB 313 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 317 mcr p15, 0, r0, c7, c10, 4 @ drain WB 330 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 331 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 332 mcr p15, 0, ip, c7, c10, 4 @ drain WB 334 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 335 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 347 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 348 mcr p15, 0, r0, c7, c10, 4 @ drain WB 370 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 371 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer 372 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer 373 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 374 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. 375 mcr p15, 0, r5, c15, c1, 0 @ CP access reg 376 mcr p15, 0, r6, c13, c0, 0 @ PID 377 mcr p15, 0, r7, c3, c0, 0 @ domain ID 379 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr 380 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg 389 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches 390 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs 393 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 396 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
H A D	proc-fa526.S	44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 92 mcr p15, 0, r0, c7, c10, 4 @ drain WB 109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 115 mcr p15, 0, ip, c7, c10, 4 @ data write barrier 116 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush 117 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB 132 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 134 mcr p15, 0, r0, c7, c10, 4 @ drain WB 142 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 145 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 147 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM 150 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR 153 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All 154 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 155 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 158 mcr p15, 0, r0, c3, c0 @ load domain access register
H A D	proc-arm926.S	67 mcr p15, 0, r0, c1, c0, 0 @ disable caches 83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 84 mcr p15, 0, ip, c7, c10, 4 @ drain WB 86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 110 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 112 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 183 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 218 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 223 mcr p15, 0, r0, c7, c10, 4 @ drain WB 238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 243 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 244 mcr p15, 0, r0, c7, c10, 4 @ drain WB 268 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 272 mcr p15, 0, r0, c7, c10, 4 @ drain WB 288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 293 mcr p15, 0, r0, c7, c10, 4 @ drain WB 308 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 310 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 315 mcr p15, 0, r0, c7, c10, 4 @ drain WB 350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 355 mcr p15, 0, r0, c7, c10, 4 @ drain WB 372 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 378 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 379 mcr p15, 0, ip, c7, c10, 4 @ drain WB 380 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 381 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 396 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 398 mcr p15, 0, r0, c7, c10, 4 @ drain WB 417 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 418 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 420 mcr p15, 0, r4, c13, c0, 0 @ PID 421 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 422 mcr p15, 0, r1, c2, c0, 0 @ TTB address 431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 432 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 434 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 440 mcr p15, 7, r0, c15, c0, 0
H A D	proc-arm1020.S	83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 159 mcr p15, 0, ip, c7, c10, 4 @ drain WB 189 mcr p15, 0, ip, c7, c10, 4 190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 191 mcr p15, 0, ip, c7, c10, 4 @ drain WB 229 mcr p15, 0, ip, c7, c10, 4 232 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 233 mcr p15, 0, ip, c7, c10, 4 @ drain WB 236 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 241 mcr p15, 0, ip, c7, c10, 4 @ drain WB 258 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 259 mcr p15, 0, ip, c7, c10, 4 @ drain WB 264 mcr p15, 0, ip, c7, c10, 4 @ drain WB 292 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 297 mcr p15, 0, ip, c7, c10, 4 @ drain WB 314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 315 mcr p15, 0, ip, c7, c10, 4 @ drain WB 320 mcr p15, 0, ip, c7, c10, 4 @ drain WB 335 mcr p15, 0, ip, c7, c10, 4 336 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 337 mcr p15, 0, ip, c7, c10, 4 @ drain WB 342 mcr p15, 0, ip, c7, c10, 4 @ drain WB 379 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 380 mcr p15, 0, ip, c7, c10, 4 @ drain WB 400 mcr p15, 0, r3, c7, c10, 4 405 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 407 mcr p15, 0, ip, c7, c10, 4 418 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 420 mcr p15, 0, r1, c7, c10, 4 @ drain WB 421 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 422 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 437 mcr p15, 0, r0, c7, c10, 4 438 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 440 mcr p15, 0, r0, c7, c10, 4 @ drain WB 447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A D	copypage-feroceon.c	33 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 37 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 41 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 45 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 49 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 53 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 57 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 61 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 64 mcr p15, 0, ip, c7, c10, 4 @ drain WB\n\ feroceon_copy_user_page() 98 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_clear_user_highpage() 101 mcr p15, 0, r1, c7, c10, 4 @ drain WB" feroceon_clear_user_highpage()
H A D	proc-arm925.S	98 mcr p15, 0, r0, c1, c0, 0 @ disable caches 123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 131 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 145 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 147 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 220 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 255 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 260 mcr p15, 0, r0, c7, c10, 4 @ drain WB 275 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 280 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 281 mcr p15, 0, r0, c7, c10, 4 @ drain WB 305 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 309 mcr p15, 0, r0, c7, c10, 4 @ drain WB 325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 330 mcr p15, 0, r0, c7, c10, 4 @ drain WB 345 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 347 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 352 mcr p15, 0, r0, c7, c10, 4 @ drain WB 387 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 392 mcr p15, 0, r0, c7, c10, 4 @ drain WB 409 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 413 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 417 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 418 mcr p15, 0, ip, c7, c10, 4 @ drain WB 419 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 435 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 437 mcr p15, 0, r0, c7, c10, 4 @ drain WB 447 mcr p15, 0, r0, c15, c1, 0 @ write TI config register 450 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 451 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 453 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 458 mcr p15, 7, r0, c15, c0, 0
H A D	cache-v6.S	43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 137 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 180 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 182 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line 189 mcr p15, 0, r0, c7, c10, 4 229 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line 231 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line 241 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 256 mcr p15, 0, r0, c7, c10, 1 @ clean D line 258 mcr p15, 0, r0, c7, c11, 1 @ clean unified line 264 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 280 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 282 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line 292 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
H A D	proc-v6.S	45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 64 mcr p15, 0, r1, c7, c5, 4 @ ISB 78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 106 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 114 mcr p15, 0, r1, c13, c0, 1 @ set context ID 156 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 158 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 159 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 164 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 167 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0 168 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1 169 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 171 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register 172 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control 173 mcr p15, 0, ip, c7, c5, 4 @ ISB 203 ALT_SMP(mcr p15, 0, r0, c1, c0, 1) 208 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 210 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 213 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 218 mcr p15, 0, r8, c2, c0, 1 @ load TTB1 220 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
H A D	proc-arm740.S	44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 58 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 68 mcr p15, 0, r0, c6, c3 @ disable area 3~7 69 mcr p15, 0, r0, c6, c4 70 mcr p15, 0, r0, c6, c5 71 mcr p15, 0, r0, c6, c6 72 mcr p15, 0, r0, c6, c7 75 mcr p15, 0, r0, c6, c0 @ set area 0, default 85 mcr p15, 0, r0, c6, c1 @ set area 1, RAM 98 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH 101 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable 107 mcr p15, 0, r0, c3, c0 111 mcr p15, 0, r0, c5, c0 @ all read/write access
H A D	proc-arm1022.S	74 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 226 mcr p15, 0, ip, c7, c10, 4 @ drain WB 243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 248 mcr p15, 0, ip, c7, c10, 4 @ drain WB 272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 277 mcr p15, 0, ip, c7, c10, 4 @ drain WB 294 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 299 mcr p15, 0, ip, c7, c10, 4 @ drain WB 314 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 319 mcr p15, 0, ip, c7, c10, 4 @ drain WB 356 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 378 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 386 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 388 mcr p15, 0, r1, c7, c10, 4 @ drain WB 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 390 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 405 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 414 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 416 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A D	proc-arm1026.S	74 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 212 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 220 mcr p15, 0, ip, c7, c10, 4 @ drain WB 237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 242 mcr p15, 0, ip, c7, c10, 4 @ drain WB 266 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 271 mcr p15, 0, ip, c7, c10, 4 @ drain WB 288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 293 mcr p15, 0, ip, c7, c10, 4 @ drain WB 308 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 313 mcr p15, 0, ip, c7, c10, 4 @ drain WB 350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 375 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 377 mcr p15, 0, r1, c7, c10, 4 @ drain WB 378 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 379 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 394 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 406 mcr p15, 0, r4, c2, c0 @ load page table pointer 410 mcr p15, 7, r0, c15, c0, 0
H A D	tlb-v6.S	40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier 71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA 86 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier 87 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
H A D	proc-arm920.S	75 mcr p15, 0, r0, c1, c0, 0 @ disable caches 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 207 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 212 mcr p15, 0, r0, c7, c10, 4 @ drain WB 227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 233 mcr p15, 0, r0, c7, c10, 4 @ drain WB 255 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 259 mcr p15, 0, r0, c7, c10, 4 @ drain WB 274 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 278 mcr p15, 0, r0, c7, c10, 4 @ drain WB 291 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 295 mcr p15, 0, r0, c7, c10, 4 @ drain WB 331 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 351 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 359 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 365 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 366 mcr p15, 0, ip, c7, c10, 4 @ drain WB 367 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 368 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 383 mcr p15, 0, r0, c7, c10, 4 @ drain WB 402 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 403 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 405 mcr p15, 0, r4, c13, c0, 0 @ PID 406 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 407 mcr p15, 0, r1, c2, c0, 0 @ TTB address 416 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 417 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 419 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A D	proc-feroceon.S	81 mcr p15, 1, r0, c15, c9, 0 @ clean L2 82 mcr p15, 0, r0, c7, c10, 4 @ drain WB 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 105 mcr p15, 0, ip, c7, c10, 4 @ drain WB 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 125 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 126 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 190 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 193 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 229 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 234 mcr p15, 0, r0, c7, c10, 4 @ drain WB 250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 256 mcr p15, 0, r0, c7, c10, 4 @ drain WB 265 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start 266 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top 269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 270 mcr p15, 0, r0, c7, c10, 4 @ drain WB 293 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 297 mcr p15, 0, r0, c7, c10, 4 @ drain WB 311 mcr p15, 5, r0, c15, c14, 0 @ D inv range start 312 mcr p15, 5, r1, c15, c14, 1 @ D inv range top 329 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 333 mcr p15, 0, r0, c7, c10, 4 @ drain WB 343 mcr p15, 5, r0, c15, c13, 0 @ D clean range start 344 mcr p15, 5, r1, c15, c13, 1 @ D clean range top 346 mcr p15, 0, r0, c7, c10, 4 @ drain WB 360 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 364 mcr p15, 0, r0, c7, c10, 4 @ drain WB 374 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start 375 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top 377 mcr p15, 0, r0, c7, c10, 4 @ drain WB 452 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 458 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry 463 mcr p15, 0, r0, c7, c10, 4 @ drain WB 491 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 492 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 508 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 511 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry 513 mcr p15, 0, r0, c7, c10, 4 @ drain WB 532 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 533 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 535 mcr p15, 0, r4, c13, c0, 0 @ PID 536 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 537 mcr p15, 0, r1, c2, c0, 0 @ TTB address 546 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 547 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 549 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A D	proc-xscale.S	94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 120 mcr p15, 0, r1, c1, c0, 1 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches 149 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 156 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 159 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 162 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 240 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 241 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 265 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 270 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 271 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 286 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 287 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry 292 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB 293 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 307 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 308 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 313 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 314 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 334 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 338 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 351 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 355 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 368 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 369 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 373 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 457 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 475 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 476 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 477 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 478 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 548 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 549 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 550 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. 551 mcr p15, 0, r5, c15, c1, 0 @ CP access reg 552 mcr p15, 0, r6, c13, c0, 0 @ PID 553 mcr p15, 0, r7, c3, c0, 0 @ domain ID 554 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr 555 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg 563 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 564 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 565 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 568 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
H A D	proc-arm922.S	77 mcr p15, 0, r0, c1, c0, 0 @ disable caches 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c7, c10, 4 @ drain WB 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 209 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 214 mcr p15, 0, r0, c7, c10, 4 @ drain WB 229 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 234 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 235 mcr p15, 0, r0, c7, c10, 4 @ drain WB 257 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 261 mcr p15, 0, r0, c7, c10, 4 @ drain WB 276 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 280 mcr p15, 0, r0, c7, c10, 4 @ drain WB 293 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 297 mcr p15, 0, r0, c7, c10, 4 @ drain WB 334 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 355 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 363 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 369 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 370 mcr p15, 0, ip, c7, c10, 4 @ drain WB 371 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 372 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 387 mcr p15, 0, r0, c7, c10, 4 @ drain WB 394 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 395 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A D	copypage-fa.c	28 mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_copy_user_page() 32 mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_copy_user_page() 36 mcr p15, 0, r2, c7, c10, 4 @ 1 drain WB\n\ fa_copy_user_page() 69 mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_clear_user_highpage() 72 mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_clear_user_highpage() 76 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" fa_clear_user_highpage()
H A D	proc-arm1020e.S	83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 227 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 235 mcr p15, 0, ip, c7, c10, 4 @ drain WB 252 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 257 mcr p15, 0, ip, c7, c10, 4 @ drain WB 281 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 286 mcr p15, 0, ip, c7, c10, 4 @ drain WB 303 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 308 mcr p15, 0, ip, c7, c10, 4 @ drain WB 323 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 328 mcr p15, 0, ip, c7, c10, 4 @ drain WB 365 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 385 mcr p15, 0, r3, c7, c10, 4 390 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry 402 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 404 mcr p15, 0, r1, c7, c10, 4 @ drain WB 405 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 406 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 430 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A D	proc-xsc3.S	71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 95 mcr p15, 0, r0, c1, c0, 0 @ disable caches 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 140 mcr p14, 0, r0, c7, c0, 0 @ go to idle 152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 233 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 234 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 254 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 255 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 275 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line 279 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 292 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 296 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 309 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 313 mcr p15, 0, r0, c7, c10, 4 @ data write barrier 347 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 365 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 366 mcr p15, 0, ip, c7, c10, 4 @ data write barrier 367 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush 369 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 370 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 433 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 434 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer 435 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer 436 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 437 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. 438 mcr p15, 0, r5, c15, c1, 0 @ CP access reg 439 mcr p15, 0, r6, c13, c0, 0 @ PID 440 mcr p15, 0, r7, c3, c0, 0 @ domain ID 442 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr 443 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg 453 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 454 mcr p15, 0, ip, c7, c10, 4 @ data write barrier 455 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush 456 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 458 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 461 mcr p15, 0, r0, c15, c1, 0 @ write CP access register 466 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
H A D	cache-fa.S	48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 137 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 138 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 152 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 158 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 179 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 184 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 197 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 202 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 212 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry 217 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
H A D	copypage-v4wb.c	32 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_copy_user_page() 37 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_copy_user_page() 44 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\ v4wb_copy_user_page() 77 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_clear_user_highpage() 80 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_clear_user_highpage() 85 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" v4wb_clear_user_highpage()
H A D	copypage-xscale.c	66 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ mc_copy_user_page() 68 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ mc_copy_user_page() 77 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ mc_copy_user_page() 79 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ mc_copy_user_page() 122 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ xscale_mc_clear_user_highpage() 124 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ xscale_mc_clear_user_highpage()
H A D	cache-v4wb.S	61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 80 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 97 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 119 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 120 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 166 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 167 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 172 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 mcr p15, 0, r0, c7, c10, 4 @ drain WB 194 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 198 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 211 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 215 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
H A D	proc-v7.S	36 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0 136 mcr p15, 0, r7, c2, c0, 1 @ TTB 1 138 mcr p15, 0, r11, c2, c0, 2 @ TTB control register 141 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control 236 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features 237 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0 238 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2 239 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1 240 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC 315 mcr p15, 1, r0, c15, c1, 1 321 mcr p15, 1, r0, c15, c1, 2 330 mcr p15, 1, r0, c15, c2, 0 335 mcr p15, 1, r0, c15, c1, 0 429 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 431 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 435 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 436 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 445 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 448 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
H A D	proc-arm720.S	60 mcr p15, 0, r0, c1, c0, 0 @ disable caches 80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 81 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 114 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 152 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
H A D	cache-v7.S	36 mcr p15, 2, r0, c0, c0, 0 58 mcr p15, 0, r5, c7, c6, 2 77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 78 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 135 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 157 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 168 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 190 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 191 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 208 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 209 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 281 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification 290 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line 295 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 296 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 334 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 367 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 389 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line 411 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
H A D	cache-v4wt.S	51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A D	proc-v7-2level.S	44 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 60 mcr p15, 0, r1, c13, c0, 1 @ set context ID 62 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 111 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 152 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register 157 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
H A D	copypage-xsc3.c	47 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ xsc3_mc_copy_user_page() 57 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ xsc3_mc_copy_user_page() 98 1: mcr p15, 0, %0, c7, c6, 1 @ invalidate line\n\ xsc3_mc_clear_user_highpage()
H A D	cache-tauros2.c	42 __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr)); tauros2_clean_pa() 47 __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr)); tauros2_clean_inv_pa() 52 __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr)); tauros2_inv_pa() 118 "mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t" tauros2_disable() 121 "mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t" tauros2_disable() 128 "mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t" tauros2_resume() 131 "mcr p15, 0, %0, c1, c0, 0 @Enable L2 Cache\n\t" tauros2_resume() 147 __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); write_extra_features() 175 __asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr)); write_actlr()
H A D	copypage-v4mc.c	50 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ mc_copy_user_page() 55 mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ mc_copy_user_page() 98 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4_mc_clear_user_highpage() 101 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4_mc_clear_user_highpage()
H A D	cache-feroceon-l2.c	70 __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); l2_clean_pa() 87 __asm__("mcr p15, 1, %0, c15, c9, 4\n\t" l2_clean_pa_range() 88 "mcr p15, 1, %1, c15, c9, 5" l2_clean_pa_range() 96 __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); l2_clean_inv_pa() 101 __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); l2_inv_pa() 118 __asm__("mcr p15, 1, %0, c15, c11, 4\n\t" l2_inv_pa_range() 119 "mcr p15, 1, %1, c15, c11, 5" l2_inv_pa_range() 127 __asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0)); l2_inv_all() 268 __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); __invalidate_icache() 303 __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); write_extra_features()
H A D	cache-xsc3l2.c	45 __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr)); xsc3_l2_clean_mva() 50 __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr)); xsc3_l2_inv_mva() 63 __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way)); xsc3_l2_inv_all() 173 __asm__("mcr p15, 1, %0, c7, c15, 2" : : "r"(set_way)); xsc3_l2_flush_all()
H A D	copypage-v4wt.c	40 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\ v4wt_copy_user_page() 78 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" v4wt_clear_user_highpage()
H A D	nommu.c	31 asm("mcr p15, 0, %0, c6, c2, 0" : : "r" (v)); rgnr_write() 39 asm("mcr p15, 0, %0, c6, c1, 4" : : "r" (v)); dracr_write() 45 asm("mcr p15, 0, %0, c6, c1, 2" : : "r" (v)); drsr_write() 51 asm("mcr p15, 0, %0, c6, c1, 0" : : "r" (v)); drbar_write() 65 asm("mcr p15, 0, %0, c6, c1, 5" : : "r" (v)); iracr_write() 71 asm("mcr p15, 0, %0, c6, c1, 3" : : "r" (v)); irsr_write() 77 asm("mcr p15, 0, %0, c6, c1, 1" : : "r" (v)); irbar_write()
H A D	flush.c	34 " mcr p15, 0, %2, c7, c10, 4" flush_pfn_alias() 59 asm( "mcr p15, 0, %0, c7, c14, 0\n" flush_cache_mm() 60 " mcr p15, 0, %0, c7, c10, 4" flush_cache_mm() 75 asm( "mcr p15, 0, %0, c7, c14, 0\n" flush_cache_range() 76 " mcr p15, 0, %0, c7, c10, 4" flush_cache_range()
H A D	proc-v7-3level.S	99 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 145 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
H A D	context.c	98 " mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n" cpu_set_reserved_ttbr0() 120 " mcr p15, 0, %0, c13, c0, 1\n" contextidr_notifier()
/linux-4.1.27/arch/arm/mach-iop33x/
H A D	irq.c	27 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); intctl0_write() 32 asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val)); intctl1_write() 37 asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val)); intstr0_write() 42 asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val)); intstr1_write() 47 asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val)); intbase_write() 52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); intsize_write()
/linux-4.1.27/arch/arm/mach-iop13xx/include/mach/
H A D	time.h	80 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); write_tmr0() 85 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val)); write_tmr1() 97 asm volatile("mcr p6, 0, %0, c2, c9, 0" : : "r" (val)); write_tcr0() 109 asm volatile("mcr p6, 0, %0, c3, c9, 0" : : "r" (val)); write_tcr1() 114 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val)); write_trr0() 119 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val)); write_trr1() 124 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val)); write_tisr()
H A D	iop13xx.h	36 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); write_wdtcr() 48 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val)); write_wdtsr()
/linux-4.1.27/arch/sh/drivers/pci/
H A D	fixups-landisk.c	43 unsigned long bcr1, mcr; pci_fixup_pcic() local 49 mcr = __raw_readl(SH7751_MCR); pci_fixup_pcic() 50 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; pci_fixup_pcic() 51 pci_write_reg(chan, mcr, SH4_PCIMCR); pci_fixup_pcic()
H A D	fixups-rts7751r2d.c	44 unsigned long bcr1, mcr; pci_fixup_pcic() local 57 mcr = __raw_readl(SH7751_MCR); pci_fixup_pcic() 58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; pci_fixup_pcic() 59 pci_write_reg(chan, mcr, SH4_PCIMCR); pci_fixup_pcic()
H A D	fixups-se7751.c	40 unsigned long bcr1, wcr1, wcr2, wcr3, mcr; pci_fixup_pcic() local 55 mcr = (*(volatile unsigned long*)(SH7751_MCR)); pci_fixup_pcic() 66 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; pci_fixup_pcic() 67 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */ pci_fixup_pcic()
/linux-4.1.27/arch/arm/mach-spear/
H A D	hotplug.c	24 " mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower() 31 " mcr p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower() 34 " mcr p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower() 46 " mcr p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower() 49 " mcr p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
H A D	headsmp.S	37 mcr p15, 0, r0, c1, c0, 1
/linux-4.1.27/arch/arm/boot/compressed/
H A D	head-xscale.S	26 mcr p15, 0, r0, c7, c10, 4 @ drain WB 27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 33 mcr p15, 0, r0, c1, c0, 0
H A D	head.S	33 mcr p14, 0, \ch, c0, c5, 0 39 mcr p14, 0, \ch, c8, c0, 0 45 mcr p14, 0, \ch, c1, c0, 0 618 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 619 mcr p15, 0, r0, c6, c7, 1 622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 624 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 627 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 628 mcr p15, 0, r0, c5, c0, 0 @ D-access permission 631 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 632 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 633 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 639 mcr p15, 0, r0, c1, c0, 0 @ write control reg 642 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 643 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 648 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 651 mcr p15, 0, r0, c2, c0, 0 @ cache on 652 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 655 mcr p15, 0, r0, c5, c0, 0 @ access permission 658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 668 mcr p15, 0, r0, c1, c0, 0 @ write control reg 671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 727 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR 733 mcr p15, 7, r0, c15, c0, 0 742 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 743 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 750 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 762 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 784 mcr p15, 0, r0, c7, c5, 4 @ ISB 785 mcr p15, 0, r0, c1, c0, 0 @ load control register 788 mcr p15, 0, r0, c7, c5, 4 @ ISB 796 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache 797 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 798 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 803 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 812 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer 813 mcr p15, 0, r1, c3, c0, 0 @ load domain access control 816 1: mcr p15, 0, r0, c1, c0, 0 @ load control register 1048 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off 1050 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 1051 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache 1052 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache 1058 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off 1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 1067 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 1069 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 1070 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 1081 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 1086 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 1088 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC 1089 mcr p15, 0, r0, c7, c10, 4 @ DSB 1090 mcr p15, 0, r0, c7, c5, 4 @ ISB 1111 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 1114 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 1122 mcr p15, 0, ip, c7, c10, 4 @ drain WB 1129 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 1130 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 1131 mcr p15, 0, r1, c7, c10, 4 @ drain WB 1138 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 1140 mcr p15, 0, r1, c7, c10, 4 @ drain WB 1150 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 1153 mcr p15, 0, r10, c7, c10, 5 @ DMB 1166 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 1167 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr 1185 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 1197 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 1199 mcr p15, 0, r10, c7, c10, 4 @ DSB 1200 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 1201 mcr p15, 0, r10, c7, c10, 4 @ DSB 1202 mcr p15, 0, r10, c7, c5, 4 @ ISB 1210 mcr p15, 0, r0, c7, c5, 0 @ flush I cache 1211 mcr p15, 0, r0, c7, c10, 4 @ drain WB 1243 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 1244 mcr p15, 0, r1, c7, c6, 0 @ flush D cache 1245 mcr p15, 0, r1, c7, c10, 4 @ drain WB 1253 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
H A D	head-sa1100.S	40 mcr p15, 0, r0, c7, c10, 4 @ drain WB 41 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 47 mcr p15, 0, r0, c1, c0, 0
H A D	misc.c	45 asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); icedcc_putc() 62 asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); icedcc_putc() 78 asm("mcr p14, 0, %0, c1, c0, 0" : : "r" (ch)); icedcc_putc()
/linux-4.1.27/arch/arm/mach-realview/
H A D	hotplug.c	23 " mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower() 24 " mcr p15, 0, %1, c7, c10, 4\n" cpu_enter_lowpower() 30 " mcr p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower() 33 " mcr p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower() 45 " mcr p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
/linux-4.1.27/arch/arm/mach-vexpress/
H A D	hotplug.c	23 "mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower() 24 " mcr p15, 0, %1, c7, c10, 4\n" cpu_enter_lowpower() 30 " mcr p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower() 33 " mcr p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower() 46 " mcr p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower() 49 " mcr p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
H A D	tc2_pm.c	107 "mcr p15, 1, %0, c15, c0, 3 \n\t" tc2_pm_cluster_cache_disable()
/linux-4.1.27/arch/arm/include/asm/
H A D	barrier.h	21 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ 23 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ 25 #define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ 28 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \ 30 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \ 35 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
H A D	arch_timer.h	26 asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); arch_timer_reg_write_cp15() 29 asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); arch_timer_reg_write_cp15() 35 asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); arch_timer_reg_write_cp15() 38 asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); arch_timer_reg_write_cp15() 108 asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); arch_timer_set_cntkctl()
H A D	tls.h	14 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register 15 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register 74 * thread_info upon resuming execution and the following mcr set_tls() 81 asm("mcr p15, 0, %0, c13, c0, 3" set_tls() 115 asm("mcr p15, 0, %0, c13, c0, 2" set_tpuser()
H A D	cp15.h	63 asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR" set_cr() 77 asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR" set_auxcr() 96 asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access" set_copro_access()
H A D	dcc.h	37 asm volatile("mcr p14, 0, %0, c0, c5, 0 @ write a char" __dcc_putchar()
H A D	percpu.h	27 asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory"); set_my_cpu_offset()
H A D	domain.h	66 "mcr p15, 0, %0, c3, c0 @ set domain" set_domain()
H A D	hw_breakpoint.h	110 asm volatile("mcr p14, 0, %0, " #N "," #M ", " #OP2 : : "r" (VAL));\
H A D	tlbflush.h	310 asm("mcr " insnarg \ 432 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); __local_flush_tlb_page() 487 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); __local_flush_tlb_kernel_page() 540 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); __local_flush_bp_all() 550 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); local_flush_bp_all() 560 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); __flush_bp_all()
H A D	cacheflush.h	188 asm("mcr p15, 0, %0, c7, c5, 0" \ 193 asm("mcr p15, 0, %0, c7, c1, 0" \ 473 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR \n\t" \ 478 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR \n\t" \
H A D	assembler.h	266 mcr p15, 0, r0, c7, c5, 4 282 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
/linux-4.1.27/drivers/mtd/nand/
H A D	txx9ndfmc.c	118 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); txx9ndfmc_write_buf() local 120 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); txx9ndfmc_write_buf() 123 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); txx9ndfmc_write_buf() 144 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); txx9ndfmc_cmd_ctrl() local 146 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); txx9ndfmc_cmd_ctrl() 147 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; txx9ndfmc_cmd_ctrl() 148 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; txx9ndfmc_cmd_ctrl() 150 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; txx9ndfmc_cmd_ctrl() 152 mcr &= ~TXX9_NDFMCR_CS_MASK; txx9ndfmc_cmd_ctrl() 153 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs); txx9ndfmc_cmd_ctrl() 155 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); txx9ndfmc_cmd_ctrl() 180 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); txx9ndfmc_calculate_ecc() local 182 mcr &= ~TXX9_NDFMCR_ECC_ALL; txx9ndfmc_calculate_ecc() 183 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); txx9ndfmc_calculate_ecc() 184 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR); txx9ndfmc_calculate_ecc() 191 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); txx9ndfmc_calculate_ecc() 218 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); txx9ndfmc_enable_hwecc() local 220 mcr &= ~TXX9_NDFMCR_ECC_ALL; txx9ndfmc_enable_hwecc() 221 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR); txx9ndfmc_enable_hwecc() 222 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); txx9ndfmc_enable_hwecc() 223 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR); txx9ndfmc_enable_hwecc()
/linux-4.1.27/arch/x86/kernel/
H A D	iosf_mbi.c	43 static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr) iosf_mbi_pci_read_mdr() argument 57 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); iosf_mbi_pci_read_mdr() 72 static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr) iosf_mbi_pci_write_mdr() argument 90 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); iosf_mbi_pci_write_mdr() 103 u32 mcr, mcrx; iosf_mbi_read() local 113 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); iosf_mbi_read() 117 ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr); iosf_mbi_read() 126 u32 mcr, mcrx; iosf_mbi_write() local 136 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); iosf_mbi_write() 140 ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr); iosf_mbi_write() 149 u32 mcr, mcrx; iosf_mbi_modify() local 160 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); iosf_mbi_modify() 166 ret = iosf_mbi_pci_read_mdr(mcrx, mcr & MBI_RD_MASK, &value); iosf_mbi_modify() 178 ret = iosf_mbi_pci_write_mdr(mcrx, mcr | MBI_WR_MASK, value); iosf_mbi_modify() 251 /* mcr - initiates mailbox tranaction */ iosf_sideband_debug_init() 252 debugfs_create_file("mcr", 0660, iosf_dbg, &dbg_mcr, &iosf_mcr_fops); iosf_sideband_debug_init()
/linux-4.1.27/arch/arm/mach-imx/
H A D	hotplug.c	25 "mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower() 26 " mcr p15, 0, %1, c7, c10, 4\n" cpu_enter_lowpower() 32 " mcr p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower() 35 " mcr p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower()
H A D	headsmp.S	24 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
H A D	mm-imx3.c	48 "mcr p15, 0, %0, c1, c0, 0\n" imx3_idle() 51 "mcr p15, 0, %0, c7, c5, 0\n" imx3_idle() 54 "mcr p15, 0, %0, c7, c14, 0\n" imx3_idle() 57 "mcr p15, 0, %0, c7, c0, 4\n" imx3_idle() 64 "mcr p15, 0, %0, c1, c0, 0\n" imx3_idle()
H A D	suspend-imx6.S	312 mcr p15, 0, r6, c7, c5, 0 313 mcr p15, 0, r6, c7, c5, 6 316 mcr p15, 0, r6, c1, c0, 0
/linux-4.1.27/arch/arm/mach-iop13xx/
H A D	irq.c	40 asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val)); write_intctl_0() 53 asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val)); write_intctl_1() 66 asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val)); write_intctl_2() 79 asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val)); write_intctl_3() 86 asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val)); write_intstr_0() 93 asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val)); write_intstr_1() 100 asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val)); write_intstr_2() 107 asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val)); write_intstr_3() 114 asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val)); write_intbase() 121 asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val)); write_intsize()
H A D	msi.c	38 asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val)); write_imipr_0() 51 asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val)); write_imipr_1() 64 asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val)); write_imipr_2() 77 asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val)); write_imipr_3()
/linux-4.1.27/arch/arm/kvm/
H A D	init.S	85 mcr p15, 4, r0, c2, c0, 2 @ HTCR 93 mcr p15, 4, r1, c2, c1, 2 @ VTCR 98 mcr p15, 4, r0, c10, c2, 0 100 mcr p15, 4, r0, c10, c2, 1 103 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH 126 mcr p15, 4, r0, c1, c0, 0 @ HSCR 136 mcr p15, 4, r1, c12, c0, 0 @ HVBAR 149 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
H A D	interrupts_head.S	339 mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL 341 mcr p15, 0, r6, c10, c3, 0 @ AMAIR0 342 mcr p15, 0, r7, c10, c3, 1 @ AMAIR1 360 mcr p15, 0, r2, c13, c0, 1 @ CID 361 mcr p15, 0, r3, c13, c0, 2 @ TID_URW 362 mcr p15, 0, r4, c13, c0, 3 @ TID_URO 363 mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV 364 mcr p15, 0, r6, c5, c0, 0 @ DFSR 365 mcr p15, 0, r7, c5, c0, 1 @ IFSR 366 mcr p15, 0, r8, c5, c1, 0 @ ADFSR 367 mcr p15, 0, r9, c5, c1, 1 @ AIFSR 368 mcr p15, 0, r10, c6, c0, 0 @ DFAR 369 mcr p15, 0, r11, c6, c0, 2 @ IFAR 370 mcr p15, 0, r12, c12, c0, 0 @ VBAR 388 mcr p15, 0, r2, c1, c0, 0 @ SCTLR 389 mcr p15, 0, r3, c1, c0, 2 @ CPACR 390 mcr p15, 0, r4, c2, c0, 2 @ TTBCR 391 mcr p15, 0, r5, c3, c0, 0 @ DACR 394 mcr p15, 0, r10, c10, c2, 0 @ PRRR 395 mcr p15, 0, r11, c10, c2, 1 @ NMRR 396 mcr p15, 2, r12, c0, c0, 0 @ CSSELR 535 mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL 540 mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL 556 mcr p15, 4, r2, c14, c1, 0 @ CNTHCTL 575 mcr p15, 0, r2, c14, c3, 1 @ CNTV_CTL 592 mcr p15, 4, r2, c1, c1, 3 610 mcr p15, 4, r3, c1, c1, 2 634 mcr p15, 4, r2, c1, c1, 1 646 mcr p15, 4, r2, c1, c1, 0 @ HCR
H A D	interrupts.S	57 mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored) 90 mcr p15, 4, r0, c8, c3, 4 92 mcr p15, 0, r0, c7, c1, 0 108 mcr p15, 4, vcpu, c13, c0, 2 @ HTPIDR 139 mcr p15, 4, r1, c0, c0, 0 143 mcr p15, 4, r1, c0, c0, 5 196 mcr p15, 4, r2, c0, c0, 0 200 mcr p15, 4, r2, c0, c0, 5 447 mcr p15, 0, r2, c7, c8, 0 @ ATS1CPR
H A D	trace.h	157 (__entry->is_write) ? "mcr" : "mrc",
/linux-4.1.27/arch/arm/mach-iop32x/
H A D	irq.c	26 asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val)); intctl_write() 31 asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val)); intstr_write()
/linux-4.1.27/arch/sh/boards/mach-hp6xx/
H A D	pm.c	43 u16 frqcr, mcr; pm_enter() local 66 mcr = __raw_readw(MCR); pm_enter() 67 __raw_writew(mcr & ~MCR_RFSH, MCR); pm_enter() 78 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR); pm_enter()
/linux-4.1.27/drivers/spi/
H A D	spi-txx9.c	155 u32 mcr; txx9spi_work_one() local 162 mcr = txx9spi_rd(c, TXx9_SPMCR); txx9spi_work_one() 163 if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) { txx9spi_work_one() 168 mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR); txx9spi_work_one() 171 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); txx9spi_work_one() 195 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, txx9spi_work_one() 199 txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR); txx9spi_work_one() 278 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); txx9spi_work_one() 330 u32 mcr; txx9spi_probe() local 365 mcr = txx9spi_rd(c, TXx9_SPMCR); txx9spi_probe() 366 mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR); txx9spi_probe() 367 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); txx9spi_probe()
/linux-4.1.27/arch/x86/kernel/cpu/mtrr/
H A D	centaur.c	50 void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) mtrr_centaur_report_mcr() argument 52 centaur_mcr[mcr].low = lo; mtrr_centaur_report_mcr() 53 centaur_mcr[mcr].high = hi; mtrr_centaur_report_mcr()
/linux-4.1.27/arch/arm/kernel/
H A D	hyp-stub.S	128 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR) 132 mcr p15, 4, r7, c1, c1, 0 @ HCR 133 mcr p15, 4, r7, c1, c1, 2 @ HCPTR 134 mcr p15, 4, r7, c1, c1, 3 @ HSTR 138 mcr p15, 4, r7, c1, c0, 0 @ HSCTLR 142 mcr p15, 4, r7, c1, c1, 1 @ HDCR 153 mcr p15, 4, r7, c14, c1, 0 @ CNTHCTL 160 mcr p15, 0, r7, c14, c3, 1 @ CNTV_CTL
H A D	perf_event_xscale.c	109 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); xscale1pmu_write_pmnc() 339 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); xscale1pmu_write_counter() 342 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); xscale1pmu_write_counter() 345 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); xscale1pmu_write_counter() 408 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); xscale2pmu_write_pmnc() 422 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val)); xscale2pmu_write_overflow_flags() 436 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val)); xscale2pmu_write_event_select() 450 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val)); xscale2pmu_write_int_enable() 709 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); xscale2pmu_write_counter() 712 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); xscale2pmu_write_counter() 715 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); xscale2pmu_write_counter() 718 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); xscale2pmu_write_counter() 721 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); xscale2pmu_write_counter()
H A D	iwmmxt.S	84 XSC(mcr p15, 0, r2, c15, c1, 0) 86 PJ4(mcr p15, 0, r2, c1, c0, 2) 215 XSC(mcr p15, 0, r4, c15, c1, 0) 218 PJ4(mcr p15, 0, r4, c1, c0, 2) 228 XSC(mcr p15, 0, r4, c15, c1, 0) 230 PJ4(mcr p15, 0, r4, c1, c0, 2) 340 XSC(mcr p15, 0, r1, c15, c1, 0) 342 PJ4(mcr p15, 0, r1, c1, c0, 2)
H A D	head-nommu.S	165 mcr p15, 0, r0, c1, c0, 0 @ write control reg 177 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR 182 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR 183 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR 184 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR 255 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
H A D	smp_tlb.c	78 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); erratum_a15_798181_partial() 85 asm("mcr p15, 0, %0, c8, c3, 1" : : "r" (0)); erratum_a15_798181_broadcast()
H A D	perf_event_v7.c	608 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); armv7_pmnc_write() 630 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); armv7_pmnc_select_counter() 664 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value)); armv7pmu_write_counter() 667 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value)); armv7pmu_write_counter() 675 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); armv7_pmnc_write_evtsel() 681 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); armv7_pmnc_enable_counter() 687 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); armv7_pmnc_disable_counter() 693 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); armv7_pmnc_enable_intens() 699 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); armv7_pmnc_disable_intens() 702 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); armv7_pmnc_disable_intens() 715 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); armv7_pmnc_getreset_flags() 1203 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); krait_write_pmresrn() 1206 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); krait_write_pmresrn() 1209 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); krait_write_pmresrn() 1225 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); venum_write_pmresr() 1423 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); krait_pmu_reset() 1585 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); scorpion_write_pmresrn() 1588 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); scorpion_write_pmresrn() 1591 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); scorpion_write_pmresrn() 1594 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); scorpion_write_pmresrn() 1634 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); scorpion_evt_setup() 1757 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); scorpion_pmu_reset()
H A D	thumbee.c	39 asm("mcr p14, 6, %0, c1, c0, 0\n" : : "r" (v)); teehbr_write()
H A D	pj4-cp0.c	68 "mcr p15, 0, %1, c1, c0, 2\n\t" pj4_cp_access_write()
H A D	tcm.c	121 asm("mcr p15, 0, %0, c9, c2, 0" setup_tcm_bank() 159 asm("mcr p15, 0, %0, c9, c1, 0" setup_tcm_bank() 163 asm("mcr p15, 0, %0, c9, c1, 1" setup_tcm_bank()
H A D	perf_event_v6.c	181 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); armv6_pmcr_write() 251 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value)); armv6pmu_write_counter() 253 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value)); armv6pmu_write_counter() 255 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value)); armv6pmu_write_counter()
H A D	xscale-cp0.c	106 "mcr p15, 0, %1, c15, c1, 0\n\t" xscale_cp_access_write()
H A D	head.S	448 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 449 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 473 mcr p15, 0, r0, c1, c0, 0 @ write control reg
H A D	sleep.S	105 mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
/linux-4.1.27/drivers/net/can/
H A D	flexcan.c	211 u32 mcr; /* 0x00 */ member in struct:flexcan_regs 343 reg = flexcan_read(&regs->mcr); flexcan_chip_enable() 345 flexcan_write(reg, &regs->mcr); flexcan_chip_enable() 347 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)) flexcan_chip_enable() 350 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK) flexcan_chip_enable() 362 reg = flexcan_read(&regs->mcr); flexcan_chip_disable() 364 flexcan_write(reg, &regs->mcr); flexcan_chip_disable() 366 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)) flexcan_chip_disable() 369 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_LPM_ACK)) flexcan_chip_disable() 381 reg = flexcan_read(&regs->mcr); flexcan_chip_freeze() 383 flexcan_write(reg, &regs->mcr); flexcan_chip_freeze() 385 while (timeout-- && !(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)) flexcan_chip_freeze() 388 if (!(flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)) flexcan_chip_freeze() 400 reg = flexcan_read(&regs->mcr); flexcan_chip_unfreeze() 402 flexcan_write(reg, &regs->mcr); flexcan_chip_unfreeze() 404 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK)) flexcan_chip_unfreeze() 407 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_FRZ_ACK) flexcan_chip_unfreeze() 418 flexcan_write(FLEXCAN_MCR_SOFTRST, &regs->mcr); flexcan_chip_softreset() 419 while (timeout-- && (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST)) flexcan_chip_softreset() 422 if (flexcan_read(&regs->mcr) & FLEXCAN_MCR_SOFTRST) flexcan_chip_softreset() 804 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, flexcan_set_bittiming() 805 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl)); flexcan_set_bittiming() 845 reg_mcr = flexcan_read(&regs->mcr); flexcan_chip_start() 851 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); flexcan_chip_start() 852 flexcan_write(reg_mcr, &regs->mcr); flexcan_chip_start() 948 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, flexcan_chip_start() 949 flexcan_read(&regs->mcr), flexcan_read(&regs->ctrl)); flexcan_chip_start() 1104 reg = flexcan_read(&regs->mcr); register_flexcandev() 1107 flexcan_write(reg, &regs->mcr); register_flexcandev() 1114 reg = flexcan_read(&regs->mcr); register_flexcandev()
/linux-4.1.27/drivers/net/wan/
H A D	n2.c	171 u8 mcr = inb(io + N2_MCR); n2_set_iface() local 178 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; n2_set_iface() 184 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; n2_set_iface() 190 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; n2_set_iface() 196 mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0; n2_set_iface() 201 outb(mcr, io + N2_MCR); n2_set_iface() 215 u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0); n2_open() local 222 mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */ n2_open() 223 outb(mcr, io + N2_MCR); n2_open() 238 u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0); n2_close() local 241 mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */ n2_close() 242 outb(mcr, io + N2_MCR); n2_close()
/linux-4.1.27/arch/mips/txx9/generic/
H A D	setup_tx3927.c	79 tx3927_dmaptr->mcr = 0; tx3927_setup() 87 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; tx3927_setup() 89 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; tx3927_setup()
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A D	mtd-xip.h	33 #define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
/linux-4.1.27/arch/arm/mach-pxa/
H A D	sleep.S	31 mcr p14, 0, r0, c7, c0, 0 @ enter sleep 131 mcr p14, 0, r0, c6, c0, 0 145 mcr p14, 0, r0, c6, c0, 0 169 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
H A D	standby.S	30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby 64 mcr p14, 0, r0, c7, c0, 0
H A D	pxa3xx.c	396 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); __pxa3xx_init_irq()
/linux-4.1.27/arch/arm/mach-shmobile/
H A D	platsmp-apmu.c	151 " mcr p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower_a15() 164 " mcr p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower_a15() 189 " mcr p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower() 192 " mcr p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
H A D	setup-rcar-gen2.c	71 " mcr p15, 0, r0, c1, c1, 0\n" rcar_gen2_timer_init() 76 " mcr p15, 0, r1, c1, c1, 0\n" rcar_gen2_timer_init() 121 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); rcar_gen2_timer_init()
/linux-4.1.27/drivers/staging/dgnc/
H A D	dgnc_cls.h	33 * mcr : WR MCR - Modem Control Reg 43 u8 mcr; member in struct:cls_uart_struct
H A D	dgnc_neo.h	35 u8 mcr; /* WR MCR - Modem Control Reg */ member in struct:neo_uart_struct
/linux-4.1.27/arch/arm/include/asm/hardware/
H A D	iop3xx.h	230 asm volatile("mcr p6, 0, %0, c0, c1, 0" : : "r" (val)); write_tmr0() 235 asm volatile("mcr p6, 0, %0, c1, c1, 0" : : "r" (val)); write_tmr1() 247 asm volatile("mcr p6, 0, %0, c2, c1, 0" : : "r" (val)); write_tcr0() 259 asm volatile("mcr p6, 0, %0, c3, c1, 0" : : "r" (val)); write_tcr1() 264 asm volatile("mcr p6, 0, %0, c4, c1, 0" : : "r" (val)); write_trr0() 269 asm volatile("mcr p6, 0, %0, c5, c1, 0" : : "r" (val)); write_trr1() 274 asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val)); write_tisr() 285 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); write_wdtcr()
/linux-4.1.27/drivers/usb/serial/
H A D	ti_usb_3410_5052.c	117 static int ti_set_mcr(struct ti_port *tport, unsigned int mcr); 712 unsigned int mcr; ti_set_termios() local 823 mcr = tport->tp_shadow_mcr; ti_set_termios() 826 mcr &= ~(TI_MCR_DTR | TI_MCR_RTS); ti_set_termios() 827 status = ti_set_mcr(tport, mcr); ti_set_termios() 843 unsigned int mcr; ti_tiocmget() local 851 mcr = tport->tp_shadow_mcr; ti_tiocmget() 854 result = ((mcr & TI_MCR_DTR) ? TIOCM_DTR : 0) ti_tiocmget() 855 | ((mcr & TI_MCR_RTS) ? TIOCM_RTS : 0) ti_tiocmget() 856 | ((mcr & TI_MCR_LOOP) ? TIOCM_LOOP : 0) ti_tiocmget() 873 unsigned int mcr; ti_tiocmset() local 880 mcr = tport->tp_shadow_mcr; ti_tiocmset() 883 mcr |= TI_MCR_RTS; ti_tiocmset() 885 mcr |= TI_MCR_DTR; ti_tiocmset() 887 mcr |= TI_MCR_LOOP; ti_tiocmset() 890 mcr &= ~TI_MCR_RTS; ti_tiocmset() 892 mcr &= ~TI_MCR_DTR; ti_tiocmset() 894 mcr &= ~TI_MCR_LOOP; ti_tiocmset() 897 return ti_set_mcr(tport, mcr); ti_tiocmset() 1166 static int ti_set_mcr(struct ti_port *tport, unsigned int mcr) ti_set_mcr() argument 1173 TI_MCR_RTS | TI_MCR_DTR | TI_MCR_LOOP, mcr); ti_set_mcr() 1177 tport->tp_shadow_mcr = mcr; ti_set_mcr()
H A D	ark3116.c	73 __u32 mcr; /* modem control register value */ member in struct:ark3116_private 161 priv->mcr = 0; ark3116_port_probe() 442 ctrl = priv->mcr; ark3116_tiocmget() 466 * in priv->mcr is actually the one that is in the hardware ark3116_tiocmset() 472 priv->mcr |= UART_MCR_RTS; ark3116_tiocmset() 474 priv->mcr |= UART_MCR_DTR; ark3116_tiocmset() 476 priv->mcr |= UART_MCR_OUT1; ark3116_tiocmset() 478 priv->mcr |= UART_MCR_OUT2; ark3116_tiocmset() 480 priv->mcr &= ~UART_MCR_RTS; ark3116_tiocmset() 482 priv->mcr &= ~UART_MCR_DTR; ark3116_tiocmset() 484 priv->mcr &= ~UART_MCR_OUT1; ark3116_tiocmset() 486 priv->mcr &= ~UART_MCR_OUT2; ark3116_tiocmset() 488 ark3116_write_reg(port->serial, UART_MCR, priv->mcr); ark3116_tiocmset()
H A D	spcp8x5.c	186 static int spcp8x5_set_ctrl_line(struct usb_serial_port *port, u8 mcr) spcp8x5_set_ctrl_line() argument 197 mcr, 0x04, NULL, 0, 100); spcp8x5_set_ctrl_line() 443 unsigned int mcr; spcp8x5_tiocmget() local 452 mcr = priv->line_control; spcp8x5_tiocmget() 455 result = ((mcr & MCR_DTR) ? TIOCM_DTR : 0) spcp8x5_tiocmget() 456 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) spcp8x5_tiocmget()
H A D	whiteheat.c	152 __u8 mcr; /* FIXME: no locking on mcr */ member in struct:whiteheat_private 447 if (info->mcr & UART_MCR_DTR) whiteheat_tiocmget() 449 if (info->mcr & UART_MCR_RTS) whiteheat_tiocmget() 462 info->mcr |= UART_MCR_RTS; whiteheat_tiocmset() 464 info->mcr |= UART_MCR_DTR; whiteheat_tiocmset() 467 info->mcr &= ~UART_MCR_RTS; whiteheat_tiocmset() 469 info->mcr &= ~UART_MCR_DTR; whiteheat_tiocmset() 471 firm_set_dtr(port, info->mcr & UART_MCR_DTR); whiteheat_tiocmset() 472 firm_set_rts(port, info->mcr & UART_MCR_RTS); whiteheat_tiocmset() 643 memcpy(&info->mcr, command_info->result_buffer, firm_send_command()
H A D	mct_u232.c	279 unsigned char mcr; mct_u232_set_modem_ctrl() local 286 mcr = MCT_U232_MCR_NONE; mct_u232_set_modem_ctrl() 288 mcr |= MCT_U232_MCR_DTR; mct_u232_set_modem_ctrl() 290 mcr |= MCT_U232_MCR_RTS; mct_u232_set_modem_ctrl() 292 buf[0] = mcr; mct_u232_set_modem_ctrl() 300 dev_dbg(&port->dev, "set_modem_ctrl: state=0x%x ==> mcr=0x%x\n", control_state, mcr); mct_u232_set_modem_ctrl() 303 dev_err(&port->dev, "Set MODEM CTRL 0x%x failed (error = %d)\n", mcr, rc); mct_u232_set_modem_ctrl()
H A D	mos7720.c	1745 unsigned int mcr ; mos7720_tiocmget() local 1748 mcr = mos7720_port->shadowMCR; mos7720_tiocmget() 1751 result = ((mcr & UART_MCR_DTR) ? TIOCM_DTR : 0) /* 0x002 */ mos7720_tiocmget() 1752 | ((mcr & UART_MCR_RTS) ? TIOCM_RTS : 0) /* 0x004 */ mos7720_tiocmget() 1766 unsigned int mcr ; mos7720_tiocmset() local 1768 mcr = mos7720_port->shadowMCR; mos7720_tiocmset() 1771 mcr |= UART_MCR_RTS; mos7720_tiocmset() 1773 mcr |= UART_MCR_DTR; mos7720_tiocmset() 1775 mcr |= UART_MCR_LOOP; mos7720_tiocmset() 1778 mcr &= ~UART_MCR_RTS; mos7720_tiocmset() 1780 mcr &= ~UART_MCR_DTR; mos7720_tiocmset() 1782 mcr &= ~UART_MCR_LOOP; mos7720_tiocmset() 1784 mos7720_port->shadowMCR = mcr; mos7720_tiocmset() 1794 unsigned int mcr; set_modem_info() local 1803 mcr = mos7720_port->shadowMCR; set_modem_info() 1811 mcr |= UART_MCR_RTS; set_modem_info() 1813 mcr |= UART_MCR_RTS; set_modem_info() 1815 mcr |= UART_MCR_LOOP; set_modem_info() 1820 mcr &= ~UART_MCR_RTS; set_modem_info() 1822 mcr &= ~UART_MCR_RTS; set_modem_info() 1824 mcr &= ~UART_MCR_LOOP; set_modem_info() 1829 mos7720_port->shadowMCR = mcr; set_modem_info()
H A D	metro-usb.c	239 unsigned char mcr = METROUSB_MCR_NONE; metrousb_set_modem_ctrl() local 246 mcr |= METROUSB_MCR_DTR; metrousb_set_modem_ctrl() 248 mcr |= METROUSB_MCR_RTS; metrousb_set_modem_ctrl() 257 __func__, mcr, retval); metrousb_set_modem_ctrl()
H A D	io_ti.c	1394 static int restore_mcr(struct edgeport_port *port, __u8 mcr) restore_mcr() argument 1398 dev_dbg(&port->port->dev, "%s - %x\n", __func__, mcr); restore_mcr() 1400 status = ti_do_config(port, UMPC_SET_CLR_DTR, mcr & MCR_DTR); restore_mcr() 1403 status = ti_do_config(port, UMPC_SET_CLR_RTS, mcr & MCR_RTS); restore_mcr() 1406 return ti_do_config(port, UMPC_SET_CLR_LOOPBACK, mcr & MCR_LOOPBACK); restore_mcr() 2263 unsigned int mcr; edge_tiocmset() local 2267 mcr = edge_port->shadow_mcr; edge_tiocmset() 2269 mcr |= MCR_RTS; edge_tiocmset() 2271 mcr |= MCR_DTR; edge_tiocmset() 2273 mcr |= MCR_LOOPBACK; edge_tiocmset() 2276 mcr &= ~MCR_RTS; edge_tiocmset() 2278 mcr &= ~MCR_DTR; edge_tiocmset() 2280 mcr &= ~MCR_LOOPBACK; edge_tiocmset() 2282 edge_port->shadow_mcr = mcr; edge_tiocmset() 2285 restore_mcr(edge_port, mcr); edge_tiocmset() 2295 unsigned int mcr; edge_tiocmget() local 2301 mcr = edge_port->shadow_mcr; edge_tiocmget() 2302 result = ((mcr & MCR_DTR) ? TIOCM_DTR: 0) /* 0x002 */ edge_tiocmget() 2303 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ edge_tiocmget()
H A D	ch341.c	519 u8 mcr; ch341_tiocmget() local 524 mcr = priv->line_control; ch341_tiocmget() 528 result = ((mcr & CH341_BIT_DTR) ? TIOCM_DTR : 0) ch341_tiocmget() 529 | ((mcr & CH341_BIT_RTS) ? TIOCM_RTS : 0) ch341_tiocmget()
H A D	f81232.c	505 u8 mcr, msr; f81232_tiocmget() local 511 mcr = port_priv->modem_control; f81232_tiocmget() 515 r = (mcr & UART_MCR_DTR ? TIOCM_DTR : 0) | f81232_tiocmget() 516 (mcr & UART_MCR_RTS ? TIOCM_RTS : 0) | f81232_tiocmget()
H A D	mos7840.c	1484 __u16 mcr; mos7840_tiocmget() local 1494 status = mos7840_get_uart_reg(port, MODEM_CONTROL_REGISTER, &mcr); mos7840_tiocmget() 1497 result = ((mcr & MCR_DTR) ? TIOCM_DTR : 0) mos7840_tiocmget() 1498 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) mos7840_tiocmget() 1499 | ((mcr & MCR_LOOPBACK) ? TIOCM_LOOP : 0) mos7840_tiocmget() 1515 unsigned int mcr; mos7840_tiocmset() local 1524 mcr = mos7840_port->shadowMCR; mos7840_tiocmset() 1526 mcr &= ~MCR_RTS; mos7840_tiocmset() 1528 mcr &= ~MCR_DTR; mos7840_tiocmset() 1530 mcr &= ~MCR_LOOPBACK; mos7840_tiocmset() 1533 mcr |= MCR_RTS; mos7840_tiocmset() 1535 mcr |= MCR_DTR; mos7840_tiocmset() 1537 mcr |= MCR_LOOPBACK; mos7840_tiocmset() 1539 mos7840_port->shadowMCR = mcr; mos7840_tiocmset() 1541 status = mos7840_set_uart_reg(port, MODEM_CONTROL_REGISTER, mcr); mos7840_tiocmset()
H A D	pl2303.c	706 unsigned int mcr; pl2303_tiocmget() local 711 mcr = priv->line_control; pl2303_tiocmget() 715 result = ((mcr & CONTROL_DTR) ? TIOCM_DTR : 0) pl2303_tiocmget() 716 | ((mcr & CONTROL_RTS) ? TIOCM_RTS : 0) pl2303_tiocmget()
H A D	io_edgeport.c	1510 unsigned int mcr; edge_tiocmset() local 1512 mcr = edge_port->shadowMCR; edge_tiocmset() 1514 mcr |= MCR_RTS; edge_tiocmset() 1516 mcr |= MCR_DTR; edge_tiocmset() 1518 mcr |= MCR_LOOPBACK; edge_tiocmset() 1521 mcr &= ~MCR_RTS; edge_tiocmset() 1523 mcr &= ~MCR_DTR; edge_tiocmset() 1525 mcr &= ~MCR_LOOPBACK; edge_tiocmset() 1527 edge_port->shadowMCR = mcr; edge_tiocmset() 1540 unsigned int mcr; edge_tiocmget() local 1543 mcr = edge_port->shadowMCR; edge_tiocmget() 1544 result = ((mcr & MCR_DTR) ? TIOCM_DTR: 0) /* 0x002 */ edge_tiocmget() 1545 | ((mcr & MCR_RTS) ? TIOCM_RTS: 0) /* 0x004 */ edge_tiocmget()
H A D	mxuport.c	748 unsigned int mcr; mxuport_tiocmget() local 756 mcr = mxport->mcr_state; mxuport_tiocmget() 761 result = (((mcr & UART_MCR_DTR) ? TIOCM_DTR : 0) | /* 0x002 */ mxuport_tiocmget() 762 ((mcr & UART_MCR_RTS) ? TIOCM_RTS : 0) | /* 0x004 */ mxuport_tiocmget()
H A D	whiteheat.h	243 __u8 mcr; /* copy of uart's MCR register */ member in struct:whiteheat_dr_info
/linux-4.1.27/drivers/tty/serial/
H A D	pxa.c	54 unsigned char mcr; member in struct:uart_pxa_port 306 unsigned char mcr = 0; serial_pxa_set_mctrl() local 309 mcr |= UART_MCR_RTS; serial_pxa_set_mctrl() 311 mcr |= UART_MCR_DTR; serial_pxa_set_mctrl() 313 mcr |= UART_MCR_OUT1; serial_pxa_set_mctrl() 315 mcr |= UART_MCR_OUT2; serial_pxa_set_mctrl() 317 mcr |= UART_MCR_LOOP; serial_pxa_set_mctrl() 319 mcr |= up->mcr; serial_pxa_set_mctrl() 321 serial_out(up, UART_MCR, mcr); serial_pxa_set_mctrl() 345 up->mcr |= UART_MCR_AFE; serial_pxa_startup() 347 up->mcr = 0; serial_pxa_startup() 533 up->mcr |= UART_MCR_AFE; serial_pxa_set_termios() 535 up->mcr &= ~UART_MCR_AFE; serial_pxa_set_termios()
H A D	serial-tegra.c	178 unsigned long mcr; set_rts() local 180 mcr = tup->mcr_shadow; set_rts() 182 mcr |= TEGRA_UART_MCR_RTS_EN; set_rts() 184 mcr &= ~TEGRA_UART_MCR_RTS_EN; set_rts() 185 if (mcr != tup->mcr_shadow) { set_rts() 186 tegra_uart_write(tup, mcr, UART_MCR); set_rts() 187 tup->mcr_shadow = mcr; set_rts() 194 unsigned long mcr; set_dtr() local 196 mcr = tup->mcr_shadow; set_dtr() 198 mcr |= UART_MCR_DTR; set_dtr() 200 mcr &= ~UART_MCR_DTR; set_dtr() 201 if (mcr != tup->mcr_shadow) { set_dtr() 202 tegra_uart_write(tup, mcr, UART_MCR); set_dtr() 203 tup->mcr_shadow = mcr; set_dtr() 211 unsigned long mcr; tegra_uart_set_mctrl() local 214 mcr = tup->mcr_shadow; tegra_uart_set_mctrl() 785 unsigned long mcr; tegra_uart_hw_deinit() local 793 mcr = tegra_uart_read(tup, UART_MCR); tegra_uart_hw_deinit() 794 if ((mcr & TEGRA_UART_MCR_CTS_EN) && (msr & UART_MSR_CTS)) tegra_uart_hw_deinit() 805 mcr = tegra_uart_read(tup, UART_MCR); tegra_uart_hw_deinit() 806 if ((mcr & TEGRA_UART_MCR_CTS_EN) && tegra_uart_hw_deinit()
H A D	serial_ks8695.c	297 unsigned int mcr; ks8695uart_set_mctrl() local 299 mcr = UART_GET_MCR(port); ks8695uart_set_mctrl() 301 mcr |= URMC_URRTS; ks8695uart_set_mctrl() 303 mcr &= ~URMC_URRTS; ks8695uart_set_mctrl() 306 mcr |= URMC_URDTR; ks8695uart_set_mctrl() 308 mcr &= ~URMC_URDTR; ks8695uart_set_mctrl() 310 UART_PUT_MCR(port, mcr); ks8695uart_set_mctrl()
H A D	omap-serial.c	142 unsigned char mcr; member in struct:uart_omap_port 684 unsigned char mcr = 0, old_mcr, lcr; serial_omap_set_mctrl() local 688 mcr |= UART_MCR_RTS; serial_omap_set_mctrl() 690 mcr |= UART_MCR_DTR; serial_omap_set_mctrl() 692 mcr |= UART_MCR_OUT1; serial_omap_set_mctrl() 694 mcr |= UART_MCR_OUT2; serial_omap_set_mctrl() 696 mcr |= UART_MCR_LOOP; serial_omap_set_mctrl() 702 up->mcr = old_mcr | mcr; serial_omap_set_mctrl() 703 serial_out(up, UART_MCR, up->mcr); serial_omap_set_mctrl() 982 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; serial_omap_set_termios() 983 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); serial_omap_set_termios() 1012 serial_out(up, UART_MCR, up->mcr); serial_omap_set_termios() 1061 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); serial_omap_set_termios() 1105 up->mcr |= UART_MCR_XONANY; serial_omap_set_termios() 1107 up->mcr &= ~UART_MCR_XONANY; serial_omap_set_termios() 1109 serial_out(up, UART_MCR, up->mcr); serial_omap_set_termios() 1815 serial_out(up, UART_MCR, up->mcr); serial_omap_restore_context()
H A D	vr41xx_siu.c	205 uint8_t mcr = 0; siu_set_mctrl() local 208 mcr |= UART_MCR_DTR; siu_set_mctrl() 210 mcr |= UART_MCR_RTS; siu_set_mctrl() 212 mcr |= UART_MCR_OUT1; siu_set_mctrl() 214 mcr |= UART_MCR_OUT2; siu_set_mctrl() 216 mcr |= UART_MCR_LOOP; siu_set_mctrl() 218 siu_write(port, UART_MCR, mcr); siu_set_mctrl()
H A D	nwpserial.c	38 unsigned int mcr; member in struct:nwpserial_port 174 up->mcr = dcr_read(up->dcr_host, UART_MCR) & ~UART_MCR_AFE; nwpserial_startup() 175 dcr_write(up->dcr_host, UART_MCR, up->mcr); nwpserial_startup()
H A D	pch_uart.c	244 unsigned int mcr; member in struct:eg20t_port 1215 u32 mcr = 0; pch_uart_set_mctrl() local 1219 mcr |= UART_MCR_DTR; pch_uart_set_mctrl() 1221 mcr |= UART_MCR_RTS; pch_uart_set_mctrl() 1223 mcr |= UART_MCR_LOOP; pch_uart_set_mctrl() 1225 if (priv->mcr & UART_MCR_AFE) pch_uart_set_mctrl() 1226 mcr |= UART_MCR_AFE; pch_uart_set_mctrl() 1229 iowrite8(mcr, priv->membase + UART_MCR); pch_uart_set_mctrl() 1425 priv->mcr |= UART_MCR_AFE; pch_uart_set_termios() 1427 priv->mcr &= ~UART_MCR_AFE; pch_uart_set_termios()
H A D	ioc3_serial.c	822 * @mask1: mcr mask 831 char mcr; set_mcr() local 848 mcr = (shadow & 0xff000000) >> 24; set_mcr() 851 mcr |= mask1; set_mcr() 853 writeb(mcr, &port->ip_uart_regs->iu_mcr); set_mcr() 1746 unsigned char mcr = 0; ic3_set_mctrl() local 1749 mcr |= UART_MCR_RTS; ic3_set_mctrl() 1751 mcr |= UART_MCR_DTR; ic3_set_mctrl() 1753 mcr |= UART_MCR_OUT1; ic3_set_mctrl() 1755 mcr |= UART_MCR_OUT2; ic3_set_mctrl() 1757 mcr |= UART_MCR_LOOP; ic3_set_mctrl() 1759 set_mcr(the_port, mcr, SHADOW_DTR); ic3_set_mctrl()
H A D	sunsu.c	587 unsigned char mcr = 0; sunsu_set_mctrl() local 590 mcr |= UART_MCR_RTS; sunsu_set_mctrl() 592 mcr |= UART_MCR_DTR; sunsu_set_mctrl() 594 mcr |= UART_MCR_OUT1; sunsu_set_mctrl() 596 mcr |= UART_MCR_OUT2; sunsu_set_mctrl() 598 mcr |= UART_MCR_LOOP; sunsu_set_mctrl() 600 serial_out(up, UART_MCR, mcr); sunsu_set_mctrl()
H A D	ioc4_serial.c	1552 * @mask1: mcr mask 1561 char mcr; set_mcr() local 1578 mcr = (shadow & 0xff000000) >> 24; set_mcr() 1581 mcr |= mask1; set_mcr() 1584 writeb(mcr, &port->ip_uart_regs->i4u_mcr); set_mcr() 2460 unsigned char mcr = 0; ic4_set_mctrl() local 2468 mcr |= UART_MCR_RTS; ic4_set_mctrl() 2470 mcr |= UART_MCR_DTR; ic4_set_mctrl() 2472 mcr |= UART_MCR_OUT1; ic4_set_mctrl() 2474 mcr |= UART_MCR_OUT2; ic4_set_mctrl() 2476 mcr |= UART_MCR_LOOP; ic4_set_mctrl() 2478 set_mcr(the_port, mcr, IOC4_SHADOW_DTR); ic4_set_mctrl()
/linux-4.1.27/arch/arm/mach-omap1/
H A D	sleep.S	73 mcr p15, 0, r0, c7, c10, 4 111 mcr p15, 0, r2, c1, c0, 0 119 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 127 mcr p15, 0, r9, c1, c0, 0 202 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 228 mcr p15, 0, r0, c7, c10, 4 268 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
/linux-4.1.27/arch/arm/mach-omap2/
H A D	sleep24xx.S	68 mov r3, #0x0 @ clear for mcr call 69 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 77 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
H A D	sram34xx.S	159 mcr p15, 0, r10, c1, c0, 0 @ write ctrl register 179 mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
H A D	sleep34xx.S	203 mcr p15, 0, r0, c1, c0, 0 432 mcr p15, 0, r0, c1, c0, 1 505 mcr p15, 0, r1, c1, c0, 1
H A D	sram242x.S	152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
H A D	sram243x.S	152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
H A D	pm24xx.c	157 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc"); omap2_enter_mpu_retention()
/linux-4.1.27/drivers/i2c/busses/
H A D	i2c-nomadik.c	305 u32 mcr = 0; load_i2c_mcr_reg() local 308 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); load_i2c_mcr_reg() 312 mcr |= GEN_MASK(2, I2C_MCR_AM, 12); load_i2c_mcr_reg() 321 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); load_i2c_mcr_reg() 324 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); load_i2c_mcr_reg() 328 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); load_i2c_mcr_reg() 332 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); load_i2c_mcr_reg() 334 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); load_i2c_mcr_reg() 338 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); load_i2c_mcr_reg() 340 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); load_i2c_mcr_reg() 342 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15); load_i2c_mcr_reg() 344 return mcr; load_i2c_mcr_reg() 450 u32 mcr, irq_mask; read_i2c() local 453 mcr = load_i2c_mcr_reg(dev, flags); read_i2c() 454 writel(mcr, dev->virtbase + I2C_MCR); read_i2c() 519 u32 mcr, irq_mask; write_i2c() local 522 mcr = load_i2c_mcr_reg(dev, flags); write_i2c() 524 writel(mcr, dev->virtbase + I2C_MCR); write_i2c()
/linux-4.1.27/arch/arm/mach-s5pv210/
H A D	pm.c	55 "mcr p15, 0, %0, c7, c10, 5\n\t" s5pv210_cpu_suspend() 56 "mcr p15, 0, %0, c7, c10, 4\n\t" s5pv210_cpu_suspend()
/linux-4.1.27/arch/arm/mach-rockchip/
H A D	sleep.S	43 mcr p15, 1, r3, c9, c0, 2
/linux-4.1.27/arch/arm/mach-zynq/
H A D	common.h	46 "mcr p15, 0, r12, c15, c0, 0\n" zynq_core_pm_init()
/linux-4.1.27/arch/arm/plat-iop/
H A D	cp6.c	31 "mcr p15, 0, %0, c15, c1, 0\n\t" cp6_trap()
/linux-4.1.27/arch/arm/mach-omap1/include/mach/
H A D	mtd-xip.h	59 #define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
/linux-4.1.27/drivers/sn/
H A D	ioc3.c	42 unsigned mcr; nic_wait() local 45 mcr = readl(&idd->vma->mcr); nic_wait() 46 } while (!(mcr & 2)); nic_wait() 48 return mcr & 1; nic_wait() 57 writel(mcr_pack(500, 65), &idd->vma->mcr); nic_reset() 72 writel(mcr_pack(6, 13), &idd->vma->mcr); nic_read_bit() 84 writel(mcr_pack(6, 110), &idd->vma->mcr); nic_write_bit() 86 writel(mcr_pack(80, 30), &idd->vma->mcr); nic_write_bit()
/linux-4.1.27/drivers/staging/comedi/drivers/
H A D	mite.c	352 unsigned int chor, chcr, mcr, dcr, lkcr; mite_prep_dma() local 387 mcr = CR_RL(64) | CR_ASEQUP; mite_prep_dma() 390 mcr |= CR_PSIZE8; mite_prep_dma() 393 mcr |= CR_PSIZE16; mite_prep_dma() 396 mcr |= CR_PSIZE32; mite_prep_dma() 402 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); mite_prep_dma()
/linux-4.1.27/arch/arm64/kernel/
H A D	armv8_deprecated.c	476 * dmb - mcr p15, 0, Rt, c7, c10, 5 cp15barrier_handler() 477 * dsb - mcr p15, 0, Rt, c7, c10, 4 cp15barrier_handler() 482 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc); cp15barrier_handler() 486 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc); cp15barrier_handler() 491 * isb - mcr p15, 0, Rt, c7, c5, 4 cp15barrier_handler() 497 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc); cp15barrier_handler()
/linux-4.1.27/drivers/dma/
H A D	txx9dmac.c	655 u32 mcr; txx9dmac_tasklet() local 658 mcr = dma_readl(ddev, MCR); txx9dmac_tasklet() 659 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr); txx9dmac_tasklet() 661 if ((mcr >> (24 + i)) & 0x11) { txx9dmac_tasklet() 1180 u32 mcr; txx9dmac_probe() local 1217 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE; txx9dmac_probe() 1219 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan); txx9dmac_probe() 1220 dma_writel(ddev, MCR, mcr); txx9dmac_probe() 1257 u32 mcr; txx9dmac_resume_noirq() local 1259 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE; txx9dmac_resume_noirq() 1261 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan); txx9dmac_resume_noirq() 1262 dma_writel(ddev, MCR, mcr); txx9dmac_resume_noirq()
/linux-4.1.27/drivers/gpu/drm/gma500/
H A D	psb_drv.h	788 int mcr = (0xD0<<24) | (port << 16) | (offset << 8); MRST_MSG_READ32() local 791 pci_write_config_dword(pci_root, 0xD0, mcr); MRST_MSG_READ32() 798 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; MRST_MSG_WRITE32() local 801 pci_write_config_dword(pci_root, 0xD0, mcr); MRST_MSG_WRITE32() 806 int mcr = (0x10<<24) | (port << 16) | (offset << 8); MDFLD_MSG_READ32() local 809 pci_write_config_dword(pci_root, 0xD0, mcr); MDFLD_MSG_READ32() 816 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; MDFLD_MSG_WRITE32() local 819 pci_write_config_dword(pci_root, 0xD0, mcr); MDFLD_MSG_WRITE32()
H A D	cdv_device.c	190 int mcr = (0x10<<24) | (port << 16) | (offset << 8); CDV_MSG_READ32() local 193 pci_write_config_dword(pci_root, 0xD0, mcr); CDV_MSG_READ32() 201 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; CDV_MSG_WRITE32() local 204 pci_write_config_dword(pci_root, 0xD0, mcr); CDV_MSG_WRITE32()
/linux-4.1.27/arch/x86/include/asm/
H A D	mtrr.h	43 extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); 84 static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) mtrr_centaur_report_mcr() argument
/linux-4.1.27/arch/arm/mach-tegra/
H A D	sleep.S	55 mcr p15, 0, r2, c1, c0, 0 132 mcr p15, 0, r3, c1, c0, 0
H A D	reset-handler.S	132 mcr p15, 0, r0, c1, c0, 0 @ write system control register 136 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 149 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
H A D	sleep-tegra20.S	292 mcr p15, 0, r10, c1, c0, 0 295 mcr p15, 0, r11, c1, c0, 1 @ reenable coherency 299 mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs 300 mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
H A D	sleep.h	103 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
/linux-4.1.27/arch/arm/mach-hisi/
H A D	hotplug.c	255 " mcr p15, 0, %0, c1, c0, 1\n" cpu_enter_lowpower() 258 " mcr p15, 0, %0, c1, c0, 0\n" cpu_enter_lowpower()
H A D	platmcpm.c	168 "mcr p15, 1, %0, c15, c0, 3 \n\t" hip04_mcpm_power_down()
/linux-4.1.27/arch/arm/vfp/
H A D	vfpinstr.h	82 asm("mcr p10, 7, %0, " vfpreg(_vfp_) ", cr0, 0 @ fmxr " #_vfp_ ", %0" \
H A D	vfphw.S	277 1: mcr p10, 0, r0, c\dr, c0, 0 @ fmsr r0, s0 280 1: mcr p10, 0, r0, c\dr, c0, 4 @ fmsr r0, s1
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A D	sleep-s3c2412.S	52 mcr p15, 0, r0, c7, c10, 4
/linux-4.1.27/arch/arm/mach-mvebu/
H A D	pmsu_ll.S	40 mcr p15, 0, r1, c1, c0, 0
/linux-4.1.27/drivers/pcmcia/
H A D	pxa2xx_sharpsl.c	115 unsigned short cpr, ncpr, ccr, nccr, mcr, nmcr, imr, nimr; sharpsl_pcmcia_configure_socket() local 133 nmcr = (mcr = read_scoop_reg(scoop, SCOOP_MCR)) & ~0x0010; sharpsl_pcmcia_configure_socket() 164 if (mcr != nmcr) sharpsl_pcmcia_configure_socket()
/linux-4.1.27/arch/mips/dec/
H A D	ecc-berr.c	249 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); dec_kn03_be_init() local 262 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | dec_kn03_be_init()
/linux-4.1.27/arch/arm/mach-s3c64xx/
H A D	pm.c	276 "mcr p15, 0, %0, c7, c10, 5\n\t" s3c64xx_cpu_suspend() 277 "mcr p15, 0, %0, c7, c10, 4\n\t" s3c64xx_cpu_suspend() 278 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); s3c64xx_cpu_suspend()
/linux-4.1.27/arch/arm/common/
H A D	scoop.c	147 unsigned short mcr; check_scoop_reg() local 149 mcr = ioread16(sdev->base + SCOOP_MCR); check_scoop_reg() 150 if ((mcr & 0x100) == 0) check_scoop_reg()
/linux-4.1.27/arch/arm/mach-exynos/
H A D	mcpm-exynos.c	47 "mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \ 56 "mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \ 143 "mcr p15, 1, %0, c15, c0, 3\n\t" exynos_cluster_cache_disable()
H A D	pm.c	81 asm volatile ("mcr p15, 0, %0, c15, c0, 0" exynos_cpu_restore_register() 88 asm volatile ("mcr p15, 0, %0, c15, c0, 1" exynos_cpu_restore_register()
H A D	platsmp.c	45 " mcr p15, 0, %0, c1, c0, 0\n" cpu_leave_lowpower() 48 " mcr p15, 0, %0, c1, c0, 1\n" cpu_leave_lowpower()
/linux-4.1.27/drivers/video/fbdev/
H A D	cg14.c	101 u8 mcr; /* Master Control Reg */ member in struct:cg14_regs 211 val = sbus_readb(&regs->mcr); __cg14_reset() 213 sbus_writeb(val, &regs->mcr); __cg14_reset() 314 cur_mode = sbus_readb(&regs->mcr); cg14_ioctl() 335 sbus_writeb(cur_mode, &regs->mcr); cg14_ioctl()
/linux-4.1.27/drivers/mtd/maps/
H A D	pxa2xx-flash.c	37 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); pxa2xx_map_inval_cache()
/linux-4.1.27/drivers/usb/phy/
H A D	phy-mv-usb.h	133 u32 mcr; /* Mux Control */ member in struct:mv_otg_regs
/linux-4.1.27/arch/arm/mach-sa1100/
H A D	sleep.S	34 mcr p15, 0, r1, c15, c2, 2
/linux-4.1.27/sound/pci/ice1712/
H A D	quartet.c	41 unsigned int mcr; /* monitoring control register */ member in struct:qtet_spec 460 return spec->mcr; get_mcr() 480 spec->mcr = val; set_mcr() 686 PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr), 687 PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr), 688 PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr), 689 PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr), 690 PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr), 691 PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
/linux-4.1.27/arch/arm/mach-at91/
H A D	pm_suspend.S	66 mcr p15, 0, tmp1, c7, c0, 4 92 mcr p15, 0, tmp1, c7, c10, 4
H A D	pm.c	241 "1: mcr p15, 0, %0, c7, c10, 4\n\t" at91rm9200_standby() 244 " mcr p15, 0, %0, c7, c0, 4\n\t" at91rm9200_standby()
/linux-4.1.27/arch/arm/mach-ebsa110/
H A D	core.c	297 asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc"); ebsa110_idle() 303 asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); ebsa110_idle()
/linux-4.1.27/arch/arm/mach-ep93xx/
H A D	core.c	269 unsigned int mcr; ep93xx_uart_set_mctrl() local 271 mcr = 0; ep93xx_uart_set_mctrl() 273 mcr |= 2; ep93xx_uart_set_mctrl() 275 mcr |= 1; ep93xx_uart_set_mctrl() 277 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); ep93xx_uart_set_mctrl()
/linux-4.1.27/drivers/mmc/card/
H A D	sdio_uart.c	222 unsigned char mcr = 0; sdio_uart_write_mctrl() local 225 mcr |= UART_MCR_RTS; sdio_uart_write_mctrl() 227 mcr |= UART_MCR_DTR; sdio_uart_write_mctrl() 229 mcr |= UART_MCR_OUT1; sdio_uart_write_mctrl() 231 mcr |= UART_MCR_OUT2; sdio_uart_write_mctrl() 233 mcr |= UART_MCR_LOOP; sdio_uart_write_mctrl() 235 sdio_out(port, UART_MCR, mcr); sdio_uart_write_mctrl()
/linux-4.1.27/drivers/cpufreq/
H A D	pxa3xx-cpufreq.c	129 __asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg)); __update_core_freq()
H A D	sa1110-cpufreq.c	277 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); sa1110_target()
H A D	pxa2xx-cpufreq.c	331 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ pxa_set_target()
/linux-4.1.27/include/linux/
H A D	serial_8250.h	97 unsigned char mcr; member in struct:uart_8250_port
/linux-4.1.27/arch/sh/include/asm/
H A D	smc37c93x.h	75 volatile __u16 mcr; member in struct:uart_reg
/linux-4.1.27/arch/arm/mach-vt8500/
H A D	vt8500.c	72 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (0)); vt8500_power_off()
/linux-4.1.27/drivers/ide/
H A D	hpt366.c	781 u8 mcr = 0, mcr_addr = hwif->select_data; hpt374_dma_end() local 785 pci_read_config_byte(dev, mcr_addr, &mcr); hpt374_dma_end() 787 pci_write_config_byte(dev, mcr_addr, mcr | 0x30); hpt374_dma_end() 1173 u16 mcr; hpt3xx_cable_detect() local 1175 pci_read_config_word(dev, mcr_addr, &mcr); hpt3xx_cable_detect() 1176 pci_write_config_word(dev, mcr_addr, mcr | 0x8000); hpt3xx_cable_detect() 1180 pci_write_config_word(dev, mcr_addr, mcr); hpt3xx_cable_detect()
/linux-4.1.27/drivers/isdn/i4l/
H A D	isdn_tty.c	71 if (!(info->mcr & UART_MCR_RTS)) isdn_tty_try_read() 142 if (info->mcr & UART_MCR_RTS) { isdn_tty_readmodem() 1023 info->mcr |= UART_MCR_DTR; isdn_tty_change_speed() 1026 info->mcr &= ~UART_MCR_DTR; isdn_tty_change_speed() 1065 info->mcr = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; isdn_tty_startup() 1094 info->mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); isdn_tty_shutdown() 1299 info->mcr &= ~UART_MCR_RTS; isdn_tty_throttle() 1315 info->mcr |= UART_MCR_RTS; isdn_tty_unthrottle() 1362 control = info->mcr; isdn_tty_tiocmget() 1390 info->mcr |= UART_MCR_RTS; isdn_tty_tiocmset() 1392 info->mcr |= UART_MCR_DTR; isdn_tty_tiocmset() 1397 info->mcr &= ~UART_MCR_RTS; isdn_tty_tiocmset() 1399 info->mcr &= ~UART_MCR_DTR; isdn_tty_tiocmset()
/linux-4.1.27/drivers/net/ethernet/sgi/
H A D	ioc3-eth.c	170 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr) 171 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0) 231 u32 mcr; nic_wait() local 234 mcr = ioc3_r_mcr(); nic_wait() 235 } while (!(mcr & 2)); nic_wait() 237 return mcr & 1; nic_wait()
/linux-4.1.27/drivers/net/ethernet/smsc/
H A D	smc911x.c	1301 unsigned int mcr, update_multicast = 0; smc911x_set_multicast_list() local 1307 SMC_GET_MAC_CR(lp, mcr); smc911x_set_multicast_list() 1313 mcr |= MAC_CR_PRMS_; smc911x_set_multicast_list() 1322 mcr |= MAC_CR_MCPAS_; smc911x_set_multicast_list() 1341 mcr |= MAC_CR_HPFILT_; smc911x_set_multicast_list() 1356 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); 1362 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); 1373 SMC_SET_MAC_CR(lp, mcr);
/linux-4.1.27/drivers/tty/serial/jsm/
H A D	jsm.h	273 u8 mcr; /* WR MCR - Modem Control Reg */ member in struct:cls_uart_struct 328 u8 mcr; /* WR MCR - Modem Control Reg */ member in struct:neo_uart_struct
/linux-4.1.27/arch/blackfin/include/asm/
H A D	bfin_serial.h	237 __BFP(mcr); 259 __BFP(mcr);
/linux-4.1.27/drivers/tty/serial/8250/
H A D	8250_omap.c	269 serial_out(up, UART_MCR, up->mcr); omap8250_restore_regs() 420 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); omap_8250_set_termios() 453 up->mcr |= UART_MCR_XONANY; omap_8250_set_termios() 607 up->mcr = 0; omap_8250_startup()
H A D	8250_core.c	2008 unsigned char mcr = 0; serial8250_do_set_mctrl() local 2011 mcr |= UART_MCR_RTS; serial8250_do_set_mctrl() 2013 mcr |= UART_MCR_DTR; serial8250_do_set_mctrl() 2015 mcr |= UART_MCR_OUT1; serial8250_do_set_mctrl() 2017 mcr |= UART_MCR_OUT2; serial8250_do_set_mctrl() 2019 mcr |= UART_MCR_LOOP; serial8250_do_set_mctrl() 2021 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; serial8250_do_set_mctrl() 2023 serial_port_out(port, UART_MCR, mcr); serial8250_do_set_mctrl() 2161 up->mcr = 0; serial8250_do_startup() 2606 up->mcr &= ~UART_MCR_AFE; serial8250_do_set_termios() 2608 up->mcr |= UART_MCR_AFE; serial8250_do_set_termios()
/linux-4.1.27/drivers/usb/gadget/udc/
H A D	mv_udc.h	168 u32 mcr; /* Mux Control */ member in struct:mv_op_regs
/linux-4.1.27/arch/ia64/include/asm/sn/
H A D	ioc3.h	72 uint32_t mcr; member in struct:ioc3
/linux-4.1.27/drivers/atm/
H A D	iphase.c	361 srv_p->mcr = 0; init_abr_vc() 391 if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate) ia_open_abr_vc() 393 if (srv_p->mcr > srv_p->pcr) ia_open_abr_vc() 397 if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr)) ia_open_abr_vc() 437 f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr); ia_open_abr_vc() 451 dev->sum_mcr += srv_p->mcr; ia_open_abr_vc() 1846 srv_p.mcr = vcc->qos.txtp.min_pcr; open_tx() 1849 else srv_p.mcr = 0; open_tx() 1870 IF_ABR(printk("ABR:vcc->qos.txtp.max_pcr = %d mcr = %d\n", open_tx() 1871 srv_p.pcr, srv_p.mcr);) open_tx()
/linux-4.1.27/drivers/net/irda/
H A D	nsc-ircc.c	1257 __u8 mcr = MCR_SIR; nsc_ircc_change_speed() local 1294 mcr = MCR_MIR; nsc_ircc_change_speed() 1298 mcr = MCR_MIR; nsc_ircc_change_speed() 1302 mcr = MCR_FIR; nsc_ircc_change_speed() 1306 mcr = MCR_FIR; nsc_ircc_change_speed() 1314 outb(mcr | MCR_TX_DFR, iobase+MCR); nsc_ircc_change_speed()
/linux-4.1.27/arch/mips/include/asm/txx9/
H A D	tx3927.h	49 volatile unsigned long mcr; member in struct:tx3927_dma_reg

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