/linux-4.1.27/arch/arm/mm/ |
D | proc-arm940.S | 43 mcr p15, 0, r0, c1, c0, 0 @ disable caches 54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 56 mcr p15, 0, ip, c7, c10, 4 @ drain WB 60 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 116 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 166 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index [all …]
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D | proc-mohawk.S | 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches 75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 76 mcr p15, 0, ip, c7, c10, 4 @ drain WB 77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt 105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry [all …]
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D | proc-arm946.S | 50 mcr p15, 0, r0, c1, c0, 0 @ disable caches 61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache 62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 63 mcr p15, 0, ip, c7, c10, 4 @ drain WB 67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache 111 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index 141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
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D | proc-fa526.S | 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 64 mcr p15, 0, ip, c7, c10, 4 @ drain WB 66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 72 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 92 mcr p15, 0, r0, c7, c10, 4 @ drain WB 109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache [all …]
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D | proc-arm1020.S | 83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 159 mcr p15, 0, ip, c7, c10, 4 @ drain WB [all …]
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D | proc-arm926.S | 67 mcr p15, 0, r0, c1, c0, 0 @ disable caches 83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 84 mcr p15, 0, ip, c7, c10, 4 @ drain WB 86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 91 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 110 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 112 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
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D | proc-arm925.S | 98 mcr p15, 0, r0, c1, c0, 0 @ disable caches 123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 124 mcr p15, 0, ip, c7, c10, 4 @ drain WB 126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 131 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 145 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache 146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 147 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
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D | proc-arm920.S | 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c7, c10, 4 @ drain WB 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 99 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 207 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
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D | proc-sa1100.S | 44 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 45 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland 56 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c7, c10, 4 @ drain WB 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 84 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 111 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching 113 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt [all …]
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D | proc-v6.S | 45 mcr p15, 0, r0, c1, c0, 0 @ disable caches 62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 64 mcr p15, 0, r1, c7, c5, 4 @ ISB 78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode 79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt 83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 106 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 107 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 114 mcr p15, 0, r1, c13, c0, 1 @ set context ID [all …]
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D | proc-arm922.S | 77 mcr p15, 0, r0, c1, c0, 0 @ disable caches 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c7, c10, 4 @ drain WB 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 101 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 209 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
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D | proc-feroceon.S | 81 mcr p15, 1, r0, c15, c9, 0 @ clean L2 82 mcr p15, 0, r0, c7, c10, 4 @ drain WB 88 mcr p15, 0, r0, c1, c0, 0 @ disable caches 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 105 mcr p15, 0, ip, c7, c10, 4 @ drain WB 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 125 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer 126 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
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D | proc-arm1020e.S | 83 mcr p15, 0, r0, c1, c0, 0 @ disable caches 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 100 mcr p15, 0, ip, c7, c10, 4 @ drain WB 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 107 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 155 mcr p15, 0, ip, c7, c10, 4 @ drain WB 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry [all …]
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D | cache-v6.S | 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 137 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line 144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer [all …]
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D | proc-xscale.S | 94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 120 mcr p15, 0, r1, c1, c0, 1 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches 149 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB 150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 156 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB [all …]
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D | proc-xsc3.S | 71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 95 mcr p15, 0, r0, c1, c0, 0 @ disable caches 115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 118 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 140 mcr p14, 0, r0, c7, c0, 0 @ go to idle 152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line [all …]
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D | proc-arm1026.S | 74 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 212 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry [all …]
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D | proc-arm1022.S | 74 mcr p15, 0, r0, c1, c0, 0 @ disable caches 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 91 mcr p15, 0, ip, c7, c10, 4 @ drain WB 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 98 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry [all …]
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D | proc-sa110.S | 40 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching 48 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching 52 mcr p15, 0, r0, c1, c0, 0 @ disable caches 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 69 mcr p15, 0, ip, c7, c10, 4 @ drain WB 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 76 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 95 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching 101 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned 105 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching [all …]
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D | cache-fa.S | 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 137 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 138 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush 152 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache [all …]
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D | proc-arm740.S | 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches 55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 58 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches 68 mcr p15, 0, r0, c6, c3 @ disable area 3~7 69 mcr p15, 0, r0, c6, c4 70 mcr p15, 0, r0, c6, c5 71 mcr p15, 0, r0, c6, c6 72 mcr p15, 0, r0, c6, c7 75 mcr p15, 0, r0, c6, c0 @ set area 0, default [all …]
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D | tlb-v6.S | 40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier 71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA 86 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier 87 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
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D | cache-v4wb.S | 61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 80 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 97 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 119 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 120 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 166 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 167 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 172 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 173 mcr p15, 0, r0, c7, c10, 4 @ drain WB 194 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry [all …]
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D | tlb-fa.S | 43 mcr p15, 0, r3, c7, c10, 4 @ drain WB 46 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 50 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 56 mcr p15, 0, r3, c7, c10, 4 @ drain WB 59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 63 mcr p15, 0, r3, c7, c10, 4 @ data write barrier 64 mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb)
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D | proc-arm720.S | 60 mcr p15, 0, r0, c1, c0, 0 @ disable caches 80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 81 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr 82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) 107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) 114 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) 150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches [all …]
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D | proc-v7.S | 36 mcr p15, 0, r0, c1, c0, 0 @ disable caches 58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0 [all …]
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D | tlb-v4wb.S | 39 mcr p15, 0, r3, c7, c10, 4 @ drain WB 44 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 61 mcr p15, 0, r3, c7, c10, 4 @ drain WB 64 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB 65 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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D | tlb-v4wbi.S | 38 mcr p15, 0, r3, c7, c10, 4 @ drain WB 44 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 52 mcr p15, 0, r3, c7, c10, 4 @ drain WB 55 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 56 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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D | tlb-v7.S | 50 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 52 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 54 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA 79 ALT_SMP(mcr p15, 0, r0, c8, c3, 3) @ TLB invalidate U MVA all ASID (shareable) 81 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable) 83 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
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D | cache-v7.S | 36 mcr p15, 2, r0, c0, c0, 0 58 mcr p15, 0, r5, c7, c6, 2 77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 78 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 135 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 157 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 168 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 190 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 191 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 208 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable [all …]
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D | cache-v4wt.S | 51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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D | proc-v7-2level.S | 44 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 60 mcr p15, 0, r1, c13, c0, 1 @ set context ID 62 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 111 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 152 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register 157 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1
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D | cache-v4.S | 43 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache 62 mcr p15, 0, ip, c7, c7, 0 @ flush ID cache 118 mcr p15, 0, r0, c7, c7, 0 @ flush ID cache
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D | proc-v7-3level.S | 99 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 145 mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
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D | tlb-v4.S | 41 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
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D | abort-ev7.S | 33 mcr p15, 0, r0, c7, c8, 0 @ Retranslate FAR
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D | proc-macros.S | 174 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 257 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line 258 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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/linux-4.1.27/arch/x86/kernel/ |
D | iosf_mbi.c | 43 static int iosf_mbi_pci_read_mdr(u32 mcrx, u32 mcr, u32 *mdr) in iosf_mbi_pci_read_mdr() argument 57 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); in iosf_mbi_pci_read_mdr() 72 static int iosf_mbi_pci_write_mdr(u32 mcrx, u32 mcr, u32 mdr) in iosf_mbi_pci_write_mdr() argument 90 result = pci_write_config_dword(mbi_pdev, MBI_MCR_OFFSET, mcr); in iosf_mbi_pci_write_mdr() 103 u32 mcr, mcrx; in iosf_mbi_read() local 113 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); in iosf_mbi_read() 117 ret = iosf_mbi_pci_read_mdr(mcrx, mcr, mdr); in iosf_mbi_read() 126 u32 mcr, mcrx; in iosf_mbi_write() local 136 mcr = iosf_mbi_form_mcr(opcode, port, offset & MBI_MASK_LO); in iosf_mbi_write() 140 ret = iosf_mbi_pci_write_mdr(mcrx, mcr, mdr); in iosf_mbi_write() [all …]
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/linux-4.1.27/drivers/mtd/nand/ |
D | txx9ndfmc.c | 118 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_write_buf() local 120 txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); in txx9ndfmc_write_buf() 123 txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); in txx9ndfmc_write_buf() 144 u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); in txx9ndfmc_cmd_ctrl() local 146 mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); in txx9ndfmc_cmd_ctrl() 147 mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; in txx9ndfmc_cmd_ctrl() 148 mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; in txx9ndfmc_cmd_ctrl() 150 mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; in txx9ndfmc_cmd_ctrl() 152 mcr &= ~TXX9_NDFMCR_CS_MASK; in txx9ndfmc_cmd_ctrl() 153 mcr |= TXX9_NDFMCR_CS(txx9_priv->cs); in txx9ndfmc_cmd_ctrl() [all …]
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/linux-4.1.27/arch/arm/boot/compressed/ |
D | head.S | 33 mcr p14, 0, \ch, c0, c5, 0 39 mcr p14, 0, \ch, c8, c0, 0 45 mcr p14, 0, \ch, c1, c0, 0 618 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 619 mcr p15, 0, r0, c6, c7, 1 622 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 623 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 624 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 627 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 628 mcr p15, 0, r0, c5, c0, 0 @ D-access permission [all …]
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D | head-xscale.S | 26 mcr p15, 0, r0, c7, c10, 4 @ drain WB 27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 33 mcr p15, 0, r0, c1, c0, 0
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D | big-endian.S | 12 mcr p15, 0, r0, c1, c0, 0 @ write control reg
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/linux-4.1.27/arch/sh/drivers/pci/ |
D | fixups-landisk.c | 43 unsigned long bcr1, mcr; in pci_fixup_pcic() local 49 mcr = __raw_readl(SH7751_MCR); in pci_fixup_pcic() 50 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; in pci_fixup_pcic() 51 pci_write_reg(chan, mcr, SH4_PCIMCR); in pci_fixup_pcic()
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D | fixups-rts7751r2d.c | 44 unsigned long bcr1, mcr; in pci_fixup_pcic() local 57 mcr = __raw_readl(SH7751_MCR); in pci_fixup_pcic() 58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; in pci_fixup_pcic() 59 pci_write_reg(chan, mcr, SH4_PCIMCR); in pci_fixup_pcic()
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D | fixups-se7751.c | 40 unsigned long bcr1, wcr1, wcr2, wcr3, mcr; in pci_fixup_pcic() local 55 mcr = (*(volatile unsigned long*)(SH7751_MCR)); in pci_fixup_pcic() 66 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; in pci_fixup_pcic() 67 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */ in pci_fixup_pcic()
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/linux-4.1.27/arch/arm/kvm/ |
D | interrupts_head.S | 339 mcr p15, 0, r2, c14, c1, 0 @ CNTKCTL 341 mcr p15, 0, r6, c10, c3, 0 @ AMAIR0 342 mcr p15, 0, r7, c10, c3, 1 @ AMAIR1 360 mcr p15, 0, r2, c13, c0, 1 @ CID 361 mcr p15, 0, r3, c13, c0, 2 @ TID_URW 362 mcr p15, 0, r4, c13, c0, 3 @ TID_URO 363 mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV 364 mcr p15, 0, r6, c5, c0, 0 @ DFSR 365 mcr p15, 0, r7, c5, c0, 1 @ IFSR 366 mcr p15, 0, r8, c5, c1, 0 @ ADFSR [all …]
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D | init.S | 85 mcr p15, 4, r0, c2, c0, 2 @ HTCR 93 mcr p15, 4, r1, c2, c1, 2 @ VTCR 98 mcr p15, 4, r0, c10, c2, 0 100 mcr p15, 4, r0, c10, c2, 1 103 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH 126 mcr p15, 4, r0, c1, c0, 0 @ HSCR 136 mcr p15, 4, r1, c12, c0, 0 @ HVBAR
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D | interrupts.S | 57 mcr p15, 0, r0, c8, c3, 0 @ TLBIALLIS (rt ignored) 90 mcr p15, 4, r0, c8, c3, 4 92 mcr p15, 0, r0, c7, c1, 0 108 mcr p15, 4, vcpu, c13, c0, 2 @ HTPIDR 196 mcr p15, 4, r2, c0, c0, 0 200 mcr p15, 4, r2, c0, c0, 5 447 mcr p15, 0, r2, c7, c8, 0 @ ATS1CPR
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/linux-4.1.27/drivers/spi/ |
D | spi-txx9.c | 155 u32 mcr; in txx9spi_work_one() local 162 mcr = txx9spi_rd(c, TXx9_SPMCR); in txx9spi_work_one() 163 if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) { in txx9spi_work_one() 168 mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR); in txx9spi_work_one() 171 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); in txx9spi_work_one() 195 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, in txx9spi_work_one() 199 txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR); in txx9spi_work_one() 278 txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); in txx9spi_work_one() 330 u32 mcr; in txx9spi_probe() local 365 mcr = txx9spi_rd(c, TXx9_SPMCR); in txx9spi_probe() [all …]
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/linux-4.1.27/drivers/net/can/ |
D | flexcan.c | 211 u32 mcr; /* 0x00 */ member 343 reg = flexcan_read(®s->mcr); in flexcan_chip_enable() 345 flexcan_write(reg, ®s->mcr); in flexcan_chip_enable() 347 while (timeout-- && (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_chip_enable() 350 if (flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) in flexcan_chip_enable() 362 reg = flexcan_read(®s->mcr); in flexcan_chip_disable() 364 flexcan_write(reg, ®s->mcr); in flexcan_chip_disable() 366 while (timeout-- && !(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_chip_disable() 369 if (!(flexcan_read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_chip_disable() 381 reg = flexcan_read(®s->mcr); in flexcan_chip_freeze() [all …]
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/linux-4.1.27/drivers/i2c/busses/ |
D | i2c-nomadik.c | 305 u32 mcr = 0; in load_i2c_mcr_reg() local 308 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1); in load_i2c_mcr_reg() 312 mcr |= GEN_MASK(2, I2C_MCR_AM, 12); in load_i2c_mcr_reg() 321 mcr |= GEN_MASK(slave_adr_3msb_bits, I2C_MCR_EA10, 8); in load_i2c_mcr_reg() 324 mcr |= GEN_MASK(1, I2C_MCR_AM, 12); in load_i2c_mcr_reg() 328 mcr |= GEN_MASK(0, I2C_MCR_SB, 11); in load_i2c_mcr_reg() 332 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0); in load_i2c_mcr_reg() 334 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0); in load_i2c_mcr_reg() 338 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14); in load_i2c_mcr_reg() 340 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14)); in load_i2c_mcr_reg() [all …]
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/linux-4.1.27/drivers/net/wan/ |
D | n2.c | 171 u8 mcr = inb(io + N2_MCR); in n2_set_iface() local 178 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; in n2_set_iface() 184 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; in n2_set_iface() 190 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; in n2_set_iface() 196 mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0; in n2_set_iface() 201 outb(mcr, io + N2_MCR); in n2_set_iface() 215 u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0); in n2_open() local 222 mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */ in n2_open() 223 outb(mcr, io + N2_MCR); in n2_open() 238 u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0); in n2_close() local [all …]
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/linux-4.1.27/arch/sh/boards/mach-hp6xx/ |
D | pm.c | 43 u16 frqcr, mcr; in pm_enter() local 66 mcr = __raw_readw(MCR); in pm_enter() 67 __raw_writew(mcr & ~MCR_RFSH, MCR); in pm_enter() 78 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR); in pm_enter()
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/linux-4.1.27/drivers/usb/serial/ |
D | ark3116.c | 73 __u32 mcr; /* modem control register value */ member 161 priv->mcr = 0; in ark3116_port_probe() 442 ctrl = priv->mcr; in ark3116_tiocmget() 472 priv->mcr |= UART_MCR_RTS; in ark3116_tiocmset() 474 priv->mcr |= UART_MCR_DTR; in ark3116_tiocmset() 476 priv->mcr |= UART_MCR_OUT1; in ark3116_tiocmset() 478 priv->mcr |= UART_MCR_OUT2; in ark3116_tiocmset() 480 priv->mcr &= ~UART_MCR_RTS; in ark3116_tiocmset() 482 priv->mcr &= ~UART_MCR_DTR; in ark3116_tiocmset() 484 priv->mcr &= ~UART_MCR_OUT1; in ark3116_tiocmset() [all …]
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D | ti_usb_3410_5052.c | 117 static int ti_set_mcr(struct ti_port *tport, unsigned int mcr); 712 unsigned int mcr; in ti_set_termios() local 823 mcr = tport->tp_shadow_mcr; in ti_set_termios() 826 mcr &= ~(TI_MCR_DTR | TI_MCR_RTS); in ti_set_termios() 827 status = ti_set_mcr(tport, mcr); in ti_set_termios() 843 unsigned int mcr; in ti_tiocmget() local 851 mcr = tport->tp_shadow_mcr; in ti_tiocmget() 854 result = ((mcr & TI_MCR_DTR) ? TIOCM_DTR : 0) in ti_tiocmget() 855 | ((mcr & TI_MCR_RTS) ? TIOCM_RTS : 0) in ti_tiocmget() 856 | ((mcr & TI_MCR_LOOP) ? TIOCM_LOOP : 0) in ti_tiocmget() [all …]
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D | mos7720.c | 1745 unsigned int mcr ; in mos7720_tiocmget() local 1748 mcr = mos7720_port->shadowMCR; in mos7720_tiocmget() 1751 result = ((mcr & UART_MCR_DTR) ? TIOCM_DTR : 0) /* 0x002 */ in mos7720_tiocmget() 1752 | ((mcr & UART_MCR_RTS) ? TIOCM_RTS : 0) /* 0x004 */ in mos7720_tiocmget() 1766 unsigned int mcr ; in mos7720_tiocmset() local 1768 mcr = mos7720_port->shadowMCR; in mos7720_tiocmset() 1771 mcr |= UART_MCR_RTS; in mos7720_tiocmset() 1773 mcr |= UART_MCR_DTR; in mos7720_tiocmset() 1775 mcr |= UART_MCR_LOOP; in mos7720_tiocmset() 1778 mcr &= ~UART_MCR_RTS; in mos7720_tiocmset() [all …]
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D | spcp8x5.c | 186 static int spcp8x5_set_ctrl_line(struct usb_serial_port *port, u8 mcr) in spcp8x5_set_ctrl_line() argument 197 mcr, 0x04, NULL, 0, 100); in spcp8x5_set_ctrl_line() 443 unsigned int mcr; in spcp8x5_tiocmget() local 452 mcr = priv->line_control; in spcp8x5_tiocmget() 455 result = ((mcr & MCR_DTR) ? TIOCM_DTR : 0) in spcp8x5_tiocmget() 456 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in spcp8x5_tiocmget()
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D | whiteheat.c | 152 __u8 mcr; /* FIXME: no locking on mcr */ member 447 if (info->mcr & UART_MCR_DTR) in whiteheat_tiocmget() 449 if (info->mcr & UART_MCR_RTS) in whiteheat_tiocmget() 462 info->mcr |= UART_MCR_RTS; in whiteheat_tiocmset() 464 info->mcr |= UART_MCR_DTR; in whiteheat_tiocmset() 467 info->mcr &= ~UART_MCR_RTS; in whiteheat_tiocmset() 469 info->mcr &= ~UART_MCR_DTR; in whiteheat_tiocmset() 471 firm_set_dtr(port, info->mcr & UART_MCR_DTR); in whiteheat_tiocmset() 472 firm_set_rts(port, info->mcr & UART_MCR_RTS); in whiteheat_tiocmset() 643 memcpy(&info->mcr, command_info->result_buffer, in firm_send_command()
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D | mct_u232.c | 279 unsigned char mcr; in mct_u232_set_modem_ctrl() local 286 mcr = MCT_U232_MCR_NONE; in mct_u232_set_modem_ctrl() 288 mcr |= MCT_U232_MCR_DTR; in mct_u232_set_modem_ctrl() 290 mcr |= MCT_U232_MCR_RTS; in mct_u232_set_modem_ctrl() 292 buf[0] = mcr; in mct_u232_set_modem_ctrl() 300 dev_dbg(&port->dev, "set_modem_ctrl: state=0x%x ==> mcr=0x%x\n", control_state, mcr); in mct_u232_set_modem_ctrl() 303 dev_err(&port->dev, "Set MODEM CTRL 0x%x failed (error = %d)\n", mcr, rc); in mct_u232_set_modem_ctrl()
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D | metro-usb.c | 239 unsigned char mcr = METROUSB_MCR_NONE; in metrousb_set_modem_ctrl() local 246 mcr |= METROUSB_MCR_DTR; in metrousb_set_modem_ctrl() 248 mcr |= METROUSB_MCR_RTS; in metrousb_set_modem_ctrl() 257 __func__, mcr, retval); in metrousb_set_modem_ctrl()
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D | io_ti.c | 1394 static int restore_mcr(struct edgeport_port *port, __u8 mcr) in restore_mcr() argument 1398 dev_dbg(&port->port->dev, "%s - %x\n", __func__, mcr); in restore_mcr() 1400 status = ti_do_config(port, UMPC_SET_CLR_DTR, mcr & MCR_DTR); in restore_mcr() 1403 status = ti_do_config(port, UMPC_SET_CLR_RTS, mcr & MCR_RTS); in restore_mcr() 1406 return ti_do_config(port, UMPC_SET_CLR_LOOPBACK, mcr & MCR_LOOPBACK); in restore_mcr() 2263 unsigned int mcr; in edge_tiocmset() local 2267 mcr = edge_port->shadow_mcr; in edge_tiocmset() 2269 mcr |= MCR_RTS; in edge_tiocmset() 2271 mcr |= MCR_DTR; in edge_tiocmset() 2273 mcr |= MCR_LOOPBACK; in edge_tiocmset() [all …]
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D | mos7840.c | 1484 __u16 mcr; in mos7840_tiocmget() local 1494 status = mos7840_get_uart_reg(port, MODEM_CONTROL_REGISTER, &mcr); in mos7840_tiocmget() 1497 result = ((mcr & MCR_DTR) ? TIOCM_DTR : 0) in mos7840_tiocmget() 1498 | ((mcr & MCR_RTS) ? TIOCM_RTS : 0) in mos7840_tiocmget() 1499 | ((mcr & MCR_LOOPBACK) ? TIOCM_LOOP : 0) in mos7840_tiocmget() 1515 unsigned int mcr; in mos7840_tiocmset() local 1524 mcr = mos7840_port->shadowMCR; in mos7840_tiocmset() 1526 mcr &= ~MCR_RTS; in mos7840_tiocmset() 1528 mcr &= ~MCR_DTR; in mos7840_tiocmset() 1530 mcr &= ~MCR_LOOPBACK; in mos7840_tiocmset() [all …]
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D | ch341.c | 519 u8 mcr; in ch341_tiocmget() local 524 mcr = priv->line_control; in ch341_tiocmget() 528 result = ((mcr & CH341_BIT_DTR) ? TIOCM_DTR : 0) in ch341_tiocmget() 529 | ((mcr & CH341_BIT_RTS) ? TIOCM_RTS : 0) in ch341_tiocmget()
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D | f81232.c | 505 u8 mcr, msr; in f81232_tiocmget() local 511 mcr = port_priv->modem_control; in f81232_tiocmget() 515 r = (mcr & UART_MCR_DTR ? TIOCM_DTR : 0) | in f81232_tiocmget() 516 (mcr & UART_MCR_RTS ? TIOCM_RTS : 0) | in f81232_tiocmget()
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D | io_edgeport.c | 1510 unsigned int mcr; in edge_tiocmset() local 1512 mcr = edge_port->shadowMCR; in edge_tiocmset() 1514 mcr |= MCR_RTS; in edge_tiocmset() 1516 mcr |= MCR_DTR; in edge_tiocmset() 1518 mcr |= MCR_LOOPBACK; in edge_tiocmset() 1521 mcr &= ~MCR_RTS; in edge_tiocmset() 1523 mcr &= ~MCR_DTR; in edge_tiocmset() 1525 mcr &= ~MCR_LOOPBACK; in edge_tiocmset() 1527 edge_port->shadowMCR = mcr; in edge_tiocmset() 1540 unsigned int mcr; in edge_tiocmget() local [all …]
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D | whiteheat.h | 243 __u8 mcr; /* copy of uart's MCR register */ member
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D | pl2303.c | 706 unsigned int mcr; in pl2303_tiocmget() local 711 mcr = priv->line_control; in pl2303_tiocmget() 715 result = ((mcr & CONTROL_DTR) ? TIOCM_DTR : 0) in pl2303_tiocmget() 716 | ((mcr & CONTROL_RTS) ? TIOCM_RTS : 0) in pl2303_tiocmget()
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D | mxuport.c | 748 unsigned int mcr; in mxuport_tiocmget() local 756 mcr = mxport->mcr_state; in mxuport_tiocmget() 761 result = (((mcr & UART_MCR_DTR) ? TIOCM_DTR : 0) | /* 0x002 */ in mxuport_tiocmget() 762 ((mcr & UART_MCR_RTS) ? TIOCM_RTS : 0) | /* 0x004 */ in mxuport_tiocmget()
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/linux-4.1.27/drivers/tty/serial/ |
D | serial-tegra.c | 178 unsigned long mcr; in set_rts() local 180 mcr = tup->mcr_shadow; in set_rts() 182 mcr |= TEGRA_UART_MCR_RTS_EN; in set_rts() 184 mcr &= ~TEGRA_UART_MCR_RTS_EN; in set_rts() 185 if (mcr != tup->mcr_shadow) { in set_rts() 186 tegra_uart_write(tup, mcr, UART_MCR); in set_rts() 187 tup->mcr_shadow = mcr; in set_rts() 194 unsigned long mcr; in set_dtr() local 196 mcr = tup->mcr_shadow; in set_dtr() 198 mcr |= UART_MCR_DTR; in set_dtr() [all …]
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D | pxa.c | 54 unsigned char mcr; member 306 unsigned char mcr = 0; in serial_pxa_set_mctrl() local 309 mcr |= UART_MCR_RTS; in serial_pxa_set_mctrl() 311 mcr |= UART_MCR_DTR; in serial_pxa_set_mctrl() 313 mcr |= UART_MCR_OUT1; in serial_pxa_set_mctrl() 315 mcr |= UART_MCR_OUT2; in serial_pxa_set_mctrl() 317 mcr |= UART_MCR_LOOP; in serial_pxa_set_mctrl() 319 mcr |= up->mcr; in serial_pxa_set_mctrl() 321 serial_out(up, UART_MCR, mcr); in serial_pxa_set_mctrl() 345 up->mcr |= UART_MCR_AFE; in serial_pxa_startup() [all …]
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D | serial_ks8695.c | 297 unsigned int mcr; in ks8695uart_set_mctrl() local 299 mcr = UART_GET_MCR(port); in ks8695uart_set_mctrl() 301 mcr |= URMC_URRTS; in ks8695uart_set_mctrl() 303 mcr &= ~URMC_URRTS; in ks8695uart_set_mctrl() 306 mcr |= URMC_URDTR; in ks8695uart_set_mctrl() 308 mcr &= ~URMC_URDTR; in ks8695uart_set_mctrl() 310 UART_PUT_MCR(port, mcr); in ks8695uart_set_mctrl()
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D | omap-serial.c | 142 unsigned char mcr; member 684 unsigned char mcr = 0, old_mcr, lcr; in serial_omap_set_mctrl() local 688 mcr |= UART_MCR_RTS; in serial_omap_set_mctrl() 690 mcr |= UART_MCR_DTR; in serial_omap_set_mctrl() 692 mcr |= UART_MCR_OUT1; in serial_omap_set_mctrl() 694 mcr |= UART_MCR_OUT2; in serial_omap_set_mctrl() 696 mcr |= UART_MCR_LOOP; in serial_omap_set_mctrl() 702 up->mcr = old_mcr | mcr; in serial_omap_set_mctrl() 703 serial_out(up, UART_MCR, up->mcr); in serial_omap_set_mctrl() 982 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; in serial_omap_set_termios() [all …]
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D | vr41xx_siu.c | 205 uint8_t mcr = 0; in siu_set_mctrl() local 208 mcr |= UART_MCR_DTR; in siu_set_mctrl() 210 mcr |= UART_MCR_RTS; in siu_set_mctrl() 212 mcr |= UART_MCR_OUT1; in siu_set_mctrl() 214 mcr |= UART_MCR_OUT2; in siu_set_mctrl() 216 mcr |= UART_MCR_LOOP; in siu_set_mctrl() 218 siu_write(port, UART_MCR, mcr); in siu_set_mctrl()
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D | ioc3_serial.c | 831 char mcr; in set_mcr() local 848 mcr = (shadow & 0xff000000) >> 24; in set_mcr() 851 mcr |= mask1; in set_mcr() 853 writeb(mcr, &port->ip_uart_regs->iu_mcr); in set_mcr() 1746 unsigned char mcr = 0; in ic3_set_mctrl() local 1749 mcr |= UART_MCR_RTS; in ic3_set_mctrl() 1751 mcr |= UART_MCR_DTR; in ic3_set_mctrl() 1753 mcr |= UART_MCR_OUT1; in ic3_set_mctrl() 1755 mcr |= UART_MCR_OUT2; in ic3_set_mctrl() 1757 mcr |= UART_MCR_LOOP; in ic3_set_mctrl() [all …]
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D | nwpserial.c | 38 unsigned int mcr; member 174 up->mcr = dcr_read(up->dcr_host, UART_MCR) & ~UART_MCR_AFE; in nwpserial_startup() 175 dcr_write(up->dcr_host, UART_MCR, up->mcr); in nwpserial_startup()
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D | ioc4_serial.c | 1561 char mcr; in set_mcr() local 1578 mcr = (shadow & 0xff000000) >> 24; in set_mcr() 1581 mcr |= mask1; in set_mcr() 1584 writeb(mcr, &port->ip_uart_regs->i4u_mcr); in set_mcr() 2460 unsigned char mcr = 0; in ic4_set_mctrl() local 2468 mcr |= UART_MCR_RTS; in ic4_set_mctrl() 2470 mcr |= UART_MCR_DTR; in ic4_set_mctrl() 2472 mcr |= UART_MCR_OUT1; in ic4_set_mctrl() 2474 mcr |= UART_MCR_OUT2; in ic4_set_mctrl() 2476 mcr |= UART_MCR_LOOP; in ic4_set_mctrl() [all …]
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D | pch_uart.c | 244 unsigned int mcr; member 1215 u32 mcr = 0; in pch_uart_set_mctrl() local 1219 mcr |= UART_MCR_DTR; in pch_uart_set_mctrl() 1221 mcr |= UART_MCR_RTS; in pch_uart_set_mctrl() 1223 mcr |= UART_MCR_LOOP; in pch_uart_set_mctrl() 1225 if (priv->mcr & UART_MCR_AFE) in pch_uart_set_mctrl() 1226 mcr |= UART_MCR_AFE; in pch_uart_set_mctrl() 1229 iowrite8(mcr, priv->membase + UART_MCR); in pch_uart_set_mctrl() 1425 priv->mcr |= UART_MCR_AFE; in pch_uart_set_termios() 1427 priv->mcr &= ~UART_MCR_AFE; in pch_uart_set_termios()
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D | sunsu.c | 587 unsigned char mcr = 0; in sunsu_set_mctrl() local 590 mcr |= UART_MCR_RTS; in sunsu_set_mctrl() 592 mcr |= UART_MCR_DTR; in sunsu_set_mctrl() 594 mcr |= UART_MCR_OUT1; in sunsu_set_mctrl() 596 mcr |= UART_MCR_OUT2; in sunsu_set_mctrl() 598 mcr |= UART_MCR_LOOP; in sunsu_set_mctrl() 600 serial_out(up, UART_MCR, mcr); in sunsu_set_mctrl()
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/linux-4.1.27/arch/x86/kernel/cpu/mtrr/ |
D | centaur.c | 50 void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) in mtrr_centaur_report_mcr() argument 52 centaur_mcr[mcr].low = lo; in mtrr_centaur_report_mcr() 53 centaur_mcr[mcr].high = hi; in mtrr_centaur_report_mcr()
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/linux-4.1.27/arch/arm/mach-omap2/ |
D | sleep24xx.S | 68 mov r3, #0x0 @ clear for mcr call 69 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 77 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
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D | omap-smc.S | 52 mcr p15, 0, r7, c7, c5, 6
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D | sleep34xx.S | 203 mcr p15, 0, r0, c1, c0, 0 432 mcr p15, 0, r0, c1, c0, 1 505 mcr p15, 0, r1, c1, c0, 1
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D | sram34xx.S | 159 mcr p15, 0, r10, c1, c0, 0 @ write ctrl register 179 mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
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D | sram243x.S | 152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
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D | sram242x.S | 152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
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D | sleep44xx.S | 90 mcr p15, 0, r0, c1, c0, 0
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/linux-4.1.27/arch/arm/include/debug/ |
D | icedcc.S | 20 mcr p14, 0, \rd, c0, c5, 0 44 mcr p14, 0, \rd, c8, c0, 0 68 mcr p14, 0, \rd, c1, c0, 0
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/linux-4.1.27/arch/mips/txx9/generic/ |
D | setup_tx3927.c | 79 tx3927_dmaptr->mcr = 0; in tx3927_setup() 87 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN; in tx3927_setup() 89 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; in tx3927_setup()
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/linux-4.1.27/arch/arm/kernel/ |
D | head-nommu.S | 165 mcr p15, 0, r0, c1, c0, 0 @ write control reg 177 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR 182 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR 183 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR 184 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR 255 mcr p15, 0, r0, c1, c0, 0 @ Enable MPU
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D | iwmmxt.S | 84 XSC(mcr p15, 0, r2, c15, c1, 0) 86 PJ4(mcr p15, 0, r2, c1, c0, 2) 215 XSC(mcr p15, 0, r4, c15, c1, 0) 218 PJ4(mcr p15, 0, r4, c1, c0, 2) 228 XSC(mcr p15, 0, r4, c15, c1, 0) 230 PJ4(mcr p15, 0, r4, c1, c0, 2) 340 XSC(mcr p15, 0, r1, c15, c1, 0) 342 PJ4(mcr p15, 0, r1, c1, c0, 2)
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D | hyp-stub.S | 128 mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
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D | head.S | 448 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 449 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 473 mcr p15, 0, r0, c1, c0, 0 @ write control reg
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D | sleep.S | 105 mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
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/linux-4.1.27/arch/arm/mach-omap1/ |
D | sleep.S | 73 mcr p15, 0, r0, c7, c10, 4 111 mcr p15, 0, r2, c1, c0, 0 119 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 127 mcr p15, 0, r9, c1, c0, 0 202 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 228 mcr p15, 0, r0, c7, c10, 4 268 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
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/linux-4.1.27/drivers/sn/ |
D | ioc3.c | 42 unsigned mcr; in nic_wait() local 45 mcr = readl(&idd->vma->mcr); in nic_wait() 46 } while (!(mcr & 2)); in nic_wait() 48 return mcr & 1; in nic_wait() 57 writel(mcr_pack(500, 65), &idd->vma->mcr); in nic_reset() 72 writel(mcr_pack(6, 13), &idd->vma->mcr); in nic_read_bit() 84 writel(mcr_pack(6, 110), &idd->vma->mcr); in nic_write_bit() 86 writel(mcr_pack(80, 30), &idd->vma->mcr); in nic_write_bit()
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/linux-4.1.27/arch/mips/dec/ |
D | ecc-berr.c | 249 volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR); in dec_kn03_be_init() local 262 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | in dec_kn03_be_init()
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/linux-4.1.27/arch/arm/mach-pxa/ |
D | sleep.S | 31 mcr p14, 0, r0, c7, c0, 0 @ enter sleep 131 mcr p14, 0, r0, c6, c0, 0 145 mcr p14, 0, r0, c6, c0, 0 169 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
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D | standby.S | 30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby 64 mcr p14, 0, r0, c7, c0, 0
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/linux-4.1.27/arch/x86/include/asm/ |
D | mtrr.h | 43 extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); 84 static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi) in mtrr_centaur_report_mcr() argument
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/linux-4.1.27/drivers/gpu/drm/gma500/ |
D | psb_drv.h | 788 int mcr = (0xD0<<24) | (port << 16) | (offset << 8); in MRST_MSG_READ32() local 791 pci_write_config_dword(pci_root, 0xD0, mcr); in MRST_MSG_READ32() 798 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0; in MRST_MSG_WRITE32() local 801 pci_write_config_dword(pci_root, 0xD0, mcr); in MRST_MSG_WRITE32() 806 int mcr = (0x10<<24) | (port << 16) | (offset << 8); in MDFLD_MSG_READ32() local 809 pci_write_config_dword(pci_root, 0xD0, mcr); in MDFLD_MSG_READ32() 816 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; in MDFLD_MSG_WRITE32() local 819 pci_write_config_dword(pci_root, 0xD0, mcr); in MDFLD_MSG_WRITE32()
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D | cdv_device.c | 190 int mcr = (0x10<<24) | (port << 16) | (offset << 8); in CDV_MSG_READ32() local 193 pci_write_config_dword(pci_root, 0xD0, mcr); in CDV_MSG_READ32() 201 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0; in CDV_MSG_WRITE32() local 204 pci_write_config_dword(pci_root, 0xD0, mcr); in CDV_MSG_WRITE32()
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/linux-4.1.27/sound/pci/ice1712/ |
D | quartet.c | 41 unsigned int mcr; /* monitoring control register */ member 460 return spec->mcr; in get_mcr() 480 spec->mcr = val; in set_mcr() 686 PRIV_SW(IN12_MON12, MCR_IN12_MON12, mcr), 687 PRIV_SW(IN12_MON34, MCR_IN12_MON34, mcr), 688 PRIV_SW(IN34_MON12, MCR_IN34_MON12, mcr), 689 PRIV_SW(IN34_MON34, MCR_IN34_MON34, mcr), 690 PRIV_SW(OUT12_MON34, MCR_OUT12_MON34, mcr), 691 PRIV_SW(OUT34_MON12, MCR_OUT34_MON12, mcr),
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/linux-4.1.27/drivers/staging/comedi/drivers/ |
D | mite.c | 352 unsigned int chor, chcr, mcr, dcr, lkcr; in mite_prep_dma() local 387 mcr = CR_RL(64) | CR_ASEQUP; in mite_prep_dma() 390 mcr |= CR_PSIZE8; in mite_prep_dma() 393 mcr |= CR_PSIZE16; in mite_prep_dma() 396 mcr |= CR_PSIZE32; in mite_prep_dma() 402 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); in mite_prep_dma()
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/linux-4.1.27/arch/arm/include/asm/ |
D | tls.h | 14 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register 15 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
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D | assembler.h | 266 mcr p15, 0, r0, c7, c5, 4 282 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
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/linux-4.1.27/drivers/pcmcia/ |
D | pxa2xx_sharpsl.c | 115 unsigned short cpr, ncpr, ccr, nccr, mcr, nmcr, imr, nimr; in sharpsl_pcmcia_configure_socket() local 133 nmcr = (mcr = read_scoop_reg(scoop, SCOOP_MCR)) & ~0x0010; in sharpsl_pcmcia_configure_socket() 164 if (mcr != nmcr) in sharpsl_pcmcia_configure_socket()
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/linux-4.1.27/arch/arm/mach-tegra/ |
D | sleep.S | 55 mcr p15, 0, r2, c1, c0, 0 132 mcr p15, 0, r3, c1, c0, 0
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D | reset-handler.S | 132 mcr p15, 0, r0, c1, c0, 0 @ write system control register 136 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register 149 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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D | sleep-tegra20.S | 292 mcr p15, 0, r10, c1, c0, 0 295 mcr p15, 0, r11, c1, c0, 1 @ reenable coherency 299 mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs 300 mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
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D | sleep.h | 103 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
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/linux-4.1.27/drivers/dma/ |
D | txx9dmac.c | 655 u32 mcr; in txx9dmac_tasklet() local 658 mcr = dma_readl(ddev, MCR); in txx9dmac_tasklet() 659 dev_vdbg(ddev->chan[0]->dma.dev, "tasklet: mcr=%x\n", mcr); in txx9dmac_tasklet() 661 if ((mcr >> (24 + i)) & 0x11) { in txx9dmac_tasklet() 1180 u32 mcr; in txx9dmac_probe() local 1217 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE; in txx9dmac_probe() 1219 mcr |= TXX9_DMA_MCR_FIFUM(pdata->memcpy_chan); in txx9dmac_probe() 1220 dma_writel(ddev, MCR, mcr); in txx9dmac_probe() 1257 u32 mcr; in txx9dmac_resume_noirq() local 1259 mcr = TXX9_DMA_MCR_MSTEN | MCR_LE; in txx9dmac_resume_noirq() [all …]
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/linux-4.1.27/drivers/video/fbdev/ |
D | cg14.c | 101 u8 mcr; /* Master Control Reg */ member 211 val = sbus_readb(®s->mcr); in __cg14_reset() 213 sbus_writeb(val, ®s->mcr); in __cg14_reset() 314 cur_mode = sbus_readb(®s->mcr); in cg14_ioctl() 335 sbus_writeb(cur_mode, ®s->mcr); in cg14_ioctl()
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/linux-4.1.27/arch/arm/common/ |
D | scoop.c | 147 unsigned short mcr; in check_scoop_reg() local 149 mcr = ioread16(sdev->base + SCOOP_MCR); in check_scoop_reg() 150 if ((mcr & 0x100) == 0) in check_scoop_reg()
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/linux-4.1.27/drivers/staging/dgnc/ |
D | dgnc_cls.h | 43 u8 mcr; member
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D | dgnc_neo.h | 35 u8 mcr; /* WR MCR - Modem Control Reg */ member
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D | dgnc_cls.c | 142 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control() 271 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control() 1131 writeb(out, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
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D | dgnc_neo.c | 472 cause = readb(&ch->ch_neo_uart->mcr); in neo_parse_isr() 1625 writeb(out, &ch->ch_neo_uart->mcr); in neo_assert_modem_signals() 1681 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_uart_init()
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/linux-4.1.27/arch/arm/mach-imx/ |
D | headsmp.S | 24 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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D | suspend-imx6.S | 312 mcr p15, 0, r6, c7, c5, 0 313 mcr p15, 0, r6, c7, c5, 6 316 mcr p15, 0, r6, c1, c0, 0
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/linux-4.1.27/arch/arm/mach-ep93xx/ |
D | core.c | 269 unsigned int mcr; in ep93xx_uart_set_mctrl() local 271 mcr = 0; in ep93xx_uart_set_mctrl() 273 mcr |= 2; in ep93xx_uart_set_mctrl() 275 mcr |= 1; in ep93xx_uart_set_mctrl() 277 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); in ep93xx_uart_set_mctrl()
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/linux-4.1.27/drivers/ide/ |
D | hpt366.c | 781 u8 mcr = 0, mcr_addr = hwif->select_data; in hpt374_dma_end() local 785 pci_read_config_byte(dev, mcr_addr, &mcr); in hpt374_dma_end() 787 pci_write_config_byte(dev, mcr_addr, mcr | 0x30); in hpt374_dma_end() 1173 u16 mcr; in hpt3xx_cable_detect() local 1175 pci_read_config_word(dev, mcr_addr, &mcr); in hpt3xx_cable_detect() 1176 pci_write_config_word(dev, mcr_addr, mcr | 0x8000); in hpt3xx_cable_detect() 1180 pci_write_config_word(dev, mcr_addr, mcr); in hpt3xx_cable_detect()
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/linux-4.1.27/arch/arm/mach-spear/ |
D | headsmp.S | 37 mcr p15, 0, r0, c1, c0, 1
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/linux-4.1.27/arch/arm/mach-s3c24xx/ |
D | sleep-s3c2412.S | 52 mcr p15, 0, r0, c7, c10, 4
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/linux-4.1.27/drivers/mmc/card/ |
D | sdio_uart.c | 222 unsigned char mcr = 0; in sdio_uart_write_mctrl() local 225 mcr |= UART_MCR_RTS; in sdio_uart_write_mctrl() 227 mcr |= UART_MCR_DTR; in sdio_uart_write_mctrl() 229 mcr |= UART_MCR_OUT1; in sdio_uart_write_mctrl() 231 mcr |= UART_MCR_OUT2; in sdio_uart_write_mctrl() 233 mcr |= UART_MCR_LOOP; in sdio_uart_write_mctrl() 235 sdio_out(port, UART_MCR, mcr); in sdio_uart_write_mctrl()
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/linux-4.1.27/arch/arm/mach-rockchip/ |
D | sleep.S | 43 mcr p15, 1, r3, c9, c0, 2
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/linux-4.1.27/arch/arm/mach-iop32x/include/mach/ |
D | entry-macro.S | 15 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
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/linux-4.1.27/arch/arm/mach-iop13xx/include/mach/ |
D | entry-macro.S | 22 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
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/linux-4.1.27/arch/arm/mach-iop33x/include/mach/ |
D | entry-macro.S | 15 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
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/linux-4.1.27/drivers/tty/serial/jsm/ |
D | jsm.h | 273 u8 mcr; /* WR MCR - Modem Control Reg */ member 328 u8 mcr; /* WR MCR - Modem Control Reg */ member
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D | jsm_cls.c | 123 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixon_flow_control() 249 writeb(ch->ch_startc, &ch->ch_cls_uart->mcr); in cls_set_ixoff_flow_control() 356 writeb(ch->ch_mostat, &ch->ch_cls_uart->mcr); in cls_assert_modem_signals()
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D | jsm_neo.c | 622 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_assert_modem_signals() 809 cause = readb(&ch->ch_neo_uart->mcr); in neo_parse_isr() 1323 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr); in neo_uart_init()
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/linux-4.1.27/arch/arm/mach-at91/ |
D | pm_suspend.S | 66 mcr p15, 0, tmp1, c7, c0, 4 92 mcr p15, 0, tmp1, c7, c10, 4
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/linux-4.1.27/arch/sh/include/asm/ |
D | smc37c93x.h | 75 volatile __u16 mcr; member
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/linux-4.1.27/arch/arm/mach-mvebu/ |
D | pmsu_ll.S | 40 mcr p15, 0, r1, c1, c0, 0
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/linux-4.1.27/include/linux/ |
D | serial_8250.h | 97 unsigned char mcr; member
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D | isdn.h | 315 int mcr; /* Modem control register */ member
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/linux-4.1.27/drivers/net/ethernet/smsc/ |
D | smc911x.c | 1301 unsigned int mcr, update_multicast = 0; in smc911x_set_multicast_list() local 1307 SMC_GET_MAC_CR(lp, mcr); in smc911x_set_multicast_list() 1313 mcr |= MAC_CR_PRMS_; in smc911x_set_multicast_list() 1322 mcr |= MAC_CR_MCPAS_; in smc911x_set_multicast_list() 1341 mcr |= MAC_CR_HPFILT_; in smc911x_set_multicast_list() 1356 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); in smc911x_set_multicast_list() 1362 mcr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_); in smc911x_set_multicast_list() 1373 SMC_SET_MAC_CR(lp, mcr); in smc911x_set_multicast_list()
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D | smc91c92_cs.c | 887 u_long mcr; in smc91c92_config() local 892 mcr = ((rev >> 4) > 3) ? inw(ioaddr + MEMCFG) : 0x0200; in smc91c92_config() 893 mir *= 128 * (1<<((mcr >> 9) & 7)); in smc91c92_config()
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/linux-4.1.27/drivers/usb/phy/ |
D | phy-mv-usb.h | 133 u32 mcr; /* Mux Control */ member
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/linux-4.1.27/arch/ia64/include/asm/sn/ |
D | ioc3.h | 72 uint32_t mcr; member
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/linux-4.1.27/drivers/tty/serial/8250/ |
D | 8250_core.c | 2008 unsigned char mcr = 0; in serial8250_do_set_mctrl() local 2011 mcr |= UART_MCR_RTS; in serial8250_do_set_mctrl() 2013 mcr |= UART_MCR_DTR; in serial8250_do_set_mctrl() 2015 mcr |= UART_MCR_OUT1; in serial8250_do_set_mctrl() 2017 mcr |= UART_MCR_OUT2; in serial8250_do_set_mctrl() 2019 mcr |= UART_MCR_LOOP; in serial8250_do_set_mctrl() 2021 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; in serial8250_do_set_mctrl() 2023 serial_port_out(port, UART_MCR, mcr); in serial8250_do_set_mctrl() 2161 up->mcr = 0; in serial8250_do_startup() 2606 up->mcr &= ~UART_MCR_AFE; in serial8250_do_set_termios() [all …]
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D | 8250_omap.c | 269 serial_out(up, UART_MCR, up->mcr); in omap8250_restore_regs() 420 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); in omap_8250_set_termios() 453 up->mcr |= UART_MCR_XONANY; in omap_8250_set_termios() 607 up->mcr = 0; in omap_8250_startup()
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/linux-4.1.27/drivers/isdn/i4l/ |
D | isdn_tty.c | 71 if (!(info->mcr & UART_MCR_RTS)) in isdn_tty_try_read() 142 if (info->mcr & UART_MCR_RTS) { in isdn_tty_readmodem() 1023 info->mcr |= UART_MCR_DTR; in isdn_tty_change_speed() 1026 info->mcr &= ~UART_MCR_DTR; in isdn_tty_change_speed() 1065 info->mcr = UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2; in isdn_tty_startup() 1094 info->mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); in isdn_tty_shutdown() 1299 info->mcr &= ~UART_MCR_RTS; in isdn_tty_throttle() 1315 info->mcr |= UART_MCR_RTS; in isdn_tty_unthrottle() 1362 control = info->mcr; in isdn_tty_tiocmget() 1390 info->mcr |= UART_MCR_RTS; in isdn_tty_tiocmset() [all …]
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/linux-4.1.27/arch/blackfin/include/asm/ |
D | bfin_serial.h | 237 __BFP(mcr); 259 __BFP(mcr);
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/linux-4.1.27/drivers/net/ethernet/sgi/ |
D | ioc3-eth.c | 170 #define ioc3_r_mcr() be32_to_cpu(ioc3->mcr) 171 #define ioc3_w_mcr(v) do { ioc3->mcr = cpu_to_be32(v); } while (0) 231 u32 mcr; in nic_wait() local 234 mcr = ioc3_r_mcr(); in nic_wait() 235 } while (!(mcr & 2)); in nic_wait() 237 return mcr & 1; in nic_wait()
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/linux-4.1.27/arch/arm/mach-sa1100/ |
D | sleep.S | 34 mcr p15, 0, r1, c15, c2, 2
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/linux-4.1.27/drivers/usb/gadget/udc/ |
D | mv_udc.h | 168 u32 mcr; /* Mux Control */ member
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/linux-4.1.27/drivers/net/irda/ |
D | nsc-ircc.c | 1257 __u8 mcr = MCR_SIR; in nsc_ircc_change_speed() local 1294 mcr = MCR_MIR; in nsc_ircc_change_speed() 1298 mcr = MCR_MIR; in nsc_ircc_change_speed() 1302 mcr = MCR_FIR; in nsc_ircc_change_speed() 1306 mcr = MCR_FIR; in nsc_ircc_change_speed() 1314 outb(mcr | MCR_TX_DFR, iobase+MCR); in nsc_ircc_change_speed()
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/linux-4.1.27/arch/mips/include/asm/txx9/ |
D | tx3927.h | 49 volatile unsigned long mcr; member
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/linux-4.1.27/drivers/net/ethernet/3com/ |
D | 3c574_cs.c | 370 u_char mcr; in tc574_config() local 372 mcr = inb(ioaddr + 2); in tc574_config() 374 pr_info(" ASIC rev %d,", mcr>>3); in tc574_config()
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/linux-4.1.27/drivers/atm/ |
D | iphase.c | 361 srv_p->mcr = 0; in init_abr_vc() 391 if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate) in ia_open_abr_vc() 393 if (srv_p->mcr > srv_p->pcr) in ia_open_abr_vc() 397 if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr)) in ia_open_abr_vc() 437 f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr); in ia_open_abr_vc() 451 dev->sum_mcr += srv_p->mcr; in ia_open_abr_vc() 1846 srv_p.mcr = vcc->qos.txtp.min_pcr; 1849 else srv_p.mcr = 0; 1871 srv_p.pcr, srv_p.mcr);)
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D | iphase.h | 254 u_short mcr; member 817 u32 mcr; /* Min Cell Rate (24-bit) */ member
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/linux-4.1.27/arch/mips/include/asm/sn/ |
D | ioc3.h | 77 volatile u32 mcr; /* 0x00030 */ member
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/linux-4.1.27/drivers/crypto/caam/ |
D | regs.h | 336 u32 mcr; /* MCFG Master Config Register */ member
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D | ctrl.c | 447 setbits32(&ctrl->mcr, MCFGR_WDENABLE | in caam_probe()
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/linux-4.1.27/drivers/crypto/ |
D | talitos.c | 123 u32 mcr = TALITOS_MCR_SWR; in reset_device() local 125 setbits32(priv->reg + TALITOS_MCR, mcr); in reset_device() 132 mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3; in reset_device() 133 setbits32(priv->reg + TALITOS_MCR, mcr); in reset_device()
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/linux-4.1.27/drivers/tty/ |
D | mxser.c | 1766 int mcr, status; in mxser_ioctl() local 1772 mcr = inb(info->ioaddr + UART_MCR); in mxser_ioctl() 1775 if (mcr & MOXA_MUST_MCR_XON_FLAG) in mxser_ioctl() 1780 if (mcr & MOXA_MUST_MCR_TX_XON) in mxser_ioctl()
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/linux-4.1.27/arch/blackfin/kernel/ |
D | debug-mmrs.c | 551 __UART(MCR, mcr); in bfin_debug_mmrs_uart() 567 __UART(MCR, mcr); in bfin_debug_mmrs_uart()
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/linux-4.1.27/Documentation/ioctl/ |
D | ioctl-number.txt | 92 <mailto:mcr@solidum.com>
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