Lines Matching refs:mcr

71 1:	mcr	p15, 0, \rd, c7, c14, 2		@ clean/invalidate L1 D line
95 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
115 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
116 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
118 	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
121 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
140 	mcr	p14, 0, r0, c7, c0, 0		@ go to idle
152 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
200 	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
227 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
232 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
233 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
234 	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
248 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
253 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
254 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
255 	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
275 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate L1 D line
279 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
292 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
296 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
309 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
313 	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
347 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
365 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
366 	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
367 	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
369 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
370 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
433 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I & D caches, BTB
434 	mcr	p15, 0, ip, c7, c10, 4	@ drain write (&fill) buffer
435 	mcr	p15, 0, ip, c7, c5, 4	@ flush prefetch buffer
436 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I & D TLBs
437 	mcr	p14, 0, r4, c6, c0, 0	@ clock configuration, turbo mode.
438 	mcr	p15, 0, r5, c15, c1, 0	@ CP access reg
439 	mcr	p15, 0, r6, c13, c0, 0	@ PID
440 	mcr	p15, 0, r7, c3, c0, 0	@ domain ID
442 	mcr	p15, 0, r1, c2, c0, 0	@ translation table base addr
443 	mcr	p15, 0, r8, c1, c0, 1	@ auxiliary control reg
453 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
454 	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
455 	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
456 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
458 	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer
461 	mcr	p15, 0, r0, c15, c1, 0		@ write CP access register
466 	mcr	p15, 0, r0, c1, c0, 1		@ set auxiliary control reg