Lines Matching refs:mcr
60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
81 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
114 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
152 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)