Lines Matching refs:mcr
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
128 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
135 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
136 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
138 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
141 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
142 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
147 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
236 mcr p15, 1, r6, c15, c1, 0 @ restore CP15 - extra features
237 mcr p15, 1, r7, c15, c2, 0 @ restore CP15 - Aux Func Modes Ctrl 0
238 mcr p15, 1, r8, c15, c1, 2 @ restore CP15 - Aux Debug Modes Ctrl 2
239 mcr p15, 1, r9, c15, c1, 1 @ restore CP15 - Aux Debug Modes Ctrl 1
240 mcr p15, 0, r10, c9, c14, 0 @ restore CP15 - PMC
315 mcr p15, 1, r0, c15, c1, 1
321 mcr p15, 1, r0, c15, c1, 2
330 mcr p15, 1, r0, c15, c2, 0
335 mcr p15, 1, r0, c15, c1, 0
429 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
431 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
435 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
436 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
445 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
448 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access