1 /*
2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE. See the GNU General Public License for more details.
14 */
15
16
17 #include <linux/kernel.h>
18 #include <linux/sched.h> /* For jiffies, task states */
19 #include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
20 #include <linux/delay.h> /* For udelay */
21 #include <linux/io.h> /* For read[bwl]/write[bwl] */
22 #include <linux/serial.h> /* For struct async_serial */
23 #include <linux/serial_reg.h> /* For the various UART offsets */
24
25 #include "dgnc_driver.h" /* Driver main header file */
26 #include "dgnc_neo.h" /* Our header file */
27 #include "dgnc_tty.h"
28
29 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
30 static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
31 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
32 static inline void neo_clear_break(struct channel_t *ch, int force);
33 static inline void neo_set_cts_flow_control(struct channel_t *ch);
34 static inline void neo_set_rts_flow_control(struct channel_t *ch);
35 static inline void neo_set_ixon_flow_control(struct channel_t *ch);
36 static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
37 static inline void neo_set_no_output_flow_control(struct channel_t *ch);
38 static inline void neo_set_no_input_flow_control(struct channel_t *ch);
39 static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
40 static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
41 static void neo_tasklet(unsigned long data);
42 static void neo_vpd(struct dgnc_board *brd);
43 static void neo_uart_init(struct channel_t *ch);
44 static void neo_uart_off(struct channel_t *ch);
45 static int neo_drain(struct tty_struct *tty, uint seconds);
46 static void neo_param(struct tty_struct *tty);
47 static void neo_assert_modem_signals(struct channel_t *ch);
48 static void neo_flush_uart_write(struct channel_t *ch);
49 static void neo_flush_uart_read(struct channel_t *ch);
50 static void neo_disable_receiver(struct channel_t *ch);
51 static void neo_enable_receiver(struct channel_t *ch);
52 static void neo_send_break(struct channel_t *ch, int msecs);
53 static void neo_send_start_character(struct channel_t *ch);
54 static void neo_send_stop_character(struct channel_t *ch);
55 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
56 static uint neo_get_uart_bytes_left(struct channel_t *ch);
57 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
58 static irqreturn_t neo_intr(int irq, void *voidbrd);
59
60
61 struct board_ops dgnc_neo_ops = {
62 .tasklet = neo_tasklet,
63 .intr = neo_intr,
64 .uart_init = neo_uart_init,
65 .uart_off = neo_uart_off,
66 .drain = neo_drain,
67 .param = neo_param,
68 .vpd = neo_vpd,
69 .assert_modem_signals = neo_assert_modem_signals,
70 .flush_uart_write = neo_flush_uart_write,
71 .flush_uart_read = neo_flush_uart_read,
72 .disable_receiver = neo_disable_receiver,
73 .enable_receiver = neo_enable_receiver,
74 .send_break = neo_send_break,
75 .send_start_character = neo_send_start_character,
76 .send_stop_character = neo_send_stop_character,
77 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
78 .get_uart_bytes_left = neo_get_uart_bytes_left,
79 .send_immediate_char = neo_send_immediate_char
80 };
81
82 static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
83
84
85 /*
86 * This function allows calls to ensure that all outstanding
87 * PCI writes have been completed, by doing a PCI read against
88 * a non-destructive, read-only location on the Neo card.
89 *
90 * In this case, we are reading the DVID (Read-only Device Identification)
91 * value of the Neo card.
92 */
neo_pci_posting_flush(struct dgnc_board * bd)93 static inline void neo_pci_posting_flush(struct dgnc_board *bd)
94 {
95 readb(bd->re_map_membase + 0x8D);
96 }
97
neo_set_cts_flow_control(struct channel_t * ch)98 static inline void neo_set_cts_flow_control(struct channel_t *ch)
99 {
100 unsigned char ier = readb(&ch->ch_neo_uart->ier);
101 unsigned char efr = readb(&ch->ch_neo_uart->efr);
102
103
104 /* Turn on auto CTS flow control */
105 #if 1
106 ier |= UART_17158_IER_CTSDSR;
107 #else
108 ier &= ~(UART_17158_IER_CTSDSR);
109 #endif
110
111 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
112
113 /* Turn off auto Xon flow control */
114 efr &= ~UART_17158_EFR_IXON;
115
116 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
117 writeb(0, &ch->ch_neo_uart->efr);
118
119 /* Turn on UART enhanced bits */
120 writeb(efr, &ch->ch_neo_uart->efr);
121
122 /* Turn on table D, with 8 char hi/low watermarks */
123 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
124
125 /* Feed the UART our trigger levels */
126 writeb(8, &ch->ch_neo_uart->tfifo);
127 ch->ch_t_tlevel = 8;
128
129 writeb(ier, &ch->ch_neo_uart->ier);
130
131 neo_pci_posting_flush(ch->ch_bd);
132 }
133
134
neo_set_rts_flow_control(struct channel_t * ch)135 static inline void neo_set_rts_flow_control(struct channel_t *ch)
136 {
137 unsigned char ier = readb(&ch->ch_neo_uart->ier);
138 unsigned char efr = readb(&ch->ch_neo_uart->efr);
139
140 /* Turn on auto RTS flow control */
141 #if 1
142 ier |= UART_17158_IER_RTSDTR;
143 #else
144 ier &= ~(UART_17158_IER_RTSDTR);
145 #endif
146 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
147
148 /* Turn off auto Xoff flow control */
149 ier &= ~UART_17158_IER_XOFF;
150 efr &= ~UART_17158_EFR_IXOFF;
151
152 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
153 writeb(0, &ch->ch_neo_uart->efr);
154
155 /* Turn on UART enhanced bits */
156 writeb(efr, &ch->ch_neo_uart->efr);
157
158 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
159 ch->ch_r_watermark = 4;
160
161 writeb(32, &ch->ch_neo_uart->rfifo);
162 ch->ch_r_tlevel = 32;
163
164 writeb(ier, &ch->ch_neo_uart->ier);
165
166 /*
167 * From the Neo UART spec sheet:
168 * The auto RTS/DTR function must be started by asserting
169 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
170 * it is enabled.
171 */
172 ch->ch_mostat |= UART_MCR_RTS;
173
174 neo_pci_posting_flush(ch->ch_bd);
175 }
176
177
neo_set_ixon_flow_control(struct channel_t * ch)178 static inline void neo_set_ixon_flow_control(struct channel_t *ch)
179 {
180 unsigned char ier = readb(&ch->ch_neo_uart->ier);
181 unsigned char efr = readb(&ch->ch_neo_uart->efr);
182
183 /* Turn off auto CTS flow control */
184 ier &= ~UART_17158_IER_CTSDSR;
185 efr &= ~UART_17158_EFR_CTSDSR;
186
187 /* Turn on auto Xon flow control */
188 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
189
190 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
191 writeb(0, &ch->ch_neo_uart->efr);
192
193 /* Turn on UART enhanced bits */
194 writeb(efr, &ch->ch_neo_uart->efr);
195
196 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
197 ch->ch_r_watermark = 4;
198
199 writeb(32, &ch->ch_neo_uart->rfifo);
200 ch->ch_r_tlevel = 32;
201
202 /* Tell UART what start/stop chars it should be looking for */
203 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
204 writeb(0, &ch->ch_neo_uart->xonchar2);
205
206 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
207 writeb(0, &ch->ch_neo_uart->xoffchar2);
208
209 writeb(ier, &ch->ch_neo_uart->ier);
210
211 neo_pci_posting_flush(ch->ch_bd);
212 }
213
214
neo_set_ixoff_flow_control(struct channel_t * ch)215 static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
216 {
217 unsigned char ier = readb(&ch->ch_neo_uart->ier);
218 unsigned char efr = readb(&ch->ch_neo_uart->efr);
219
220 /* Turn off auto RTS flow control */
221 ier &= ~UART_17158_IER_RTSDTR;
222 efr &= ~UART_17158_EFR_RTSDTR;
223
224 /* Turn on auto Xoff flow control */
225 ier |= UART_17158_IER_XOFF;
226 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
227
228 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
229 writeb(0, &ch->ch_neo_uart->efr);
230
231 /* Turn on UART enhanced bits */
232 writeb(efr, &ch->ch_neo_uart->efr);
233
234 /* Turn on table D, with 8 char hi/low watermarks */
235 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
236
237 writeb(8, &ch->ch_neo_uart->tfifo);
238 ch->ch_t_tlevel = 8;
239
240 /* Tell UART what start/stop chars it should be looking for */
241 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
242 writeb(0, &ch->ch_neo_uart->xonchar2);
243
244 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
245 writeb(0, &ch->ch_neo_uart->xoffchar2);
246
247 writeb(ier, &ch->ch_neo_uart->ier);
248
249 neo_pci_posting_flush(ch->ch_bd);
250 }
251
252
neo_set_no_input_flow_control(struct channel_t * ch)253 static inline void neo_set_no_input_flow_control(struct channel_t *ch)
254 {
255 unsigned char ier = readb(&ch->ch_neo_uart->ier);
256 unsigned char efr = readb(&ch->ch_neo_uart->efr);
257
258 /* Turn off auto RTS flow control */
259 ier &= ~UART_17158_IER_RTSDTR;
260 efr &= ~UART_17158_EFR_RTSDTR;
261
262 /* Turn off auto Xoff flow control */
263 ier &= ~UART_17158_IER_XOFF;
264 if (ch->ch_c_iflag & IXON)
265 efr &= ~(UART_17158_EFR_IXOFF);
266 else
267 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
268
269
270 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
271 writeb(0, &ch->ch_neo_uart->efr);
272
273 /* Turn on UART enhanced bits */
274 writeb(efr, &ch->ch_neo_uart->efr);
275
276 /* Turn on table D, with 8 char hi/low watermarks */
277 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
278
279 ch->ch_r_watermark = 0;
280
281 writeb(16, &ch->ch_neo_uart->tfifo);
282 ch->ch_t_tlevel = 16;
283
284 writeb(16, &ch->ch_neo_uart->rfifo);
285 ch->ch_r_tlevel = 16;
286
287 writeb(ier, &ch->ch_neo_uart->ier);
288
289 neo_pci_posting_flush(ch->ch_bd);
290 }
291
292
neo_set_no_output_flow_control(struct channel_t * ch)293 static inline void neo_set_no_output_flow_control(struct channel_t *ch)
294 {
295 unsigned char ier = readb(&ch->ch_neo_uart->ier);
296 unsigned char efr = readb(&ch->ch_neo_uart->efr);
297
298 /* Turn off auto CTS flow control */
299 ier &= ~UART_17158_IER_CTSDSR;
300 efr &= ~UART_17158_EFR_CTSDSR;
301
302 /* Turn off auto Xon flow control */
303 if (ch->ch_c_iflag & IXOFF)
304 efr &= ~UART_17158_EFR_IXON;
305 else
306 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
307
308 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
309 writeb(0, &ch->ch_neo_uart->efr);
310
311 /* Turn on UART enhanced bits */
312 writeb(efr, &ch->ch_neo_uart->efr);
313
314 /* Turn on table D, with 8 char hi/low watermarks */
315 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
316
317 ch->ch_r_watermark = 0;
318
319 writeb(16, &ch->ch_neo_uart->tfifo);
320 ch->ch_t_tlevel = 16;
321
322 writeb(16, &ch->ch_neo_uart->rfifo);
323 ch->ch_r_tlevel = 16;
324
325 writeb(ier, &ch->ch_neo_uart->ier);
326
327 neo_pci_posting_flush(ch->ch_bd);
328 }
329
330
331 /* change UARTs start/stop chars */
neo_set_new_start_stop_chars(struct channel_t * ch)332 static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
333 {
334
335 /* if hardware flow control is set, then skip this whole thing */
336 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
337 return;
338
339 /* Tell UART what start/stop chars it should be looking for */
340 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
341 writeb(0, &ch->ch_neo_uart->xonchar2);
342
343 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
344 writeb(0, &ch->ch_neo_uart->xoffchar2);
345
346 neo_pci_posting_flush(ch->ch_bd);
347 }
348
349
350 /*
351 * No locks are assumed to be held when calling this function.
352 */
neo_clear_break(struct channel_t * ch,int force)353 static inline void neo_clear_break(struct channel_t *ch, int force)
354 {
355 unsigned long flags;
356
357 spin_lock_irqsave(&ch->ch_lock, flags);
358
359 /* Bail if we aren't currently sending a break. */
360 if (!ch->ch_stop_sending_break) {
361 spin_unlock_irqrestore(&ch->ch_lock, flags);
362 return;
363 }
364
365 /* Turn break off, and unset some variables */
366 if (ch->ch_flags & CH_BREAK_SENDING) {
367 if (time_after_eq(jiffies, ch->ch_stop_sending_break)
368 || force) {
369 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
370
371 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
372 neo_pci_posting_flush(ch->ch_bd);
373 ch->ch_flags &= ~(CH_BREAK_SENDING);
374 ch->ch_stop_sending_break = 0;
375 }
376 }
377 spin_unlock_irqrestore(&ch->ch_lock, flags);
378 }
379
380
381 /*
382 * Parse the ISR register.
383 */
neo_parse_isr(struct dgnc_board * brd,uint port)384 static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
385 {
386 struct channel_t *ch;
387 unsigned char isr;
388 unsigned char cause;
389 unsigned long flags;
390
391 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
392 return;
393
394 if (port >= brd->maxports)
395 return;
396
397 ch = brd->channels[port];
398 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
399 return;
400
401 /* Here we try to figure out what caused the interrupt to happen */
402 while (1) {
403
404 isr = readb(&ch->ch_neo_uart->isr_fcr);
405
406 /* Bail if no pending interrupt */
407 if (isr & UART_IIR_NO_INT)
408 break;
409
410 /*
411 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
412 */
413 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
414
415 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
416 /* Read data from uart -> queue */
417 brd->intr_rx++;
418 ch->ch_intr_rx++;
419 neo_copy_data_from_uart_to_queue(ch);
420
421 /* Call our tty layer to enforce queue flow control if needed. */
422 spin_lock_irqsave(&ch->ch_lock, flags);
423 dgnc_check_queue_flow_control(ch);
424 spin_unlock_irqrestore(&ch->ch_lock, flags);
425 }
426
427 if (isr & UART_IIR_THRI) {
428 brd->intr_tx++;
429 ch->ch_intr_tx++;
430 /* Transfer data (if any) from Write Queue -> UART. */
431 spin_lock_irqsave(&ch->ch_lock, flags);
432 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
433 spin_unlock_irqrestore(&ch->ch_lock, flags);
434 neo_copy_data_from_queue_to_uart(ch);
435 }
436
437 if (isr & UART_17158_IIR_XONXOFF) {
438 cause = readb(&ch->ch_neo_uart->xoffchar1);
439
440 /*
441 * Since the UART detected either an XON or
442 * XOFF match, we need to figure out which
443 * one it was, so we can suspend or resume data flow.
444 */
445 if (cause == UART_17158_XON_DETECT) {
446 /* Is output stopped right now, if so, resume it */
447 if (brd->channels[port]->ch_flags & CH_STOP) {
448 spin_lock_irqsave(&ch->ch_lock,
449 flags);
450 ch->ch_flags &= ~(CH_STOP);
451 spin_unlock_irqrestore(&ch->ch_lock,
452 flags);
453 }
454 } else if (cause == UART_17158_XOFF_DETECT) {
455 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
456 spin_lock_irqsave(&ch->ch_lock,
457 flags);
458 ch->ch_flags |= CH_STOP;
459 spin_unlock_irqrestore(&ch->ch_lock,
460 flags);
461 }
462 }
463 }
464
465 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
466 /*
467 * If we get here, this means the hardware is doing auto flow control.
468 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
469 */
470 brd->intr_modem++;
471 ch->ch_intr_modem++;
472 cause = readb(&ch->ch_neo_uart->mcr);
473 /* Which pin is doing auto flow? RTS or DTR? */
474 if ((cause & 0x4) == 0) {
475 if (cause & UART_MCR_RTS) {
476 spin_lock_irqsave(&ch->ch_lock,
477 flags);
478 ch->ch_mostat |= UART_MCR_RTS;
479 spin_unlock_irqrestore(&ch->ch_lock,
480 flags);
481 } else {
482 spin_lock_irqsave(&ch->ch_lock,
483 flags);
484 ch->ch_mostat &= ~(UART_MCR_RTS);
485 spin_unlock_irqrestore(&ch->ch_lock,
486 flags);
487 }
488 } else {
489 if (cause & UART_MCR_DTR) {
490 spin_lock_irqsave(&ch->ch_lock,
491 flags);
492 ch->ch_mostat |= UART_MCR_DTR;
493 spin_unlock_irqrestore(&ch->ch_lock,
494 flags);
495 } else {
496 spin_lock_irqsave(&ch->ch_lock,
497 flags);
498 ch->ch_mostat &= ~(UART_MCR_DTR);
499 spin_unlock_irqrestore(&ch->ch_lock,
500 flags);
501 }
502 }
503 }
504
505 /* Parse any modem signal changes */
506 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
507 }
508 }
509
510
neo_parse_lsr(struct dgnc_board * brd,uint port)511 static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
512 {
513 struct channel_t *ch;
514 int linestatus;
515 unsigned long flags;
516
517 /*
518 * Check to make sure it didn't receive interrupt with a null board
519 * associated or a board pointer that wasn't ours.
520 */
521 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
522 return;
523
524 if (port >= brd->maxports)
525 return;
526
527 ch = brd->channels[port];
528 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
529 return;
530
531 linestatus = readb(&ch->ch_neo_uart->lsr);
532
533 ch->ch_cached_lsr |= linestatus;
534
535 if (ch->ch_cached_lsr & UART_LSR_DR) {
536 brd->intr_rx++;
537 ch->ch_intr_rx++;
538 /* Read data from uart -> queue */
539 neo_copy_data_from_uart_to_queue(ch);
540 spin_lock_irqsave(&ch->ch_lock, flags);
541 dgnc_check_queue_flow_control(ch);
542 spin_unlock_irqrestore(&ch->ch_lock, flags);
543 }
544
545 /*
546 * The next 3 tests should *NOT* happen, as the above test
547 * should encapsulate all 3... At least, thats what Exar says.
548 */
549
550 if (linestatus & UART_LSR_PE)
551 ch->ch_err_parity++;
552
553 if (linestatus & UART_LSR_FE)
554 ch->ch_err_frame++;
555
556 if (linestatus & UART_LSR_BI)
557 ch->ch_err_break++;
558
559 if (linestatus & UART_LSR_OE) {
560 /*
561 * Rx Oruns. Exar says that an orun will NOT corrupt
562 * the FIFO. It will just replace the holding register
563 * with this new data byte. So basically just ignore this.
564 * Probably we should eventually have an orun stat in our driver...
565 */
566 ch->ch_err_overrun++;
567 }
568
569 if (linestatus & UART_LSR_THRE) {
570 brd->intr_tx++;
571 ch->ch_intr_tx++;
572 spin_lock_irqsave(&ch->ch_lock, flags);
573 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
574 spin_unlock_irqrestore(&ch->ch_lock, flags);
575
576 /* Transfer data (if any) from Write Queue -> UART. */
577 neo_copy_data_from_queue_to_uart(ch);
578 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
579 brd->intr_tx++;
580 ch->ch_intr_tx++;
581 spin_lock_irqsave(&ch->ch_lock, flags);
582 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
583 spin_unlock_irqrestore(&ch->ch_lock, flags);
584
585 /* Transfer data (if any) from Write Queue -> UART. */
586 neo_copy_data_from_queue_to_uart(ch);
587 }
588 }
589
590
591 /*
592 * neo_param()
593 * Send any/all changes to the line to the UART.
594 */
neo_param(struct tty_struct * tty)595 static void neo_param(struct tty_struct *tty)
596 {
597 unsigned char lcr = 0;
598 unsigned char uart_lcr = 0;
599 unsigned char ier = 0;
600 unsigned char uart_ier = 0;
601 uint baud = 9600;
602 int quot = 0;
603 struct dgnc_board *bd;
604 struct channel_t *ch;
605 struct un_t *un;
606
607 if (!tty || tty->magic != TTY_MAGIC)
608 return;
609
610 un = (struct un_t *) tty->driver_data;
611 if (!un || un->magic != DGNC_UNIT_MAGIC)
612 return;
613
614 ch = un->un_ch;
615 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
616 return;
617
618 bd = ch->ch_bd;
619 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
620 return;
621
622 /*
623 * If baud rate is zero, flush queues, and set mval to drop DTR.
624 */
625 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
626 ch->ch_r_head = 0;
627 ch->ch_r_tail = 0;
628 ch->ch_e_head = 0;
629 ch->ch_e_tail = 0;
630 ch->ch_w_head = 0;
631 ch->ch_w_tail = 0;
632
633 neo_flush_uart_write(ch);
634 neo_flush_uart_read(ch);
635
636 /* The baudrate is B0 so all modem lines are to be dropped. */
637 ch->ch_flags |= (CH_BAUD0);
638 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
639 neo_assert_modem_signals(ch);
640 ch->ch_old_baud = 0;
641 return;
642
643 } else if (ch->ch_custom_speed) {
644
645 baud = ch->ch_custom_speed;
646 /* Handle transition from B0 */
647 if (ch->ch_flags & CH_BAUD0) {
648 ch->ch_flags &= ~(CH_BAUD0);
649
650 /*
651 * Bring back up RTS and DTR...
652 * Also handle RTS or DTR toggle if set.
653 */
654 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
655 ch->ch_mostat |= (UART_MCR_RTS);
656 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
657 ch->ch_mostat |= (UART_MCR_DTR);
658 }
659 } else {
660 int iindex = 0;
661 int jindex = 0;
662
663 ulong bauds[4][16] = {
664 { /* slowbaud */
665 0, 50, 75, 110,
666 134, 150, 200, 300,
667 600, 1200, 1800, 2400,
668 4800, 9600, 19200, 38400 },
669 { /* slowbaud & CBAUDEX */
670 0, 57600, 115200, 230400,
671 460800, 150, 200, 921600,
672 600, 1200, 1800, 2400,
673 4800, 9600, 19200, 38400 },
674 { /* fastbaud */
675 0, 57600, 76800, 115200,
676 131657, 153600, 230400, 460800,
677 921600, 1200, 1800, 2400,
678 4800, 9600, 19200, 38400 },
679 { /* fastbaud & CBAUDEX */
680 0, 57600, 115200, 230400,
681 460800, 150, 200, 921600,
682 600, 1200, 1800, 2400,
683 4800, 9600, 19200, 38400 }
684 };
685
686 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
687 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
688 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
689 else
690 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
691
692 if (ch->ch_c_cflag & CBAUDEX)
693 iindex = 1;
694
695 if (ch->ch_digi.digi_flags & DIGI_FAST)
696 iindex += 2;
697
698 jindex = baud;
699
700 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16))
701 baud = bauds[iindex][jindex];
702 else
703 baud = 0;
704
705 if (baud == 0)
706 baud = 9600;
707
708 /* Handle transition from B0 */
709 if (ch->ch_flags & CH_BAUD0) {
710 ch->ch_flags &= ~(CH_BAUD0);
711
712 /*
713 * Bring back up RTS and DTR...
714 * Also handle RTS or DTR toggle if set.
715 */
716 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
717 ch->ch_mostat |= (UART_MCR_RTS);
718 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
719 ch->ch_mostat |= (UART_MCR_DTR);
720 }
721 }
722
723 if (ch->ch_c_cflag & PARENB)
724 lcr |= UART_LCR_PARITY;
725
726 if (!(ch->ch_c_cflag & PARODD))
727 lcr |= UART_LCR_EPAR;
728
729 /*
730 * Not all platforms support mark/space parity,
731 * so this will hide behind an ifdef.
732 */
733 #ifdef CMSPAR
734 if (ch->ch_c_cflag & CMSPAR)
735 lcr |= UART_LCR_SPAR;
736 #endif
737
738 if (ch->ch_c_cflag & CSTOPB)
739 lcr |= UART_LCR_STOP;
740
741 switch (ch->ch_c_cflag & CSIZE) {
742 case CS5:
743 lcr |= UART_LCR_WLEN5;
744 break;
745 case CS6:
746 lcr |= UART_LCR_WLEN6;
747 break;
748 case CS7:
749 lcr |= UART_LCR_WLEN7;
750 break;
751 case CS8:
752 default:
753 lcr |= UART_LCR_WLEN8;
754 break;
755 }
756
757 uart_ier = readb(&ch->ch_neo_uart->ier);
758 ier = uart_ier;
759
760 uart_lcr = readb(&ch->ch_neo_uart->lcr);
761
762 if (baud == 0)
763 baud = 9600;
764
765 quot = ch->ch_bd->bd_dividend / baud;
766
767 if (quot != 0 && ch->ch_old_baud != baud) {
768 ch->ch_old_baud = baud;
769 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
770 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
771 writeb((quot >> 8), &ch->ch_neo_uart->ier);
772 writeb(lcr, &ch->ch_neo_uart->lcr);
773 }
774
775 if (uart_lcr != lcr)
776 writeb(lcr, &ch->ch_neo_uart->lcr);
777
778 if (ch->ch_c_cflag & CREAD)
779 ier |= (UART_IER_RDI | UART_IER_RLSI);
780 else
781 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
782
783 /*
784 * Have the UART interrupt on modem signal changes ONLY when
785 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
786 */
787 if ((ch->ch_digi.digi_flags & CTSPACE) ||
788 (ch->ch_digi.digi_flags & RTSPACE) ||
789 (ch->ch_c_cflag & CRTSCTS) ||
790 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
791 !(ch->ch_c_cflag & CLOCAL))
792 ier |= UART_IER_MSI;
793 else
794 ier &= ~UART_IER_MSI;
795
796 ier |= UART_IER_THRI;
797
798 if (ier != uart_ier)
799 writeb(ier, &ch->ch_neo_uart->ier);
800
801 /* Set new start/stop chars */
802 neo_set_new_start_stop_chars(ch);
803
804 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
805 neo_set_cts_flow_control(ch);
806 } else if (ch->ch_c_iflag & IXON) {
807 /* If start/stop is set to disable, then we should disable flow control */
808 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
809 neo_set_no_output_flow_control(ch);
810 else
811 neo_set_ixon_flow_control(ch);
812 } else {
813 neo_set_no_output_flow_control(ch);
814 }
815
816 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
817 neo_set_rts_flow_control(ch);
818 } else if (ch->ch_c_iflag & IXOFF) {
819 /* If start/stop is set to disable, then we should disable flow control */
820 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
821 neo_set_no_input_flow_control(ch);
822 else
823 neo_set_ixoff_flow_control(ch);
824 } else {
825 neo_set_no_input_flow_control(ch);
826 }
827
828 /*
829 * Adjust the RX FIFO Trigger level if baud is less than 9600.
830 * Not exactly elegant, but this is needed because of the Exar chip's
831 * delay on firing off the RX FIFO interrupt on slower baud rates.
832 */
833 if (baud < 9600) {
834 writeb(1, &ch->ch_neo_uart->rfifo);
835 ch->ch_r_tlevel = 1;
836 }
837
838 neo_assert_modem_signals(ch);
839
840 /* Get current status of the modem signals now */
841 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
842 }
843
844
845 /*
846 * Our board poller function.
847 */
neo_tasklet(unsigned long data)848 static void neo_tasklet(unsigned long data)
849 {
850 struct dgnc_board *bd = (struct dgnc_board *) data;
851 struct channel_t *ch;
852 unsigned long flags;
853 int i;
854 int state = 0;
855 int ports = 0;
856
857 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
858 return;
859
860 /* Cache a couple board values */
861 spin_lock_irqsave(&bd->bd_lock, flags);
862 state = bd->state;
863 ports = bd->nasync;
864 spin_unlock_irqrestore(&bd->bd_lock, flags);
865
866 /*
867 * Do NOT allow the interrupt routine to read the intr registers
868 * Until we release this lock.
869 */
870 spin_lock_irqsave(&bd->bd_intr_lock, flags);
871
872 /*
873 * If board is ready, parse deeper to see if there is anything to do.
874 */
875 if ((state == BOARD_READY) && (ports > 0)) {
876 /* Loop on each port */
877 for (i = 0; i < ports; i++) {
878 ch = bd->channels[i];
879
880 /* Just being careful... */
881 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
882 continue;
883
884 /*
885 * NOTE: Remember you CANNOT hold any channel
886 * locks when calling the input routine.
887 *
888 * During input processing, its possible we
889 * will call the Linux ld, which might in turn,
890 * do a callback right back into us, resulting
891 * in us trying to grab the channel lock twice!
892 */
893 dgnc_input(ch);
894
895 /*
896 * Channel lock is grabbed and then released
897 * inside both of these routines, but neither
898 * call anything else that could call back into us.
899 */
900 neo_copy_data_from_queue_to_uart(ch);
901 dgnc_wakeup_writes(ch);
902
903 /*
904 * Call carrier carrier function, in case something
905 * has changed.
906 */
907 dgnc_carrier(ch);
908
909 /*
910 * Check to see if we need to turn off a sending break.
911 * The timing check is done inside clear_break()
912 */
913 if (ch->ch_stop_sending_break)
914 neo_clear_break(ch, 0);
915 }
916 }
917
918 /* Allow interrupt routine to access the interrupt register again */
919 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
920
921 }
922
923
924 /*
925 * dgnc_neo_intr()
926 *
927 * Neo specific interrupt handler.
928 */
neo_intr(int irq,void * voidbrd)929 static irqreturn_t neo_intr(int irq, void *voidbrd)
930 {
931 struct dgnc_board *brd = voidbrd;
932 struct channel_t *ch;
933 int port = 0;
934 int type = 0;
935 int current_port;
936 u32 tmp;
937 u32 uart_poll;
938 unsigned long flags;
939 unsigned long flags2;
940
941 /*
942 * Check to make sure it didn't receive interrupt with a null board
943 * associated or a board pointer that wasn't ours.
944 */
945 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
946 return IRQ_NONE;
947
948 brd->intr_count++;
949
950 /* Lock out the slow poller from running on this board. */
951 spin_lock_irqsave(&brd->bd_intr_lock, flags);
952
953 /*
954 * Read in "extended" IRQ information from the 32bit Neo register.
955 * Bits 0-7: What port triggered the interrupt.
956 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
957 */
958 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
959
960 /*
961 * If 0, no interrupts pending.
962 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
963 */
964 if (!uart_poll) {
965 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
966 return IRQ_NONE;
967 }
968
969 /* At this point, we have at least SOMETHING to service, dig further... */
970
971 current_port = 0;
972
973 /* Loop on each port */
974 while ((uart_poll & 0xff) != 0) {
975
976 tmp = uart_poll;
977
978 /* Check current port to see if it has interrupt pending */
979 if ((tmp & dgnc_offset_table[current_port]) != 0) {
980 port = current_port;
981 type = tmp >> (8 + (port * 3));
982 type &= 0x7;
983 } else {
984 current_port++;
985 continue;
986 }
987
988 /* Remove this port + type from uart_poll */
989 uart_poll &= ~(dgnc_offset_table[port]);
990
991 if (!type) {
992 /* If no type, just ignore it, and move onto next port */
993 continue;
994 }
995
996 /* Switch on type of interrupt we have */
997 switch (type) {
998
999 case UART_17158_RXRDY_TIMEOUT:
1000 /*
1001 * RXRDY Time-out is cleared by reading data in the
1002 * RX FIFO until it falls below the trigger level.
1003 */
1004
1005 /* Verify the port is in range. */
1006 if (port >= brd->nasync)
1007 continue;
1008
1009 ch = brd->channels[port];
1010 neo_copy_data_from_uart_to_queue(ch);
1011
1012 /* Call our tty layer to enforce queue flow control if needed. */
1013 spin_lock_irqsave(&ch->ch_lock, flags2);
1014 dgnc_check_queue_flow_control(ch);
1015 spin_unlock_irqrestore(&ch->ch_lock, flags2);
1016
1017 continue;
1018
1019 case UART_17158_RX_LINE_STATUS:
1020 /*
1021 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1022 */
1023 neo_parse_lsr(brd, port);
1024 continue;
1025
1026 case UART_17158_TXRDY:
1027 /*
1028 * TXRDY interrupt clears after reading ISR register for the UART channel.
1029 */
1030
1031 /*
1032 * Yes, this is odd...
1033 * Why would I check EVERY possibility of type of
1034 * interrupt, when we know its TXRDY???
1035 * Becuz for some reason, even tho we got triggered for TXRDY,
1036 * it seems to be occasionally wrong. Instead of TX, which
1037 * it should be, I was getting things like RXDY too. Weird.
1038 */
1039 neo_parse_isr(brd, port);
1040 continue;
1041
1042 case UART_17158_MSR:
1043 /*
1044 * MSR or flow control was seen.
1045 */
1046 neo_parse_isr(brd, port);
1047 continue;
1048
1049 default:
1050 /*
1051 * The UART triggered us with a bogus interrupt type.
1052 * It appears the Exar chip, when REALLY bogged down, will throw
1053 * these once and awhile.
1054 * Its harmless, just ignore it and move on.
1055 */
1056 continue;
1057 }
1058 }
1059
1060 /*
1061 * Schedule tasklet to more in-depth servicing at a better time.
1062 */
1063 tasklet_schedule(&brd->helper_tasklet);
1064
1065 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
1066
1067 return IRQ_HANDLED;
1068 }
1069
1070
1071 /*
1072 * Neo specific way of turning off the receiver.
1073 * Used as a way to enforce queue flow control when in
1074 * hardware flow control mode.
1075 */
neo_disable_receiver(struct channel_t * ch)1076 static void neo_disable_receiver(struct channel_t *ch)
1077 {
1078 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1079
1080 tmp &= ~(UART_IER_RDI);
1081 writeb(tmp, &ch->ch_neo_uart->ier);
1082 neo_pci_posting_flush(ch->ch_bd);
1083 }
1084
1085
1086 /*
1087 * Neo specific way of turning on the receiver.
1088 * Used as a way to un-enforce queue flow control when in
1089 * hardware flow control mode.
1090 */
neo_enable_receiver(struct channel_t * ch)1091 static void neo_enable_receiver(struct channel_t *ch)
1092 {
1093 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1094
1095 tmp |= (UART_IER_RDI);
1096 writeb(tmp, &ch->ch_neo_uart->ier);
1097 neo_pci_posting_flush(ch->ch_bd);
1098 }
1099
1100
neo_copy_data_from_uart_to_queue(struct channel_t * ch)1101 static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1102 {
1103 int qleft = 0;
1104 unsigned char linestatus = 0;
1105 unsigned char error_mask = 0;
1106 int n = 0;
1107 int total = 0;
1108 ushort head;
1109 ushort tail;
1110 unsigned long flags;
1111
1112 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1113 return;
1114
1115 spin_lock_irqsave(&ch->ch_lock, flags);
1116
1117 /* cache head and tail of queue */
1118 head = ch->ch_r_head & RQUEUEMASK;
1119 tail = ch->ch_r_tail & RQUEUEMASK;
1120
1121 /* Get our cached LSR */
1122 linestatus = ch->ch_cached_lsr;
1123 ch->ch_cached_lsr = 0;
1124
1125 /* Store how much space we have left in the queue */
1126 qleft = tail - head - 1;
1127 if (qleft < 0)
1128 qleft += RQUEUEMASK + 1;
1129
1130 /*
1131 * If the UART is not in FIFO mode, force the FIFO copy to
1132 * NOT be run, by setting total to 0.
1133 *
1134 * On the other hand, if the UART IS in FIFO mode, then ask
1135 * the UART to give us an approximation of data it has RX'ed.
1136 */
1137 if (!(ch->ch_flags & CH_FIFO_ENABLED))
1138 total = 0;
1139 else {
1140 total = readb(&ch->ch_neo_uart->rfifo);
1141
1142 /*
1143 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1144 *
1145 * This resolves a problem/bug with the Exar chip that sometimes
1146 * returns a bogus value in the rfifo register.
1147 * The count can be any where from 0-3 bytes "off".
1148 * Bizarre, but true.
1149 */
1150 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
1151 total -= 1;
1152 else
1153 total -= 3;
1154 }
1155
1156
1157 /*
1158 * Finally, bound the copy to make sure we don't overflow
1159 * our own queue...
1160 * The byte by byte copy loop below this loop this will
1161 * deal with the queue overflow possibility.
1162 */
1163 total = min(total, qleft);
1164
1165 while (total > 0) {
1166
1167 /*
1168 * Grab the linestatus register, we need to check
1169 * to see if there are any errors in the FIFO.
1170 */
1171 linestatus = readb(&ch->ch_neo_uart->lsr);
1172
1173 /*
1174 * Break out if there is a FIFO error somewhere.
1175 * This will allow us to go byte by byte down below,
1176 * finding the exact location of the error.
1177 */
1178 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1179 break;
1180
1181 /* Make sure we don't go over the end of our queue */
1182 n = min(((uint) total), (RQUEUESIZE - (uint) head));
1183
1184 /*
1185 * Cut down n even further if needed, this is to fix
1186 * a problem with memcpy_fromio() with the Neo on the
1187 * IBM pSeries platform.
1188 * 15 bytes max appears to be the magic number.
1189 */
1190 n = min_t(uint, n, 12);
1191
1192 /*
1193 * Since we are grabbing the linestatus register, which
1194 * will reset some bits after our read, we need to ensure
1195 * we don't miss our TX FIFO emptys.
1196 */
1197 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
1198 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1199
1200 linestatus = 0;
1201
1202 /* Copy data from uart to the queue */
1203 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
1204
1205 /*
1206 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
1207 * that all the data currently in the FIFO is free of
1208 * breaks and parity/frame/orun errors.
1209 */
1210 memset(ch->ch_equeue + head, 0, n);
1211
1212 /* Add to and flip head if needed */
1213 head = (head + n) & RQUEUEMASK;
1214 total -= n;
1215 qleft -= n;
1216 ch->ch_rxcount += n;
1217 }
1218
1219 /*
1220 * Create a mask to determine whether we should
1221 * insert the character (if any) into our queue.
1222 */
1223 if (ch->ch_c_iflag & IGNBRK)
1224 error_mask |= UART_LSR_BI;
1225
1226 /*
1227 * Now cleanup any leftover bytes still in the UART.
1228 * Also deal with any possible queue overflow here as well.
1229 */
1230 while (1) {
1231
1232 /*
1233 * Its possible we have a linestatus from the loop above
1234 * this, so we "OR" on any extra bits.
1235 */
1236 linestatus |= readb(&ch->ch_neo_uart->lsr);
1237
1238 /*
1239 * If the chip tells us there is no more data pending to
1240 * be read, we can then leave.
1241 * But before we do, cache the linestatus, just in case.
1242 */
1243 if (!(linestatus & UART_LSR_DR)) {
1244 ch->ch_cached_lsr = linestatus;
1245 break;
1246 }
1247
1248 /* No need to store this bit */
1249 linestatus &= ~UART_LSR_DR;
1250
1251 /*
1252 * Since we are grabbing the linestatus register, which
1253 * will reset some bits after our read, we need to ensure
1254 * we don't miss our TX FIFO emptys.
1255 */
1256 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1257 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
1258 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1259 }
1260
1261 /*
1262 * Discard character if we are ignoring the error mask.
1263 */
1264 if (linestatus & error_mask) {
1265 unsigned char discard;
1266
1267 linestatus = 0;
1268 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1269 continue;
1270 }
1271
1272 /*
1273 * If our queue is full, we have no choice but to drop some data.
1274 * The assumption is that HWFLOW or SWFLOW should have stopped
1275 * things way way before we got to this point.
1276 *
1277 * I decided that I wanted to ditch the oldest data first,
1278 * I hope thats okay with everyone? Yes? Good.
1279 */
1280 while (qleft < 1) {
1281 tail = (tail + 1) & RQUEUEMASK;
1282 ch->ch_r_tail = tail;
1283 ch->ch_err_overrun++;
1284 qleft++;
1285 }
1286
1287 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
1288 ch->ch_equeue[head] = (unsigned char) linestatus;
1289
1290 /* Ditch any remaining linestatus value. */
1291 linestatus = 0;
1292
1293 /* Add to and flip head if needed */
1294 head = (head + 1) & RQUEUEMASK;
1295
1296 qleft--;
1297 ch->ch_rxcount++;
1298 }
1299
1300 /*
1301 * Write new final heads to channel structure.
1302 */
1303 ch->ch_r_head = head & RQUEUEMASK;
1304 ch->ch_e_head = head & EQUEUEMASK;
1305
1306 spin_unlock_irqrestore(&ch->ch_lock, flags);
1307 }
1308
1309
1310 /*
1311 * This function basically goes to sleep for secs, or until
1312 * it gets signalled that the port has fully drained.
1313 */
neo_drain(struct tty_struct * tty,uint seconds)1314 static int neo_drain(struct tty_struct *tty, uint seconds)
1315 {
1316 unsigned long flags;
1317 struct channel_t *ch;
1318 struct un_t *un;
1319 int rc = 0;
1320
1321 if (!tty || tty->magic != TTY_MAGIC)
1322 return -ENXIO;
1323
1324 un = (struct un_t *) tty->driver_data;
1325 if (!un || un->magic != DGNC_UNIT_MAGIC)
1326 return -ENXIO;
1327
1328 ch = un->un_ch;
1329 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1330 return -ENXIO;
1331
1332 spin_lock_irqsave(&ch->ch_lock, flags);
1333 un->un_flags |= UN_EMPTY;
1334 spin_unlock_irqrestore(&ch->ch_lock, flags);
1335
1336 /*
1337 * Go to sleep waiting for the tty layer to wake me back up when
1338 * the empty flag goes away.
1339 *
1340 * NOTE: TODO: Do something with time passed in.
1341 */
1342 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
1343
1344 /* If ret is non-zero, user ctrl-c'ed us */
1345 return rc;
1346 }
1347
1348
1349 /*
1350 * Flush the WRITE FIFO on the Neo.
1351 *
1352 * NOTE: Channel lock MUST be held before calling this function!
1353 */
neo_flush_uart_write(struct channel_t * ch)1354 static void neo_flush_uart_write(struct channel_t *ch)
1355 {
1356 unsigned char tmp = 0;
1357 int i = 0;
1358
1359 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1360 return;
1361
1362 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1363 neo_pci_posting_flush(ch->ch_bd);
1364
1365 for (i = 0; i < 10; i++) {
1366
1367 /* Check to see if the UART feels it completely flushed the FIFO. */
1368 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1369 if (tmp & 4)
1370 udelay(10);
1371 else
1372 break;
1373 }
1374
1375 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1376 }
1377
1378
1379 /*
1380 * Flush the READ FIFO on the Neo.
1381 *
1382 * NOTE: Channel lock MUST be held before calling this function!
1383 */
neo_flush_uart_read(struct channel_t * ch)1384 static void neo_flush_uart_read(struct channel_t *ch)
1385 {
1386 unsigned char tmp = 0;
1387 int i = 0;
1388
1389 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1390 return;
1391
1392 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
1393 neo_pci_posting_flush(ch->ch_bd);
1394
1395 for (i = 0; i < 10; i++) {
1396
1397 /* Check to see if the UART feels it completely flushed the FIFO. */
1398 tmp = readb(&ch->ch_neo_uart->isr_fcr);
1399 if (tmp & 2)
1400 udelay(10);
1401 else
1402 break;
1403 }
1404 }
1405
1406
neo_copy_data_from_queue_to_uart(struct channel_t * ch)1407 static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1408 {
1409 ushort head;
1410 ushort tail;
1411 int n;
1412 int s;
1413 int qlen;
1414 uint len_written = 0;
1415 unsigned long flags;
1416
1417 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1418 return;
1419
1420 spin_lock_irqsave(&ch->ch_lock, flags);
1421
1422 /* No data to write to the UART */
1423 if (ch->ch_w_tail == ch->ch_w_head)
1424 goto exit_unlock;
1425
1426 /* If port is "stopped", don't send any data to the UART */
1427 if ((ch->ch_flags & CH_FORCED_STOP) ||
1428 (ch->ch_flags & CH_BREAK_SENDING))
1429 goto exit_unlock;
1430
1431 /*
1432 * If FIFOs are disabled. Send data directly to txrx register
1433 */
1434 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
1435 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
1436
1437 /* Cache the LSR bits for later parsing */
1438 ch->ch_cached_lsr |= lsrbits;
1439 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1440 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1441
1442 /*
1443 * If RTS Toggle mode is on, turn on RTS now if not already set,
1444 * and make sure we get an event when the data transfer has completed.
1445 */
1446 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1447 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1448 ch->ch_mostat |= (UART_MCR_RTS);
1449 neo_assert_modem_signals(ch);
1450 }
1451 ch->ch_tun.un_flags |= (UN_EMPTY);
1452 }
1453 /*
1454 * If DTR Toggle mode is on, turn on DTR now if not already set,
1455 * and make sure we get an event when the data transfer has completed.
1456 */
1457 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1458 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1459 ch->ch_mostat |= (UART_MCR_DTR);
1460 neo_assert_modem_signals(ch);
1461 }
1462 ch->ch_tun.un_flags |= (UN_EMPTY);
1463 }
1464
1465 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
1466 ch->ch_w_tail++;
1467 ch->ch_w_tail &= WQUEUEMASK;
1468 ch->ch_txcount++;
1469 }
1470
1471 goto exit_unlock;
1472 }
1473
1474 /*
1475 * We have to do it this way, because of the EXAR TXFIFO count bug.
1476 */
1477 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1478 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
1479 goto exit_unlock;
1480
1481 len_written = 0;
1482
1483 n = readb(&ch->ch_neo_uart->tfifo);
1484
1485 if ((unsigned int) n > ch->ch_t_tlevel)
1486 goto exit_unlock;
1487
1488 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
1489 } else {
1490 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1491 }
1492
1493 /* cache head and tail of queue */
1494 head = ch->ch_w_head & WQUEUEMASK;
1495 tail = ch->ch_w_tail & WQUEUEMASK;
1496 qlen = (head - tail) & WQUEUEMASK;
1497
1498 /* Find minimum of the FIFO space, versus queue length */
1499 n = min(n, qlen);
1500
1501 while (n > 0) {
1502
1503 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1504 s = min(s, n);
1505
1506 if (s <= 0)
1507 break;
1508
1509 /*
1510 * If RTS Toggle mode is on, turn on RTS now if not already set,
1511 * and make sure we get an event when the data transfer has completed.
1512 */
1513 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1514 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1515 ch->ch_mostat |= (UART_MCR_RTS);
1516 neo_assert_modem_signals(ch);
1517 }
1518 ch->ch_tun.un_flags |= (UN_EMPTY);
1519 }
1520
1521 /*
1522 * If DTR Toggle mode is on, turn on DTR now if not already set,
1523 * and make sure we get an event when the data transfer has completed.
1524 */
1525 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1526 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1527 ch->ch_mostat |= (UART_MCR_DTR);
1528 neo_assert_modem_signals(ch);
1529 }
1530 ch->ch_tun.un_flags |= (UN_EMPTY);
1531 }
1532
1533 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
1534
1535 /* Add and flip queue if needed */
1536 tail = (tail + s) & WQUEUEMASK;
1537 n -= s;
1538 ch->ch_txcount += s;
1539 len_written += s;
1540 }
1541
1542 /* Update the final tail */
1543 ch->ch_w_tail = tail & WQUEUEMASK;
1544
1545 if (len_written > 0) {
1546 neo_pci_posting_flush(ch->ch_bd);
1547 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1548 }
1549
1550 exit_unlock:
1551 spin_unlock_irqrestore(&ch->ch_lock, flags);
1552 }
1553
1554
neo_parse_modem(struct channel_t * ch,unsigned char signals)1555 static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
1556 {
1557 unsigned char msignals = signals;
1558
1559 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1560 return;
1561
1562 /*
1563 * Do altpin switching. Altpin switches DCD and DSR.
1564 * This prolly breaks DSRPACE, so we should be more clever here.
1565 */
1566 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
1567 unsigned char mswap = msignals;
1568
1569 if (mswap & UART_MSR_DDCD) {
1570 msignals &= ~UART_MSR_DDCD;
1571 msignals |= UART_MSR_DDSR;
1572 }
1573 if (mswap & UART_MSR_DDSR) {
1574 msignals &= ~UART_MSR_DDSR;
1575 msignals |= UART_MSR_DDCD;
1576 }
1577 if (mswap & UART_MSR_DCD) {
1578 msignals &= ~UART_MSR_DCD;
1579 msignals |= UART_MSR_DSR;
1580 }
1581 if (mswap & UART_MSR_DSR) {
1582 msignals &= ~UART_MSR_DSR;
1583 msignals |= UART_MSR_DCD;
1584 }
1585 }
1586
1587 /* Scrub off lower bits. They signify delta's, which I don't care about */
1588 msignals &= 0xf0;
1589
1590 if (msignals & UART_MSR_DCD)
1591 ch->ch_mistat |= UART_MSR_DCD;
1592 else
1593 ch->ch_mistat &= ~UART_MSR_DCD;
1594
1595 if (msignals & UART_MSR_DSR)
1596 ch->ch_mistat |= UART_MSR_DSR;
1597 else
1598 ch->ch_mistat &= ~UART_MSR_DSR;
1599
1600 if (msignals & UART_MSR_RI)
1601 ch->ch_mistat |= UART_MSR_RI;
1602 else
1603 ch->ch_mistat &= ~UART_MSR_RI;
1604
1605 if (msignals & UART_MSR_CTS)
1606 ch->ch_mistat |= UART_MSR_CTS;
1607 else
1608 ch->ch_mistat &= ~UART_MSR_CTS;
1609 }
1610
1611
1612 /* Make the UART raise any of the output signals we want up */
neo_assert_modem_signals(struct channel_t * ch)1613 static void neo_assert_modem_signals(struct channel_t *ch)
1614 {
1615 unsigned char out;
1616
1617 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1618 return;
1619
1620 out = ch->ch_mostat;
1621
1622 if (ch->ch_flags & CH_LOOPBACK)
1623 out |= UART_MCR_LOOP;
1624
1625 writeb(out, &ch->ch_neo_uart->mcr);
1626 neo_pci_posting_flush(ch->ch_bd);
1627
1628 /* Give time for the UART to actually raise/drop the signals */
1629 udelay(10);
1630 }
1631
1632
neo_send_start_character(struct channel_t * ch)1633 static void neo_send_start_character(struct channel_t *ch)
1634 {
1635 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1636 return;
1637
1638 if (ch->ch_startc != _POSIX_VDISABLE) {
1639 ch->ch_xon_sends++;
1640 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1641 neo_pci_posting_flush(ch->ch_bd);
1642 udelay(10);
1643 }
1644 }
1645
1646
neo_send_stop_character(struct channel_t * ch)1647 static void neo_send_stop_character(struct channel_t *ch)
1648 {
1649 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1650 return;
1651
1652 if (ch->ch_stopc != _POSIX_VDISABLE) {
1653 ch->ch_xoff_sends++;
1654 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1655 neo_pci_posting_flush(ch->ch_bd);
1656 udelay(10);
1657 }
1658 }
1659
1660
1661 /*
1662 * neo_uart_init
1663 */
neo_uart_init(struct channel_t * ch)1664 static void neo_uart_init(struct channel_t *ch)
1665 {
1666
1667 writeb(0, &ch->ch_neo_uart->ier);
1668 writeb(0, &ch->ch_neo_uart->efr);
1669 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1670
1671
1672 /* Clear out UART and FIFO */
1673 readb(&ch->ch_neo_uart->txrx);
1674 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1675 readb(&ch->ch_neo_uart->lsr);
1676 readb(&ch->ch_neo_uart->msr);
1677
1678 ch->ch_flags |= CH_FIFO_ENABLED;
1679
1680 /* Assert any signals we want up */
1681 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1682 neo_pci_posting_flush(ch->ch_bd);
1683 }
1684
1685
1686 /*
1687 * Make the UART completely turn off.
1688 */
neo_uart_off(struct channel_t * ch)1689 static void neo_uart_off(struct channel_t *ch)
1690 {
1691 /* Turn off UART enhanced bits */
1692 writeb(0, &ch->ch_neo_uart->efr);
1693
1694 /* Stop all interrupts from occurring. */
1695 writeb(0, &ch->ch_neo_uart->ier);
1696 neo_pci_posting_flush(ch->ch_bd);
1697 }
1698
1699
neo_get_uart_bytes_left(struct channel_t * ch)1700 static uint neo_get_uart_bytes_left(struct channel_t *ch)
1701 {
1702 unsigned char left = 0;
1703 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
1704
1705 /* We must cache the LSR as some of the bits get reset once read... */
1706 ch->ch_cached_lsr |= lsr;
1707
1708 /* Determine whether the Transmitter is empty or not */
1709 if (!(lsr & UART_LSR_TEMT)) {
1710 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
1711 tasklet_schedule(&ch->ch_bd->helper_tasklet);
1712 left = 1;
1713 } else {
1714 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1715 left = 0;
1716 }
1717
1718 return left;
1719 }
1720
1721
1722 /* Channel lock MUST be held by the calling function! */
neo_send_break(struct channel_t * ch,int msecs)1723 static void neo_send_break(struct channel_t *ch, int msecs)
1724 {
1725 /*
1726 * If we receive a time of 0, this means turn off the break.
1727 */
1728 if (msecs == 0) {
1729 if (ch->ch_flags & CH_BREAK_SENDING) {
1730 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1731
1732 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1733 neo_pci_posting_flush(ch->ch_bd);
1734 ch->ch_flags &= ~(CH_BREAK_SENDING);
1735 ch->ch_stop_sending_break = 0;
1736 }
1737 return;
1738 }
1739
1740 /*
1741 * Set the time we should stop sending the break.
1742 * If we are already sending a break, toss away the existing
1743 * time to stop, and use this new value instead.
1744 */
1745 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1746
1747 /* Tell the UART to start sending the break */
1748 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1749 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1750
1751 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1752 neo_pci_posting_flush(ch->ch_bd);
1753 ch->ch_flags |= (CH_BREAK_SENDING);
1754 }
1755 }
1756
1757
1758 /*
1759 * neo_send_immediate_char.
1760 *
1761 * Sends a specific character as soon as possible to the UART,
1762 * jumping over any bytes that might be in the write queue.
1763 *
1764 * The channel lock MUST be held by the calling function.
1765 */
neo_send_immediate_char(struct channel_t * ch,unsigned char c)1766 static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1767 {
1768 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1769 return;
1770
1771 writeb(c, &ch->ch_neo_uart->txrx);
1772 neo_pci_posting_flush(ch->ch_bd);
1773 }
1774
1775
neo_read_eeprom(unsigned char __iomem * base,unsigned int address)1776 static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address)
1777 {
1778 unsigned int enable;
1779 unsigned int bits;
1780 unsigned int databit;
1781 unsigned int val;
1782
1783 /* enable chip select */
1784 writeb(NEO_EECS, base + NEO_EEREG);
1785 /* READ */
1786 enable = (address | 0x180);
1787
1788 for (bits = 9; bits--; ) {
1789 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1790 /* Set read address */
1791 writeb(databit | NEO_EECS, base + NEO_EEREG);
1792 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1793 }
1794
1795 val = 0;
1796
1797 for (bits = 17; bits--; ) {
1798 /* clock to EEPROM */
1799 writeb(NEO_EECS, base + NEO_EEREG);
1800 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1801 val <<= 1;
1802 /* read EEPROM */
1803 if (readb(base + NEO_EEREG) & NEO_EEDO)
1804 val |= 1;
1805 }
1806
1807 /* clock falling edge */
1808 writeb(NEO_EECS, base + NEO_EEREG);
1809
1810 /* drop chip select */
1811 writeb(0x00, base + NEO_EEREG);
1812
1813 return val;
1814 }
1815
1816
neo_vpd(struct dgnc_board * brd)1817 static void neo_vpd(struct dgnc_board *brd)
1818 {
1819 unsigned int i = 0;
1820 unsigned int a;
1821
1822 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1823 return;
1824
1825 if (!brd->re_map_membase)
1826 return;
1827
1828 /* Store the VPD into our buffer */
1829 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1830 a = neo_read_eeprom(brd->re_map_membase, i);
1831 brd->vpd[i*2] = a & 0xff;
1832 brd->vpd[(i*2)+1] = (a >> 8) & 0xff;
1833 }
1834
1835 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */
1836 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/
1837 || (brd->vpd[0x7F] != 0x78)) { /* small resource end tag */
1838
1839 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
1840 } else {
1841 /* Search for the serial number */
1842 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1843 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
1844 strncpy(brd->serial_num, &(brd->vpd[i + 3]), 9);
1845 }
1846 }
1847