1/*
2 * Copyright 2003 Digi International (www.digi.com)
3 *	Scott H Kilau <Scott_Kilau at digi dot com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
13 * PURPOSE.  See the GNU General Public License for more details.
14 */
15
16#ifndef __DGNC_CLS_H
17#define __DGNC_CLS_H
18
19/************************************************************************
20 * Per channel/port Classic UART structure				*
21 ************************************************************************
22 *		Base Structure Entries Usage Meanings to Host		*
23 *									*
24 *	W = read write		R = read only				*
25 *			U = Unused.					*
26 ************************************************************************/
27
28/*
29 * txrx    : WR RHR/THR - Holding reg
30 * ier     : WR IER - Interrupt Enable Reg
31 * isr_fcr : WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg
32 * lcr     : WR LCR - Line Control Reg
33 * mcr     : WR MCR - Modem Control Reg
34 * lsr     : WR LSR - Line Status Reg
35 * msr     : WR MSG - Modem Status Reg
36 * spr     : WR SPR - Scratch pad Reg
37 */
38struct cls_uart_struct {
39	u8 txrx;
40	u8 ier;
41	u8 isr_fcr;
42	u8 lcr;
43	u8 mcr;
44	u8 lsr;
45	u8 msr;
46	u8 spr;
47};
48
49/* Where to read the interrupt register (8bits) */
50#define	UART_CLASSIC_POLL_ADDR_OFFSET	0x40
51
52#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
53
54#define UART_16654_FCR_TXTRIGGER_16	0x10
55#define UART_16654_FCR_RXTRIGGER_16	0x40
56#define UART_16654_FCR_RXTRIGGER_56	0x80
57
58/* Received CTS/RTS change of state */
59#define UART_IIR_CTSRTS			0x20
60
61/* Receiver data TIMEOUT */
62#define UART_IIR_RDI_TIMEOUT		0x0C
63
64/*
65 * These are the EXTENDED definitions for the Exar 654's Interrupt
66 * Enable Register.
67 */
68#define UART_EXAR654_EFR_ECB      0x10    /* Enhanced control bit */
69#define UART_EXAR654_EFR_IXON     0x2     /* Receiver compares Xon1/Xoff1 */
70#define UART_EXAR654_EFR_IXOFF    0x8     /* Transmit Xon1/Xoff1 */
71#define UART_EXAR654_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
72#define UART_EXAR654_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
73#define UART_EXAR654_IER_XOFF     0x20    /* Xoff Interrupt Enable */
74#define UART_EXAR654_IER_RTSDTR   0x40    /* Output Interrupt Enable */
75#define UART_EXAR654_IER_CTSDSR   0x80    /* Input Interrupt Enable */
76
77/*
78 * Our Global Variables
79 */
80extern struct board_ops dgnc_cls_ops;
81
82#endif
83