Lines Matching refs:mcr
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
58 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
68 mcr p15, 0, r0, c6, c3 @ disable area 3~7
69 mcr p15, 0, r0, c6, c4
70 mcr p15, 0, r0, c6, c5
71 mcr p15, 0, r0, c6, c6
72 mcr p15, 0, r0, c6, c7
75 mcr p15, 0, r0, c6, c0 @ set area 0, default
85 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
98 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
101 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
107 mcr p15, 0, r0, c3, c0
111 mcr p15, 0, r0, c5, c0 @ all read/write access