1/* 2 * arch/arm/mm/proc-v7-2level.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#define TTB_S (1 << 1) 12#define TTB_RGN_NC (0 << 3) 13#define TTB_RGN_OC_WBWA (1 << 3) 14#define TTB_RGN_OC_WT (2 << 3) 15#define TTB_RGN_OC_WB (3 << 3) 16#define TTB_NOS (1 << 5) 17#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 18#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 19#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 20#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 21 22/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 23#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB 24#define PMD_FLAGS_UP PMD_SECT_WB 25 26/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 27#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 28#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S 29 30/* 31 * cpu_v7_switch_mm(pgd_phys, tsk) 32 * 33 * Set the translation table base pointer to be pgd_phys 34 * 35 * - pgd_phys - physical address of new TTB 36 * 37 * It is assumed that: 38 * - we are not using split page tables 39 */ 40ENTRY(cpu_ca8_switch_mm) 41#ifdef CONFIG_MMU 42 mov r2, #0 43#ifdef CONFIG_ARM_ERRATA_430973 44 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 45#endif 46#endif 47ENTRY(cpu_v7_switch_mm) 48#ifdef CONFIG_MMU 49 mmid r1, r1 @ get mm->context.id 50 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) 51 ALT_UP(orr r0, r0, #TTB_FLAGS_UP) 52#ifdef CONFIG_PID_IN_CONTEXTIDR 53 mrc p15, 0, r2, c13, c0, 1 @ read current context ID 54 lsr r2, r2, #8 @ extract the PID 55 bfi r1, r2, #8, #24 @ insert into new context ID 56#endif 57#ifdef CONFIG_ARM_ERRATA_754322 58 dsb 59#endif 60 mcr p15, 0, r1, c13, c0, 1 @ set context ID 61 isb 62 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 63 isb 64#endif 65 bx lr 66ENDPROC(cpu_v7_switch_mm) 67ENDPROC(cpu_ca8_switch_mm) 68 69/* 70 * cpu_v7_set_pte_ext(ptep, pte) 71 * 72 * Set a level 2 translation table entry. 73 * 74 * - ptep - pointer to level 2 translation table entry 75 * (hardware version is stored at +2048 bytes) 76 * - pte - PTE value to store 77 * - ext - value for extended PTE bits 78 */ 79ENTRY(cpu_v7_set_pte_ext) 80#ifdef CONFIG_MMU 81 str r1, [r0] @ linux version 82 83 bic r3, r1, #0x000003f0 84 bic r3, r3, #PTE_TYPE_MASK 85 orr r3, r3, r2 86 orr r3, r3, #PTE_EXT_AP0 | 2 87 88 tst r1, #1 << 4 89 orrne r3, r3, #PTE_EXT_TEX(1) 90 91 eor r1, r1, #L_PTE_DIRTY 92 tst r1, #L_PTE_RDONLY | L_PTE_DIRTY 93 orrne r3, r3, #PTE_EXT_APX 94 95 tst r1, #L_PTE_USER 96 orrne r3, r3, #PTE_EXT_AP1 97 98 tst r1, #L_PTE_XN 99 orrne r3, r3, #PTE_EXT_XN 100 101 tst r1, #L_PTE_YOUNG 102 tstne r1, #L_PTE_VALID 103 eorne r1, r1, #L_PTE_NONE 104 tstne r1, #L_PTE_NONE 105 moveq r3, #0 106 107 ARM( str r3, [r0, #2048]! ) 108 THUMB( add r0, r0, #2048 ) 109 THUMB( str r3, [r0] ) 110 ALT_SMP(W(nop)) 111 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte 112#endif 113 bx lr 114ENDPROC(cpu_v7_set_pte_ext) 115 116 /* 117 * Memory region attributes with SCTLR.TRE=1 118 * 119 * n = TEX[0],C,B 120 * TR = PRRR[2n+1:2n] - memory type 121 * IR = NMRR[2n+1:2n] - inner cacheable property 122 * OR = NMRR[2n+17:2n+16] - outer cacheable property 123 * 124 * n TR IR OR 125 * UNCACHED 000 00 126 * BUFFERABLE 001 10 00 00 127 * WRITETHROUGH 010 10 10 10 128 * WRITEBACK 011 10 11 11 129 * reserved 110 130 * WRITEALLOC 111 10 01 01 131 * DEV_SHARED 100 01 132 * DEV_NONSHARED 100 01 133 * DEV_WC 001 10 134 * DEV_CACHED 011 10 135 * 136 * Other attributes: 137 * 138 * DS0 = PRRR[16] = 0 - device shareable property 139 * DS1 = PRRR[17] = 1 - device shareable property 140 * NS0 = PRRR[18] = 0 - normal shareable property 141 * NS1 = PRRR[19] = 1 - normal shareable property 142 * NOS = PRRR[24+n] = 1 - not outer shareable 143 */ 144.equ PRRR, 0xff0a81a8 145.equ NMRR, 0x40e040e0 146 147 /* 148 * Macro for setting up the TTBRx and TTBCR registers. 149 * - \ttb0 and \ttb1 updated with the corresponding flags. 150 */ 151 .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp 152 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register 153 ALT_SMP(orr \ttbr0, \ttbr0, #TTB_FLAGS_SMP) 154 ALT_UP(orr \ttbr0, \ttbr0, #TTB_FLAGS_UP) 155 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP) 156 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP) 157 mcr p15, 0, \ttbr1, c2, c0, 1 @ load TTB1 158 .endm 159 160 /* AT 161 * TFR EV X F I D LR S 162 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 163 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 164 * 01 0 110 0011 1100 .111 1101 < we want 165 */ 166 .align 2 167 .type v7_crval, #object 168v7_crval: 169 crval clear=0x2120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 170