Lines Matching refs:mcr

81 	mcr	p15, 1, r0, c15, c9, 0		@ clean L2
82 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
88 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
104 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
105 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
107 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
112 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
125 	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
126 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
136 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
162 2:	mcr	p15, 0, ip, c7, c14, 2		@ clean + invalidate D set/way
190 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
193 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
229 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
230 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
234 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
250 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
255 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
256 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
265 	mcr	p15, 5, r0, c15, c15, 0		@ D clean/inv range start
266 	mcr	p15, 5, r1, c15, c15, 1		@ D clean/inv range top
269 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
270 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
293 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
297 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
311 	mcr	p15, 5, r0, c15, c14, 0		@ D inv range start
312 	mcr	p15, 5, r1, c15, c14, 1		@ D inv range top
329 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
333 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
343 	mcr	p15, 5, r0, c15, c13, 0		@ D clean range start
344 	mcr	p15, 5, r1, c15, c13, 1		@ D clean range top
346 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
360 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
364 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
374 	mcr	p15, 5, r0, c15, c15, 0		@ D clean/inv range start
375 	mcr	p15, 5, r1, c15, c15, 1		@ D clean/inv range top
377 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
452 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
458 1:	mcr	p15, 1, r2, c15, c9, 1		@ clean L2 entry
463 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
491 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
492 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
508 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
511 	mcr	p15, 1, r0, c15, c9, 1		@ clean L2 entry
513 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
532 	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
533 	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
535 	mcr	p15, 0, r4, c13, c0, 0	@ PID
536 	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
537 	mcr	p15, 0, r1, c2, c0, 0	@ TTB address
546 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
547 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
549 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4