Lines Matching refs:mcr

98 	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
123 	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
124 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
126 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
131 	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
143 	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
145 	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
146 	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
147 	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
157 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
180 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
184 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
210 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
213 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
217 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
220 	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
255 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
256 	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
260 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
275 1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
280 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
281 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
305 1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
309 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
325 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
330 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
345 	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
347 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
352 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
387 1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
392 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
409 	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
413 2:	mcr	p15, 0, r3, c7, c14, 2		@ clean & invalidate D index
417 	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
418 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
419 	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
420 	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
435 	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
437 	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
447         mcr     p15, 0, r0, c15, c1, 0          @ write TI config register
450 	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
451 	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
453 	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
458 	mcr	p15, 7, r0, c15, c0, 0