| /linux-4.1.27/drivers/gpu/drm/msm/edp/ |
| H A D | edp_ctrl.c | 153 static int edp_clk_init(struct edp_ctrl *ctrl) edp_clk_init() argument
155 struct device *dev = &ctrl->pdev->dev; edp_clk_init()
158 ctrl->aux_clk = devm_clk_get(dev, "core_clk"); edp_clk_init()
159 if (IS_ERR(ctrl->aux_clk)) { edp_clk_init()
160 ret = PTR_ERR(ctrl->aux_clk); edp_clk_init()
162 ctrl->aux_clk = NULL; edp_clk_init()
166 ctrl->pixel_clk = devm_clk_get(dev, "pixel_clk"); edp_clk_init()
167 if (IS_ERR(ctrl->pixel_clk)) { edp_clk_init()
168 ret = PTR_ERR(ctrl->pixel_clk); edp_clk_init()
170 ctrl->pixel_clk = NULL; edp_clk_init()
174 ctrl->ahb_clk = devm_clk_get(dev, "iface_clk"); edp_clk_init()
175 if (IS_ERR(ctrl->ahb_clk)) { edp_clk_init()
176 ret = PTR_ERR(ctrl->ahb_clk); edp_clk_init()
178 ctrl->ahb_clk = NULL; edp_clk_init()
182 ctrl->link_clk = devm_clk_get(dev, "link_clk"); edp_clk_init()
183 if (IS_ERR(ctrl->link_clk)) { edp_clk_init()
184 ret = PTR_ERR(ctrl->link_clk); edp_clk_init()
186 ctrl->link_clk = NULL; edp_clk_init()
191 ctrl->mdp_core_clk = devm_clk_get(dev, "mdp_core_clk"); edp_clk_init()
192 if (IS_ERR(ctrl->mdp_core_clk)) { edp_clk_init()
193 ret = PTR_ERR(ctrl->mdp_core_clk); edp_clk_init()
195 ctrl->mdp_core_clk = NULL; edp_clk_init()
202 static int edp_clk_enable(struct edp_ctrl *ctrl, u32 clk_mask) edp_clk_enable() argument
209 ret = clk_prepare_enable(ctrl->ahb_clk); edp_clk_enable()
216 ret = clk_set_rate(ctrl->aux_clk, 19200000); edp_clk_enable()
221 ret = clk_prepare_enable(ctrl->aux_clk); edp_clk_enable()
230 (unsigned long)ctrl->link_rate * 27000000); edp_clk_enable()
231 ret = clk_set_rate(ctrl->link_clk, edp_clk_enable()
232 (unsigned long)ctrl->link_rate * 27000000); edp_clk_enable()
239 ret = clk_prepare_enable(ctrl->link_clk); edp_clk_enable()
247 (unsigned long)ctrl->pixel_rate * 1000); edp_clk_enable()
248 ret = clk_set_rate(ctrl->pixel_clk, edp_clk_enable()
249 (unsigned long)ctrl->pixel_rate * 1000); edp_clk_enable()
256 ret = clk_prepare_enable(ctrl->pixel_clk); edp_clk_enable()
263 ret = clk_prepare_enable(ctrl->mdp_core_clk); edp_clk_enable()
274 clk_disable_unprepare(ctrl->pixel_clk); edp_clk_enable()
277 clk_disable_unprepare(ctrl->link_clk); edp_clk_enable()
280 clk_disable_unprepare(ctrl->aux_clk); edp_clk_enable()
283 clk_disable_unprepare(ctrl->ahb_clk); edp_clk_enable()
288 static void edp_clk_disable(struct edp_ctrl *ctrl, u32 clk_mask) edp_clk_disable() argument
291 clk_disable_unprepare(ctrl->mdp_core_clk); edp_clk_disable()
293 clk_disable_unprepare(ctrl->pixel_clk); edp_clk_disable()
295 clk_disable_unprepare(ctrl->link_clk); edp_clk_disable()
297 clk_disable_unprepare(ctrl->aux_clk); edp_clk_disable()
299 clk_disable_unprepare(ctrl->ahb_clk); edp_clk_disable()
302 static int edp_regulator_init(struct edp_ctrl *ctrl) edp_regulator_init() argument
304 struct device *dev = &ctrl->pdev->dev; edp_regulator_init()
307 ctrl->vdda_vreg = devm_regulator_get(dev, "vdda"); edp_regulator_init()
308 if (IS_ERR(ctrl->vdda_vreg)) { edp_regulator_init()
310 PTR_ERR(ctrl->vdda_vreg)); edp_regulator_init()
311 ctrl->vdda_vreg = NULL; edp_regulator_init()
312 return PTR_ERR(ctrl->vdda_vreg); edp_regulator_init()
314 ctrl->lvl_vreg = devm_regulator_get(dev, "lvl-vdd"); edp_regulator_init()
315 if (IS_ERR(ctrl->lvl_vreg)) { edp_regulator_init()
317 PTR_ERR(ctrl->lvl_vreg)); edp_regulator_init()
318 ctrl->lvl_vreg = NULL; edp_regulator_init()
319 return PTR_ERR(ctrl->lvl_vreg); edp_regulator_init()
325 static int edp_regulator_enable(struct edp_ctrl *ctrl) edp_regulator_enable() argument
329 ret = regulator_set_voltage(ctrl->vdda_vreg, VDDA_MIN_UV, VDDA_MAX_UV); edp_regulator_enable()
335 ret = regulator_set_load(ctrl->vdda_vreg, VDDA_UA_ON_LOAD); edp_regulator_enable()
341 ret = regulator_enable(ctrl->vdda_vreg); edp_regulator_enable()
347 ret = regulator_enable(ctrl->lvl_vreg); edp_regulator_enable()
357 regulator_disable(ctrl->vdda_vreg); edp_regulator_enable()
359 regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); edp_regulator_enable()
364 static void edp_regulator_disable(struct edp_ctrl *ctrl) edp_regulator_disable() argument
366 regulator_disable(ctrl->lvl_vreg); edp_regulator_disable()
367 regulator_disable(ctrl->vdda_vreg); edp_regulator_disable()
368 regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); edp_regulator_disable()
371 static int edp_gpio_config(struct edp_ctrl *ctrl) edp_gpio_config() argument
373 struct device *dev = &ctrl->pdev->dev; edp_gpio_config()
376 ctrl->panel_hpd_gpio = devm_gpiod_get(dev, "panel-hpd"); edp_gpio_config()
377 if (IS_ERR(ctrl->panel_hpd_gpio)) { edp_gpio_config()
378 ret = PTR_ERR(ctrl->panel_hpd_gpio); edp_gpio_config()
379 ctrl->panel_hpd_gpio = NULL; edp_gpio_config()
384 ret = gpiod_direction_input(ctrl->panel_hpd_gpio); edp_gpio_config()
390 ctrl->panel_en_gpio = devm_gpiod_get(dev, "panel-en"); edp_gpio_config()
391 if (IS_ERR(ctrl->panel_en_gpio)) { edp_gpio_config()
392 ret = PTR_ERR(ctrl->panel_en_gpio); edp_gpio_config()
393 ctrl->panel_en_gpio = NULL; edp_gpio_config()
398 ret = gpiod_direction_output(ctrl->panel_en_gpio, 0); edp_gpio_config()
410 static void edp_ctrl_irq_enable(struct edp_ctrl *ctrl, int enable) edp_ctrl_irq_enable() argument
415 spin_lock_irqsave(&ctrl->irq_lock, flags); edp_ctrl_irq_enable()
417 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, EDP_INTR_MASK1); edp_ctrl_irq_enable()
418 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, EDP_INTR_MASK2); edp_ctrl_irq_enable()
420 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, 0x0); edp_ctrl_irq_enable()
421 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, 0x0); edp_ctrl_irq_enable()
423 spin_unlock_irqrestore(&ctrl->irq_lock, flags); edp_ctrl_irq_enable()
427 static void edp_fill_link_cfg(struct edp_ctrl *ctrl) edp_fill_link_cfg() argument
432 u8 max_lane = ctrl->dp_link.num_lanes; edp_fill_link_cfg()
435 prate = ctrl->pixel_rate; edp_fill_link_cfg()
436 bpp = ctrl->color_depth * 3; edp_fill_link_cfg()
442 ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate); edp_fill_link_cfg()
448 lrate *= ctrl->link_rate; edp_fill_link_cfg()
457 ctrl->lane_cnt = lane; edp_fill_link_cfg()
458 DBG("rate=%d lane=%d", ctrl->link_rate, ctrl->lane_cnt); edp_fill_link_cfg()
461 static void edp_config_ctrl(struct edp_ctrl *ctrl) edp_config_ctrl() argument
466 data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1); edp_config_ctrl()
468 if (ctrl->dp_link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) edp_config_ctrl()
472 if (ctrl->color_depth == 8) edp_config_ctrl()
477 if (!ctrl->interlaced) /* progressive */ edp_config_ctrl()
483 edp_write(ctrl->base + REG_EDP_CONFIGURATION_CTRL, data); edp_config_ctrl()
486 static void edp_state_ctrl(struct edp_ctrl *ctrl, u32 state) edp_state_ctrl() argument
488 edp_write(ctrl->base + REG_EDP_STATE_CTRL, state); edp_state_ctrl()
493 static int edp_lane_set_write(struct edp_ctrl *ctrl, edp_lane_set_write() argument
511 if (drm_dp_dpcd_write(ctrl->drm_aux, 0x103, buf, 4) < 4) { edp_lane_set_write()
519 static int edp_train_pattern_set_write(struct edp_ctrl *ctrl, u8 pattern) edp_train_pattern_set_write() argument
524 if (drm_dp_dpcd_write(ctrl->drm_aux, edp_train_pattern_set_write()
533 static void edp_sink_train_set_adjust(struct edp_ctrl *ctrl, edp_sink_train_set_adjust() argument
541 for (i = 0; i < ctrl->lane_cnt; i++) { edp_sink_train_set_adjust()
548 ctrl->v_level = max >> DP_TRAIN_VOLTAGE_SWING_SHIFT; edp_sink_train_set_adjust()
552 for (i = 0; i < ctrl->lane_cnt; i++) { edp_sink_train_set_adjust()
559 ctrl->p_level = max >> DP_TRAIN_PRE_EMPHASIS_SHIFT; edp_sink_train_set_adjust()
560 DBG("v_level=%d, p_level=%d", ctrl->v_level, ctrl->p_level); edp_sink_train_set_adjust()
563 static void edp_host_train_set(struct edp_ctrl *ctrl, u32 train) edp_host_train_set() argument
571 edp_state_ctrl(ctrl, EDP_STATE_CTRL_TRAIN_PATTERN_1 << shift); edp_host_train_set()
573 data = edp_read(ctrl->base + REG_EDP_MAINLINK_READY); edp_host_train_set()
597 static int edp_voltage_pre_emphasise_set(struct edp_ctrl *ctrl) edp_voltage_pre_emphasise_set() argument
602 DBG("v=%d p=%d", ctrl->v_level, ctrl->p_level); edp_voltage_pre_emphasise_set()
604 value0 = vm_pre_emphasis[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; edp_voltage_pre_emphasise_set()
605 value1 = vm_voltage_swing[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; edp_voltage_pre_emphasise_set()
609 msm_edp_phy_vm_pe_cfg(ctrl->phy, value0, value1); edp_voltage_pre_emphasise_set()
610 return edp_lane_set_write(ctrl, ctrl->v_level, ctrl->p_level); edp_voltage_pre_emphasise_set()
616 static int edp_start_link_train_1(struct edp_ctrl *ctrl) edp_start_link_train_1() argument
626 edp_host_train_set(ctrl, DP_TRAINING_PATTERN_1); edp_start_link_train_1()
627 ret = edp_voltage_pre_emphasise_set(ctrl); edp_start_link_train_1()
630 ret = edp_train_pattern_set_write(ctrl, edp_start_link_train_1()
636 old_v_level = ctrl->v_level; edp_start_link_train_1()
638 drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); edp_start_link_train_1()
640 rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); edp_start_link_train_1()
645 if (drm_dp_clock_recovery_ok(link_status, ctrl->lane_cnt)) { edp_start_link_train_1()
650 if (ctrl->v_level == DPCD_LINK_VOLTAGE_MAX) { edp_start_link_train_1()
655 if (old_v_level == ctrl->v_level) { edp_start_link_train_1()
663 old_v_level = ctrl->v_level; edp_start_link_train_1()
666 edp_sink_train_set_adjust(ctrl, link_status); edp_start_link_train_1()
667 ret = edp_voltage_pre_emphasise_set(ctrl); edp_start_link_train_1()
675 static int edp_start_link_train_2(struct edp_ctrl *ctrl) edp_start_link_train_2() argument
684 edp_host_train_set(ctrl, DP_TRAINING_PATTERN_2); edp_start_link_train_2()
685 ret = edp_voltage_pre_emphasise_set(ctrl); edp_start_link_train_2()
689 ret = edp_train_pattern_set_write(ctrl, edp_start_link_train_2()
695 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); edp_start_link_train_2()
697 rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); edp_start_link_train_2()
702 if (drm_dp_channel_eq_ok(link_status, ctrl->lane_cnt)) { edp_start_link_train_2()
713 edp_sink_train_set_adjust(ctrl, link_status); edp_start_link_train_2()
714 ret = edp_voltage_pre_emphasise_set(ctrl); edp_start_link_train_2()
722 static int edp_link_rate_down_shift(struct edp_ctrl *ctrl) edp_link_rate_down_shift() argument
728 rate = ctrl->link_rate; edp_link_rate_down_shift()
729 lane = ctrl->lane_cnt; edp_link_rate_down_shift()
730 max_lane = ctrl->dp_link.num_lanes; edp_link_rate_down_shift()
732 bpp = ctrl->color_depth * 3; edp_link_rate_down_shift()
733 prate = ctrl->pixel_rate; edp_link_rate_down_shift()
753 ctrl->pixel_rate, edp_link_rate_down_shift()
757 ctrl->link_rate = rate; edp_link_rate_down_shift()
758 ctrl->lane_cnt = lane; edp_link_rate_down_shift()
767 static int edp_clear_training_pattern(struct edp_ctrl *ctrl) edp_clear_training_pattern() argument
771 ret = edp_train_pattern_set_write(ctrl, 0); edp_clear_training_pattern()
773 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); edp_clear_training_pattern()
778 static int edp_do_link_train(struct edp_ctrl *ctrl) edp_do_link_train() argument
788 dp_link.num_lanes = ctrl->lane_cnt; edp_do_link_train()
789 dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate); edp_do_link_train()
790 dp_link.capabilities = ctrl->dp_link.capabilities; edp_do_link_train()
791 if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0) edp_do_link_train()
794 ctrl->v_level = 0; /* start from default level */ edp_do_link_train()
795 ctrl->p_level = 0; edp_do_link_train()
797 edp_state_ctrl(ctrl, 0); edp_do_link_train()
798 if (edp_clear_training_pattern(ctrl)) edp_do_link_train()
801 ret = edp_start_link_train_1(ctrl); edp_do_link_train()
803 if (edp_link_rate_down_shift(ctrl) == 0) { edp_do_link_train()
815 edp_state_ctrl(ctrl, 0); edp_do_link_train()
816 if (edp_clear_training_pattern(ctrl)) edp_do_link_train()
819 ret = edp_start_link_train_2(ctrl); edp_do_link_train()
821 if (edp_link_rate_down_shift(ctrl) == 0) { edp_do_link_train()
833 edp_state_ctrl(ctrl, EDP_STATE_CTRL_SEND_VIDEO); edp_do_link_train()
835 edp_clear_training_pattern(ctrl); edp_do_link_train()
840 static void edp_clock_synchrous(struct edp_ctrl *ctrl, int sync) edp_clock_synchrous() argument
845 data = edp_read(ctrl->base + REG_EDP_MISC1_MISC0); edp_clock_synchrous()
854 if (ctrl->color_depth == 8) edp_clock_synchrous()
856 else if (ctrl->color_depth == 10) edp_clock_synchrous()
858 else if (ctrl->color_depth == 12) edp_clock_synchrous()
860 else if (ctrl->color_depth == 16) edp_clock_synchrous()
865 edp_write(ctrl->base + REG_EDP_MISC1_MISC0, data); edp_clock_synchrous()
868 static int edp_sw_mvid_nvid(struct edp_ctrl *ctrl, u32 m, u32 n) edp_sw_mvid_nvid() argument
872 if (ctrl->link_rate == DP_LINK_BW_1_62) { edp_sw_mvid_nvid()
874 } else if (ctrl->link_rate == DP_LINK_BW_2_7) { edp_sw_mvid_nvid()
878 ctrl->link_rate); edp_sw_mvid_nvid()
882 edp_write(ctrl->base + REG_EDP_SOFTWARE_MVID, m * m_multi); edp_sw_mvid_nvid()
883 edp_write(ctrl->base + REG_EDP_SOFTWARE_NVID, n * n_multi); edp_sw_mvid_nvid()
888 static void edp_mainlink_ctrl(struct edp_ctrl *ctrl, int enable) edp_mainlink_ctrl() argument
892 edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, EDP_MAINLINK_CTRL_RESET); edp_mainlink_ctrl()
900 edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, data); edp_mainlink_ctrl()
903 static void edp_ctrl_phy_aux_enable(struct edp_ctrl *ctrl, int enable) edp_ctrl_phy_aux_enable() argument
906 edp_regulator_enable(ctrl); edp_ctrl_phy_aux_enable()
907 edp_clk_enable(ctrl, EDP_CLK_MASK_AUX_CHAN); edp_ctrl_phy_aux_enable()
908 msm_edp_phy_ctrl(ctrl->phy, 1); edp_ctrl_phy_aux_enable()
909 msm_edp_aux_ctrl(ctrl->aux, 1); edp_ctrl_phy_aux_enable()
910 gpiod_set_value(ctrl->panel_en_gpio, 1); edp_ctrl_phy_aux_enable()
912 gpiod_set_value(ctrl->panel_en_gpio, 0); edp_ctrl_phy_aux_enable()
913 msm_edp_aux_ctrl(ctrl->aux, 0); edp_ctrl_phy_aux_enable()
914 msm_edp_phy_ctrl(ctrl->phy, 0); edp_ctrl_phy_aux_enable()
915 edp_clk_disable(ctrl, EDP_CLK_MASK_AUX_CHAN); edp_ctrl_phy_aux_enable()
916 edp_regulator_disable(ctrl); edp_ctrl_phy_aux_enable()
920 static void edp_ctrl_link_enable(struct edp_ctrl *ctrl, int enable) edp_ctrl_link_enable() argument
926 edp_clk_enable(ctrl, EDP_CLK_MASK_LINK_CHAN); edp_ctrl_link_enable()
928 msm_edp_phy_lane_power_ctrl(ctrl->phy, true, ctrl->lane_cnt); edp_ctrl_link_enable()
930 msm_edp_phy_vm_pe_init(ctrl->phy); edp_ctrl_link_enable()
934 msm_edp_phy_ready(ctrl->phy); edp_ctrl_link_enable()
936 edp_config_ctrl(ctrl); edp_ctrl_link_enable()
937 msm_edp_ctrl_pixel_clock_valid(ctrl, ctrl->pixel_rate, &m, &n); edp_ctrl_link_enable()
938 edp_sw_mvid_nvid(ctrl, m, n); edp_ctrl_link_enable()
939 edp_mainlink_ctrl(ctrl, 1); edp_ctrl_link_enable()
941 edp_mainlink_ctrl(ctrl, 0); edp_ctrl_link_enable()
943 msm_edp_phy_lane_power_ctrl(ctrl->phy, false, 0); edp_ctrl_link_enable()
944 edp_clk_disable(ctrl, EDP_CLK_MASK_LINK_CHAN); edp_ctrl_link_enable()
948 static int edp_ctrl_training(struct edp_ctrl *ctrl) edp_ctrl_training() argument
953 if (!ctrl->power_on) edp_ctrl_training()
957 ret = edp_do_link_train(ctrl); edp_ctrl_training()
960 edp_ctrl_irq_enable(ctrl, 0); edp_ctrl_training()
961 edp_ctrl_link_enable(ctrl, 0); edp_ctrl_training()
962 msm_edp_phy_ctrl(ctrl->phy, 0); edp_ctrl_training()
968 msm_edp_phy_ctrl(ctrl->phy, 1); edp_ctrl_training()
969 edp_ctrl_link_enable(ctrl, 1); edp_ctrl_training()
970 edp_ctrl_irq_enable(ctrl, 1); edp_ctrl_training()
979 struct edp_ctrl *ctrl = container_of( edp_ctrl_on_worker() local
983 mutex_lock(&ctrl->dev_mutex); edp_ctrl_on_worker()
985 if (ctrl->power_on) { edp_ctrl_on_worker()
990 edp_ctrl_phy_aux_enable(ctrl, 1); edp_ctrl_on_worker()
991 edp_ctrl_link_enable(ctrl, 1); edp_ctrl_on_worker()
993 edp_ctrl_irq_enable(ctrl, 1); edp_ctrl_on_worker()
994 ret = drm_dp_link_power_up(ctrl->drm_aux, &ctrl->dp_link); edp_ctrl_on_worker()
998 ctrl->power_on = true; edp_ctrl_on_worker()
1001 ret = edp_ctrl_training(ctrl); edp_ctrl_on_worker()
1009 edp_ctrl_irq_enable(ctrl, 0); edp_ctrl_on_worker()
1010 edp_ctrl_link_enable(ctrl, 0); edp_ctrl_on_worker()
1011 edp_ctrl_phy_aux_enable(ctrl, 0); edp_ctrl_on_worker()
1012 ctrl->power_on = false; edp_ctrl_on_worker()
1014 mutex_unlock(&ctrl->dev_mutex); edp_ctrl_on_worker()
1019 struct edp_ctrl *ctrl = container_of( edp_ctrl_off_worker() local
1023 mutex_lock(&ctrl->dev_mutex); edp_ctrl_off_worker()
1025 if (!ctrl->power_on) { edp_ctrl_off_worker()
1030 reinit_completion(&ctrl->idle_comp); edp_ctrl_off_worker()
1031 edp_state_ctrl(ctrl, EDP_STATE_CTRL_PUSH_IDLE); edp_ctrl_off_worker()
1033 ret = wait_for_completion_timeout(&ctrl->idle_comp, edp_ctrl_off_worker()
1039 edp_state_ctrl(ctrl, 0); edp_ctrl_off_worker()
1041 drm_dp_link_power_down(ctrl->drm_aux, &ctrl->dp_link); edp_ctrl_off_worker()
1043 edp_ctrl_irq_enable(ctrl, 0); edp_ctrl_off_worker()
1045 edp_ctrl_link_enable(ctrl, 0); edp_ctrl_off_worker()
1047 edp_ctrl_phy_aux_enable(ctrl, 0); edp_ctrl_off_worker()
1049 ctrl->power_on = false; edp_ctrl_off_worker()
1052 mutex_unlock(&ctrl->dev_mutex); edp_ctrl_off_worker()
1055 irqreturn_t msm_edp_ctrl_irq(struct edp_ctrl *ctrl) msm_edp_ctrl_irq() argument
1061 spin_lock(&ctrl->irq_lock); msm_edp_ctrl_irq()
1062 isr1 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_1); msm_edp_ctrl_irq()
1063 isr2 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_2); msm_edp_ctrl_irq()
1077 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, ack); msm_edp_ctrl_irq()
1082 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, ack); msm_edp_ctrl_irq()
1083 spin_unlock(&ctrl->irq_lock); msm_edp_ctrl_irq()
1093 complete(&ctrl->idle_comp); msm_edp_ctrl_irq()
1096 msm_edp_aux_irq(ctrl->aux, isr1); msm_edp_ctrl_irq()
1101 void msm_edp_ctrl_power(struct edp_ctrl *ctrl, bool on) msm_edp_ctrl_power() argument
1104 queue_work(ctrl->workqueue, &ctrl->on_work); msm_edp_ctrl_power()
1106 queue_work(ctrl->workqueue, &ctrl->off_work); msm_edp_ctrl_power()
1111 struct edp_ctrl *ctrl = NULL; msm_edp_ctrl_init() local
1120 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); msm_edp_ctrl_init()
1121 if (!ctrl) msm_edp_ctrl_init()
1124 edp->ctrl = ctrl; msm_edp_ctrl_init()
1125 ctrl->pdev = edp->pdev; msm_edp_ctrl_init()
1127 ctrl->base = msm_ioremap(ctrl->pdev, "edp", "eDP"); msm_edp_ctrl_init()
1128 if (IS_ERR(ctrl->base)) msm_edp_ctrl_init()
1129 return PTR_ERR(ctrl->base); msm_edp_ctrl_init()
1132 ret = edp_regulator_init(ctrl); msm_edp_ctrl_init()
1137 ret = edp_clk_init(ctrl); msm_edp_ctrl_init()
1142 ret = edp_gpio_config(ctrl); msm_edp_ctrl_init()
1149 ctrl->aux = msm_edp_aux_init(dev, ctrl->base, &ctrl->drm_aux); msm_edp_ctrl_init()
1150 if (!ctrl->aux || !ctrl->drm_aux) { msm_edp_ctrl_init()
1155 ctrl->phy = msm_edp_phy_init(dev, ctrl->base); msm_edp_ctrl_init()
1156 if (!ctrl->phy) { msm_edp_ctrl_init()
1162 spin_lock_init(&ctrl->irq_lock); msm_edp_ctrl_init()
1163 mutex_init(&ctrl->dev_mutex); msm_edp_ctrl_init()
1164 init_completion(&ctrl->idle_comp); msm_edp_ctrl_init()
1167 ctrl->workqueue = alloc_ordered_workqueue("edp_drm_work", 0); msm_edp_ctrl_init()
1168 INIT_WORK(&ctrl->on_work, edp_ctrl_on_worker); msm_edp_ctrl_init()
1169 INIT_WORK(&ctrl->off_work, edp_ctrl_off_worker); msm_edp_ctrl_init()
1174 msm_edp_aux_destroy(dev, ctrl->aux); msm_edp_ctrl_init()
1175 ctrl->aux = NULL; msm_edp_ctrl_init()
1179 void msm_edp_ctrl_destroy(struct edp_ctrl *ctrl) msm_edp_ctrl_destroy() argument
1181 if (!ctrl) msm_edp_ctrl_destroy()
1184 if (ctrl->workqueue) { msm_edp_ctrl_destroy()
1185 flush_workqueue(ctrl->workqueue); msm_edp_ctrl_destroy()
1186 destroy_workqueue(ctrl->workqueue); msm_edp_ctrl_destroy()
1187 ctrl->workqueue = NULL; msm_edp_ctrl_destroy()
1190 if (ctrl->aux) { msm_edp_ctrl_destroy()
1191 msm_edp_aux_destroy(&ctrl->pdev->dev, ctrl->aux); msm_edp_ctrl_destroy()
1192 ctrl->aux = NULL; msm_edp_ctrl_destroy()
1195 kfree(ctrl->edid); msm_edp_ctrl_destroy()
1196 ctrl->edid = NULL; msm_edp_ctrl_destroy()
1198 mutex_destroy(&ctrl->dev_mutex); msm_edp_ctrl_destroy()
1201 bool msm_edp_ctrl_panel_connected(struct edp_ctrl *ctrl) msm_edp_ctrl_panel_connected() argument
1203 mutex_lock(&ctrl->dev_mutex); msm_edp_ctrl_panel_connected()
1204 DBG("connect status = %d", ctrl->edp_connected); msm_edp_ctrl_panel_connected()
1205 if (ctrl->edp_connected) { msm_edp_ctrl_panel_connected()
1206 mutex_unlock(&ctrl->dev_mutex); msm_edp_ctrl_panel_connected()
1210 if (!ctrl->power_on) { msm_edp_ctrl_panel_connected()
1211 edp_ctrl_phy_aux_enable(ctrl, 1); msm_edp_ctrl_panel_connected()
1212 edp_ctrl_irq_enable(ctrl, 1); msm_edp_ctrl_panel_connected()
1215 if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, msm_edp_ctrl_panel_connected()
1218 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); msm_edp_ctrl_panel_connected()
1220 ctrl->edp_connected = true; msm_edp_ctrl_panel_connected()
1223 if (!ctrl->power_on) { msm_edp_ctrl_panel_connected()
1224 edp_ctrl_irq_enable(ctrl, 0); msm_edp_ctrl_panel_connected()
1225 edp_ctrl_phy_aux_enable(ctrl, 0); msm_edp_ctrl_panel_connected()
1228 DBG("exit: connect status=%d", ctrl->edp_connected); msm_edp_ctrl_panel_connected()
1230 mutex_unlock(&ctrl->dev_mutex); msm_edp_ctrl_panel_connected()
1232 return ctrl->edp_connected; msm_edp_ctrl_panel_connected()
1235 int msm_edp_ctrl_get_panel_info(struct edp_ctrl *ctrl, msm_edp_ctrl_get_panel_info() argument
1240 mutex_lock(&ctrl->dev_mutex); msm_edp_ctrl_get_panel_info()
1242 if (ctrl->edid) { msm_edp_ctrl_get_panel_info()
1245 *edid = ctrl->edid; msm_edp_ctrl_get_panel_info()
1250 if (!ctrl->power_on) { msm_edp_ctrl_get_panel_info()
1251 edp_ctrl_phy_aux_enable(ctrl, 1); msm_edp_ctrl_get_panel_info()
1252 edp_ctrl_irq_enable(ctrl, 1); msm_edp_ctrl_get_panel_info()
1255 ret = drm_dp_link_probe(ctrl->drm_aux, &ctrl->dp_link); msm_edp_ctrl_get_panel_info()
1262 ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate); msm_edp_ctrl_get_panel_info()
1264 ctrl->edid = drm_get_edid(connector, &ctrl->drm_aux->ddc); msm_edp_ctrl_get_panel_info()
1265 if (!ctrl->edid) { msm_edp_ctrl_get_panel_info()
1271 *edid = ctrl->edid; msm_edp_ctrl_get_panel_info()
1274 if (!ctrl->power_on) { msm_edp_ctrl_get_panel_info()
1275 edp_ctrl_irq_enable(ctrl, 0); msm_edp_ctrl_get_panel_info()
1276 edp_ctrl_phy_aux_enable(ctrl, 0); msm_edp_ctrl_get_panel_info()
1279 mutex_unlock(&ctrl->dev_mutex); msm_edp_ctrl_get_panel_info()
1283 int msm_edp_ctrl_timing_cfg(struct edp_ctrl *ctrl, msm_edp_ctrl_timing_cfg() argument
1291 mutex_lock(&ctrl->dev_mutex); msm_edp_ctrl_timing_cfg()
1294 * interlaced information in ctrl context msm_edp_ctrl_timing_cfg()
1296 ctrl->color_depth = info->bpc; msm_edp_ctrl_timing_cfg()
1297 ctrl->pixel_rate = mode->clock; msm_edp_ctrl_timing_cfg()
1298 ctrl->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); msm_edp_ctrl_timing_cfg()
1301 edp_fill_link_cfg(ctrl); msm_edp_ctrl_timing_cfg()
1303 if (edp_clk_enable(ctrl, EDP_CLK_MASK_AHB)) { msm_edp_ctrl_timing_cfg()
1308 edp_clock_synchrous(ctrl, 1); msm_edp_ctrl_timing_cfg()
1311 edp_write(ctrl->base + REG_EDP_TOTAL_HOR_VER, msm_edp_ctrl_timing_cfg()
1317 edp_write(ctrl->base + REG_EDP_START_HOR_VER_FROM_SYNC, msm_edp_ctrl_timing_cfg()
1329 edp_write(ctrl->base + REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY, data); msm_edp_ctrl_timing_cfg()
1331 edp_write(ctrl->base + REG_EDP_ACTIVE_HOR_VER, msm_edp_ctrl_timing_cfg()
1335 edp_clk_disable(ctrl, EDP_CLK_MASK_AHB); msm_edp_ctrl_timing_cfg()
1338 mutex_unlock(&ctrl->dev_mutex); msm_edp_ctrl_timing_cfg()
1342 bool msm_edp_ctrl_pixel_clock_valid(struct edp_ctrl *ctrl, msm_edp_ctrl_pixel_clock_valid() argument
1350 if (ctrl->link_rate == DP_LINK_BW_1_62) { msm_edp_ctrl_pixel_clock_valid()
1352 } else if (ctrl->link_rate == DP_LINK_BW_2_7) { msm_edp_ctrl_pixel_clock_valid()
1355 pr_err("%s: Invalid link rate,%d\n", __func__, ctrl->link_rate); msm_edp_ctrl_pixel_clock_valid()
|
| H A D | edp.h | 43 struct edp_ctrl *ctrl; member in struct:msm_edp
71 irqreturn_t msm_edp_ctrl_irq(struct edp_ctrl *ctrl);
72 void msm_edp_ctrl_power(struct edp_ctrl *ctrl, bool on);
74 void msm_edp_ctrl_destroy(struct edp_ctrl *ctrl);
75 bool msm_edp_ctrl_panel_connected(struct edp_ctrl *ctrl);
76 int msm_edp_ctrl_get_panel_info(struct edp_ctrl *ctrl,
78 int msm_edp_ctrl_timing_cfg(struct edp_ctrl *ctrl,
82 bool msm_edp_ctrl_pixel_clock_valid(struct edp_ctrl *ctrl,
|
| H A D | edp_bridge.c | 32 msm_edp_ctrl_power(edp->ctrl, true); edp_bridge_pre_enable()
51 msm_edp_ctrl_power(edp->ctrl, false); edp_bridge_post_disable()
75 msm_edp_ctrl_timing_cfg(edp->ctrl, edp_bridge_mode_set()
|
| /linux-4.1.27/drivers/pci/hotplug/ |
| H A D | pciehp_hpc.c | 44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl) ctrl_dev() argument
46 return ctrl->pcie->port; ctrl_dev()
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
55 struct controller *ctrl = (struct controller *)data; int_poll_timeout() local
58 pcie_isr(0, ctrl); int_poll_timeout()
60 init_timer(&ctrl->poll_timer); int_poll_timeout()
64 start_int_poll_timer(ctrl, pciehp_poll_time); int_poll_timeout()
68 static void start_int_poll_timer(struct controller *ctrl, int sec) start_int_poll_timer() argument
74 ctrl->poll_timer.function = &int_poll_timeout; start_int_poll_timer()
75 ctrl->poll_timer.data = (unsigned long)ctrl; start_int_poll_timer()
76 ctrl->poll_timer.expires = jiffies + sec * HZ; start_int_poll_timer()
77 add_timer(&ctrl->poll_timer); start_int_poll_timer()
80 static inline int pciehp_request_irq(struct controller *ctrl) pciehp_request_irq() argument
82 int retval, irq = ctrl->pcie->irq; pciehp_request_irq()
86 init_timer(&ctrl->poll_timer); pciehp_request_irq()
87 start_int_poll_timer(ctrl, 10); pciehp_request_irq()
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl); pciehp_request_irq()
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n", pciehp_request_irq()
99 static inline void pciehp_free_irq(struct controller *ctrl) pciehp_free_irq() argument
102 del_timer_sync(&ctrl->poll_timer); pciehp_free_irq()
104 free_irq(ctrl->pcie->irq, ctrl); pciehp_free_irq()
107 static int pcie_poll_cmd(struct controller *ctrl, int timeout) pcie_poll_cmd() argument
109 struct pci_dev *pdev = ctrl_dev(ctrl); pcie_poll_cmd()
131 static void pcie_wait_cmd(struct controller *ctrl) pcie_wait_cmd() argument
135 unsigned long cmd_timeout = ctrl->cmd_started + duration; pcie_wait_cmd()
143 if (NO_CMD_CMPL(ctrl)) pcie_wait_cmd()
146 if (!ctrl->cmd_busy) pcie_wait_cmd()
159 if (ctrl->slot_ctrl & PCI_EXP_SLTCTL_HPIE && pcie_wait_cmd()
160 ctrl->slot_ctrl & PCI_EXP_SLTCTL_CCIE) pcie_wait_cmd()
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout); pcie_wait_cmd()
163 rc = pcie_poll_cmd(ctrl, jiffies_to_msecs(timeout)); pcie_wait_cmd()
174 ctrl_info(ctrl, "Timeout on hotplug command %#06x (issued %u msec ago)\n", pcie_wait_cmd()
175 ctrl->slot_ctrl, pcie_wait_cmd()
176 jiffies_to_msecs(jiffies - ctrl->cmd_started)); pcie_wait_cmd()
179 static void pcie_do_write_cmd(struct controller *ctrl, u16 cmd, pcie_do_write_cmd() argument
182 struct pci_dev *pdev = ctrl_dev(ctrl); pcie_do_write_cmd()
185 mutex_lock(&ctrl->ctrl_lock); pcie_do_write_cmd()
190 pcie_wait_cmd(ctrl); pcie_do_write_cmd()
195 ctrl->cmd_busy = 1; pcie_do_write_cmd()
198 ctrl->cmd_started = jiffies; pcie_do_write_cmd()
199 ctrl->slot_ctrl = slot_ctrl; pcie_do_write_cmd()
206 pcie_wait_cmd(ctrl); pcie_do_write_cmd()
208 mutex_unlock(&ctrl->ctrl_lock); pcie_do_write_cmd()
213 * @ctrl: controller to which the command is issued
217 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) pcie_write_cmd() argument
219 pcie_do_write_cmd(ctrl, cmd, mask, true); pcie_write_cmd()
223 static void pcie_write_cmd_nowait(struct controller *ctrl, u16 cmd, u16 mask) pcie_write_cmd_nowait() argument
225 pcie_do_write_cmd(ctrl, cmd, mask, false); pcie_write_cmd_nowait()
228 bool pciehp_check_link_active(struct controller *ctrl) pciehp_check_link_active() argument
230 struct pci_dev *pdev = ctrl_dev(ctrl); pciehp_check_link_active()
238 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); pciehp_check_link_active()
243 static void __pcie_wait_link_active(struct controller *ctrl, bool active) __pcie_wait_link_active() argument
247 if (pciehp_check_link_active(ctrl) == active) __pcie_wait_link_active()
252 if (pciehp_check_link_active(ctrl) == active) __pcie_wait_link_active()
255 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n", __pcie_wait_link_active()
259 static void pcie_wait_link_active(struct controller *ctrl) pcie_wait_link_active() argument
261 __pcie_wait_link_active(ctrl, true); pcie_wait_link_active()
290 int pciehp_check_link_status(struct controller *ctrl) pciehp_check_link_status() argument
292 struct pci_dev *pdev = ctrl_dev(ctrl); pciehp_check_link_status()
301 if (ctrl->link_active_reporting) pciehp_check_link_status()
302 pcie_wait_link_active(ctrl); pciehp_check_link_status()
308 found = pci_bus_check_dev(ctrl->pcie->port->subordinate, pciehp_check_link_status()
312 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status); pciehp_check_link_status()
315 ctrl_err(ctrl, "Link Training Error occurs\n"); pciehp_check_link_status()
319 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status); pciehp_check_link_status()
327 static int __pciehp_link_set(struct controller *ctrl, bool enable) __pciehp_link_set() argument
329 struct pci_dev *pdev = ctrl_dev(ctrl); __pciehp_link_set()
340 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); __pciehp_link_set()
344 static int pciehp_link_enable(struct controller *ctrl) pciehp_link_enable() argument
346 return __pciehp_link_set(ctrl, true); pciehp_link_enable()
351 struct controller *ctrl = slot->ctrl; pciehp_get_attention_status() local
352 struct pci_dev *pdev = ctrl_dev(ctrl); pciehp_get_attention_status()
356 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__, pciehp_get_attention_status()
357 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); pciehp_get_attention_status()
377 struct controller *ctrl = slot->ctrl; pciehp_get_power_status() local
378 struct pci_dev *pdev = ctrl_dev(ctrl); pciehp_get_power_status()
382 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__, pciehp_get_power_status()
383 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl); pciehp_get_power_status()
400 struct pci_dev *pdev = ctrl_dev(slot->ctrl); pciehp_get_latch_status()
409 struct pci_dev *pdev = ctrl_dev(slot->ctrl); pciehp_get_adapter_status()
418 struct pci_dev *pdev = ctrl_dev(slot->ctrl); pciehp_query_power_fault()
427 struct controller *ctrl = slot->ctrl; pciehp_set_attention_status() local
430 if (!ATTN_LED(ctrl)) pciehp_set_attention_status()
446 pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC); pciehp_set_attention_status()
447 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_set_attention_status()
448 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); pciehp_set_attention_status()
453 struct controller *ctrl = slot->ctrl; pciehp_green_led_on() local
455 if (!PWR_LED(ctrl)) pciehp_green_led_on()
458 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, pciehp_green_led_on()
460 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_green_led_on()
461 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_green_led_on()
467 struct controller *ctrl = slot->ctrl; pciehp_green_led_off() local
469 if (!PWR_LED(ctrl)) pciehp_green_led_off()
472 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, pciehp_green_led_off()
474 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_green_led_off()
475 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_green_led_off()
481 struct controller *ctrl = slot->ctrl; pciehp_green_led_blink() local
483 if (!PWR_LED(ctrl)) pciehp_green_led_blink()
486 pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, pciehp_green_led_blink()
488 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_green_led_blink()
489 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_green_led_blink()
495 struct controller *ctrl = slot->ctrl; pciehp_power_on_slot() local
496 struct pci_dev *pdev = ctrl_dev(ctrl); pciehp_power_on_slot()
505 ctrl->power_fault_detected = 0; pciehp_power_on_slot()
507 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC); pciehp_power_on_slot()
508 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_power_on_slot()
509 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_power_on_slot()
512 retval = pciehp_link_enable(ctrl); pciehp_power_on_slot()
514 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); pciehp_power_on_slot()
521 struct controller *ctrl = slot->ctrl; pciehp_power_off_slot() local
523 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC); pciehp_power_off_slot()
524 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_power_off_slot()
525 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, pciehp_power_off_slot()
531 struct controller *ctrl = (struct controller *)dev_id; pcie_isr() local
532 struct pci_dev *pdev = ctrl_dev(ctrl); pcie_isr()
535 struct slot *slot = ctrl->slot; pcie_isr()
559 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc); pcie_isr()
563 ctrl->cmd_busy = 0; pcie_isr()
565 wake_up(&ctrl->queue); pcie_isr()
571 ctrl_dbg(ctrl, "ignoring hotplug event %#06x (%s requested no hotplug)\n", pcie_isr()
594 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) { pcie_isr()
595 ctrl->power_fault_detected = 1; pcie_isr()
605 void pcie_enable_notification(struct controller *ctrl) pcie_enable_notification() argument
626 if (ATTN_BUTTN(ctrl)) pcie_enable_notification()
630 if (MRL_SENS(ctrl)) pcie_enable_notification()
640 pcie_write_cmd_nowait(ctrl, cmd, mask); pcie_enable_notification()
641 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pcie_enable_notification()
642 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); pcie_enable_notification()
645 static void pcie_disable_notification(struct controller *ctrl) pcie_disable_notification() argument
653 pcie_write_cmd(ctrl, 0, mask); pcie_disable_notification()
654 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pcie_disable_notification()
655 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); pcie_disable_notification()
668 struct controller *ctrl = slot->ctrl; pciehp_reset_slot() local
669 struct pci_dev *pdev = ctrl_dev(ctrl); pciehp_reset_slot()
675 if (!ATTN_BUTTN(ctrl)) { pciehp_reset_slot()
682 pcie_write_cmd(ctrl, 0, ctrl_mask); pciehp_reset_slot()
683 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_reset_slot()
684 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0); pciehp_reset_slot()
686 del_timer_sync(&ctrl->poll_timer); pciehp_reset_slot()
688 pci_reset_bridge_secondary_bus(ctrl->pcie->port); pciehp_reset_slot()
691 pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask); pciehp_reset_slot()
692 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, pciehp_reset_slot()
693 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask); pciehp_reset_slot()
695 int_poll_timeout(ctrl->poll_timer.data); pciehp_reset_slot()
700 int pcie_init_notification(struct controller *ctrl) pcie_init_notification() argument
702 if (pciehp_request_irq(ctrl)) pcie_init_notification()
704 pcie_enable_notification(ctrl); pcie_init_notification()
705 ctrl->notification_enabled = 1; pcie_init_notification()
709 static void pcie_shutdown_notification(struct controller *ctrl) pcie_shutdown_notification() argument
711 if (ctrl->notification_enabled) { pcie_shutdown_notification()
712 pcie_disable_notification(ctrl); pcie_shutdown_notification()
713 pciehp_free_irq(ctrl); pcie_shutdown_notification()
714 ctrl->notification_enabled = 0; pcie_shutdown_notification()
718 static int pcie_init_slot(struct controller *ctrl) pcie_init_slot() argument
726 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl)); pcie_init_slot()
730 slot->ctrl = ctrl; pcie_init_slot()
734 ctrl->slot = slot; pcie_init_slot()
741 static void pcie_cleanup_slot(struct controller *ctrl) pcie_cleanup_slot() argument
743 struct slot *slot = ctrl->slot; pcie_cleanup_slot()
749 static inline void dbg_ctrl(struct controller *ctrl) dbg_ctrl() argument
753 struct pci_dev *pdev = ctrl->pcie->port; dbg_ctrl()
758 ctrl_info(ctrl, "Hotplug Controller:\n"); dbg_ctrl()
759 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", dbg_ctrl()
761 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor); dbg_ctrl()
762 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device); dbg_ctrl()
763 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n", dbg_ctrl()
765 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n", dbg_ctrl()
767 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n", dbg_ctrl()
772 ctrl_info(ctrl, " PCI resource [%d] : %pR\n", dbg_ctrl()
775 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap); dbg_ctrl()
776 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl)); dbg_ctrl()
777 ctrl_info(ctrl, " Attention Button : %3s\n", dbg_ctrl()
778 ATTN_BUTTN(ctrl) ? "yes" : "no"); dbg_ctrl()
779 ctrl_info(ctrl, " Power Controller : %3s\n", dbg_ctrl()
780 POWER_CTRL(ctrl) ? "yes" : "no"); dbg_ctrl()
781 ctrl_info(ctrl, " MRL Sensor : %3s\n", dbg_ctrl()
782 MRL_SENS(ctrl) ? "yes" : "no"); dbg_ctrl()
783 ctrl_info(ctrl, " Attention Indicator : %3s\n", dbg_ctrl()
784 ATTN_LED(ctrl) ? "yes" : "no"); dbg_ctrl()
785 ctrl_info(ctrl, " Power Indicator : %3s\n", dbg_ctrl()
786 PWR_LED(ctrl) ? "yes" : "no"); dbg_ctrl()
787 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n", dbg_ctrl()
788 HP_SUPR_RM(ctrl) ? "yes" : "no"); dbg_ctrl()
789 ctrl_info(ctrl, " EMI Present : %3s\n", dbg_ctrl()
790 EMI(ctrl) ? "yes" : "no"); dbg_ctrl()
791 ctrl_info(ctrl, " Command Completed : %3s\n", dbg_ctrl()
792 NO_CMD_CMPL(ctrl) ? "no" : "yes"); dbg_ctrl()
794 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); dbg_ctrl()
796 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); dbg_ctrl()
803 struct controller *ctrl; pcie_init() local
807 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); pcie_init()
808 if (!ctrl) { pcie_init()
812 ctrl->pcie = dev; pcie_init()
814 ctrl->slot_cap = slot_cap; pcie_init()
815 mutex_init(&ctrl->ctrl_lock); pcie_init()
816 init_waitqueue_head(&ctrl->queue); pcie_init()
817 dbg_ctrl(ctrl); pcie_init()
822 ctrl_dbg(ctrl, "Link Active Reporting supported\n"); pcie_init()
823 ctrl->link_active_reporting = 1; pcie_init()
832 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n", pcie_init()
843 if (pcie_init_slot(ctrl)) pcie_init()
846 return ctrl; pcie_init()
849 kfree(ctrl); pcie_init()
854 void pciehp_release_ctrl(struct controller *ctrl) pciehp_release_ctrl() argument
856 pcie_shutdown_notification(ctrl); pciehp_release_ctrl()
857 pcie_cleanup_slot(ctrl); pciehp_release_ctrl()
858 kfree(ctrl); pciehp_release_ctrl()
|
| H A D | cpqphp_core.c | 130 * @ctrl: controller to use
134 static int init_SERR(struct controller *ctrl) init_SERR() argument
140 if (!ctrl) init_SERR()
143 tempdword = ctrl->first_slot; init_SERR()
145 number_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0F; init_SERR()
149 writeb(0, ctrl->hpc_reg + SLOT_SERR); init_SERR()
294 static int ctrl_slot_cleanup (struct controller *ctrl) ctrl_slot_cleanup() argument
298 old_slot = ctrl->slot; ctrl_slot_cleanup()
299 ctrl->slot = NULL; ctrl_slot_cleanup()
308 cpqhp_remove_debugfs_files(ctrl); ctrl_slot_cleanup()
311 free_irq(ctrl->interrupt, ctrl); ctrl_slot_cleanup()
313 iounmap(ctrl->hpc_reg); ctrl_slot_cleanup()
315 release_mem_region(pci_resource_start(ctrl->pci_dev, 0), ctrl_slot_cleanup()
316 pci_resource_len(ctrl->pci_dev, 0)); ctrl_slot_cleanup()
397 * @ctrl: struct controller to use
402 cpqhp_set_attention_status(struct controller *ctrl, struct pci_func *func, cpqhp_set_attention_status() argument
410 hp_slot = func->device - ctrl->slot_device_offset; cpqhp_set_attention_status()
413 mutex_lock(&ctrl->crit_sect); cpqhp_set_attention_status()
416 amber_LED_on (ctrl, hp_slot); cpqhp_set_attention_status()
418 amber_LED_off (ctrl, hp_slot); cpqhp_set_attention_status()
421 mutex_unlock(&ctrl->crit_sect); cpqhp_set_attention_status()
425 set_SOGO(ctrl); cpqhp_set_attention_status()
428 wait_for_ctrl_irq (ctrl); cpqhp_set_attention_status()
431 mutex_unlock(&ctrl->crit_sect); cpqhp_set_attention_status()
446 struct controller *ctrl = slot->ctrl; set_attention_status() local
454 if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1) set_attention_status()
465 return cpqhp_set_attention_status(ctrl, slot_func, status); set_attention_status()
473 struct controller *ctrl = slot->ctrl; process_SI() local
481 if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1) process_SI()
496 dbg("board_added(%p, %p)\n", slot_func, ctrl); process_SI()
497 return cpqhp_process_SI(ctrl, slot_func); process_SI()
505 struct controller *ctrl = slot->ctrl; process_SS() local
513 if (cpqhp_get_bus_dev(ctrl, &bus, &devfn, slot->number) == -1) process_SS()
524 dbg("In %s, slot_func = %p, ctrl = %p\n", __func__, slot_func, ctrl); process_SS()
525 return cpqhp_process_SS(ctrl, slot_func); process_SS()
532 struct controller *ctrl = slot->ctrl; hardware_test() local
536 return cpqhp_hardware_test(ctrl, value); hardware_test()
543 struct controller *ctrl = slot->ctrl; get_power_status() local
547 *value = get_slot_enabled(ctrl, slot); get_power_status()
554 struct controller *ctrl = slot->ctrl; get_attention_status() local
558 *value = cpq_get_attention_status(ctrl, slot); get_attention_status()
565 struct controller *ctrl = slot->ctrl; get_latch_status() local
569 *value = cpq_get_latch_status(ctrl, slot); get_latch_status()
577 struct controller *ctrl = slot->ctrl; get_adapter_status() local
581 *value = get_presence_status(ctrl, slot); get_adapter_status()
599 static int ctrl_slot_setup(struct controller *ctrl, ctrl_slot_setup() argument
606 struct pci_bus *bus = ctrl->pci_bus; ctrl_slot_setup()
618 tempdword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR); ctrl_slot_setup()
620 number_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0F; ctrl_slot_setup()
621 slot_device = readb(ctrl->hpc_reg + SLOT_MASK) >> 4; ctrl_slot_setup()
622 slot_number = ctrl->first_slot; ctrl_slot_setup()
647 slot->ctrl = ctrl; ctrl_slot_setup()
648 slot->bus = ctrl->bus; ctrl_slot_setup()
682 slot_device - (readb(ctrl->hpc_reg + SLOT_MASK) >> 4); ctrl_slot_setup()
693 ((read_slot_enable(ctrl) << 2) >> ctrl_slot) & 0x04; ctrl_slot_setup()
701 hotplug_slot_info->power_status = get_slot_enabled(ctrl, slot); ctrl_slot_setup()
703 cpq_get_attention_status(ctrl, slot); ctrl_slot_setup()
705 cpq_get_latch_status(ctrl, slot); ctrl_slot_setup()
707 get_presence_status(ctrl, slot); ctrl_slot_setup()
709 dbg("registering bus %d, dev %d, number %d, ctrl->slot_device_offset %d, slot %d\n", ctrl_slot_setup()
711 slot->number, ctrl->slot_device_offset, ctrl_slot_setup()
714 ctrl->pci_dev->bus, ctrl_slot_setup()
722 slot->next = ctrl->slot; ctrl_slot_setup()
723 ctrl->slot = slot; ctrl_slot_setup()
825 struct controller *ctrl; cpqhpc_probe() local
884 ctrl = kzalloc(sizeof(struct controller), GFP_KERNEL); cpqhpc_probe()
885 if (!ctrl) { cpqhpc_probe()
898 ctrl->vendor_id = vendor_id; cpqhpc_probe()
903 ctrl->push_flag = 1; cpqhpc_probe()
904 ctrl->slot_switch_type = 1; cpqhpc_probe()
905 ctrl->push_button = 1; cpqhpc_probe()
906 ctrl->pci_config_space = 1; cpqhpc_probe()
907 ctrl->defeature_PHP = 1; cpqhpc_probe()
908 ctrl->pcix_support = 1; cpqhpc_probe()
909 ctrl->pcix_speed_capability = 1; cpqhpc_probe()
938 ctrl->slot_switch_type = 1; cpqhpc_probe()
940 ctrl->push_button = 0; cpqhpc_probe()
941 ctrl->pci_config_space = 1; cpqhpc_probe()
942 ctrl->defeature_PHP = 1; cpqhpc_probe()
943 ctrl->pcix_support = 0; cpqhpc_probe()
944 ctrl->pcix_speed_capability = 0; cpqhpc_probe()
948 ctrl->push_flag = 1; cpqhpc_probe()
949 ctrl->slot_switch_type = 1; cpqhpc_probe()
951 ctrl->push_button = 1; cpqhpc_probe()
952 ctrl->pci_config_space = 1; cpqhpc_probe()
953 ctrl->defeature_PHP = 1; cpqhpc_probe()
954 ctrl->pcix_support = 0; cpqhpc_probe()
955 ctrl->pcix_speed_capability = 0; cpqhpc_probe()
959 ctrl->slot_switch_type = 1; cpqhpc_probe()
961 ctrl->push_button = 0; cpqhpc_probe()
962 ctrl->pci_config_space = 1; cpqhpc_probe()
963 ctrl->defeature_PHP = 1; cpqhpc_probe()
964 ctrl->pcix_support = 0; cpqhpc_probe()
965 ctrl->pcix_speed_capability = 0; cpqhpc_probe()
969 ctrl->push_flag = 1; cpqhpc_probe()
970 ctrl->slot_switch_type = 1; cpqhpc_probe()
972 ctrl->push_button = 1; cpqhpc_probe()
973 ctrl->pci_config_space = 1; cpqhpc_probe()
974 ctrl->defeature_PHP = 1; cpqhpc_probe()
975 ctrl->pcix_support = 0; cpqhpc_probe()
976 ctrl->pcix_speed_capability = 0; cpqhpc_probe()
980 ctrl->push_flag = 1; cpqhpc_probe()
981 ctrl->slot_switch_type = 1; cpqhpc_probe()
983 ctrl->push_button = 1; cpqhpc_probe()
984 ctrl->pci_config_space = 1; cpqhpc_probe()
985 ctrl->defeature_PHP = 1; cpqhpc_probe()
986 ctrl->pcix_support = 1; cpqhpc_probe()
987 ctrl->pcix_speed_capability = 0; cpqhpc_probe()
1005 ctrl->push_button = 0; cpqhpc_probe()
1007 ctrl->push_button = 1; cpqhpc_probe()
1011 ctrl->slot_switch_type = 0; cpqhpc_probe()
1013 ctrl->slot_switch_type = 1; cpqhpc_probe()
1017 ctrl->defeature_PHP = 1; /* PHP supported */ cpqhpc_probe()
1019 ctrl->defeature_PHP = 0; /* PHP not supported */ cpqhpc_probe()
1025 ctrl->alternate_base_address = 1; cpqhpc_probe()
1027 ctrl->alternate_base_address = 0; cpqhpc_probe()
1031 ctrl->pci_config_space = 1; cpqhpc_probe()
1033 ctrl->pci_config_space = 0; cpqhpc_probe()
1037 ctrl->pcix_support = 1; cpqhpc_probe()
1040 ctrl->pcix_speed_capability = 1; cpqhpc_probe()
1044 ctrl->pcix_speed_capability = 0; cpqhpc_probe()
1047 ctrl->pcix_support = 0; cpqhpc_probe()
1048 ctrl->pcix_speed_capability = 0; cpqhpc_probe()
1064 dbg(" slot_switch_type %s\n", ctrl->slot_switch_type ? cpqhpc_probe()
1066 dbg(" defeature_PHP %s\n", ctrl->defeature_PHP ? cpqhpc_probe()
1068 dbg(" alternate_base_address %s\n", ctrl->alternate_base_address ? cpqhpc_probe()
1070 dbg(" pci_config_space %s\n", ctrl->pci_config_space ? cpqhpc_probe()
1072 dbg(" pcix_speed_capability %s\n", ctrl->pcix_speed_capability ? cpqhpc_probe()
1074 dbg(" pcix_support %s\n", ctrl->pcix_support ? cpqhpc_probe()
1077 ctrl->pci_dev = pdev; cpqhpc_probe()
1078 pci_set_drvdata(pdev, ctrl); cpqhpc_probe()
1082 ctrl->pci_bus = kmemdup(pdev->bus, sizeof(*ctrl->pci_bus), GFP_KERNEL); cpqhpc_probe()
1083 if (!ctrl->pci_bus) { cpqhpc_probe()
1089 ctrl->bus = pdev->bus->number; cpqhpc_probe()
1090 ctrl->rev = pdev->revision; cpqhpc_probe()
1091 dbg("bus device function rev: %d %d %d %d\n", ctrl->bus, cpqhpc_probe()
1092 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ctrl->rev); cpqhpc_probe()
1094 mutex_init(&ctrl->crit_sect); cpqhpc_probe()
1095 init_waitqueue_head(&ctrl->queue); cpqhpc_probe()
1113 ctrl->hpc_reg = ioremap(pci_resource_start(pdev, 0), cpqhpc_probe()
1115 if (!ctrl->hpc_reg) { cpqhpc_probe()
1124 bus->cur_bus_speed = get_controller_speed(ctrl); cpqhpc_probe()
1141 rc = get_slot_mapping(ctrl->pci_bus, pdev->bus->number, cpqhpc_probe()
1142 (readb(ctrl->hpc_reg + SLOT_MASK) >> 4), cpqhpc_probe()
1143 &(ctrl->first_slot)); cpqhpc_probe()
1145 ctrl->first_slot, rc); cpqhpc_probe()
1152 rc = cpqhp_save_config(ctrl, ctrl->bus, readb(ctrl->hpc_reg + SLOT_MASK)); cpqhpc_probe()
1163 ctrl->interrupt = pdev->irq; cpqhpc_probe()
1164 if (ctrl->interrupt < 0x10) { cpqhpc_probe()
1169 ctrl->cfgspc_irq = 0; cpqhpc_probe()
1170 pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &ctrl->cfgspc_irq); cpqhpc_probe()
1172 rc = cpqhp_find_available_resources(ctrl, cpqhp_rom_start); cpqhpc_probe()
1173 ctrl->add_support = !rc; cpqhpc_probe()
1181 * Finish setting up the hot plug ctrl device cpqhpc_probe()
1183 ctrl->slot_device_offset = readb(ctrl->hpc_reg + SLOT_MASK) >> 4; cpqhpc_probe()
1184 dbg("NumSlots %d \n", ctrl->slot_device_offset); cpqhpc_probe()
1186 ctrl->next_event = 0; cpqhpc_probe()
1189 rc = ctrl_slot_setup(ctrl, smbios_start, smbios_table); cpqhpc_probe()
1198 writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_MASK); cpqhpc_probe()
1201 dbg("HPC interrupt = %d \n", ctrl->interrupt); cpqhpc_probe()
1202 if (request_irq(ctrl->interrupt, cpqhp_ctrl_intr, cpqhpc_probe()
1203 IRQF_SHARED, MY_NAME, ctrl)) { cpqhpc_probe()
1205 ctrl->interrupt); cpqhpc_probe()
1213 temp_word = readw(ctrl->hpc_reg + MISC); cpqhpc_probe()
1215 writew(temp_word, ctrl->hpc_reg + MISC); cpqhpc_probe()
1218 writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_INPUT_CLEAR); cpqhpc_probe()
1220 ctrl->ctrl_int_comp = readl(ctrl->hpc_reg + INT_INPUT_CLEAR); cpqhpc_probe()
1222 writel(0x0L, ctrl->hpc_reg + INT_MASK); cpqhpc_probe()
1225 cpqhp_ctrl_list = ctrl; cpqhpc_probe()
1226 ctrl->next = NULL; cpqhpc_probe()
1228 ctrl->next = cpqhp_ctrl_list; cpqhpc_probe()
1229 cpqhp_ctrl_list = ctrl; cpqhpc_probe()
1235 mutex_lock(&ctrl->crit_sect); cpqhpc_probe()
1237 num_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0F; cpqhpc_probe()
1239 /* find first device number for the ctrl */ cpqhpc_probe()
1240 device = readb(ctrl->hpc_reg + SLOT_MASK) >> 4; cpqhpc_probe()
1244 func = cpqhp_slot_find(ctrl->bus, device, 0); cpqhpc_probe()
1248 hp_slot = func->device - ctrl->slot_device_offset; cpqhpc_probe()
1252 temp_word = ctrl->ctrl_int_comp >> 16; cpqhpc_probe()
1256 if (ctrl->ctrl_int_comp & (0x1L << hp_slot)) cpqhpc_probe()
1263 green_LED_off(ctrl, hp_slot); cpqhpc_probe()
1264 slot_disable(ctrl, hp_slot); cpqhpc_probe()
1272 set_SOGO(ctrl); cpqhpc_probe()
1274 wait_for_ctrl_irq(ctrl); cpqhpc_probe()
1277 rc = init_SERR(ctrl); cpqhpc_probe()
1280 mutex_unlock(&ctrl->crit_sect); cpqhpc_probe()
1285 mutex_unlock(&ctrl->crit_sect); cpqhpc_probe()
1287 cpqhp_create_debugfs_files(ctrl); cpqhpc_probe()
1292 free_irq(ctrl->interrupt, ctrl); cpqhpc_probe()
1294 iounmap(ctrl->hpc_reg); cpqhpc_probe()
1298 kfree(ctrl->pci_bus); cpqhpc_probe()
1300 kfree(ctrl); cpqhpc_probe()
1312 struct controller *ctrl; unload_cpqphpd() local
1319 ctrl = cpqhp_ctrl_list; unload_cpqphpd()
1321 while (ctrl) { unload_cpqphpd()
1322 if (ctrl->hpc_reg) { unload_cpqphpd()
1324 rc = read_slot_enable (ctrl); unload_cpqphpd()
1326 writeb(0, ctrl->hpc_reg + SLOT_SERR); unload_cpqphpd()
1327 writel(0xFFFFFFC0L | ~rc, ctrl->hpc_reg + INT_MASK); unload_cpqphpd()
1329 misc = readw(ctrl->hpc_reg + MISC); unload_cpqphpd()
1331 writew(misc, ctrl->hpc_reg + MISC); unload_cpqphpd()
1334 ctrl_slot_cleanup(ctrl); unload_cpqphpd()
1336 res = ctrl->io_head; unload_cpqphpd()
1343 res = ctrl->mem_head; unload_cpqphpd()
1350 res = ctrl->p_mem_head; unload_cpqphpd()
1357 res = ctrl->bus_head; unload_cpqphpd()
1364 kfree (ctrl->pci_bus); unload_cpqphpd()
1366 tctrl = ctrl; unload_cpqphpd()
1367 ctrl = ctrl->next; unload_cpqphpd()
|
| H A D | shpchp_hpc.c | 183 static void start_int_poll_timer(struct controller *ctrl, int sec);
184 static int hpc_check_cmd_status(struct controller *ctrl);
186 static inline u8 shpc_readb(struct controller *ctrl, int reg) shpc_readb() argument
188 return readb(ctrl->creg + reg); shpc_readb()
191 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val) shpc_writeb() argument
193 writeb(val, ctrl->creg + reg); shpc_writeb()
196 static inline u16 shpc_readw(struct controller *ctrl, int reg) shpc_readw() argument
198 return readw(ctrl->creg + reg); shpc_readw()
201 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val) shpc_writew() argument
203 writew(val, ctrl->creg + reg); shpc_writew()
206 static inline u32 shpc_readl(struct controller *ctrl, int reg) shpc_readl() argument
208 return readl(ctrl->creg + reg); shpc_readl()
211 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val) shpc_writel() argument
213 writel(val, ctrl->creg + reg); shpc_writel()
216 static inline int shpc_indirect_read(struct controller *ctrl, int index, shpc_indirect_read() argument
220 u32 cap_offset = ctrl->cap_offset; shpc_indirect_read()
221 struct pci_dev *pdev = ctrl->pci_dev; shpc_indirect_read()
234 struct controller *ctrl = (struct controller *)data; int_poll_timeout() local
237 shpc_isr(0, ctrl); int_poll_timeout()
239 init_timer(&ctrl->poll_timer); int_poll_timeout()
243 start_int_poll_timer(ctrl, shpchp_poll_time); int_poll_timeout()
249 static void start_int_poll_timer(struct controller *ctrl, int sec) start_int_poll_timer() argument
255 ctrl->poll_timer.function = &int_poll_timeout; start_int_poll_timer()
256 ctrl->poll_timer.data = (unsigned long)ctrl; start_int_poll_timer()
257 ctrl->poll_timer.expires = jiffies + sec * HZ; start_int_poll_timer()
258 add_timer(&ctrl->poll_timer); start_int_poll_timer()
261 static inline int is_ctrl_busy(struct controller *ctrl) is_ctrl_busy() argument
263 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS); is_ctrl_busy()
271 static inline int shpc_poll_ctrl_busy(struct controller *ctrl) shpc_poll_ctrl_busy() argument
275 if (!is_ctrl_busy(ctrl)) shpc_poll_ctrl_busy()
281 if (!is_ctrl_busy(ctrl)) shpc_poll_ctrl_busy()
288 static inline int shpc_wait_cmd(struct controller *ctrl) shpc_wait_cmd() argument
295 rc = shpc_poll_ctrl_busy(ctrl); shpc_wait_cmd()
297 rc = wait_event_interruptible_timeout(ctrl->queue, shpc_wait_cmd()
298 !is_ctrl_busy(ctrl), timeout); shpc_wait_cmd()
299 if (!rc && is_ctrl_busy(ctrl)) { shpc_wait_cmd()
301 ctrl_err(ctrl, "Command not completed in 1000 msec\n"); shpc_wait_cmd()
304 ctrl_info(ctrl, "Command was interrupted by a signal\n"); shpc_wait_cmd()
312 struct controller *ctrl = slot->ctrl; shpc_write_cmd() local
317 mutex_lock(&slot->ctrl->cmd_lock); shpc_write_cmd()
319 if (!shpc_poll_ctrl_busy(ctrl)) { shpc_write_cmd()
321 ctrl_err(ctrl, "Controller is still busy after 1 sec\n"); shpc_write_cmd()
328 ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd); shpc_write_cmd()
333 shpc_writew(ctrl, CMD, temp_word); shpc_write_cmd()
338 retval = shpc_wait_cmd(slot->ctrl); shpc_write_cmd()
342 cmd_status = hpc_check_cmd_status(slot->ctrl); shpc_write_cmd()
344 ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n", shpc_write_cmd()
349 mutex_unlock(&slot->ctrl->cmd_lock); shpc_write_cmd()
353 static int hpc_check_cmd_status(struct controller *ctrl) hpc_check_cmd_status() argument
356 u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F; hpc_check_cmd_status()
364 ctrl_err(ctrl, "Switch opened!\n"); hpc_check_cmd_status()
368 ctrl_err(ctrl, "Invalid HPC command!\n"); hpc_check_cmd_status()
372 ctrl_err(ctrl, "Invalid bus speed/mode!\n"); hpc_check_cmd_status()
384 struct controller *ctrl = slot->ctrl; hpc_get_attention_status() local
385 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); hpc_get_attention_status()
408 struct controller *ctrl = slot->ctrl; hpc_get_power_status() local
409 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); hpc_get_power_status()
433 struct controller *ctrl = slot->ctrl; hpc_get_latch_status() local
434 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); hpc_get_latch_status()
443 struct controller *ctrl = slot->ctrl; hpc_get_adapter_status() local
444 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); hpc_get_adapter_status()
454 struct controller *ctrl = slot->ctrl; hpc_get_prog_int() local
456 *prog_int = shpc_readb(ctrl, PROG_INTERFACE); hpc_get_prog_int()
464 struct controller *ctrl = slot->ctrl; hpc_get_adapter_speed() local
465 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); hpc_get_adapter_speed()
484 ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n", hpc_get_adapter_speed()
510 ctrl_dbg(ctrl, "Adapter speed = %d\n", *value); hpc_get_adapter_speed()
517 struct controller *ctrl = slot->ctrl; hpc_get_mode1_ECC_cap() local
518 u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG); hpc_get_mode1_ECC_cap()
519 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); hpc_get_mode1_ECC_cap()
527 ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode); hpc_get_mode1_ECC_cap()
533 struct controller *ctrl = slot->ctrl; hpc_query_power_fault() local
534 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot)); hpc_query_power_fault()
577 static void hpc_release_ctlr(struct controller *ctrl) hpc_release_ctlr() argument
585 for (i = 0; i < ctrl->num_slots; i++) { hpc_release_ctlr()
586 slot_reg = shpc_readl(ctrl, SLOT_REG(i)); hpc_release_ctlr()
592 shpc_writel(ctrl, SLOT_REG(i), slot_reg); hpc_release_ctlr()
595 cleanup_slots(ctrl); hpc_release_ctlr()
600 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); hpc_release_ctlr()
604 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); hpc_release_ctlr()
607 del_timer(&ctrl->poll_timer); hpc_release_ctlr()
609 free_irq(ctrl->pci_dev->irq, ctrl); hpc_release_ctlr()
610 pci_disable_msi(ctrl->pci_dev); hpc_release_ctlr()
613 iounmap(ctrl->creg); hpc_release_ctlr()
614 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); hpc_release_ctlr()
623 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); hpc_power_on_slot()
636 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); hpc_slot_enable()
649 ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__); hpc_slot_disable()
654 static int shpc_get_cur_bus_speed(struct controller *ctrl) shpc_get_cur_bus_speed() argument
657 struct pci_bus *bus = ctrl->pci_dev->subordinate; shpc_get_cur_bus_speed()
659 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG); shpc_get_cur_bus_speed()
660 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); shpc_get_cur_bus_speed()
726 struct controller *ctrl = slot->ctrl; hpc_set_bus_speed_mode() local
729 pi = shpc_readb(ctrl, PROG_INTERFACE); hpc_set_bus_speed_mode()
782 ctrl_err(ctrl, "%s: Write command failed!\n", __func__); hpc_set_bus_speed_mode()
784 shpc_get_cur_bus_speed(ctrl); hpc_set_bus_speed_mode()
791 struct controller *ctrl = (struct controller *)dev_id; shpc_isr() local
796 intr_loc = shpc_readl(ctrl, INTR_LOC); shpc_isr()
800 ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc); shpc_isr()
807 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); shpc_isr()
810 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); shpc_isr()
812 intr_loc2 = shpc_readl(ctrl, INTR_LOC); shpc_isr()
813 ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2); shpc_isr()
822 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); shpc_isr()
824 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); shpc_isr()
826 wake_up_interruptible(&ctrl->queue); shpc_isr()
832 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { shpc_isr()
837 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); shpc_isr()
838 ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n", shpc_isr()
842 shpchp_handle_switch_change(hp_slot, ctrl); shpc_isr()
845 shpchp_handle_attention_button(hp_slot, ctrl); shpc_isr()
848 shpchp_handle_presence_change(hp_slot, ctrl); shpc_isr()
851 shpchp_handle_power_fault(hp_slot, ctrl); shpc_isr()
855 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); shpc_isr()
860 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); shpc_isr()
862 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int); shpc_isr()
868 static int shpc_get_max_bus_speed(struct controller *ctrl) shpc_get_max_bus_speed() argument
871 struct pci_bus *bus = ctrl->pci_dev->subordinate; shpc_get_max_bus_speed()
873 u8 pi = shpc_readb(ctrl, PROG_INTERFACE); shpc_get_max_bus_speed()
874 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1); shpc_get_max_bus_speed()
875 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2); shpc_get_max_bus_speed()
908 ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed); shpc_get_max_bus_speed()
936 int shpc_init(struct controller *ctrl, struct pci_dev *pdev) shpc_init() argument
944 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ shpc_init()
945 ctrl_dbg(ctrl, "Hotplug Controller:\n"); shpc_init()
950 ctrl->mmio_base = pci_resource_start(pdev, 0); shpc_init()
951 ctrl->mmio_size = pci_resource_len(pdev, 0); shpc_init()
953 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC); shpc_init()
954 if (!ctrl->cap_offset) { shpc_init()
955 ctrl_err(ctrl, "Cannot find PCI capability\n"); shpc_init()
958 ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset); shpc_init()
960 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset); shpc_init()
962 ctrl_err(ctrl, "Cannot read base_offset\n"); shpc_init()
966 rc = shpc_indirect_read(ctrl, 3, &tempdword); shpc_init()
968 ctrl_err(ctrl, "Cannot read slot config\n"); shpc_init()
972 ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots); shpc_init()
975 rc = shpc_indirect_read(ctrl, i, &tempdword); shpc_init()
977 ctrl_err(ctrl, "Cannot read creg (index = %d)\n", shpc_init()
981 ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword); shpc_init()
984 ctrl->mmio_base = shpc_init()
986 ctrl->mmio_size = 0x24 + 0x4 * num_slots; shpc_init()
989 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", shpc_init()
995 ctrl_err(ctrl, "pci_enable_device failed\n"); shpc_init()
999 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) { shpc_init()
1000 ctrl_err(ctrl, "Cannot reserve MMIO region\n"); shpc_init()
1005 ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size); shpc_init()
1006 if (!ctrl->creg) { shpc_init()
1007 ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n", shpc_init()
1008 ctrl->mmio_size, ctrl->mmio_base); shpc_init()
1009 release_mem_region(ctrl->mmio_base, ctrl->mmio_size); shpc_init()
1013 ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg); shpc_init()
1015 mutex_init(&ctrl->crit_sect); shpc_init()
1016 mutex_init(&ctrl->cmd_lock); shpc_init()
1019 init_waitqueue_head(&ctrl->queue); shpc_init()
1021 ctrl->hpc_ops = &shpchp_hpc_ops; shpc_init()
1024 slot_config = shpc_readl(ctrl, SLOT_CONFIG); shpc_init()
1025 ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8; shpc_init()
1026 ctrl->num_slots = slot_config & SLOT_NUM; shpc_init()
1027 ctrl->first_slot = (slot_config & PSN) >> 16; shpc_init()
1028 ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1; shpc_init()
1031 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); shpc_init()
1032 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); shpc_init()
1036 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); shpc_init()
1037 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); shpc_init()
1038 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); shpc_init()
1043 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { shpc_init()
1044 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); shpc_init()
1045 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", shpc_init()
1052 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); shpc_init()
1057 init_timer(&ctrl->poll_timer); shpc_init()
1058 start_int_poll_timer(ctrl, 10); shpc_init()
1063 ctrl_info(ctrl, "Can't get msi for the hotplug controller\n"); shpc_init()
1064 ctrl_info(ctrl, "Use INTx for the hotplug controller\n"); shpc_init()
1067 rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED, shpc_init()
1068 MY_NAME, (void *)ctrl); shpc_init()
1069 ctrl_dbg(ctrl, "request_irq %d (returns %d)\n", shpc_init()
1070 ctrl->pci_dev->irq, rc); shpc_init()
1072 ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n", shpc_init()
1073 ctrl->pci_dev->irq); shpc_init()
1077 ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq); shpc_init()
1079 shpc_get_max_bus_speed(ctrl); shpc_init()
1080 shpc_get_cur_bus_speed(ctrl); shpc_init()
1085 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { shpc_init()
1086 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot)); shpc_init()
1087 ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n", shpc_init()
1092 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg); shpc_init()
1096 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); shpc_init()
1099 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword); shpc_init()
1100 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE); shpc_init()
1101 ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword); shpc_init()
1108 iounmap(ctrl->creg); shpc_init()
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| H A D | pciehp_ctrl.c | 60 struct controller *ctrl = p_slot->ctrl; pciehp_handle_attention_button() local
63 ctrl_dbg(ctrl, "Attention button interrupt received\n"); pciehp_handle_attention_button()
68 ctrl_info(ctrl, "Button pressed on Slot(%s)\n", slot_name(p_slot)); pciehp_handle_attention_button()
80 struct controller *ctrl = p_slot->ctrl; pciehp_handle_switch_change() local
83 ctrl_dbg(ctrl, "Switch interrupt received\n"); pciehp_handle_switch_change()
90 ctrl_info(ctrl, "Latch open on Slot(%s)\n", slot_name(p_slot)); pciehp_handle_switch_change()
96 ctrl_info(ctrl, "Latch close on Slot(%s)\n", slot_name(p_slot)); pciehp_handle_switch_change()
109 struct controller *ctrl = p_slot->ctrl; pciehp_handle_presence_change() local
112 ctrl_dbg(ctrl, "Presence/Notify input change\n"); pciehp_handle_presence_change()
122 ctrl_info(ctrl, "Card present on Slot(%s)\n", slot_name(p_slot)); pciehp_handle_presence_change()
128 ctrl_info(ctrl, "Card not present on Slot(%s)\n", pciehp_handle_presence_change()
141 struct controller *ctrl = p_slot->ctrl; pciehp_handle_power_fault() local
144 ctrl_dbg(ctrl, "Power fault interrupt received\n"); pciehp_handle_power_fault()
145 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot)); pciehp_handle_power_fault()
147 ctrl_info(ctrl, "Power fault bit %x set\n", 0); pciehp_handle_power_fault()
156 struct controller *ctrl = p_slot->ctrl; pciehp_handle_linkstate_change() local
159 ctrl_dbg(ctrl, "Data Link Layer State change\n"); pciehp_handle_linkstate_change()
161 if (pciehp_check_link_active(ctrl)) { pciehp_handle_linkstate_change()
162 ctrl_info(ctrl, "slot(%s): Link Up event\n", pciehp_handle_linkstate_change()
166 ctrl_info(ctrl, "slot(%s): Link Down event\n", pciehp_handle_linkstate_change()
178 static void set_slot_off(struct controller *ctrl, struct slot *pslot) set_slot_off() argument
181 if (POWER_CTRL(ctrl)) { set_slot_off()
206 struct controller *ctrl = p_slot->ctrl; board_added() local
207 struct pci_bus *parent = ctrl->pcie->port->subordinate; board_added()
209 if (POWER_CTRL(ctrl)) { board_added()
219 retval = pciehp_check_link_status(ctrl); board_added()
221 ctrl_err(ctrl, "Failed to check link status\n"); board_added()
226 if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) { board_added()
227 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot)); board_added()
234 ctrl_err(ctrl, "Cannot add device at %04x:%02x:00\n", board_added()
244 set_slot_off(ctrl, p_slot); board_added()
255 struct controller *ctrl = p_slot->ctrl; remove_board() local
261 if (POWER_CTRL(ctrl)) { remove_board()
301 ctrl_dbg(p_slot->ctrl, pciehp_power_thread()
303 pci_domain_nr(p_slot->ctrl->pcie->port->subordinate), pciehp_power_thread()
304 p_slot->ctrl->pcie->port->subordinate->number); pciehp_power_thread()
313 ctrl_dbg(p_slot->ctrl, pciehp_power_thread()
315 pci_domain_nr(p_slot->ctrl->pcie->port->subordinate), pciehp_power_thread()
316 p_slot->ctrl->pcie->port->subordinate->number); pciehp_power_thread()
340 ctrl_err(p_slot->ctrl, "%s: Cannot allocate memory\n", pciehp_queue_pushbutton_work()
371 struct controller *ctrl = p_slot->ctrl; handle_button_press_event() local
379 ctrl_info(ctrl, "PCI slot #%s - powering off due to button press\n", handle_button_press_event()
383 ctrl_info(ctrl, "PCI slot #%s - powering on due to button press\n", handle_button_press_event()
398 ctrl_info(ctrl, "Button cancel on Slot(%s)\n", slot_name(p_slot)); handle_button_press_event()
405 ctrl_info(ctrl, "PCI slot #%s - action canceled due to button press\n", handle_button_press_event()
416 ctrl_info(ctrl, "Button ignore on Slot(%s)\n", slot_name(p_slot)); handle_button_press_event()
419 ctrl_warn(ctrl, "Not a valid state\n"); handle_button_press_event()
434 ctrl_err(p_slot->ctrl, "%s: Cannot allocate memory\n", handle_surprise_event()
458 struct controller *ctrl = p_slot->ctrl; handle_link_event() local
463 ctrl_err(p_slot->ctrl, "%s: Cannot allocate memory\n", handle_link_event()
483 ctrl_info(ctrl, handle_link_event()
488 ctrl_info(ctrl, handle_link_event()
497 ctrl_info(ctrl, handle_link_event()
503 ctrl_info(ctrl, handle_link_event()
510 ctrl_err(ctrl, "Not a valid state on slot(%s)\n", handle_link_event()
521 struct controller *ctrl = p_slot->ctrl; interrupt_event_handler() local
529 if (!POWER_CTRL(ctrl)) interrupt_event_handler()
535 ctrl_dbg(ctrl, "Surprise Insertion\n"); interrupt_event_handler()
543 ctrl_dbg(ctrl, "Surprise Removal\n"); interrupt_event_handler()
565 struct controller *ctrl = p_slot->ctrl; pciehp_enable_slot() local
569 ctrl_info(ctrl, "No adapter on slot(%s)\n", slot_name(p_slot)); pciehp_enable_slot()
572 if (MRL_SENS(p_slot->ctrl)) { pciehp_enable_slot()
575 ctrl_info(ctrl, "Latch open on slot(%s)\n", pciehp_enable_slot()
581 if (POWER_CTRL(p_slot->ctrl)) { pciehp_enable_slot()
584 ctrl_info(ctrl, "Already enabled on slot(%s)\n", pciehp_enable_slot()
605 struct controller *ctrl = p_slot->ctrl; pciehp_disable_slot() local
607 if (!p_slot->ctrl) pciehp_disable_slot()
610 if (POWER_CTRL(p_slot->ctrl)) { pciehp_disable_slot()
613 ctrl_info(ctrl, "Already disabled on slot(%s)\n", pciehp_disable_slot()
625 struct controller *ctrl = p_slot->ctrl; pciehp_sysfs_enable_slot() local
641 ctrl_info(ctrl, "Slot %s is already in powering on state\n", pciehp_sysfs_enable_slot()
646 ctrl_info(ctrl, "Already enabled on slot %s\n", pciehp_sysfs_enable_slot()
650 ctrl_err(ctrl, "Not a valid state on slot %s\n", pciehp_sysfs_enable_slot()
662 struct controller *ctrl = p_slot->ctrl; pciehp_sysfs_disable_slot() local
676 ctrl_info(ctrl, "Slot %s is already in powering off state\n", pciehp_sysfs_disable_slot()
681 ctrl_info(ctrl, "Already disabled on slot %s\n", pciehp_sysfs_disable_slot()
685 ctrl_err(ctrl, "Not a valid state on slot %s\n", pciehp_sysfs_disable_slot()
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| H A D | shpchp_ctrl.c | 59 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl) shpchp_handle_attention_button() argument
65 ctrl_dbg(ctrl, "Attention button interrupt received\n"); shpchp_handle_attention_button()
67 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); shpchp_handle_attention_button()
73 ctrl_info(ctrl, "Button pressed on Slot(%s)\n", slot_name(p_slot)); shpchp_handle_attention_button()
82 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl) shpchp_handle_switch_change() argument
89 ctrl_dbg(ctrl, "Switch interrupt received\n"); shpchp_handle_switch_change()
91 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); shpchp_handle_switch_change()
94 ctrl_dbg(ctrl, "Card present %x Power status %x\n", shpchp_handle_switch_change()
101 ctrl_info(ctrl, "Latch open on Slot(%s)\n", slot_name(p_slot)); shpchp_handle_switch_change()
105 ctrl_err(ctrl, "Surprise Removal of card\n"); shpchp_handle_switch_change()
111 ctrl_info(ctrl, "Latch close on Slot(%s)\n", slot_name(p_slot)); shpchp_handle_switch_change()
120 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl) shpchp_handle_presence_change() argument
126 ctrl_dbg(ctrl, "Presence/Notify input change\n"); shpchp_handle_presence_change()
128 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); shpchp_handle_presence_change()
138 ctrl_info(ctrl, "Card present on Slot(%s)\n", shpchp_handle_presence_change()
145 ctrl_info(ctrl, "Card not present on Slot(%s)\n", shpchp_handle_presence_change()
155 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl) shpchp_handle_power_fault() argument
161 ctrl_dbg(ctrl, "Power fault interrupt received\n"); shpchp_handle_power_fault()
163 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); shpchp_handle_power_fault()
169 ctrl_info(ctrl, "Power fault cleared on Slot(%s)\n", shpchp_handle_power_fault()
177 ctrl_info(ctrl, "Power fault on Slot(%s)\n", slot_name(p_slot)); shpchp_handle_power_fault()
181 ctrl_info(ctrl, "Power fault bit %x set\n", hp_slot); shpchp_handle_power_fault()
192 static int change_bus_speed(struct controller *ctrl, struct slot *p_slot, change_bus_speed() argument
197 ctrl_dbg(ctrl, "Change speed to %d\n", speed); change_bus_speed()
200 ctrl_err(ctrl, "%s: Issue of set bus speed mode command failed\n", change_bus_speed()
207 static int fix_bus_speed(struct controller *ctrl, struct slot *pslot, fix_bus_speed() argument
219 ctrl_err(ctrl, "Speed of bus %x and adapter %x mismatch\n", fix_bus_speed()
228 rc = change_bus_speed(ctrl, pslot, asp); fix_bus_speed()
231 rc = change_bus_speed(ctrl, pslot, msp); fix_bus_speed()
249 struct controller *ctrl = p_slot->ctrl; board_added() local
250 struct pci_bus *parent = ctrl->pci_dev->subordinate; board_added()
252 hp_slot = p_slot->device - ctrl->slot_device_offset; board_added()
254 ctrl_dbg(ctrl, "%s: p_slot->device, slot_offset, hp_slot = %d, %d ,%d\n", board_added()
255 __func__, p_slot->device, ctrl->slot_device_offset, hp_slot); board_added()
260 ctrl_err(ctrl, "Failed to power on slot\n"); board_added()
264 if ((ctrl->pci_dev->vendor == 0x8086) && (ctrl->pci_dev->device == 0x0332)) { board_added()
267 ctrl_err(ctrl, "%s: Issue of set bus speed mode command failed\n", board_added()
275 ctrl_err(ctrl, "Issue of Slot Enable command failed\n"); board_added()
282 ctrl_err(ctrl, "Can't get adapter speed or bus mode mismatch\n"); board_added()
286 bsp = ctrl->pci_dev->subordinate->cur_bus_speed; board_added()
287 msp = ctrl->pci_dev->subordinate->max_bus_speed; board_added()
290 if (!list_empty(&ctrl->pci_dev->subordinate->devices)) board_added()
293 ctrl_dbg(ctrl, "%s: slots_not_empty %d, adapter_speed %d, bus_speed %d, max_bus_speed %d\n", board_added()
297 rc = fix_bus_speed(ctrl, p_slot, slots_not_empty, asp, bsp, msp); board_added()
304 ctrl_err(ctrl, "Issue of Slot Enable command failed\n"); board_added()
311 ctrl_dbg(ctrl, "%s: slot status = %x\n", __func__, p_slot->status); board_added()
315 ctrl_dbg(ctrl, "%s: Power fault\n", __func__); board_added()
322 ctrl_err(ctrl, "Cannot add device at %04x:%02x:%02x\n", board_added()
339 ctrl_err(ctrl, "%s: Issue of Slot Disable command failed\n", board_added()
354 struct controller *ctrl = p_slot->ctrl; remove_board() local
361 hp_slot = p_slot->device - ctrl->slot_device_offset; remove_board()
362 p_slot = shpchp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); remove_board()
364 ctrl_dbg(ctrl, "%s: hp_slot = %d\n", __func__, hp_slot); remove_board()
373 ctrl_err(ctrl, "%s: Issue of Slot Disable command failed\n", remove_board()
380 ctrl_err(ctrl, "Issue of Set Attention command failed\n"); remove_board()
439 ctrl_err(p_slot->ctrl, "%s: Cannot allocate memory\n", shpchp_queue_pushbutton_work()
488 struct controller *ctrl = p_slot->ctrl; handle_button_press_event() local
495 ctrl_info(ctrl, "PCI slot #%s - powering off due to button press\n", handle_button_press_event()
499 ctrl_info(ctrl, "PCI slot #%s - powering on due to button press\n", handle_button_press_event()
515 ctrl_info(ctrl, "Button cancel on Slot(%s)\n", handle_button_press_event()
523 ctrl_info(ctrl, "PCI slot #%s - action canceled due to button press\n", handle_button_press_event()
534 ctrl_info(ctrl, "Button ignore on Slot(%s)\n", handle_button_press_event()
539 ctrl_warn(ctrl, "Not a valid state\n"); handle_button_press_event()
555 ctrl_dbg(p_slot->ctrl, "%s: Power fault\n", __func__); interrupt_event_handler()
573 struct controller *ctrl = p_slot->ctrl; shpchp_enable_slot() local
576 mutex_lock(&p_slot->ctrl->crit_sect); shpchp_enable_slot()
579 ctrl_info(ctrl, "No adapter on slot(%s)\n", slot_name(p_slot)); shpchp_enable_slot()
584 ctrl_info(ctrl, "Latch open on slot(%s)\n", slot_name(p_slot)); shpchp_enable_slot()
589 ctrl_info(ctrl, "Already enabled on slot(%s)\n", shpchp_enable_slot()
599 ctrl_dbg(ctrl, "%s: p_slot->pwr_save %x\n", __func__, p_slot->pwr_save); shpchp_enable_slot()
602 if (((p_slot->ctrl->pci_dev->vendor == PCI_VENDOR_ID_AMD) || shpchp_enable_slot()
603 (p_slot->ctrl->pci_dev->device == PCI_DEVICE_ID_AMD_POGO_7458)) shpchp_enable_slot()
604 && p_slot->ctrl->num_slots == 1) { shpchp_enable_slot()
621 mutex_unlock(&p_slot->ctrl->crit_sect); shpchp_enable_slot()
630 struct controller *ctrl = p_slot->ctrl; shpchp_disable_slot() local
632 if (!p_slot->ctrl) shpchp_disable_slot()
636 mutex_lock(&p_slot->ctrl->crit_sect); shpchp_disable_slot()
640 ctrl_info(ctrl, "No adapter on slot(%s)\n", slot_name(p_slot)); shpchp_disable_slot()
645 ctrl_info(ctrl, "Latch open on slot(%s)\n", slot_name(p_slot)); shpchp_disable_slot()
650 ctrl_info(ctrl, "Already disabled on slot(%s)\n", shpchp_disable_slot()
658 mutex_unlock(&p_slot->ctrl->crit_sect); shpchp_disable_slot()
665 struct controller *ctrl = p_slot->ctrl; shpchp_sysfs_enable_slot() local
679 ctrl_info(ctrl, "Slot %s is already in powering on state\n", shpchp_sysfs_enable_slot()
684 ctrl_info(ctrl, "Already enabled on slot %s\n", shpchp_sysfs_enable_slot()
688 ctrl_err(ctrl, "Not a valid state on slot %s\n", shpchp_sysfs_enable_slot()
700 struct controller *ctrl = p_slot->ctrl; shpchp_sysfs_disable_slot() local
714 ctrl_info(ctrl, "Slot %s is already in powering off state\n", shpchp_sysfs_disable_slot()
719 ctrl_info(ctrl, "Already disabled on slot %s\n", shpchp_sysfs_disable_slot()
723 ctrl_err(ctrl, "Not a valid state on slot %s\n", shpchp_sysfs_disable_slot()
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| H A D | shpchp_core.c | 86 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", release_slot()
94 static int init_slots(struct controller *ctrl) init_slots() argument
103 for (i = 0; i < ctrl->num_slots; i++) { init_slots()
125 slot->ctrl = ctrl; init_slots()
126 slot->bus = ctrl->pci_dev->subordinate->number; init_slots()
127 slot->device = ctrl->slot_device_offset + i; init_slots()
128 slot->hpc_ops = ctrl->hpc_ops; init_slots()
129 slot->number = ctrl->first_slot + (ctrl->slot_num_inc * i); init_slots()
146 ctrl_dbg(ctrl, "Registering domain:bus:dev=%04x:%02x:%02x hp_slot=%x sun=%x slot_device_offset=%x\n", init_slots()
147 pci_domain_nr(ctrl->pci_dev->subordinate), init_slots()
149 ctrl->slot_device_offset); init_slots()
151 ctrl->pci_dev->subordinate, slot->device, name); init_slots()
153 ctrl_err(ctrl, "pci_hp_register failed with error %d\n", init_slots()
163 list_add(&slot->slot_list, &ctrl->slot_list); init_slots()
179 void cleanup_slots(struct controller *ctrl) cleanup_slots() argument
185 list_for_each_safe(tmp, next, &ctrl->slot_list) { cleanup_slots()
201 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", set_attention_status()
214 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", enable_slot()
224 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", disable_slot()
235 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_power_status()
250 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_attention_status()
265 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_latch_status()
280 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_adapter_status()
305 struct controller *ctrl; shpc_probe() local
310 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); shpc_probe()
311 if (!ctrl) { shpc_probe()
315 INIT_LIST_HEAD(&ctrl->slot_list); shpc_probe()
317 rc = shpc_init(ctrl, pdev); shpc_probe()
319 ctrl_dbg(ctrl, "Controller initialization failed\n"); shpc_probe()
323 pci_set_drvdata(pdev, ctrl); shpc_probe()
326 rc = init_slots(ctrl); shpc_probe()
328 ctrl_err(ctrl, "Slot initialization failed\n"); shpc_probe()
332 rc = shpchp_create_ctrl_files(ctrl); shpc_probe()
339 cleanup_slots(ctrl); shpc_probe()
341 ctrl->hpc_ops->release_ctlr(ctrl); shpc_probe()
343 kfree(ctrl); shpc_probe()
350 struct controller *ctrl = pci_get_drvdata(dev); shpc_remove() local
352 shpchp_remove_ctrl_files(ctrl); shpc_remove()
353 ctrl->hpc_ops->release_ctlr(ctrl); shpc_remove()
354 kfree(ctrl); shpc_remove()
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| H A D | cpqphp_ctrl.c | 42 static u32 configure_new_device(struct controller *ctrl, struct pci_func *func,
44 static int configure_new_function(struct controller *ctrl, struct pci_func *func,
46 static void interrupt_event_handler(struct controller *ctrl);
67 static u8 handle_switch_change(u8 change, struct controller *ctrl) handle_switch_change() argument
86 func = cpqhp_slot_find(ctrl->bus, handle_switch_change()
87 (hp_slot + ctrl->slot_device_offset), 0); handle_switch_change()
92 taskInfo = &(ctrl->event_queue[ctrl->next_event]); handle_switch_change()
93 ctrl->next_event = (ctrl->next_event + 1) % 10; handle_switch_change()
98 temp_word = ctrl->ctrl_int_comp >> 16; handle_switch_change()
102 if (ctrl->ctrl_int_comp & (0x1L << hp_slot)) { handle_switch_change()
127 * @ctrl: scan lots of this controller
130 static struct slot *cpqhp_find_slot(struct controller *ctrl, u8 device) cpqhp_find_slot() argument
132 struct slot *slot = ctrl->slot; cpqhp_find_slot()
141 static u8 handle_presence_change(u16 change, struct controller *ctrl) handle_presence_change() argument
165 func = cpqhp_slot_find(ctrl->bus, handle_presence_change()
166 (hp_slot + ctrl->slot_device_offset), 0); handle_presence_change()
168 taskInfo = &(ctrl->event_queue[ctrl->next_event]); handle_presence_change()
169 ctrl->next_event = (ctrl->next_event + 1) % 10; handle_presence_change()
174 p_slot = cpqhp_find_slot(ctrl, hp_slot + (readb(ctrl->hpc_reg + SLOT_MASK) >> 4)); handle_presence_change()
181 if (func->switch_save && (ctrl->push_button == 1)) { handle_presence_change()
182 temp_word = ctrl->ctrl_int_comp >> 16; handle_presence_change()
215 temp_word = ctrl->ctrl_int_comp >> 16; handle_presence_change()
219 if ((!(ctrl->ctrl_int_comp & (0x010000 << hp_slot))) || handle_presence_change()
220 (!(ctrl->ctrl_int_comp & (0x01000000 << hp_slot)))) { handle_presence_change()
235 static u8 handle_power_fault(u8 change, struct controller *ctrl) handle_power_fault() argument
256 func = cpqhp_slot_find(ctrl->bus, handle_power_fault()
257 (hp_slot + ctrl->slot_device_offset), 0); handle_power_fault()
259 taskInfo = &(ctrl->event_queue[ctrl->next_event]); handle_power_fault()
260 ctrl->next_event = (ctrl->next_event + 1) % 10; handle_power_fault()
265 if (ctrl->ctrl_int_comp & (0x00000100 << hp_slot)) { handle_power_fault()
278 if (ctrl->rev < 4) { handle_power_fault()
279 amber_LED_on (ctrl, hp_slot); handle_power_fault()
280 green_LED_off (ctrl, hp_slot); handle_power_fault()
281 set_SOGO (ctrl); handle_power_fault()
288 simulated_NMI(hp_slot, ctrl); */ handle_power_fault()
893 struct controller *ctrl = data; cpqhp_ctrl_intr() local
901 misc = readw(ctrl->hpc_reg + MISC); cpqhp_ctrl_intr()
915 writew(misc, ctrl->hpc_reg + MISC); cpqhp_ctrl_intr()
918 misc = readw(ctrl->hpc_reg + MISC); cpqhp_ctrl_intr()
921 wake_up_interruptible(&ctrl->queue); cpqhp_ctrl_intr()
926 Diff = readl(ctrl->hpc_reg + INT_INPUT_CLEAR) ^ ctrl->ctrl_int_comp; cpqhp_ctrl_intr()
928 ctrl->ctrl_int_comp = readl(ctrl->hpc_reg + INT_INPUT_CLEAR); cpqhp_ctrl_intr()
931 writel(Diff, ctrl->hpc_reg + INT_INPUT_CLEAR); cpqhp_ctrl_intr()
934 temp_dword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR); cpqhp_ctrl_intr()
938 writel(0xFFFFFFFF, ctrl->hpc_reg + INT_INPUT_CLEAR); cpqhp_ctrl_intr()
940 schedule_flag += handle_switch_change((u8)(Diff & 0xFFL), ctrl); cpqhp_ctrl_intr()
941 schedule_flag += handle_presence_change((u16)((Diff & 0xFFFF0000L) >> 16), ctrl); cpqhp_ctrl_intr()
942 schedule_flag += handle_power_fault((u8)((Diff & 0xFF00L) >> 8), ctrl); cpqhp_ctrl_intr()
945 reset = readb(ctrl->hpc_reg + RESET_FREQ_MODE); cpqhp_ctrl_intr()
949 writeb(reset, ctrl->hpc_reg + RESET_FREQ_MODE); cpqhp_ctrl_intr()
950 reset = readb(ctrl->hpc_reg + RESET_FREQ_MODE); cpqhp_ctrl_intr()
951 wake_up_interruptible(&ctrl->queue); cpqhp_ctrl_intr()
1122 * @ctrl: controller to change frequency/mode for.
1129 static u8 set_controller_speed(struct controller *ctrl, u8 adapter_speed, u8 hp_slot) set_controller_speed() argument
1132 struct pci_bus *bus = ctrl->pci_bus; set_controller_speed()
1134 u8 slot_power = readb(ctrl->hpc_reg + SLOT_POWER); set_controller_speed()
1136 u32 leds = readl(ctrl->hpc_reg + LED_CONTROL); set_controller_speed()
1144 for (slot = ctrl->slot; slot; slot = slot->next) { set_controller_speed()
1145 if (slot->device == (hp_slot + ctrl->slot_device_offset)) set_controller_speed()
1164 if ((bus->cur_bus_speed > adapter_speed) && (!ctrl->pcix_speed_capability)) set_controller_speed()
1168 if ((bus->cur_bus_speed < adapter_speed) && (!ctrl->pcix_speed_capability)) set_controller_speed()
1180 writel(0x0L, ctrl->hpc_reg + LED_CONTROL); set_controller_speed()
1181 writeb(0x00, ctrl->hpc_reg + SLOT_ENABLE); set_controller_speed()
1183 set_SOGO(ctrl); set_controller_speed()
1184 wait_for_ctrl_irq(ctrl); set_controller_speed()
1190 pci_write_config_byte(ctrl->pci_dev, 0x41, reg); set_controller_speed()
1192 reg16 = readw(ctrl->hpc_reg + NEXT_CURR_FREQ); set_controller_speed()
1217 writew(reg16, ctrl->hpc_reg + NEXT_CURR_FREQ); set_controller_speed()
1222 writel(0, ctrl->hpc_reg + INT_MASK); set_controller_speed()
1224 pci_write_config_byte(ctrl->pci_dev, 0x41, reg); set_controller_speed()
1228 pci_read_config_byte(ctrl->pci_dev, 0x43, ®); set_controller_speed()
1229 pci_write_config_byte(ctrl->pci_dev, 0x43, reg); set_controller_speed()
1234 set_SOGO(ctrl); set_controller_speed()
1236 wait_for_ctrl_irq(ctrl); set_controller_speed()
1240 writel(leds, ctrl->hpc_reg + LED_CONTROL); set_controller_speed()
1241 writeb(slot_power, ctrl->hpc_reg + SLOT_ENABLE); set_controller_speed()
1243 set_SOGO(ctrl); set_controller_speed()
1244 wait_for_ctrl_irq(ctrl); set_controller_speed()
1247 slot = cpqhp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); set_controller_speed()
1262 * @ctrl: hotplug controller
1270 static u32 board_replaced(struct pci_func *func, struct controller *ctrl) board_replaced() argument
1272 struct pci_bus *bus = ctrl->pci_bus; board_replaced()
1278 hp_slot = func->device - ctrl->slot_device_offset; board_replaced()
1283 if (readl(ctrl->hpc_reg + INT_INPUT_CLEAR) & (0x01L << hp_slot)) board_replaced()
1288 else if (is_slot_enabled (ctrl, hp_slot)) board_replaced()
1291 mutex_lock(&ctrl->crit_sect); board_replaced()
1294 enable_slot_power (ctrl, hp_slot); board_replaced()
1296 set_SOGO(ctrl); board_replaced()
1299 wait_for_ctrl_irq (ctrl); board_replaced()
1303 temp_byte = readb(ctrl->hpc_reg + SLOT_POWER); board_replaced()
1304 writeb(0x00, ctrl->hpc_reg + SLOT_POWER); board_replaced()
1305 writeb(temp_byte, ctrl->hpc_reg + SLOT_POWER); board_replaced()
1307 set_SOGO(ctrl); board_replaced()
1310 wait_for_ctrl_irq (ctrl); board_replaced()
1312 adapter_speed = get_adapter_speed(ctrl, hp_slot); board_replaced()
1314 if (set_controller_speed(ctrl, adapter_speed, hp_slot)) board_replaced()
1318 disable_slot_power (ctrl, hp_slot); board_replaced()
1320 set_SOGO(ctrl); board_replaced()
1323 wait_for_ctrl_irq (ctrl); board_replaced()
1325 mutex_unlock(&ctrl->crit_sect); board_replaced()
1330 mutex_lock(&ctrl->crit_sect); board_replaced()
1332 slot_enable (ctrl, hp_slot); board_replaced()
1333 green_LED_blink (ctrl, hp_slot); board_replaced()
1335 amber_LED_off (ctrl, hp_slot); board_replaced()
1337 set_SOGO(ctrl); board_replaced()
1340 wait_for_ctrl_irq (ctrl); board_replaced()
1342 mutex_unlock(&ctrl->crit_sect); board_replaced()
1353 rc = cpqhp_valid_replace(ctrl, func); board_replaced()
1358 rc = cpqhp_configure_board(ctrl, func); board_replaced()
1367 mutex_lock(&ctrl->crit_sect); board_replaced()
1369 amber_LED_on (ctrl, hp_slot); board_replaced()
1370 green_LED_off (ctrl, hp_slot); board_replaced()
1371 slot_disable (ctrl, hp_slot); board_replaced()
1373 set_SOGO(ctrl); board_replaced()
1376 wait_for_ctrl_irq (ctrl); board_replaced()
1378 mutex_unlock(&ctrl->crit_sect); board_replaced()
1393 mutex_lock(&ctrl->crit_sect); board_replaced()
1395 amber_LED_on (ctrl, hp_slot); board_replaced()
1396 green_LED_off (ctrl, hp_slot); board_replaced()
1397 slot_disable (ctrl, hp_slot); board_replaced()
1399 set_SOGO(ctrl); board_replaced()
1402 wait_for_ctrl_irq (ctrl); board_replaced()
1404 mutex_unlock(&ctrl->crit_sect); board_replaced()
1416 * @ctrl: hotplug controller
1421 static u32 board_added(struct pci_func *func, struct controller *ctrl) board_added() argument
1430 struct pci_bus *bus = ctrl->pci_bus; board_added()
1434 hp_slot = func->device - ctrl->slot_device_offset; board_added()
1436 __func__, func->device, ctrl->slot_device_offset, hp_slot); board_added()
1438 mutex_lock(&ctrl->crit_sect); board_added()
1441 enable_slot_power(ctrl, hp_slot); board_added()
1443 set_SOGO(ctrl); board_added()
1446 wait_for_ctrl_irq (ctrl); board_added()
1451 temp_byte = readb(ctrl->hpc_reg + SLOT_POWER); board_added()
1452 writeb(0x00, ctrl->hpc_reg + SLOT_POWER); board_added()
1453 writeb(temp_byte, ctrl->hpc_reg + SLOT_POWER); board_added()
1455 set_SOGO(ctrl); board_added()
1458 wait_for_ctrl_irq (ctrl); board_added()
1460 adapter_speed = get_adapter_speed(ctrl, hp_slot); board_added()
1462 if (set_controller_speed(ctrl, adapter_speed, hp_slot)) board_added()
1466 disable_slot_power (ctrl, hp_slot); board_added()
1468 set_SOGO(ctrl); board_added()
1471 wait_for_ctrl_irq(ctrl); board_added()
1473 mutex_unlock(&ctrl->crit_sect); board_added()
1478 p_slot = cpqhp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); board_added()
1483 mutex_lock(&ctrl->crit_sect); board_added()
1487 slot_enable (ctrl, hp_slot); board_added()
1490 green_LED_blink (ctrl, hp_slot); board_added()
1493 amber_LED_off (ctrl, hp_slot); board_added()
1496 set_SOGO(ctrl); board_added()
1500 wait_for_ctrl_irq (ctrl); board_added()
1504 mutex_unlock(&ctrl->crit_sect); board_added()
1522 ctrl->pci_bus->number = func->bus; board_added()
1523 rc = pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(func->device, func->function), PCI_VENDOR_ID, &temp_register); board_added()
1538 res_lists.io_head = ctrl->io_head; board_added()
1539 res_lists.mem_head = ctrl->mem_head; board_added()
1540 res_lists.p_mem_head = ctrl->p_mem_head; board_added()
1541 res_lists.bus_head = ctrl->bus_head; board_added()
1544 rc = configure_new_device(ctrl, func, 0, &res_lists); board_added()
1547 ctrl->io_head = res_lists.io_head; board_added()
1548 ctrl->mem_head = res_lists.mem_head; board_added()
1549 ctrl->p_mem_head = res_lists.p_mem_head; board_added()
1550 ctrl->bus_head = res_lists.bus_head; board_added()
1552 cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); board_added()
1553 cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); board_added()
1554 cpqhp_resource_sort_and_combine(&(ctrl->io_head)); board_added()
1555 cpqhp_resource_sort_and_combine(&(ctrl->bus_head)); board_added()
1558 mutex_lock(&ctrl->crit_sect); board_added()
1560 amber_LED_on (ctrl, hp_slot); board_added()
1561 green_LED_off (ctrl, hp_slot); board_added()
1562 slot_disable (ctrl, hp_slot); board_added()
1564 set_SOGO(ctrl); board_added()
1567 wait_for_ctrl_irq (ctrl); board_added()
1569 mutex_unlock(&ctrl->crit_sect); board_added()
1572 cpqhp_save_slot_config(ctrl, func); board_added()
1585 new_slot = cpqhp_slot_find(ctrl->bus, func->device, index++); board_added()
1587 cpqhp_configure_device(ctrl, new_slot); board_added()
1590 mutex_lock(&ctrl->crit_sect); board_added()
1592 green_LED_on (ctrl, hp_slot); board_added()
1594 set_SOGO(ctrl); board_added()
1597 wait_for_ctrl_irq (ctrl); board_added()
1599 mutex_unlock(&ctrl->crit_sect); board_added()
1601 mutex_lock(&ctrl->crit_sect); board_added()
1603 amber_LED_on (ctrl, hp_slot); board_added()
1604 green_LED_off (ctrl, hp_slot); board_added()
1605 slot_disable (ctrl, hp_slot); board_added()
1607 set_SOGO(ctrl); board_added()
1610 wait_for_ctrl_irq (ctrl); board_added()
1612 mutex_unlock(&ctrl->crit_sect); board_added()
1624 * @ctrl: target controller
1626 static u32 remove_board(struct pci_func *func, u32 replace_flag, struct controller *ctrl) remove_board() argument
1642 hp_slot = func->device - ctrl->slot_device_offset; remove_board()
1647 if (replace_flag || !ctrl->add_support) remove_board()
1648 rc = cpqhp_save_base_addr_length(ctrl, func); remove_board()
1666 rc = cpqhp_save_used_resources(ctrl, func); remove_board()
1673 mutex_lock(&ctrl->crit_sect); remove_board()
1675 green_LED_off (ctrl, hp_slot); remove_board()
1676 slot_disable (ctrl, hp_slot); remove_board()
1678 set_SOGO(ctrl); remove_board()
1681 temp_byte = readb(ctrl->hpc_reg + SLOT_SERR); remove_board()
1683 writeb(temp_byte, ctrl->hpc_reg + SLOT_SERR); remove_board()
1686 wait_for_ctrl_irq (ctrl); remove_board()
1688 mutex_unlock(&ctrl->crit_sect); remove_board()
1690 if (!replace_flag && ctrl->add_support) { remove_board()
1692 res_lists.io_head = ctrl->io_head; remove_board()
1693 res_lists.mem_head = ctrl->mem_head; remove_board()
1694 res_lists.p_mem_head = ctrl->p_mem_head; remove_board()
1695 res_lists.bus_head = ctrl->bus_head; remove_board()
1699 ctrl->io_head = res_lists.io_head; remove_board()
1700 ctrl->mem_head = res_lists.mem_head; remove_board()
1701 ctrl->p_mem_head = res_lists.p_mem_head; remove_board()
1702 ctrl->bus_head = res_lists.bus_head; remove_board()
1704 cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); remove_board()
1705 cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); remove_board()
1706 cpqhp_resource_sort_and_combine(&(ctrl->io_head)); remove_board()
1707 cpqhp_resource_sort_and_combine(&(ctrl->bus_head)); remove_board()
1714 func = cpqhp_slot_find(ctrl->bus, device, 0); remove_board()
1718 func = cpqhp_slot_create(ctrl->bus); remove_board()
1723 func->bus = ctrl->bus; remove_board()
1745 struct controller *ctrl; event_thread() local
1758 for (ctrl = cpqhp_ctrl_list; ctrl; ctrl=ctrl->next) event_thread()
1759 interrupt_event_handler(ctrl); event_thread()
1783 static int update_slot_info(struct controller *ctrl, struct slot *slot) update_slot_info() argument
1792 info->power_status = get_slot_enabled(ctrl, slot); update_slot_info()
1793 info->attention_status = cpq_get_attention_status(ctrl, slot); update_slot_info()
1794 info->latch_status = cpq_get_latch_status(ctrl, slot); update_slot_info()
1795 info->adapter_status = get_presence_status(ctrl, slot); update_slot_info()
1801 static void interrupt_event_handler(struct controller *ctrl) interrupt_event_handler() argument
1814 if (ctrl->event_queue[loop].event_type != 0) { interrupt_event_handler()
1815 hp_slot = ctrl->event_queue[loop].hp_slot; interrupt_event_handler()
1817 func = cpqhp_slot_find(ctrl->bus, (hp_slot + ctrl->slot_device_offset), 0); interrupt_event_handler()
1821 p_slot = cpqhp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset); interrupt_event_handler()
1828 if (ctrl->event_queue[loop].event_type == INT_BUTTON_PRESS) { interrupt_event_handler()
1830 } else if (ctrl->event_queue[loop].event_type == interrupt_event_handler()
1835 mutex_lock(&ctrl->crit_sect); interrupt_event_handler()
1840 green_LED_on (ctrl, hp_slot); interrupt_event_handler()
1844 green_LED_off (ctrl, hp_slot); interrupt_event_handler()
1851 amber_LED_off (ctrl, hp_slot); interrupt_event_handler()
1853 set_SOGO(ctrl); interrupt_event_handler()
1856 wait_for_ctrl_irq (ctrl); interrupt_event_handler()
1858 mutex_unlock(&ctrl->crit_sect); interrupt_event_handler()
1861 else if (ctrl->event_queue[loop].event_type == INT_BUTTON_RELEASE) { interrupt_event_handler()
1864 if (is_slot_enabled (ctrl, hp_slot)) { interrupt_event_handler()
1873 mutex_lock(&ctrl->crit_sect); interrupt_event_handler()
1877 amber_LED_off (ctrl, hp_slot); interrupt_event_handler()
1878 green_LED_blink (ctrl, hp_slot); interrupt_event_handler()
1880 set_SOGO(ctrl); interrupt_event_handler()
1883 wait_for_ctrl_irq (ctrl); interrupt_event_handler()
1885 mutex_unlock(&ctrl->crit_sect); interrupt_event_handler()
1888 p_slot->ctrl = ctrl; interrupt_event_handler()
1898 else if (ctrl->event_queue[loop].event_type == INT_POWER_FAULT) { interrupt_event_handler()
1902 update_slot_info(ctrl, p_slot); interrupt_event_handler()
1905 ctrl->event_queue[loop].event_type = 0; interrupt_event_handler()
1929 struct controller *ctrl = (struct controller *) p_slot->ctrl; cpqhp_pushbutton_thread() local
1936 if (is_slot_enabled(ctrl, hp_slot)) { cpqhp_pushbutton_thread()
1940 dbg("In power_down_board, func = %p, ctrl = %p\n", func, ctrl); cpqhp_pushbutton_thread()
1946 if (cpqhp_process_SS(ctrl, func) != 0) { cpqhp_pushbutton_thread()
1947 amber_LED_on(ctrl, hp_slot); cpqhp_pushbutton_thread()
1948 green_LED_on(ctrl, hp_slot); cpqhp_pushbutton_thread()
1950 set_SOGO(ctrl); cpqhp_pushbutton_thread()
1953 wait_for_ctrl_irq(ctrl); cpqhp_pushbutton_thread()
1962 dbg("In add_board, func = %p, ctrl = %p\n", func, ctrl); cpqhp_pushbutton_thread()
1968 if (ctrl != NULL) { cpqhp_pushbutton_thread()
1969 if (cpqhp_process_SI(ctrl, func) != 0) { cpqhp_pushbutton_thread()
1970 amber_LED_on(ctrl, hp_slot); cpqhp_pushbutton_thread()
1971 green_LED_off(ctrl, hp_slot); cpqhp_pushbutton_thread()
1973 set_SOGO(ctrl); cpqhp_pushbutton_thread()
1976 wait_for_ctrl_irq (ctrl); cpqhp_pushbutton_thread()
1987 int cpqhp_process_SI(struct controller *ctrl, struct pci_func *func) cpqhp_process_SI() argument
1999 hp_slot = device - ctrl->slot_device_offset; cpqhp_process_SI()
2000 p_slot = cpqhp_find_slot(ctrl, device); cpqhp_process_SI()
2005 tempdword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR); cpqhp_process_SI()
2011 rc = board_replaced(func, ctrl); cpqhp_process_SI()
2016 func = cpqhp_slot_create(ctrl->bus); cpqhp_process_SI()
2020 func->bus = ctrl->bus; cpqhp_process_SI()
2027 temp_word = ctrl->ctrl_int_comp >> 16; cpqhp_process_SI()
2031 if (ctrl->ctrl_int_comp & (0x1L << hp_slot)) { cpqhp_process_SI()
2037 rc = board_added(func, ctrl); cpqhp_process_SI()
2045 func = cpqhp_slot_create(ctrl->bus); cpqhp_process_SI()
2050 func->bus = ctrl->bus; cpqhp_process_SI()
2057 temp_word = ctrl->ctrl_int_comp >> 16; cpqhp_process_SI()
2062 if (ctrl->ctrl_int_comp & (0x1L << hp_slot)) { cpqhp_process_SI()
2074 update_slot_info(ctrl, p_slot); cpqhp_process_SI()
2080 int cpqhp_process_SS(struct controller *ctrl, struct pci_func *func) cpqhp_process_SS() argument
2088 struct pci_bus *pci_bus = ctrl->pci_bus; cpqhp_process_SS()
2092 func = cpqhp_slot_find(ctrl->bus, device, index++); cpqhp_process_SS()
2093 p_slot = cpqhp_find_slot(ctrl, device); cpqhp_process_SS()
2129 func = cpqhp_slot_find(ctrl->bus, device, index++); cpqhp_process_SS()
2132 func = cpqhp_slot_find(ctrl->bus, device, 0); cpqhp_process_SS()
2135 replace_flag = !(ctrl->add_support); cpqhp_process_SS()
2136 rc = remove_board(func, replace_flag, ctrl); cpqhp_process_SS()
2142 update_slot_info(ctrl, p_slot); cpqhp_process_SS()
2149 * @ctrl: controller to use
2154 static void switch_leds(struct controller *ctrl, const int num_of_slots, switch_leds() argument
2164 writel(*work_LED, ctrl->hpc_reg + LED_CONTROL); switch_leds()
2166 set_SOGO(ctrl); switch_leds()
2169 wait_for_ctrl_irq(ctrl); switch_leds()
2178 * @ctrl: target controller
2181 * For hot plug ctrl folks to play with.
2183 int cpqhp_hardware_test(struct controller *ctrl, int test_num) cpqhp_hardware_test() argument
2190 num_of_slots = readb(ctrl->hpc_reg + SLOT_MASK) & 0x0f; cpqhp_hardware_test()
2198 save_LED = readl(ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2200 switch_leds(ctrl, num_of_slots, &work_LED, 0); cpqhp_hardware_test()
2201 switch_leds(ctrl, num_of_slots, &work_LED, 1); cpqhp_hardware_test()
2202 switch_leds(ctrl, num_of_slots, &work_LED, 0); cpqhp_hardware_test()
2203 switch_leds(ctrl, num_of_slots, &work_LED, 1); cpqhp_hardware_test()
2206 writel(work_LED, ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2207 switch_leds(ctrl, num_of_slots, &work_LED, 0); cpqhp_hardware_test()
2208 switch_leds(ctrl, num_of_slots, &work_LED, 1); cpqhp_hardware_test()
2210 writel(work_LED, ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2211 switch_leds(ctrl, num_of_slots, &work_LED, 0); cpqhp_hardware_test()
2212 switch_leds(ctrl, num_of_slots, &work_LED, 1); cpqhp_hardware_test()
2215 writel(work_LED, ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2217 set_SOGO(ctrl); cpqhp_hardware_test()
2220 wait_for_ctrl_irq (ctrl); cpqhp_hardware_test()
2225 writel(work_LED, ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2227 set_SOGO(ctrl); cpqhp_hardware_test()
2230 wait_for_ctrl_irq (ctrl); cpqhp_hardware_test()
2235 writel(work_LED, ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2237 writel(work_LED, ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2241 writel(save_LED, ctrl->hpc_reg + LED_CONTROL); cpqhp_hardware_test()
2243 set_SOGO(ctrl); cpqhp_hardware_test()
2246 wait_for_ctrl_irq (ctrl); cpqhp_hardware_test()
2261 * @ctrl: pointer to controller structure
2268 static u32 configure_new_device(struct controller *ctrl, struct pci_func *func, configure_new_device() argument
2281 ctrl->pci_bus->number = func->bus; configure_new_device()
2282 rc = pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(func->device, func->function), 0x0E, &temp_byte); configure_new_device()
2296 rc = configure_new_function(ctrl, new_slot, behind_bridge, resources); configure_new_device()
2320 pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(func->device, function), 0x00, &ID); configure_new_device()
2356 * @ctrl: pointer to controller structure
2364 static int configure_new_function(struct controller *ctrl, struct pci_func *func, configure_new_function() argument
2394 pci_bus = ctrl->pci_bus; configure_new_function()
2581 rc = configure_new_device(ctrl, new_slot, 1, &temp_resources); configure_new_function()
|
| H A D | pciehp_core.c | 82 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", release_slot()
90 static int init_slot(struct controller *ctrl) init_slot() argument
92 struct slot *slot = ctrl->slot; init_slot()
117 if (MRL_SENS(ctrl)) init_slot()
119 if (ATTN_LED(ctrl)) { init_slot()
130 snprintf(name, SLOT_NAME_SIZE, "%u", PSN(ctrl)); init_slot()
132 ctrl_dbg(ctrl, "Registering domain:bus:dev=%04x:%02x:00 sun=%x\n", init_slot()
133 pci_domain_nr(ctrl->pcie->port->subordinate), init_slot()
134 ctrl->pcie->port->subordinate->number, PSN(ctrl)); init_slot()
136 ctrl->pcie->port->subordinate, 0, name); init_slot()
138 ctrl_err(ctrl, init_slot()
149 static void cleanup_slot(struct controller *ctrl) cleanup_slot() argument
151 pci_hp_deregister(ctrl->slot->hotplug_slot); cleanup_slot()
161 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", set_attention_status()
173 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", enable_slot()
184 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", disable_slot()
194 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_power_status()
205 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_attention_status()
216 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_latch_status()
227 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", get_adapter_status()
238 ctrl_dbg(slot->ctrl, "%s: physical_slot = %s\n", reset_slot()
247 struct controller *ctrl; pciehp_probe() local
265 ctrl = pcie_init(dev); pciehp_probe()
266 if (!ctrl) { pciehp_probe()
270 set_service_data(dev, ctrl); pciehp_probe()
273 rc = init_slot(ctrl); pciehp_probe()
276 ctrl_warn(ctrl, "Slot already registered by another hotplug driver\n"); pciehp_probe()
278 ctrl_err(ctrl, "Slot initialization failed\n"); pciehp_probe()
283 rc = pcie_init_notification(ctrl); pciehp_probe()
285 ctrl_err(ctrl, "Notification initialization failed\n"); pciehp_probe()
290 slot = ctrl->slot; pciehp_probe()
299 if (!occupied && poweron && POWER_CTRL(ctrl)) pciehp_probe()
305 cleanup_slot(ctrl); pciehp_probe()
307 pciehp_release_ctrl(ctrl); pciehp_probe()
314 struct controller *ctrl = get_service_data(dev); pciehp_remove() local
316 cleanup_slot(ctrl); pciehp_remove()
317 pciehp_release_ctrl(ctrl); pciehp_remove()
328 struct controller *ctrl; pciehp_resume() local
332 ctrl = get_service_data(dev); pciehp_resume()
335 pcie_enable_notification(ctrl); pciehp_resume()
337 slot = ctrl->slot; pciehp_resume()
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| H A D | pciehp.h | 59 #define ctrl_dbg(ctrl, format, arg...) \
62 dev_printk(KERN_DEBUG, &ctrl->pcie->device, \
65 #define ctrl_err(ctrl, format, arg...) \
66 dev_err(&ctrl->pcie->device, format, ## arg)
67 #define ctrl_info(ctrl, format, arg...) \
68 dev_info(&ctrl->pcie->device, format, ## arg)
69 #define ctrl_warn(ctrl, format, arg...) \
70 dev_warn(&ctrl->pcie->device, format, ## arg)
75 struct controller *ctrl; member in struct:slot
123 #define ATTN_BUTTN(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
124 #define POWER_CTRL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
125 #define MRL_SENS(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
126 #define ATTN_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
127 #define PWR_LED(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
128 #define HP_SUPR_RM(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS)
129 #define EMI(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP)
130 #define NO_CMD_CMPL(ctrl) ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
131 #define PSN(ctrl) (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
144 int pcie_init_notification(struct controller *ctrl);
147 void pcie_enable_notification(struct controller *ctrl);
160 int pciehp_check_link_status(struct controller *ctrl);
161 bool pciehp_check_link_active(struct controller *ctrl);
162 void pciehp_release_ctrl(struct controller *ctrl);
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| H A D | cpqphp.h | 275 struct controller *ctrl; member in struct:slot
409 void cpqhp_create_debugfs_files(struct controller *ctrl);
410 void cpqhp_remove_debugfs_files(struct controller *ctrl);
415 int cpqhp_find_available_resources(struct controller *ctrl,
422 int cpqhp_process_SI(struct controller *ctrl, struct pci_func *func);
423 int cpqhp_process_SS(struct controller *ctrl, struct pci_func *func);
424 int cpqhp_hardware_test(struct controller *ctrl, int test_num);
431 int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num,
433 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug);
434 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func);
435 int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func);
436 int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func);
437 int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot);
438 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func);
443 int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func);
479 static inline void set_SOGO(struct controller *ctrl) set_SOGO() argument
483 misc = readw(ctrl->hpc_reg + MISC); set_SOGO()
485 writew(misc, ctrl->hpc_reg + MISC); set_SOGO()
489 static inline void amber_LED_on(struct controller *ctrl, u8 slot) amber_LED_on() argument
493 led_control = readl(ctrl->hpc_reg + LED_CONTROL); amber_LED_on()
495 writel(led_control, ctrl->hpc_reg + LED_CONTROL); amber_LED_on()
499 static inline void amber_LED_off(struct controller *ctrl, u8 slot) amber_LED_off() argument
503 led_control = readl(ctrl->hpc_reg + LED_CONTROL); amber_LED_off()
505 writel(led_control, ctrl->hpc_reg + LED_CONTROL); amber_LED_off()
509 static inline int read_amber_LED(struct controller *ctrl, u8 slot) read_amber_LED() argument
513 led_control = readl(ctrl->hpc_reg + LED_CONTROL); read_amber_LED()
520 static inline void green_LED_on(struct controller *ctrl, u8 slot) green_LED_on() argument
524 led_control = readl(ctrl->hpc_reg + LED_CONTROL); green_LED_on()
526 writel(led_control, ctrl->hpc_reg + LED_CONTROL); green_LED_on()
529 static inline void green_LED_off(struct controller *ctrl, u8 slot) green_LED_off() argument
533 led_control = readl(ctrl->hpc_reg + LED_CONTROL); green_LED_off()
535 writel(led_control, ctrl->hpc_reg + LED_CONTROL); green_LED_off()
539 static inline void green_LED_blink(struct controller *ctrl, u8 slot) green_LED_blink() argument
543 led_control = readl(ctrl->hpc_reg + LED_CONTROL); green_LED_blink()
546 writel(led_control, ctrl->hpc_reg + LED_CONTROL); green_LED_blink()
550 static inline void slot_disable(struct controller *ctrl, u8 slot) slot_disable() argument
554 slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE); slot_disable()
556 writeb(slot_enable, ctrl->hpc_reg + SLOT_ENABLE); slot_disable()
560 static inline void slot_enable(struct controller *ctrl, u8 slot) slot_enable() argument
564 slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE); slot_enable()
566 writeb(slot_enable, ctrl->hpc_reg + SLOT_ENABLE); slot_enable()
570 static inline u8 is_slot_enabled(struct controller *ctrl, u8 slot) is_slot_enabled() argument
574 slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE); is_slot_enabled()
580 static inline u8 read_slot_enable(struct controller *ctrl) read_slot_enable() argument
582 return readb(ctrl->hpc_reg + SLOT_ENABLE); read_slot_enable()
589 * @ctrl: controller to get frequency/mode for.
593 static inline u8 get_controller_speed(struct controller *ctrl) get_controller_speed() argument
598 if (ctrl->pcix_support) { get_controller_speed()
599 curr_freq = readb(ctrl->hpc_reg + NEXT_CURR_FREQ); get_controller_speed()
612 misc = readw(ctrl->hpc_reg + MISC); get_controller_speed()
620 * @ctrl: hotplug controller.
625 static inline u8 get_adapter_speed(struct controller *ctrl, u8 hp_slot) get_adapter_speed() argument
627 u32 temp_dword = readl(ctrl->hpc_reg + NON_INT_INPUT); get_adapter_speed()
629 if (ctrl->pcix_support) { get_adapter_speed()
642 static inline void enable_slot_power(struct controller *ctrl, u8 slot) enable_slot_power() argument
646 slot_power = readb(ctrl->hpc_reg + SLOT_POWER); enable_slot_power()
648 writeb(slot_power, ctrl->hpc_reg + SLOT_POWER); enable_slot_power()
651 static inline void disable_slot_power(struct controller *ctrl, u8 slot) disable_slot_power() argument
655 slot_power = readb(ctrl->hpc_reg + SLOT_POWER); disable_slot_power()
657 writeb(slot_power, ctrl->hpc_reg + SLOT_POWER); disable_slot_power()
661 static inline int cpq_get_attention_status(struct controller *ctrl, struct slot *slot) cpq_get_attention_status() argument
665 hp_slot = slot->device - ctrl->slot_device_offset; cpq_get_attention_status()
667 return read_amber_LED(ctrl, hp_slot); cpq_get_attention_status()
671 static inline int get_slot_enabled(struct controller *ctrl, struct slot *slot) get_slot_enabled() argument
675 hp_slot = slot->device - ctrl->slot_device_offset; get_slot_enabled()
677 return is_slot_enabled(ctrl, hp_slot); get_slot_enabled()
681 static inline int cpq_get_latch_status(struct controller *ctrl, cpq_get_latch_status() argument
687 hp_slot = slot->device - ctrl->slot_device_offset; cpq_get_latch_status()
688 dbg("%s: slot->device = %d, ctrl->slot_device_offset = %d \n", cpq_get_latch_status()
689 __func__, slot->device, ctrl->slot_device_offset); cpq_get_latch_status()
691 status = (readl(ctrl->hpc_reg + INT_INPUT_CLEAR) & (0x01L << hp_slot)); cpq_get_latch_status()
697 static inline int get_presence_status(struct controller *ctrl, get_presence_status() argument
704 hp_slot = slot->device - ctrl->slot_device_offset; get_presence_status()
706 tempdword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR); get_presence_status()
713 static inline int wait_for_ctrl_irq(struct controller *ctrl) wait_for_ctrl_irq() argument
719 add_wait_queue(&ctrl->queue, &wait); wait_for_ctrl_irq()
722 remove_wait_queue(&ctrl->queue, &wait); wait_for_ctrl_irq()
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| H A D | shpchp.h | 62 #define ctrl_dbg(ctrl, format, arg...) \
65 dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \
68 #define ctrl_err(ctrl, format, arg...) \
69 dev_err(&ctrl->pci_dev->dev, format, ## arg)
70 #define ctrl_info(ctrl, format, arg...) \
71 dev_info(&ctrl->pci_dev->dev, format, ## arg)
72 #define ctrl_warn(ctrl, format, arg...) \
73 dev_warn(&ctrl->pci_dev->dev, format, ## arg)
86 struct controller *ctrl; member in struct:slot
171 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
172 void shpchp_remove_ctrl_files(struct controller *ctrl);
175 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
176 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
177 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
178 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
181 void cleanup_slots(struct controller *ctrl);
183 int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
239 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device) shpchp_find_slot() argument
243 list_for_each_entry(slot, &ctrl->slot_list, slot_list) { list_for_each_entry()
248 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
257 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp); amd_pogo_errata_save_misc_reg()
259 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp; amd_pogo_errata_save_misc_reg()
267 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); amd_pogo_errata_save_misc_reg()
279 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg); amd_pogo_errata_restore_misc_reg()
282 ctrl_dbg(p_slot->ctrl, amd_pogo_errata_restore_misc_reg()
286 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set); amd_pogo_errata_restore_misc_reg()
290 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg); amd_pogo_errata_restore_misc_reg()
293 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n"); amd_pogo_errata_restore_misc_reg()
295 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set); amd_pogo_errata_restore_misc_reg()
298 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp ); amd_pogo_errata_restore_misc_reg()
300 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK) amd_pogo_errata_restore_misc_reg()
305 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK) amd_pogo_errata_restore_misc_reg()
310 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK) amd_pogo_errata_restore_misc_reg()
315 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK) amd_pogo_errata_restore_misc_reg()
320 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK) amd_pogo_errata_restore_misc_reg()
324 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp); amd_pogo_errata_restore_misc_reg()
344 void (*release_ctlr)(struct controller *ctrl);
345 int (*check_cmd_status)(struct controller *ctrl);
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| H A D | pciehp_pci.c | 40 struct pci_dev *bridge = p_slot->ctrl->pcie->port; pciehp_configure_device()
43 struct controller *ctrl = p_slot->ctrl; pciehp_configure_device() local
49 ctrl_err(ctrl, "Device %s already exists at %04x:%02x:00, cannot hot-add\n", pciehp_configure_device()
58 ctrl_err(ctrl, "No new device found\n"); pciehp_configure_device()
82 struct pci_bus *parent = p_slot->ctrl->pcie->port->subordinate; pciehp_unconfigure_device()
84 struct controller *ctrl = p_slot->ctrl; pciehp_unconfigure_device() local
86 ctrl_dbg(ctrl, "%s: domain:bus:dev = %04x:%02x:00\n", pciehp_unconfigure_device()
104 ctrl_err(ctrl, pciehp_unconfigure_device()
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| H A D | shpchp_pci.c | 40 struct controller *ctrl = p_slot->ctrl; shpchp_configure_device() local
41 struct pci_dev *bridge = ctrl->pci_dev; shpchp_configure_device()
49 ctrl_err(ctrl, "Device %s already exists at %04x:%02x:%02x, cannot hot-add\n", shpchp_configure_device()
59 ctrl_err(ctrl, "No new device found\n"); shpchp_configure_device()
84 struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate; shpchp_unconfigure_device()
86 struct controller *ctrl = p_slot->ctrl; shpchp_unconfigure_device() local
88 ctrl_dbg(ctrl, "%s: domain:bus:dev = %04x:%02x:%02x\n", shpchp_unconfigure_device()
101 ctrl_err(ctrl, shpchp_unconfigure_device()
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| H A D | cpqphp_sysfs.c | 42 static int show_ctrl (struct controller *ctrl, char *buf) show_ctrl() argument
50 res = ctrl->mem_head; show_ctrl()
57 res = ctrl->p_mem_head; show_ctrl()
64 res = ctrl->io_head; show_ctrl()
71 res = ctrl->bus_head; show_ctrl()
80 static int show_dev (struct controller *ctrl, char *buf) show_dev() argument
88 slot = ctrl->slot; show_dev()
128 static int spew_debug_info(struct controller *ctrl, char *data, int size) spew_debug_info() argument
132 used = size - show_ctrl(ctrl, data); spew_debug_info()
133 used = (size - used) - show_dev(ctrl, &data[used]); spew_debug_info()
140 struct controller *ctrl; member in struct:ctrl_dbg
147 struct controller *ctrl = inode->i_private; open() local
160 dbg->size = spew_debug_info(ctrl, dbg->data, MAX_OUTPUT); open()
211 void cpqhp_create_debugfs_files(struct controller *ctrl) cpqhp_create_debugfs_files() argument
213 ctrl->dentry = debugfs_create_file(dev_name(&ctrl->pci_dev->dev), cpqhp_create_debugfs_files()
214 S_IRUGO, root, ctrl, &debug_ops); cpqhp_create_debugfs_files()
217 void cpqhp_remove_debugfs_files(struct controller *ctrl) cpqhp_remove_debugfs_files() argument
219 debugfs_remove(ctrl->dentry); cpqhp_remove_debugfs_files()
220 ctrl->dentry = NULL; cpqhp_remove_debugfs_files()
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| H A D | cpqphp_pci.c | 84 int cpqhp_configure_device (struct controller *ctrl, struct pci_func *func) cpqhp_configure_device() argument
98 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function)); cpqhp_configure_device()
100 pci_bus_add_devices(ctrl->pci_dev->bus); cpqhp_configure_device()
206 static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num) PCI_ScanBusForNonBridge() argument
212 ctrl->pci_bus->number = bus_num; PCI_ScanBusForNonBridge()
216 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) PCI_ScanBusForNonBridge()
228 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1) PCI_ScanBusForNonBridge()
233 pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus); PCI_ScanBusForNonBridge()
244 static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge) PCI_GetBusDevHelper() argument
259 ctrl->pci_bus->number = tbus; PCI_GetBusDevHelper()
260 pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work); PCI_GetBusDevHelper()
265 pci_bus_read_config_dword (ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work); PCI_GetBusDevHelper()
269 pci_bus_read_config_byte (ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus); PCI_GetBusDevHelper()
271 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) { PCI_GetBusDevHelper()
283 int cpqhp_get_bus_dev (struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot) cpqhp_get_bus_dev() argument
286 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0); cpqhp_get_bus_dev()
304 int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug) cpqhp_save_config() argument
337 ctrl->pci_bus->number = busnumber; cpqhp_save_config()
340 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID); cpqhp_save_config()
361 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code); cpqhp_save_config()
365 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type); cpqhp_save_config()
383 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus); cpqhp_save_config()
392 rc = cpqhp_save_config(ctrl, sub_bus, 0); cpqhp_save_config()
395 ctrl->pci_bus->number = busnumber; cpqhp_save_config()
422 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop])); cpqhp_save_config()
437 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID); cpqhp_save_config()
442 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code); cpqhp_save_config()
446 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type); cpqhp_save_config()
468 int cpqhp_save_slot_config (struct controller *ctrl, struct pci_func *new_slot) cpqhp_save_slot_config() argument
483 ctrl->pci_bus->number = new_slot->bus; cpqhp_save_slot_config()
484 pci_bus_read_config_dword (ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID); cpqhp_save_slot_config()
489 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code); cpqhp_save_slot_config()
490 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type); cpqhp_save_slot_config()
500 pci_bus_read_config_byte (ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus); cpqhp_save_slot_config()
507 rc = cpqhp_save_config(ctrl, sub_bus, 0); cpqhp_save_slot_config()
510 ctrl->pci_bus->number = new_slot->bus; cpqhp_save_slot_config()
517 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) & (new_slot-> config_space [cloop])); cpqhp_save_slot_config()
527 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID); cpqhp_save_slot_config()
532 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code); cpqhp_save_slot_config()
533 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type); cpqhp_save_slot_config()
552 int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func) cpqhp_save_base_addr_length() argument
564 struct pci_bus *pci_bus = ctrl->pci_bus; cpqhp_save_base_addr_length()
584 rc = cpqhp_save_base_addr_length(ctrl, next); cpqhp_save_base_addr_length()
689 int cpqhp_save_used_resources (struct controller *ctrl, struct pci_func *func) cpqhp_save_used_resources() argument
709 struct pci_bus *pci_bus = ctrl->pci_bus; cpqhp_save_used_resources()
952 int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func) cpqhp_configure_board() argument
962 struct pci_bus *pci_bus = ctrl->pci_bus; cpqhp_configure_board()
988 rc = cpqhp_configure_board(ctrl, next); cpqhp_configure_board()
1030 int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func) cpqhp_valid_replace() argument
1041 struct pci_bus *pci_bus = ctrl->pci_bus; cpqhp_valid_replace()
1086 rc = cpqhp_valid_replace(ctrl, next); cpqhp_valid_replace()
1172 int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start) cpqhp_find_available_resources() argument
1226 cpqhp_nic_irq = ctrl->cfgspc_irq; cpqhp_find_available_resources()
1229 cpqhp_disk_irq = ctrl->cfgspc_irq; cpqhp_find_available_resources()
1233 rc = compaq_nvram_load(rom_start, ctrl); cpqhp_find_available_resources()
1264 if (primary_bus != ctrl->bus) { cpqhp_find_available_resources()
1270 ctrl->pci_bus->number = primary_bus; cpqhp_find_available_resources()
1271 pci_bus_read_config_dword (ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword); cpqhp_find_available_resources()
1318 io_node->next = ctrl->io_head; cpqhp_find_available_resources()
1319 ctrl->io_head = io_node; cpqhp_find_available_resources()
1341 mem_node->next = ctrl->mem_head; cpqhp_find_available_resources()
1342 ctrl->mem_head = mem_node; cpqhp_find_available_resources()
1366 p_mem_node->next = ctrl->p_mem_head; cpqhp_find_available_resources()
1367 ctrl->p_mem_head = p_mem_node; cpqhp_find_available_resources()
1389 bus_node->next = ctrl->bus_head; cpqhp_find_available_resources()
1390 ctrl->bus_head = bus_node; cpqhp_find_available_resources()
1405 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); cpqhp_find_available_resources()
1406 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); cpqhp_find_available_resources()
1407 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head)); cpqhp_find_available_resources()
1408 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head)); cpqhp_find_available_resources()
|
| H A D | cpqphp_nvram.c | 245 struct controller *ctrl; store_HRT() local
265 ctrl = cpqhp_ctrl_list; store_HRT()
268 rc = add_byte(&pFill, 1 + ctrl->push_flag, &usedbytes, &available); store_HRT()
277 while (ctrl) { store_HRT()
283 rc = add_byte(&pFill, ctrl->bus, &usedbytes, &available); store_HRT()
288 rc = add_byte(&pFill, PCI_SLOT(ctrl->pci_dev->devfn), &usedbytes, &available); store_HRT()
293 rc = add_byte(&pFill, PCI_FUNC(ctrl->pci_dev->devfn), &usedbytes, &available); store_HRT()
304 resNode = ctrl->mem_head; store_HRT()
329 resNode = ctrl->p_mem_head; store_HRT()
354 resNode = ctrl->io_head; store_HRT()
379 resNode = ctrl->bus_head; store_HRT()
402 ctrl = ctrl->next; store_HRT()
438 int compaq_nvram_load (void __iomem *rom_start, struct controller *ctrl) compaq_nvram_load() argument
468 ((p_EV_header->Version == 1) && !ctrl->push_flag)) { compaq_nvram_load()
482 while ((bus != ctrl->bus) || compaq_nvram_load()
483 (device != PCI_SLOT(ctrl->pci_dev->devfn)) || compaq_nvram_load()
484 (function != PCI_FUNC(ctrl->pci_dev->devfn))) { compaq_nvram_load()
547 mem_node->next = ctrl->mem_head; compaq_nvram_load()
548 ctrl->mem_head = mem_node; compaq_nvram_load()
575 p_mem_node->next = ctrl->p_mem_head; compaq_nvram_load()
576 ctrl->p_mem_head = p_mem_node; compaq_nvram_load()
603 io_node->next = ctrl->io_head; compaq_nvram_load()
604 ctrl->io_head = io_node; compaq_nvram_load()
629 bus_node->next = ctrl->bus_head; compaq_nvram_load()
630 ctrl->bus_head = bus_node; compaq_nvram_load()
637 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head)); compaq_nvram_load()
638 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head)); compaq_nvram_load()
639 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head)); compaq_nvram_load()
640 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head)); compaq_nvram_load()
645 if ((evbuffer[0] != 0) && (!ctrl->push_flag)) compaq_nvram_load()
|
| H A D | shpchp_sysfs.c | 86 static DEVICE_ATTR (ctrl, S_IRUGO, show_ctrl, NULL);
88 int shpchp_create_ctrl_files (struct controller *ctrl) shpchp_create_ctrl_files() argument
90 return device_create_file (&ctrl->pci_dev->dev, &dev_attr_ctrl); shpchp_create_ctrl_files()
93 void shpchp_remove_ctrl_files(struct controller *ctrl) shpchp_remove_ctrl_files() argument
95 device_remove_file(&ctrl->pci_dev->dev, &dev_attr_ctrl); shpchp_remove_ctrl_files()
|
| /linux-4.1.27/drivers/block/rsxx/ |
| H A D | dma.c | 215 q_depth += atomic_read(&card->ctrl[i].stats.hw_q_depth); dma_intr_coal_auto_tune()
224 static void rsxx_free_dma(struct rsxx_dma_ctrl *ctrl, struct rsxx_dma *dma) rsxx_free_dma() argument
227 if (!pci_dma_mapping_error(ctrl->card->dev, dma->dma_addr)) { rsxx_free_dma()
228 pci_unmap_page(ctrl->card->dev, dma->dma_addr, rsxx_free_dma()
239 static void rsxx_complete_dma(struct rsxx_dma_ctrl *ctrl, rsxx_complete_dma() argument
244 ctrl->stats.dma_sw_err++; rsxx_complete_dma()
246 ctrl->stats.dma_hw_fault++; rsxx_complete_dma()
248 ctrl->stats.dma_cancelled++; rsxx_complete_dma()
251 dma->cb(ctrl->card, dma->cb_data, status ? 1 : 0); rsxx_complete_dma()
253 rsxx_free_dma(ctrl, dma); rsxx_complete_dma()
256 int rsxx_cleanup_dma_queue(struct rsxx_dma_ctrl *ctrl, rsxx_cleanup_dma_queue() argument
266 rsxx_complete_dma(ctrl, dma, DMA_CANCELLED); list_for_each_entry_safe()
268 rsxx_free_dma(ctrl, dma); list_for_each_entry_safe()
275 static void rsxx_requeue_dma(struct rsxx_dma_ctrl *ctrl, rsxx_requeue_dma() argument
282 spin_lock_bh(&ctrl->queue_lock); rsxx_requeue_dma()
283 ctrl->stats.sw_q_depth++; rsxx_requeue_dma()
284 list_add(&dma->list, &ctrl->queue); rsxx_requeue_dma()
285 spin_unlock_bh(&ctrl->queue_lock); rsxx_requeue_dma()
288 static void rsxx_handle_dma_error(struct rsxx_dma_ctrl *ctrl, rsxx_handle_dma_error() argument
295 dev_dbg(CARD_TO_DEV(ctrl->card), rsxx_handle_dma_error()
300 ctrl->stats.crc_errors++; rsxx_handle_dma_error()
302 ctrl->stats.hard_errors++; rsxx_handle_dma_error()
304 ctrl->stats.soft_errors++; rsxx_handle_dma_error()
309 if (ctrl->card->scrub_hard) { rsxx_handle_dma_error()
312 ctrl->stats.reads_retried++; rsxx_handle_dma_error()
315 ctrl->stats.reads_failed++; rsxx_handle_dma_error()
319 ctrl->stats.reads_failed++; rsxx_handle_dma_error()
327 ctrl->stats.reads_failed++; rsxx_handle_dma_error()
333 ctrl->stats.writes_failed++; rsxx_handle_dma_error()
338 ctrl->stats.discards_failed++; rsxx_handle_dma_error()
342 dev_err(CARD_TO_DEV(ctrl->card), rsxx_handle_dma_error()
352 rsxx_requeue_dma(ctrl, dma); rsxx_handle_dma_error()
354 rsxx_complete_dma(ctrl, dma, status); rsxx_handle_dma_error()
359 struct rsxx_dma_ctrl *ctrl = (struct rsxx_dma_ctrl *)data; dma_engine_stalled() local
362 if (atomic_read(&ctrl->stats.hw_q_depth) == 0 || dma_engine_stalled()
363 unlikely(ctrl->card->eeh_state)) dma_engine_stalled()
366 if (ctrl->cmd.idx != ioread32(ctrl->regmap + SW_CMD_IDX)) { dma_engine_stalled()
371 dev_warn(CARD_TO_DEV(ctrl->card), dma_engine_stalled()
373 iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX); dma_engine_stalled()
374 mod_timer(&ctrl->activity_timer, dma_engine_stalled()
377 dev_warn(CARD_TO_DEV(ctrl->card), dma_engine_stalled()
379 ctrl->id); dma_engine_stalled()
380 ctrl->card->dma_fault = 1; dma_engine_stalled()
383 spin_lock(&ctrl->queue_lock); dma_engine_stalled()
384 cnt = rsxx_cleanup_dma_queue(ctrl, &ctrl->queue, COMPLETE_DMA); dma_engine_stalled()
385 spin_unlock(&ctrl->queue_lock); dma_engine_stalled()
387 cnt += rsxx_dma_cancel(ctrl); dma_engine_stalled()
390 dev_info(CARD_TO_DEV(ctrl->card), dma_engine_stalled()
392 cnt, ctrl->id); dma_engine_stalled()
396 static void rsxx_issue_dmas(struct rsxx_dma_ctrl *ctrl) rsxx_issue_dmas() argument
404 hw_cmd_buf = ctrl->cmd.buf; rsxx_issue_dmas()
406 if (unlikely(ctrl->card->halt) || rsxx_issue_dmas()
407 unlikely(ctrl->card->eeh_state)) rsxx_issue_dmas()
411 spin_lock_bh(&ctrl->queue_lock); rsxx_issue_dmas()
412 if (list_empty(&ctrl->queue)) { rsxx_issue_dmas()
413 spin_unlock_bh(&ctrl->queue_lock); rsxx_issue_dmas()
416 spin_unlock_bh(&ctrl->queue_lock); rsxx_issue_dmas()
418 tag = pop_tracker(ctrl->trackers); rsxx_issue_dmas()
422 spin_lock_bh(&ctrl->queue_lock); rsxx_issue_dmas()
423 dma = list_entry(ctrl->queue.next, struct rsxx_dma, list); rsxx_issue_dmas()
425 ctrl->stats.sw_q_depth--; rsxx_issue_dmas()
426 spin_unlock_bh(&ctrl->queue_lock); rsxx_issue_dmas()
433 if (unlikely(ctrl->card->dma_fault)) { rsxx_issue_dmas()
434 push_tracker(ctrl->trackers, tag); rsxx_issue_dmas()
435 rsxx_complete_dma(ctrl, dma, DMA_CANCELLED); rsxx_issue_dmas()
455 dma->dma_addr = pci_map_page(ctrl->card->dev, dma->page, rsxx_issue_dmas()
457 if (pci_dma_mapping_error(ctrl->card->dev, dma->dma_addr)) { rsxx_issue_dmas()
458 push_tracker(ctrl->trackers, tag); rsxx_issue_dmas()
459 rsxx_complete_dma(ctrl, dma, DMA_CANCELLED); rsxx_issue_dmas()
464 set_tracker_dma(ctrl->trackers, tag, dma); rsxx_issue_dmas()
465 hw_cmd_buf[ctrl->cmd.idx].command = dma->cmd; rsxx_issue_dmas()
466 hw_cmd_buf[ctrl->cmd.idx].tag = tag; rsxx_issue_dmas()
467 hw_cmd_buf[ctrl->cmd.idx]._rsvd = 0; rsxx_issue_dmas()
468 hw_cmd_buf[ctrl->cmd.idx].sub_page = rsxx_issue_dmas()
472 hw_cmd_buf[ctrl->cmd.idx].device_addr = rsxx_issue_dmas()
475 hw_cmd_buf[ctrl->cmd.idx].host_addr = rsxx_issue_dmas()
478 dev_dbg(CARD_TO_DEV(ctrl->card), rsxx_issue_dmas()
480 ctrl->id, dma->laddr, tag, ctrl->cmd.idx); rsxx_issue_dmas()
482 ctrl->cmd.idx = (ctrl->cmd.idx + 1) & RSXX_CS_IDX_MASK; rsxx_issue_dmas()
486 ctrl->stats.writes_issued++; rsxx_issue_dmas()
488 ctrl->stats.discards_issued++; rsxx_issue_dmas()
490 ctrl->stats.reads_issued++; rsxx_issue_dmas()
495 atomic_add(cmds_pending, &ctrl->stats.hw_q_depth); rsxx_issue_dmas()
496 mod_timer(&ctrl->activity_timer, rsxx_issue_dmas()
499 if (unlikely(ctrl->card->eeh_state)) { rsxx_issue_dmas()
500 del_timer_sync(&ctrl->activity_timer); rsxx_issue_dmas()
504 iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX); rsxx_issue_dmas()
508 static void rsxx_dma_done(struct rsxx_dma_ctrl *ctrl) rsxx_dma_done() argument
517 hw_st_buf = ctrl->status.buf; rsxx_dma_done()
519 if (unlikely(ctrl->card->halt) || rsxx_dma_done()
520 unlikely(ctrl->card->dma_fault) || rsxx_dma_done()
521 unlikely(ctrl->card->eeh_state)) rsxx_dma_done()
524 count = le16_to_cpu(hw_st_buf[ctrl->status.idx].count); rsxx_dma_done()
526 while (count == ctrl->e_cnt) { rsxx_dma_done()
536 status = hw_st_buf[ctrl->status.idx].status; rsxx_dma_done()
537 tag = hw_st_buf[ctrl->status.idx].tag; rsxx_dma_done()
539 dma = get_tracker_dma(ctrl->trackers, tag); rsxx_dma_done()
541 spin_lock_irqsave(&ctrl->card->irq_lock, flags); rsxx_dma_done()
542 rsxx_disable_ier(ctrl->card, CR_INTR_DMA_ALL); rsxx_dma_done()
543 spin_unlock_irqrestore(&ctrl->card->irq_lock, flags); rsxx_dma_done()
545 dev_err(CARD_TO_DEV(ctrl->card), rsxx_dma_done()
548 tag, ctrl->status.idx, ctrl->id); rsxx_dma_done()
552 dev_dbg(CARD_TO_DEV(ctrl->card), rsxx_dma_done()
555 ctrl->id, dma->laddr, tag, status, count, rsxx_dma_done()
556 ctrl->status.idx); rsxx_dma_done()
558 atomic_dec(&ctrl->stats.hw_q_depth); rsxx_dma_done()
560 mod_timer(&ctrl->activity_timer, rsxx_dma_done()
564 rsxx_handle_dma_error(ctrl, dma, status); rsxx_dma_done()
566 rsxx_complete_dma(ctrl, dma, 0); rsxx_dma_done()
568 push_tracker(ctrl->trackers, tag); rsxx_dma_done()
570 ctrl->status.idx = (ctrl->status.idx + 1) & rsxx_dma_done()
572 ctrl->e_cnt++; rsxx_dma_done()
574 count = le16_to_cpu(hw_st_buf[ctrl->status.idx].count); rsxx_dma_done()
577 dma_intr_coal_auto_tune(ctrl->card); rsxx_dma_done()
579 if (atomic_read(&ctrl->stats.hw_q_depth) == 0) rsxx_dma_done()
580 del_timer_sync(&ctrl->activity_timer); rsxx_dma_done()
582 spin_lock_irqsave(&ctrl->card->irq_lock, flags); rsxx_dma_done()
583 rsxx_enable_ier(ctrl->card, CR_INTR_DMA(ctrl->id)); rsxx_dma_done()
584 spin_unlock_irqrestore(&ctrl->card->irq_lock, flags); rsxx_dma_done()
586 spin_lock_bh(&ctrl->queue_lock); rsxx_dma_done()
587 if (ctrl->stats.sw_q_depth) rsxx_dma_done()
588 queue_work(ctrl->issue_wq, &ctrl->issue_dma_work); rsxx_dma_done()
589 spin_unlock_bh(&ctrl->queue_lock); rsxx_dma_done()
594 struct rsxx_dma_ctrl *ctrl; rsxx_schedule_issue() local
596 ctrl = container_of(work, struct rsxx_dma_ctrl, issue_dma_work); rsxx_schedule_issue()
598 mutex_lock(&ctrl->work_lock); rsxx_schedule_issue()
599 rsxx_issue_dmas(ctrl); rsxx_schedule_issue()
600 mutex_unlock(&ctrl->work_lock); rsxx_schedule_issue()
605 struct rsxx_dma_ctrl *ctrl; rsxx_schedule_done() local
607 ctrl = container_of(work, struct rsxx_dma_ctrl, dma_done_work); rsxx_schedule_done()
609 mutex_lock(&ctrl->work_lock); rsxx_schedule_done()
610 rsxx_dma_done(ctrl); rsxx_schedule_done()
611 mutex_unlock(&ctrl->work_lock); rsxx_schedule_done()
756 spin_lock_bh(&card->ctrl[i].queue_lock);
757 card->ctrl[i].stats.sw_q_depth += dma_cnt[i];
758 list_splice_tail(&dma_list[i], &card->ctrl[i].queue);
759 spin_unlock_bh(&card->ctrl[i].queue_lock);
761 queue_work(card->ctrl[i].issue_wq,
762 &card->ctrl[i].issue_dma_work);
770 rsxx_cleanup_dma_queue(&card->ctrl[i], &dma_list[i],
778 int rsxx_hw_buffers_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl) rsxx_hw_buffers_init() argument
780 ctrl->status.buf = pci_alloc_consistent(dev, STATUS_BUFFER_SIZE8, rsxx_hw_buffers_init()
781 &ctrl->status.dma_addr); rsxx_hw_buffers_init()
782 ctrl->cmd.buf = pci_alloc_consistent(dev, COMMAND_BUFFER_SIZE8, rsxx_hw_buffers_init()
783 &ctrl->cmd.dma_addr); rsxx_hw_buffers_init()
784 if (ctrl->status.buf == NULL || ctrl->cmd.buf == NULL) rsxx_hw_buffers_init()
787 memset(ctrl->status.buf, 0xac, STATUS_BUFFER_SIZE8); rsxx_hw_buffers_init()
788 iowrite32(lower_32_bits(ctrl->status.dma_addr), rsxx_hw_buffers_init()
789 ctrl->regmap + SB_ADD_LO); rsxx_hw_buffers_init()
790 iowrite32(upper_32_bits(ctrl->status.dma_addr), rsxx_hw_buffers_init()
791 ctrl->regmap + SB_ADD_HI); rsxx_hw_buffers_init()
793 memset(ctrl->cmd.buf, 0x83, COMMAND_BUFFER_SIZE8); rsxx_hw_buffers_init()
794 iowrite32(lower_32_bits(ctrl->cmd.dma_addr), ctrl->regmap + CB_ADD_LO); rsxx_hw_buffers_init()
795 iowrite32(upper_32_bits(ctrl->cmd.dma_addr), ctrl->regmap + CB_ADD_HI); rsxx_hw_buffers_init()
797 ctrl->status.idx = ioread32(ctrl->regmap + HW_STATUS_CNT); rsxx_hw_buffers_init()
798 if (ctrl->status.idx > RSXX_MAX_OUTSTANDING_CMDS) { rsxx_hw_buffers_init()
800 ctrl->status.idx); rsxx_hw_buffers_init()
803 iowrite32(ctrl->status.idx, ctrl->regmap + HW_STATUS_CNT); rsxx_hw_buffers_init()
804 iowrite32(ctrl->status.idx, ctrl->regmap + SW_STATUS_CNT); rsxx_hw_buffers_init()
806 ctrl->cmd.idx = ioread32(ctrl->regmap + HW_CMD_IDX); rsxx_hw_buffers_init()
807 if (ctrl->cmd.idx > RSXX_MAX_OUTSTANDING_CMDS) { rsxx_hw_buffers_init()
809 ctrl->status.idx); rsxx_hw_buffers_init()
812 iowrite32(ctrl->cmd.idx, ctrl->regmap + HW_CMD_IDX); rsxx_hw_buffers_init()
813 iowrite32(ctrl->cmd.idx, ctrl->regmap + SW_CMD_IDX); rsxx_hw_buffers_init()
819 struct rsxx_dma_ctrl *ctrl) rsxx_dma_ctrl_init()
824 memset(&ctrl->stats, 0, sizeof(ctrl->stats)); rsxx_dma_ctrl_init()
826 ctrl->trackers = vmalloc(DMA_TRACKER_LIST_SIZE8); rsxx_dma_ctrl_init()
827 if (!ctrl->trackers) rsxx_dma_ctrl_init()
830 ctrl->trackers->head = 0; rsxx_dma_ctrl_init()
832 ctrl->trackers->list[i].next_tag = i + 1; rsxx_dma_ctrl_init()
833 ctrl->trackers->list[i].dma = NULL; rsxx_dma_ctrl_init()
835 ctrl->trackers->list[RSXX_MAX_OUTSTANDING_CMDS-1].next_tag = -1; rsxx_dma_ctrl_init()
836 spin_lock_init(&ctrl->trackers->lock); rsxx_dma_ctrl_init()
838 spin_lock_init(&ctrl->queue_lock); rsxx_dma_ctrl_init()
839 mutex_init(&ctrl->work_lock); rsxx_dma_ctrl_init()
840 INIT_LIST_HEAD(&ctrl->queue); rsxx_dma_ctrl_init()
842 setup_timer(&ctrl->activity_timer, dma_engine_stalled, rsxx_dma_ctrl_init()
843 (unsigned long)ctrl); rsxx_dma_ctrl_init()
845 ctrl->issue_wq = alloc_ordered_workqueue(DRIVER_NAME"_issue", 0); rsxx_dma_ctrl_init()
846 if (!ctrl->issue_wq) rsxx_dma_ctrl_init()
849 ctrl->done_wq = alloc_ordered_workqueue(DRIVER_NAME"_done", 0); rsxx_dma_ctrl_init()
850 if (!ctrl->done_wq) rsxx_dma_ctrl_init()
853 INIT_WORK(&ctrl->issue_dma_work, rsxx_schedule_issue); rsxx_dma_ctrl_init()
854 INIT_WORK(&ctrl->dma_done_work, rsxx_schedule_done); rsxx_dma_ctrl_init()
856 st = rsxx_hw_buffers_init(dev, ctrl); rsxx_dma_ctrl_init()
918 card->ctrl[i].regmap = card->regmap + (i * 4096); rsxx_dma_setup()
927 st = rsxx_dma_ctrl_init(card->dev, &card->ctrl[i]); rsxx_dma_setup()
931 card->ctrl[i].card = card; rsxx_dma_setup()
932 card->ctrl[i].id = i; rsxx_dma_setup()
951 struct rsxx_dma_ctrl *ctrl = &card->ctrl[i]; rsxx_dma_setup() local
953 if (ctrl->issue_wq) { rsxx_dma_setup()
954 destroy_workqueue(ctrl->issue_wq); rsxx_dma_setup()
955 ctrl->issue_wq = NULL; rsxx_dma_setup()
958 if (ctrl->done_wq) { rsxx_dma_setup()
959 destroy_workqueue(ctrl->done_wq); rsxx_dma_setup()
960 ctrl->done_wq = NULL; rsxx_dma_setup()
963 if (ctrl->trackers) rsxx_dma_setup()
964 vfree(ctrl->trackers); rsxx_dma_setup()
966 if (ctrl->status.buf) rsxx_dma_setup()
968 ctrl->status.buf, rsxx_dma_setup()
969 ctrl->status.dma_addr); rsxx_dma_setup()
970 if (ctrl->cmd.buf) rsxx_dma_setup()
972 ctrl->cmd.buf, ctrl->cmd.dma_addr); rsxx_dma_setup()
978 int rsxx_dma_cancel(struct rsxx_dma_ctrl *ctrl) rsxx_dma_cancel() argument
986 dma = get_tracker_dma(ctrl->trackers, i); rsxx_dma_cancel()
988 atomic_dec(&ctrl->stats.hw_q_depth); rsxx_dma_cancel()
989 rsxx_complete_dma(ctrl, dma, DMA_CANCELLED); rsxx_dma_cancel()
990 push_tracker(ctrl->trackers, i); rsxx_dma_cancel()
1000 struct rsxx_dma_ctrl *ctrl; rsxx_dma_destroy() local
1004 ctrl = &card->ctrl[i]; rsxx_dma_destroy()
1006 if (ctrl->issue_wq) { rsxx_dma_destroy()
1007 destroy_workqueue(ctrl->issue_wq); rsxx_dma_destroy()
1008 ctrl->issue_wq = NULL; rsxx_dma_destroy()
1011 if (ctrl->done_wq) { rsxx_dma_destroy()
1012 destroy_workqueue(ctrl->done_wq); rsxx_dma_destroy()
1013 ctrl->done_wq = NULL; rsxx_dma_destroy()
1016 if (timer_pending(&ctrl->activity_timer)) rsxx_dma_destroy()
1017 del_timer_sync(&ctrl->activity_timer); rsxx_dma_destroy()
1020 spin_lock_bh(&ctrl->queue_lock); rsxx_dma_destroy()
1021 rsxx_cleanup_dma_queue(ctrl, &ctrl->queue, COMPLETE_DMA); rsxx_dma_destroy()
1022 spin_unlock_bh(&ctrl->queue_lock); rsxx_dma_destroy()
1024 rsxx_dma_cancel(ctrl); rsxx_dma_destroy()
1026 vfree(ctrl->trackers); rsxx_dma_destroy()
1029 ctrl->status.buf, ctrl->status.dma_addr); rsxx_dma_destroy()
1031 ctrl->cmd.buf, ctrl->cmd.dma_addr); rsxx_dma_destroy()
1052 dma = get_tracker_dma(card->ctrl[i].trackers, j); rsxx_eeh_save_issued_dmas()
1057 card->ctrl[i].stats.writes_issued--; rsxx_eeh_save_issued_dmas()
1059 card->ctrl[i].stats.discards_issued--; rsxx_eeh_save_issued_dmas()
1061 card->ctrl[i].stats.reads_issued--; rsxx_eeh_save_issued_dmas()
1072 push_tracker(card->ctrl[i].trackers, j); rsxx_eeh_save_issued_dmas()
1076 spin_lock_bh(&card->ctrl[i].queue_lock); rsxx_eeh_save_issued_dmas()
1077 list_splice(&issued_dmas[i], &card->ctrl[i].queue); rsxx_eeh_save_issued_dmas()
1079 atomic_sub(cnt, &card->ctrl[i].stats.hw_q_depth); rsxx_eeh_save_issued_dmas()
1080 card->ctrl[i].stats.sw_q_depth += cnt; rsxx_eeh_save_issued_dmas()
1081 card->ctrl[i].e_cnt = 0; rsxx_eeh_save_issued_dmas()
1082 spin_unlock_bh(&card->ctrl[i].queue_lock); rsxx_eeh_save_issued_dmas()
818 rsxx_dma_ctrl_init(struct pci_dev *dev, struct rsxx_dma_ctrl *ctrl) rsxx_dma_ctrl_init() argument
|
| H A D | core.c | 134 i, card->ctrl[i].stats.crc_errors); rsxx_attr_stats_show()
136 i, card->ctrl[i].stats.hard_errors); rsxx_attr_stats_show()
138 i, card->ctrl[i].stats.soft_errors); rsxx_attr_stats_show()
140 i, card->ctrl[i].stats.writes_issued); rsxx_attr_stats_show()
142 i, card->ctrl[i].stats.writes_failed); rsxx_attr_stats_show()
144 i, card->ctrl[i].stats.reads_issued); rsxx_attr_stats_show()
146 i, card->ctrl[i].stats.reads_failed); rsxx_attr_stats_show()
148 i, card->ctrl[i].stats.reads_retried); rsxx_attr_stats_show()
150 i, card->ctrl[i].stats.discards_issued); rsxx_attr_stats_show()
152 i, card->ctrl[i].stats.discards_failed); rsxx_attr_stats_show()
154 i, card->ctrl[i].stats.dma_sw_err); rsxx_attr_stats_show()
156 i, card->ctrl[i].stats.dma_hw_fault); rsxx_attr_stats_show()
158 i, card->ctrl[i].stats.dma_cancelled); rsxx_attr_stats_show()
160 i, card->ctrl[i].stats.sw_q_depth); rsxx_attr_stats_show()
162 i, atomic_read(&card->ctrl[i].stats.hw_q_depth)); rsxx_attr_stats_show()
386 queue_work(card->ctrl[i].done_wq, rsxx_isr()
387 &card->ctrl[i].dma_done_work); rsxx_isr()
581 if (card->ctrl[i].status.buf) rsxx_eeh_frozen()
583 card->ctrl[i].status.buf, rsxx_eeh_frozen()
584 card->ctrl[i].status.dma_addr); rsxx_eeh_frozen()
585 if (card->ctrl[i].cmd.buf) rsxx_eeh_frozen()
587 card->ctrl[i].cmd.buf, rsxx_eeh_frozen()
588 card->ctrl[i].cmd.dma_addr); rsxx_eeh_frozen()
606 spin_lock_bh(&card->ctrl[i].queue_lock); rsxx_eeh_failure()
607 cnt = rsxx_cleanup_dma_queue(&card->ctrl[i], rsxx_eeh_failure()
608 &card->ctrl[i].queue, rsxx_eeh_failure()
610 spin_unlock_bh(&card->ctrl[i].queue_lock); rsxx_eeh_failure()
612 cnt += rsxx_dma_cancel(&card->ctrl[i]); rsxx_eeh_failure()
617 cnt, card->ctrl[i].id); rsxx_eeh_failure()
690 st = rsxx_hw_buffers_init(dev, &card->ctrl[i]); rsxx_slot_reset()
713 spin_lock(&card->ctrl[i].queue_lock); rsxx_slot_reset()
714 if (list_empty(&card->ctrl[i].queue)) { rsxx_slot_reset()
715 spin_unlock(&card->ctrl[i].queue_lock); rsxx_slot_reset()
718 spin_unlock(&card->ctrl[i].queue_lock); rsxx_slot_reset()
720 queue_work(card->ctrl[i].issue_wq, rsxx_slot_reset()
721 &card->ctrl[i].issue_dma_work); rsxx_slot_reset()
730 if (card->ctrl[i].status.buf) rsxx_slot_reset()
733 card->ctrl[i].status.buf, rsxx_slot_reset()
734 card->ctrl[i].status.dma_addr); rsxx_slot_reset()
735 if (card->ctrl[i].cmd.buf) rsxx_slot_reset()
738 card->ctrl[i].cmd.buf, rsxx_slot_reset()
739 card->ctrl[i].cmd.dma_addr); rsxx_slot_reset()
879 card->ctrl = kzalloc(card->n_targets * sizeof(*card->ctrl), GFP_KERNEL); rsxx_pci_probe()
880 if (!card->ctrl) { rsxx_pci_probe()
|
| /linux-4.1.27/arch/cris/arch-v32/mm/ |
| H A D | l2cache.c | 14 reg_l2cache_rw_ctrl ctrl = {0}; l2cache_init() local
17 ctrl.csize = L2CACHE_SIZE; l2cache_init()
18 ctrl.cbase = L2CACHE_SIZE / 4 + (L2CACHE_SIZE % 4 ? 1 : 0); l2cache_init()
19 REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl); l2cache_init()
|
| /linux-4.1.27/drivers/net/phy/ |
| H A D | mdio-bitbang.c | 47 static void mdiobb_send_bit(struct mdiobb_ctrl *ctrl, int val) mdiobb_send_bit() argument
49 const struct mdiobb_ops *ops = ctrl->ops; mdiobb_send_bit()
51 ops->set_mdio_data(ctrl, val); mdiobb_send_bit()
53 ops->set_mdc(ctrl, 1); mdiobb_send_bit()
55 ops->set_mdc(ctrl, 0); mdiobb_send_bit()
59 static int mdiobb_get_bit(struct mdiobb_ctrl *ctrl) mdiobb_get_bit() argument
61 const struct mdiobb_ops *ops = ctrl->ops; mdiobb_get_bit()
64 ops->set_mdc(ctrl, 1); mdiobb_get_bit()
66 ops->set_mdc(ctrl, 0); mdiobb_get_bit()
68 return ops->get_mdio_data(ctrl); mdiobb_get_bit()
72 static void mdiobb_send_num(struct mdiobb_ctrl *ctrl, u16 val, int bits) mdiobb_send_num() argument
77 mdiobb_send_bit(ctrl, (val >> i) & 1); mdiobb_send_num()
81 static u16 mdiobb_get_num(struct mdiobb_ctrl *ctrl, int bits) mdiobb_get_num() argument
88 ret |= mdiobb_get_bit(ctrl); mdiobb_get_num()
97 static void mdiobb_cmd(struct mdiobb_ctrl *ctrl, int op, u8 phy, u8 reg) mdiobb_cmd() argument
99 const struct mdiobb_ops *ops = ctrl->ops; mdiobb_cmd()
102 ops->set_mdio_dir(ctrl, 1); mdiobb_cmd()
114 mdiobb_send_bit(ctrl, 1); mdiobb_cmd()
119 mdiobb_send_bit(ctrl, 0); mdiobb_cmd()
121 mdiobb_send_bit(ctrl, 0); mdiobb_cmd()
123 mdiobb_send_bit(ctrl, 1); mdiobb_cmd()
124 mdiobb_send_bit(ctrl, (op >> 1) & 1); mdiobb_cmd()
125 mdiobb_send_bit(ctrl, (op >> 0) & 1); mdiobb_cmd()
127 mdiobb_send_num(ctrl, phy, 5); mdiobb_cmd()
128 mdiobb_send_num(ctrl, reg, 5); mdiobb_cmd()
137 static int mdiobb_cmd_addr(struct mdiobb_ctrl *ctrl, int phy, u32 addr) mdiobb_cmd_addr() argument
141 mdiobb_cmd(ctrl, MDIO_C45_ADDR, phy, dev_addr); mdiobb_cmd_addr()
144 mdiobb_send_bit(ctrl, 1); mdiobb_cmd_addr()
145 mdiobb_send_bit(ctrl, 0); mdiobb_cmd_addr()
147 mdiobb_send_num(ctrl, reg, 16); mdiobb_cmd_addr()
149 ctrl->ops->set_mdio_dir(ctrl, 0); mdiobb_cmd_addr()
150 mdiobb_get_bit(ctrl); mdiobb_cmd_addr()
157 struct mdiobb_ctrl *ctrl = bus->priv; mdiobb_read() local
161 reg = mdiobb_cmd_addr(ctrl, phy, reg); mdiobb_read()
162 mdiobb_cmd(ctrl, MDIO_C45_READ, phy, reg); mdiobb_read()
164 mdiobb_cmd(ctrl, MDIO_READ, phy, reg); mdiobb_read()
166 ctrl->ops->set_mdio_dir(ctrl, 0); mdiobb_read()
169 if (mdiobb_get_bit(ctrl) != 0) { mdiobb_read()
174 mdiobb_get_bit(ctrl); mdiobb_read()
179 ret = mdiobb_get_num(ctrl, 16); mdiobb_read()
180 mdiobb_get_bit(ctrl); mdiobb_read()
186 struct mdiobb_ctrl *ctrl = bus->priv; mdiobb_write() local
189 reg = mdiobb_cmd_addr(ctrl, phy, reg); mdiobb_write()
190 mdiobb_cmd(ctrl, MDIO_C45_WRITE, phy, reg); mdiobb_write()
192 mdiobb_cmd(ctrl, MDIO_WRITE, phy, reg); mdiobb_write()
195 mdiobb_send_bit(ctrl, 1); mdiobb_write()
196 mdiobb_send_bit(ctrl, 0); mdiobb_write()
198 mdiobb_send_num(ctrl, val, 16); mdiobb_write()
200 ctrl->ops->set_mdio_dir(ctrl, 0); mdiobb_write()
201 mdiobb_get_bit(ctrl); mdiobb_write()
207 struct mdiobb_ctrl *ctrl = bus->priv; mdiobb_reset() local
208 if (ctrl->reset) mdiobb_reset()
209 ctrl->reset(bus); mdiobb_reset()
213 struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl) alloc_mdio_bitbang() argument
221 __module_get(ctrl->ops->owner); alloc_mdio_bitbang()
226 bus->priv = ctrl; alloc_mdio_bitbang()
234 struct mdiobb_ctrl *ctrl = bus->priv; free_mdio_bitbang() local
236 module_put(ctrl->ops->owner); free_mdio_bitbang()
|
| H A D | mdio-moxart.c | 40 u32 ctrl = 0; moxart_mdio_read() local
45 ctrl |= MIIRD | ((mii_id << 16) & PHYAD_MASK) | moxart_mdio_read()
48 writel(ctrl, data->base + REG_PHY_CTRL); moxart_mdio_read()
51 ctrl = readl(data->base + REG_PHY_CTRL); moxart_mdio_read()
53 if (!(ctrl & MIIRD)) moxart_mdio_read()
54 return ctrl & MIIRDATA_MASK; moxart_mdio_read()
69 u32 ctrl = 0; moxart_mdio_write() local
74 ctrl |= MIIWR | ((mii_id << 16) & PHYAD_MASK) | moxart_mdio_write()
80 writel(ctrl, data->base + REG_PHY_CTRL); moxart_mdio_write()
83 ctrl = readl(data->base + REG_PHY_CTRL); moxart_mdio_write()
85 if (!(ctrl & MIIWR)) moxart_mdio_write()
|
| H A D | mdio-gpio.c | 34 struct mdiobb_ctrl ctrl; member in struct:mdio_gpio_info
72 static void mdio_dir(struct mdiobb_ctrl *ctrl, int dir) mdio_dir() argument
75 container_of(ctrl, struct mdio_gpio_info, ctrl); mdio_dir()
95 static int mdio_get(struct mdiobb_ctrl *ctrl) mdio_get() argument
98 container_of(ctrl, struct mdio_gpio_info, ctrl); mdio_get()
104 static void mdio_set(struct mdiobb_ctrl *ctrl, int what) mdio_set() argument
107 container_of(ctrl, struct mdio_gpio_info, ctrl); mdio_set()
117 static void mdc_set(struct mdiobb_ctrl *ctrl, int what) mdc_set() argument
120 container_of(ctrl, struct mdio_gpio_info, ctrl); mdc_set()
145 bitbang->ctrl.ops = &mdio_gpio_ops; mdio_gpio_bus_init()
146 bitbang->ctrl.reset = pdata->reset; mdio_gpio_bus_init()
154 new_bus = alloc_mdio_bitbang(&bitbang->ctrl); mdio_gpio_bus_init()
|
| /linux-4.1.27/drivers/scsi/fnic/ |
| H A D | vnic_cq.c | 28 cq->ctrl = NULL; vnic_cq_free()
39 cq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_CQ, index); vnic_cq_alloc()
40 if (!cq->ctrl) { vnic_cq_alloc()
61 writeq(paddr, &cq->ctrl->ring_base); vnic_cq_init()
62 iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size); vnic_cq_init()
63 iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable); vnic_cq_init()
64 iowrite32(color_enable, &cq->ctrl->color_enable); vnic_cq_init()
65 iowrite32(cq_head, &cq->ctrl->cq_head); vnic_cq_init()
66 iowrite32(cq_tail, &cq->ctrl->cq_tail); vnic_cq_init()
67 iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color); vnic_cq_init()
68 iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable); vnic_cq_init()
69 iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable); vnic_cq_init()
70 iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable); vnic_cq_init()
71 iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset); vnic_cq_init()
72 writeq(cq_message_addr, &cq->ctrl->cq_message_addr); vnic_cq_init()
80 iowrite32(0, &cq->ctrl->cq_head); vnic_cq_clean()
81 iowrite32(0, &cq->ctrl->cq_tail); vnic_cq_clean()
82 iowrite32(1, &cq->ctrl->cq_tail_color); vnic_cq_clean()
|
| H A D | vnic_wq_copy.c | 27 iowrite32(1, &wq->ctrl->enable); vnic_wq_copy_enable()
34 iowrite32(0, &wq->ctrl->enable); vnic_wq_copy_disable()
38 if (!(ioread32(&wq->ctrl->running))) vnic_wq_copy_disable()
45 wq->index, ioread32(&wq->ctrl->fetch_index), vnic_wq_copy_disable()
46 ioread32(&wq->ctrl->posted_index)); vnic_wq_copy_disable()
55 BUG_ON(ioread32(&wq->ctrl->enable)); vnic_wq_copy_clean()
62 iowrite32(0, &wq->ctrl->fetch_index); vnic_wq_copy_clean()
63 iowrite32(0, &wq->ctrl->posted_index); vnic_wq_copy_clean()
64 iowrite32(0, &wq->ctrl->error_status); vnic_wq_copy_clean()
75 wq->ctrl = NULL; vnic_wq_copy_free()
87 wq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_WQ, index); vnic_wq_copy_alloc()
88 if (!wq->ctrl) { vnic_wq_copy_alloc()
109 writeq(paddr, &wq->ctrl->ring_base); vnic_wq_copy_init()
110 iowrite32(wq->ring.desc_count, &wq->ctrl->ring_size); vnic_wq_copy_init()
111 iowrite32(0, &wq->ctrl->fetch_index); vnic_wq_copy_init()
112 iowrite32(0, &wq->ctrl->posted_index); vnic_wq_copy_init()
113 iowrite32(cq_index, &wq->ctrl->cq_index); vnic_wq_copy_init()
114 iowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable); vnic_wq_copy_init()
115 iowrite32(error_interrupt_offset, &wq->ctrl->error_interrupt_offset); vnic_wq_copy_init()
|
| H A D | vnic_intr.c | 29 intr->ctrl = NULL; vnic_intr_free()
38 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); vnic_intr_alloc()
39 if (!intr->ctrl) { vnic_intr_alloc()
40 printk(KERN_ERR "Failed to hook INTR[%d].ctrl resource\n", vnic_intr_alloc()
51 iowrite32(coalescing_timer, &intr->ctrl->coalescing_timer); vnic_intr_init()
52 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); vnic_intr_init()
53 iowrite32(mask_on_assertion, &intr->ctrl->mask_on_assertion); vnic_intr_init()
54 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_init()
59 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_clean()
|
| H A D | vnic_rq.c | 82 rq->ctrl = NULL; vnic_rq_free()
93 rq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_RQ, index); vnic_rq_alloc()
94 if (!rq->ctrl) { vnic_rq_alloc()
122 writeq(paddr, &rq->ctrl->ring_base); vnic_rq_init()
123 iowrite32(rq->ring.desc_count, &rq->ctrl->ring_size); vnic_rq_init()
124 iowrite32(cq_index, &rq->ctrl->cq_index); vnic_rq_init()
125 iowrite32(error_interrupt_enable, &rq->ctrl->error_interrupt_enable); vnic_rq_init()
126 iowrite32(error_interrupt_offset, &rq->ctrl->error_interrupt_offset); vnic_rq_init()
127 iowrite32(0, &rq->ctrl->dropped_packet_count); vnic_rq_init()
128 iowrite32(0, &rq->ctrl->error_status); vnic_rq_init()
131 fetch_index = ioread32(&rq->ctrl->fetch_index); vnic_rq_init()
135 iowrite32(fetch_index, &rq->ctrl->posted_index); vnic_rq_init()
142 return ioread32(&rq->ctrl->error_status); vnic_rq_error_status()
147 iowrite32(1, &rq->ctrl->enable); vnic_rq_enable()
154 iowrite32(0, &rq->ctrl->enable); vnic_rq_disable()
158 if (!(ioread32(&rq->ctrl->running))) vnic_rq_disable()
174 BUG_ON(ioread32(&rq->ctrl->enable)); vnic_rq_clean()
187 fetch_index = ioread32(&rq->ctrl->fetch_index); vnic_rq_clean()
191 iowrite32(fetch_index, &rq->ctrl->posted_index); vnic_rq_clean()
|
| H A D | vnic_wq.c | 81 wq->ctrl = NULL; vnic_wq_free()
93 wq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_WQ, index); vnic_wq_alloc()
94 if (!wq->ctrl) { vnic_wq_alloc()
121 writeq(paddr, &wq->ctrl->ring_base); vnic_wq_init()
122 iowrite32(wq->ring.desc_count, &wq->ctrl->ring_size); vnic_wq_init()
123 iowrite32(0, &wq->ctrl->fetch_index); vnic_wq_init()
124 iowrite32(0, &wq->ctrl->posted_index); vnic_wq_init()
125 iowrite32(cq_index, &wq->ctrl->cq_index); vnic_wq_init()
126 iowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable); vnic_wq_init()
127 iowrite32(error_interrupt_offset, &wq->ctrl->error_interrupt_offset); vnic_wq_init()
128 iowrite32(0, &wq->ctrl->error_status); vnic_wq_init()
133 return ioread32(&wq->ctrl->error_status); vnic_wq_error_status()
138 iowrite32(1, &wq->ctrl->enable); vnic_wq_enable()
145 iowrite32(0, &wq->ctrl->enable); vnic_wq_disable()
149 if (!(ioread32(&wq->ctrl->running))) vnic_wq_disable()
164 BUG_ON(ioread32(&wq->ctrl->enable)); vnic_wq_clean()
178 iowrite32(0, &wq->ctrl->fetch_index); vnic_wq_clean()
179 iowrite32(0, &wq->ctrl->posted_index); vnic_wq_clean()
180 iowrite32(0, &wq->ctrl->error_status); vnic_wq_clean()
|
| H A D | vnic_intr.h | 65 struct vnic_intr_ctrl __iomem *ctrl; /* memory-mapped */ member in struct:vnic_intr
70 iowrite32(0, &intr->ctrl->mask); vnic_intr_unmask()
75 iowrite32(1, &intr->ctrl->mask); vnic_intr_mask()
88 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); vnic_intr_return_credits()
93 return ioread32(&intr->ctrl->int_credits); vnic_intr_credits()
|
| /linux-4.1.27/drivers/staging/comedi/drivers/addi-data/ |
| H A D | hwdrv_apci1564.c | 26 unsigned int ctrl; apci1564_timer_insn_config() local
31 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); apci1564_timer_insn_config()
32 ctrl &= 0xfffff9fe; apci1564_timer_insn_config()
34 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG); apci1564_timer_insn_config()
61 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); apci1564_timer_insn_config()
62 ctrl &= 0xfff719e2; apci1564_timer_insn_config()
63 ctrl |= (2 << 13) | 0x10; apci1564_timer_insn_config()
65 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG); apci1564_timer_insn_config()
76 unsigned int ctrl; apci1564_timer_insn_write() local
78 ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG); apci1564_timer_insn_write()
81 ctrl &= 0xfffff9fe; apci1564_timer_insn_write()
84 ctrl &= 0xfffff9ff; apci1564_timer_insn_write()
85 ctrl |= 0x1; apci1564_timer_insn_write()
88 outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG); apci1564_timer_insn_write()
117 unsigned int ctrl; apci1564_counter_insn_config() local
122 ctrl = inl(iobase + ADDI_TCW_CTRL_REG); apci1564_counter_insn_config()
123 ctrl &= 0xfffff9fe; apci1564_counter_insn_config()
125 outl(ctrl, iobase + ADDI_TCW_CTRL_REG); apci1564_counter_insn_config()
138 ctrl &= 0xfffc19e2; apci1564_counter_insn_config()
139 ctrl |= 0x80000 | (data[4] << 16); apci1564_counter_insn_config()
140 outl(ctrl, iobase + ADDI_TCW_CTRL_REG); apci1564_counter_insn_config()
143 ctrl &= 0xfffff9fd; apci1564_counter_insn_config()
144 ctrl |= (data[1] << 1); apci1564_counter_insn_config()
145 outl(ctrl, iobase + ADDI_TCW_CTRL_REG); apci1564_counter_insn_config()
148 ctrl &= 0xfffbf9ff; apci1564_counter_insn_config()
149 ctrl |= (data[6] << 18); apci1564_counter_insn_config()
150 outl(ctrl, iobase + ADDI_TCW_CTRL_REG); apci1564_counter_insn_config()
163 unsigned int ctrl; apci1564_counter_insn_write() local
165 ctrl = inl(iobase + ADDI_TCW_CTRL_REG); apci1564_counter_insn_write()
168 ctrl = 0; apci1564_counter_insn_write()
171 ctrl &= 0xfffff9ff; apci1564_counter_insn_write()
172 ctrl |= 0x1; apci1564_counter_insn_write()
175 ctrl &= 0xfffff9ff; apci1564_counter_insn_write()
176 ctrl |= 0x400; apci1564_counter_insn_write()
179 outl(ctrl, iobase + ADDI_TCW_CTRL_REG); apci1564_counter_insn_write()
|
| /linux-4.1.27/arch/mips/sgi-ip22/ |
| H A D | ip22-nvram.c | 55 static inline void eeprom_cmd(unsigned int *ctrl, unsigned cmd, unsigned reg) eeprom_cmd() argument
63 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); eeprom_cmd()
65 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); eeprom_cmd() local
66 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); eeprom_cmd()
68 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); eeprom_cmd()
73 __raw_writel(__raw_readl(ctrl) & ~EEPROM_DATO, ctrl); eeprom_cmd()
76 unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg) ip22_eeprom_read() argument
81 __raw_writel(__raw_readl(ctrl) & ~EEPROM_EPROT, ctrl); ip22_eeprom_read()
82 eeprom_cs_on(ctrl); ip22_eeprom_read()
83 eeprom_cmd(ctrl, EEPROM_READ, reg); ip22_eeprom_read()
87 __raw_writel(__raw_readl(ctrl) & ~EEPROM_ECLK, ctrl); ip22_eeprom_read()
89 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); ip22_eeprom_read()
92 if (__raw_readl(ctrl) & EEPROM_DATI) ip22_eeprom_read()
96 eeprom_cs_off(ctrl); ip22_eeprom_read()
|
| /linux-4.1.27/mm/ |
| H A D | swap_cgroup.c | 41 struct swap_cgroup_ctrl *ctrl; swap_cgroup_prepare() local
44 ctrl = &swap_cgroup_ctrl[type]; swap_cgroup_prepare()
46 for (idx = 0; idx < ctrl->length; idx++) { swap_cgroup_prepare()
50 ctrl->map[idx] = page; swap_cgroup_prepare()
56 __free_page(ctrl->map[idx]); swap_cgroup_prepare()
65 struct swap_cgroup_ctrl *ctrl; lookup_swap_cgroup() local
69 ctrl = &swap_cgroup_ctrl[swp_type(ent)]; lookup_swap_cgroup()
71 *ctrlp = ctrl; lookup_swap_cgroup()
73 mappage = ctrl->map[offset / SC_PER_PAGE]; lookup_swap_cgroup()
90 struct swap_cgroup_ctrl *ctrl; swap_cgroup_cmpxchg() local
95 sc = lookup_swap_cgroup(ent, &ctrl); swap_cgroup_cmpxchg()
97 spin_lock_irqsave(&ctrl->lock, flags); swap_cgroup_cmpxchg()
103 spin_unlock_irqrestore(&ctrl->lock, flags); swap_cgroup_cmpxchg()
117 struct swap_cgroup_ctrl *ctrl; swap_cgroup_record() local
122 sc = lookup_swap_cgroup(ent, &ctrl); swap_cgroup_record()
124 spin_lock_irqsave(&ctrl->lock, flags); swap_cgroup_record()
127 spin_unlock_irqrestore(&ctrl->lock, flags); swap_cgroup_record()
148 struct swap_cgroup_ctrl *ctrl; swap_cgroup_swapon() local
160 ctrl = &swap_cgroup_ctrl[type]; swap_cgroup_swapon()
162 ctrl->length = length; swap_cgroup_swapon()
163 ctrl->map = array; swap_cgroup_swapon()
164 spin_lock_init(&ctrl->lock); swap_cgroup_swapon()
167 ctrl->map = NULL; swap_cgroup_swapon()
168 ctrl->length = 0; swap_cgroup_swapon()
187 struct swap_cgroup_ctrl *ctrl; swap_cgroup_swapoff() local
193 ctrl = &swap_cgroup_ctrl[type]; swap_cgroup_swapoff()
194 map = ctrl->map; swap_cgroup_swapoff()
195 length = ctrl->length; swap_cgroup_swapoff()
196 ctrl->map = NULL; swap_cgroup_swapoff()
197 ctrl->length = 0; swap_cgroup_swapoff()
|
| /linux-4.1.27/drivers/media/v4l2-core/ |
| H A D | v4l2-ctrls.c | 40 struct v4l2_ctrl *ctrl; member in struct:v4l2_ctrl_helper
1201 static void fill_event(struct v4l2_event *ev, struct v4l2_ctrl *ctrl, u32 changes) fill_event() argument
1205 ev->id = ctrl->id; fill_event()
1206 ev->u.ctrl.changes = changes; fill_event()
1207 ev->u.ctrl.type = ctrl->type; fill_event()
1208 ev->u.ctrl.flags = ctrl->flags; fill_event()
1209 if (ctrl->is_ptr) fill_event()
1210 ev->u.ctrl.value64 = 0; fill_event()
1212 ev->u.ctrl.value64 = *ctrl->p_cur.p_s64; fill_event()
1213 ev->u.ctrl.minimum = ctrl->minimum; fill_event()
1214 ev->u.ctrl.maximum = ctrl->maximum; fill_event()
1215 if (ctrl->type == V4L2_CTRL_TYPE_MENU fill_event()
1216 || ctrl->type == V4L2_CTRL_TYPE_INTEGER_MENU) fill_event()
1217 ev->u.ctrl.step = 1; fill_event()
1219 ev->u.ctrl.step = ctrl->step; fill_event()
1220 ev->u.ctrl.default_value = ctrl->default_value; fill_event()
1223 static void send_event(struct v4l2_fh *fh, struct v4l2_ctrl *ctrl, u32 changes) send_event() argument
1228 if (list_empty(&ctrl->ev_subs)) send_event()
1230 fill_event(&ev, ctrl, changes); send_event()
1232 list_for_each_entry(sev, &ctrl->ev_subs, node) send_event()
1238 static bool std_equal(const struct v4l2_ctrl *ctrl, u32 idx, std_equal() argument
1242 switch (ctrl->type) { std_equal()
1246 idx *= ctrl->elem_size; std_equal()
1258 if (ctrl->is_int) std_equal()
1260 idx *= ctrl->elem_size; std_equal()
1261 return !memcmp(ptr1.p + idx, ptr2.p + idx, ctrl->elem_size); std_equal()
1265 static void std_init(const struct v4l2_ctrl *ctrl, u32 idx, std_init() argument
1268 switch (ctrl->type) { std_init()
1270 idx *= ctrl->elem_size; std_init()
1271 memset(ptr.p_char + idx, ' ', ctrl->minimum); std_init()
1272 ptr.p_char[idx + ctrl->minimum] = '\0'; std_init()
1275 ptr.p_s64[idx] = ctrl->default_value; std_init()
1282 ptr.p_s32[idx] = ctrl->default_value; std_init()
1285 ptr.p_u8[idx] = ctrl->default_value; std_init()
1288 ptr.p_u16[idx] = ctrl->default_value; std_init()
1291 ptr.p_u32[idx] = ctrl->default_value; std_init()
1294 idx *= ctrl->elem_size; std_init()
1295 memset(ptr.p + idx, 0, ctrl->elem_size); std_init()
1300 static void std_log(const struct v4l2_ctrl *ctrl) std_log() argument
1302 union v4l2_ctrl_ptr ptr = ctrl->p_cur; std_log()
1304 if (ctrl->is_array) { std_log()
1307 for (i = 0; i < ctrl->nr_of_dims; i++) std_log()
1308 pr_cont("[%u]", ctrl->dims[i]); std_log()
1312 switch (ctrl->type) { std_log()
1320 pr_cont("%s", ctrl->qmenu[*ptr.p_s32]); std_log()
1323 pr_cont("%lld", ctrl->qmenu_int[*ptr.p_s32]); std_log()
1344 pr_cont("unknown type %d", ctrl->type); std_log()
1354 #define ROUND_TO_RANGE(val, offset_type, ctrl) \
1357 if ((ctrl)->maximum >= 0 && \
1358 val >= (ctrl)->maximum - (s32)((ctrl)->step / 2)) \
1359 val = (ctrl)->maximum; \
1361 val += (s32)((ctrl)->step / 2); \
1363 (ctrl)->minimum, (ctrl)->maximum); \
1364 offset = (val) - (ctrl)->minimum; \
1365 offset = (ctrl)->step * (offset / (u32)(ctrl)->step); \
1366 val = (ctrl)->minimum + offset; \
1371 static int std_validate(const struct v4l2_ctrl *ctrl, u32 idx, std_validate() argument
1378 switch (ctrl->type) { std_validate()
1380 return ROUND_TO_RANGE(ptr.p_s32[idx], u32, ctrl); std_validate()
1387 if (ctrl->maximum >= 0 && val >= ctrl->maximum - (s64)(ctrl->step / 2)) std_validate()
1388 val = ctrl->maximum; std_validate()
1390 val += (s64)(ctrl->step / 2); std_validate()
1391 val = clamp_t(s64, val, ctrl->minimum, ctrl->maximum); std_validate()
1392 offset = val - ctrl->minimum; std_validate()
1393 do_div(offset, ctrl->step); std_validate()
1394 ptr.p_s64[idx] = ctrl->minimum + offset * ctrl->step; std_validate()
1397 return ROUND_TO_RANGE(ptr.p_u8[idx], u8, ctrl); std_validate()
1399 return ROUND_TO_RANGE(ptr.p_u16[idx], u16, ctrl); std_validate()
1401 return ROUND_TO_RANGE(ptr.p_u32[idx], u32, ctrl); std_validate()
1409 if (ptr.p_s32[idx] < ctrl->minimum || ptr.p_s32[idx] > ctrl->maximum) std_validate()
1411 if (ctrl->menu_skip_mask & (1 << ptr.p_s32[idx])) std_validate()
1413 if (ctrl->type == V4L2_CTRL_TYPE_MENU && std_validate()
1414 ctrl->qmenu[ptr.p_s32[idx]][0] == '\0') std_validate()
1419 ptr.p_s32[idx] &= ctrl->maximum; std_validate()
1428 idx *= ctrl->elem_size; std_validate()
1430 if (len < ctrl->minimum) std_validate()
1432 if ((len - (u32)ctrl->minimum) % (u32)ctrl->step) std_validate()
1450 struct v4l2_ctrl *ctrl, ptr_to_user()
1455 if (ctrl->is_ptr && !ctrl->is_string) ptr_to_user()
1459 switch (ctrl->type) { ptr_to_user()
1463 c->size = ctrl->elem_size; ptr_to_user()
1480 struct v4l2_ctrl *ctrl) cur_to_user()
1482 return ptr_to_user(c, ctrl, ctrl->p_cur); cur_to_user()
1487 struct v4l2_ctrl *ctrl) new_to_user()
1489 return ptr_to_user(c, ctrl, ctrl->p_new); new_to_user()
1494 struct v4l2_ctrl *ctrl, user_to_ptr()
1500 ctrl->is_new = 1; user_to_ptr()
1501 if (ctrl->is_ptr && !ctrl->is_string) { user_to_ptr()
1505 if (ret || !ctrl->is_array) user_to_ptr()
1507 for (idx = c->size / ctrl->elem_size; idx < ctrl->elems; idx++) user_to_ptr()
1508 ctrl->type_ops->init(ctrl, idx, ptr); user_to_ptr()
1512 switch (ctrl->type) { user_to_ptr()
1520 if (size > ctrl->maximum + 1) user_to_ptr()
1521 size = ctrl->maximum + 1; user_to_ptr()
1527 /* If the string was longer than ctrl->maximum, user_to_ptr()
1529 if (strlen(ptr.p_char) == ctrl->maximum && last) user_to_ptr()
1542 struct v4l2_ctrl *ctrl) user_to_new()
1544 return user_to_ptr(c, ctrl, ctrl->p_new); user_to_new()
1548 static void ptr_to_ptr(struct v4l2_ctrl *ctrl, ptr_to_ptr() argument
1551 if (ctrl == NULL) ptr_to_ptr()
1553 memcpy(to.p, from.p, ctrl->elems * ctrl->elem_size); ptr_to_ptr()
1557 static void new_to_cur(struct v4l2_fh *fh, struct v4l2_ctrl *ctrl, u32 ch_flags) new_to_cur() argument
1561 if (ctrl == NULL) new_to_cur()
1565 changed = ctrl->has_changed; new_to_cur()
1567 ptr_to_ptr(ctrl, ctrl->p_new, ctrl->p_cur); new_to_cur()
1571 ctrl->flags &= new_to_cur()
1573 if (!is_cur_manual(ctrl->cluster[0])) { new_to_cur()
1574 ctrl->flags |= V4L2_CTRL_FLAG_INACTIVE; new_to_cur()
1575 if (ctrl->cluster[0]->has_volatiles) new_to_cur()
1576 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; new_to_cur()
1583 if (!ctrl->is_new) new_to_cur()
1585 send_event(fh, ctrl, new_to_cur()
1587 if (ctrl->call_notify && changed && ctrl->handler->notify) new_to_cur()
1588 ctrl->handler->notify(ctrl, ctrl->handler->notify_priv); new_to_cur()
1593 static void cur_to_new(struct v4l2_ctrl *ctrl) cur_to_new() argument
1595 if (ctrl == NULL) cur_to_new()
1597 ptr_to_ptr(ctrl, ctrl->p_cur, ctrl->p_new); cur_to_new()
1609 struct v4l2_ctrl *ctrl = master->cluster[i]; cluster_changed() local
1612 if (ctrl == NULL) cluster_changed()
1615 if (ctrl->flags & V4L2_CTRL_FLAG_EXECUTE_ON_WRITE) cluster_changed()
1622 if (ctrl->flags & V4L2_CTRL_FLAG_VOLATILE) { cluster_changed()
1623 ctrl->has_changed = false; cluster_changed()
1627 for (idx = 0; !ctrl_changed && idx < ctrl->elems; idx++) cluster_changed()
1628 ctrl_changed = !ctrl->type_ops->equal(ctrl, idx, cluster_changed()
1629 ctrl->p_cur, ctrl->p_new); cluster_changed()
1630 ctrl->has_changed = ctrl_changed; cluster_changed()
1631 changed |= ctrl->has_changed; cluster_changed()
1676 static int validate_new(const struct v4l2_ctrl *ctrl, union v4l2_ctrl_ptr p_new) validate_new() argument
1681 if (!ctrl->is_ptr) { validate_new()
1682 switch (ctrl->type) { validate_new()
1691 return ctrl->type_ops->validate(ctrl, 0, p_new); validate_new()
1696 for (idx = 0; !err && idx < ctrl->elems; idx++) validate_new()
1697 err = ctrl->type_ops->validate(ctrl, idx, p_new); validate_new()
1703 return list_entry(node, struct v4l2_ctrl_ref, node)->ctrl->id; node2id()
1736 struct v4l2_ctrl *ctrl, *next_ctrl; v4l2_ctrl_handler_free() local
1749 list_for_each_entry_safe(ctrl, next_ctrl, &hdl->ctrls, node) { v4l2_ctrl_handler_free()
1750 list_del(&ctrl->node); v4l2_ctrl_handler_free()
1751 list_for_each_entry_safe(sev, next_sev, &ctrl->ev_subs, node) v4l2_ctrl_handler_free()
1753 kfree(ctrl); v4l2_ctrl_handler_free()
1778 if (V4L2_CTRL_ID2CLASS(ref->ctrl->id) == V4L2_CTRL_CLASS_USER && find_private_ref()
1779 V4L2_CTRL_DRIVER_PRIV(ref->ctrl->id)) { find_private_ref()
1780 if (!ref->ctrl->is_int) find_private_ref()
1804 if (hdl->cached && hdl->cached->ctrl->id == id) find_ref()
1809 while (ref && ref->ctrl->id != id) find_ref()
1836 return ref ? ref->ctrl : NULL; v4l2_ctrl_find()
1842 struct v4l2_ctrl *ctrl) handler_new_ref()
1846 u32 id = ctrl->id; handler_new_ref()
1854 if (ctrl->type < V4L2_CTRL_COMPOUND_TYPES && handler_new_ref()
1865 new_ref->ctrl = ctrl; handler_new_ref()
1866 if (ctrl->handler == hdl) { handler_new_ref()
1868 new_ref->ctrl is basically a cluster array with one handler_new_ref()
1871 ctrl->cluster = &new_ref->ctrl; handler_new_ref()
1872 ctrl->ncontrols = 1; handler_new_ref()
1890 if (ref->ctrl->id < id) handler_new_ref()
1893 if (ref->ctrl->id == id) { handler_new_ref()
1921 struct v4l2_ctrl *ctrl; v4l2_ctrl_new() local
2002 ctrl = kzalloc(sizeof(*ctrl) + sz_extra, GFP_KERNEL); v4l2_ctrl_new()
2003 if (ctrl == NULL) { v4l2_ctrl_new()
2008 INIT_LIST_HEAD(&ctrl->node); v4l2_ctrl_new()
2009 INIT_LIST_HEAD(&ctrl->ev_subs); v4l2_ctrl_new()
2010 ctrl->handler = hdl; v4l2_ctrl_new()
2011 ctrl->ops = ops; v4l2_ctrl_new()
2012 ctrl->type_ops = type_ops ? type_ops : &std_type_ops; v4l2_ctrl_new()
2013 ctrl->id = id; v4l2_ctrl_new()
2014 ctrl->name = name; v4l2_ctrl_new()
2015 ctrl->type = type; v4l2_ctrl_new()
2016 ctrl->flags = flags; v4l2_ctrl_new()
2017 ctrl->minimum = min; v4l2_ctrl_new()
2018 ctrl->maximum = max; v4l2_ctrl_new()
2019 ctrl->step = step; v4l2_ctrl_new()
2020 ctrl->default_value = def; v4l2_ctrl_new()
2021 ctrl->is_string = !is_array && type == V4L2_CTRL_TYPE_STRING; v4l2_ctrl_new()
2022 ctrl->is_ptr = is_array || type >= V4L2_CTRL_COMPOUND_TYPES || ctrl->is_string; v4l2_ctrl_new()
2023 ctrl->is_int = !ctrl->is_ptr && type != V4L2_CTRL_TYPE_INTEGER64; v4l2_ctrl_new()
2024 ctrl->is_array = is_array; v4l2_ctrl_new()
2025 ctrl->elems = elems; v4l2_ctrl_new()
2026 ctrl->nr_of_dims = nr_of_dims; v4l2_ctrl_new()
2028 memcpy(ctrl->dims, dims, nr_of_dims * sizeof(dims[0])); v4l2_ctrl_new()
2029 ctrl->elem_size = elem_size; v4l2_ctrl_new()
2031 ctrl->qmenu = qmenu; v4l2_ctrl_new()
2033 ctrl->qmenu_int = qmenu_int; v4l2_ctrl_new()
2034 ctrl->priv = priv; v4l2_ctrl_new()
2035 ctrl->cur.val = ctrl->val = def; v4l2_ctrl_new()
2036 data = &ctrl[1]; v4l2_ctrl_new()
2038 if (!ctrl->is_int) { v4l2_ctrl_new()
2039 ctrl->p_new.p = data; v4l2_ctrl_new()
2040 ctrl->p_cur.p = data + tot_ctrl_size; v4l2_ctrl_new()
2042 ctrl->p_new.p = &ctrl->val; v4l2_ctrl_new()
2043 ctrl->p_cur.p = &ctrl->cur.val; v4l2_ctrl_new()
2046 ctrl->type_ops->init(ctrl, idx, ctrl->p_cur); v4l2_ctrl_new()
2047 ctrl->type_ops->init(ctrl, idx, ctrl->p_new); v4l2_ctrl_new()
2050 if (handler_new_ref(hdl, ctrl)) { v4l2_ctrl_new()
2051 kfree(ctrl); v4l2_ctrl_new()
2055 list_add_tail(&ctrl->node, &hdl->ctrls); v4l2_ctrl_new()
2057 return ctrl; v4l2_ctrl_new()
2064 struct v4l2_ctrl *ctrl; v4l2_ctrl_new_custom() local
2093 ctrl = v4l2_ctrl_new(hdl, cfg->ops, cfg->type_ops, cfg->id, name, v4l2_ctrl_new_custom()
2098 if (ctrl) v4l2_ctrl_new_custom()
2099 ctrl->is_private = cfg->is_private; v4l2_ctrl_new_custom()
2100 return ctrl; v4l2_ctrl_new_custom()
2218 struct v4l2_ctrl *ctrl) v4l2_ctrl_add_ctrl()
2222 if (ctrl == NULL) { v4l2_ctrl_add_ctrl()
2226 if (ctrl->handler == hdl) v4l2_ctrl_add_ctrl()
2227 return ctrl; v4l2_ctrl_add_ctrl()
2228 return handler_new_ref(hdl, ctrl) ? NULL : ctrl; v4l2_ctrl_add_ctrl()
2235 bool (*filter)(const struct v4l2_ctrl *ctrl)) v4l2_ctrl_add_handler()
2247 struct v4l2_ctrl *ctrl = ref->ctrl; v4l2_ctrl_add_handler() local
2250 if (ctrl->is_private) v4l2_ctrl_add_handler()
2253 if (ctrl->type == V4L2_CTRL_TYPE_CTRL_CLASS) v4l2_ctrl_add_handler()
2256 if (filter && !filter(ctrl)) v4l2_ctrl_add_handler()
2258 ret = handler_new_ref(hdl, ctrl); v4l2_ctrl_add_handler()
2267 bool v4l2_ctrl_radio_filter(const struct v4l2_ctrl *ctrl) v4l2_ctrl_radio_filter() argument
2269 if (V4L2_CTRL_ID2CLASS(ctrl->id) == V4L2_CTRL_CLASS_FM_TX) v4l2_ctrl_radio_filter()
2271 if (V4L2_CTRL_ID2CLASS(ctrl->id) == V4L2_CTRL_CLASS_FM_RX) v4l2_ctrl_radio_filter()
2273 switch (ctrl->id) { v4l2_ctrl_radio_filter()
2337 void v4l2_ctrl_activate(struct v4l2_ctrl *ctrl, bool active) v4l2_ctrl_activate() argument
2343 if (ctrl == NULL) v4l2_ctrl_activate()
2348 old = test_and_set_bit(4, &ctrl->flags); v4l2_ctrl_activate()
2351 old = test_and_clear_bit(4, &ctrl->flags); v4l2_ctrl_activate()
2353 send_event(NULL, ctrl, V4L2_EVENT_CTRL_CH_FLAGS); v4l2_ctrl_activate()
2363 void v4l2_ctrl_grab(struct v4l2_ctrl *ctrl, bool grabbed) v4l2_ctrl_grab() argument
2367 if (ctrl == NULL) v4l2_ctrl_grab()
2370 v4l2_ctrl_lock(ctrl); v4l2_ctrl_grab()
2373 old = test_and_set_bit(1, &ctrl->flags); v4l2_ctrl_grab()
2376 old = test_and_clear_bit(1, &ctrl->flags); v4l2_ctrl_grab()
2378 send_event(NULL, ctrl, V4L2_EVENT_CTRL_CH_FLAGS); v4l2_ctrl_grab()
2379 v4l2_ctrl_unlock(ctrl); v4l2_ctrl_grab()
2384 static void log_ctrl(const struct v4l2_ctrl *ctrl, log_ctrl() argument
2387 if (ctrl->flags & (V4L2_CTRL_FLAG_DISABLED | V4L2_CTRL_FLAG_WRITE_ONLY)) log_ctrl()
2389 if (ctrl->type == V4L2_CTRL_TYPE_CTRL_CLASS) log_ctrl()
2392 pr_info("%s%s%s: ", prefix, colon, ctrl->name); log_ctrl()
2394 ctrl->type_ops->log(ctrl); log_ctrl()
2396 if (ctrl->flags & (V4L2_CTRL_FLAG_INACTIVE | log_ctrl()
2399 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) log_ctrl()
2401 if (ctrl->flags & V4L2_CTRL_FLAG_GRABBED) log_ctrl()
2403 if (ctrl->flags & V4L2_CTRL_FLAG_VOLATILE) log_ctrl()
2413 struct v4l2_ctrl *ctrl; v4l2_ctrl_handler_log_status() local
2425 list_for_each_entry(ctrl, &hdl->ctrls, node) v4l2_ctrl_handler_log_status()
2426 if (!(ctrl->flags & V4L2_CTRL_FLAG_DISABLED)) v4l2_ctrl_handler_log_status()
2427 log_ctrl(ctrl, prefix, colon); v4l2_ctrl_handler_log_status()
2442 struct v4l2_ctrl *ctrl; v4l2_ctrl_handler_setup() local
2448 list_for_each_entry(ctrl, &hdl->ctrls, node) v4l2_ctrl_handler_setup()
2449 ctrl->done = false; v4l2_ctrl_handler_setup()
2451 list_for_each_entry(ctrl, &hdl->ctrls, node) { v4l2_ctrl_handler_setup()
2452 struct v4l2_ctrl *master = ctrl->cluster[0]; v4l2_ctrl_handler_setup()
2457 if (ctrl->done || ctrl->type == V4L2_CTRL_TYPE_BUTTON || v4l2_ctrl_handler_setup()
2458 (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY)) v4l2_ctrl_handler_setup()
2483 struct v4l2_ctrl *ctrl; v4l2_query_ext_ctrl() local
2517 ref->ctrl->type >= V4L2_CTRL_COMPOUND_TYPES; v4l2_query_ext_ctrl()
2518 if (id < ref->ctrl->id && v4l2_query_ext_ctrl()
2531 ref->ctrl->type >= V4L2_CTRL_COMPOUND_TYPES; v4l2_query_ext_ctrl()
2532 if (id < ref->ctrl->id && v4l2_query_ext_ctrl()
2545 ctrl = ref->ctrl; v4l2_query_ext_ctrl()
2550 qc->id = ctrl->id; v4l2_query_ext_ctrl()
2551 strlcpy(qc->name, ctrl->name, sizeof(qc->name)); v4l2_query_ext_ctrl()
2552 qc->flags = ctrl->flags; v4l2_query_ext_ctrl()
2553 qc->type = ctrl->type; v4l2_query_ext_ctrl()
2554 if (ctrl->is_ptr) v4l2_query_ext_ctrl()
2556 qc->elem_size = ctrl->elem_size; v4l2_query_ext_ctrl()
2557 qc->elems = ctrl->elems; v4l2_query_ext_ctrl()
2558 qc->nr_of_dims = ctrl->nr_of_dims; v4l2_query_ext_ctrl()
2559 memcpy(qc->dims, ctrl->dims, qc->nr_of_dims * sizeof(qc->dims[0])); v4l2_query_ext_ctrl()
2560 qc->minimum = ctrl->minimum; v4l2_query_ext_ctrl()
2561 qc->maximum = ctrl->maximum; v4l2_query_ext_ctrl()
2562 qc->default_value = ctrl->default_value; v4l2_query_ext_ctrl()
2563 if (ctrl->type == V4L2_CTRL_TYPE_MENU v4l2_query_ext_ctrl()
2564 || ctrl->type == V4L2_CTRL_TYPE_INTEGER_MENU) v4l2_query_ext_ctrl()
2567 qc->step = ctrl->step; v4l2_query_ext_ctrl()
2620 struct v4l2_ctrl *ctrl; v4l2_querymenu() local
2623 ctrl = v4l2_ctrl_find(hdl, qm->id); v4l2_querymenu()
2624 if (!ctrl) v4l2_querymenu()
2629 switch (ctrl->type) { v4l2_querymenu()
2631 if (ctrl->qmenu == NULL) v4l2_querymenu()
2635 if (ctrl->qmenu_int == NULL) v4l2_querymenu()
2642 if (i < ctrl->minimum || i > ctrl->maximum) v4l2_querymenu()
2646 if (ctrl->menu_skip_mask & (1 << i)) v4l2_querymenu()
2649 if (ctrl->type == V4L2_CTRL_TYPE_MENU) { v4l2_querymenu()
2650 if (ctrl->qmenu[i] == NULL || ctrl->qmenu[i][0] == '\0') v4l2_querymenu()
2652 strlcpy(qm->name, ctrl->qmenu[i], sizeof(qm->name)); v4l2_querymenu()
2654 qm->value = ctrl->qmenu_int[i]; v4l2_querymenu()
2721 struct v4l2_ctrl *ctrl; prepare_ext_ctrls() local
2736 ctrl = ref->ctrl; prepare_ext_ctrls()
2737 if (ctrl->flags & V4L2_CTRL_FLAG_DISABLED) prepare_ext_ctrls()
2740 if (ctrl->cluster[0]->ncontrols > 1) prepare_ext_ctrls()
2742 if (ctrl->cluster[0] != ctrl) prepare_ext_ctrls()
2743 ref = find_ref_lock(hdl, ctrl->cluster[0]->id); prepare_ext_ctrls()
2744 if (ctrl->is_ptr && !ctrl->is_string) { prepare_ext_ctrls()
2745 unsigned tot_size = ctrl->elems * ctrl->elem_size; prepare_ext_ctrls()
2758 h->ctrl = ctrl; prepare_ext_ctrls()
2840 if (helpers[i].ctrl->flags & V4L2_CTRL_FLAG_WRITE_ONLY) v4l2_g_ext_ctrls()
2845 struct v4l2_ctrl *ctrl) = cur_to_user; v4l2_g_ext_ctrls()
2851 master = helpers[i].mref->ctrl; v4l2_g_ext_ctrls()
2872 helpers[idx].ctrl); v4l2_g_ext_ctrls()
2892 static int get_ctrl(struct v4l2_ctrl *ctrl, struct v4l2_ext_control *c) get_ctrl() argument
2894 struct v4l2_ctrl *master = ctrl->cluster[0]; get_ctrl()
2902 if (!ctrl->is_int) get_ctrl()
2905 if (ctrl->flags & V4L2_CTRL_FLAG_WRITE_ONLY) get_ctrl()
2910 if (ctrl->flags & V4L2_CTRL_FLAG_VOLATILE) { get_ctrl()
2914 new_to_user(c, ctrl); get_ctrl()
2916 cur_to_user(c, ctrl); get_ctrl()
2924 struct v4l2_ctrl *ctrl = v4l2_ctrl_find(hdl, control->id); v4l2_g_ctrl() local
2928 if (ctrl == NULL || !ctrl->is_int) v4l2_g_ctrl()
2930 ret = get_ctrl(ctrl, &c); v4l2_g_ctrl()
2942 s32 v4l2_ctrl_g_ctrl(struct v4l2_ctrl *ctrl) v4l2_ctrl_g_ctrl() argument
2947 WARN_ON(!ctrl->is_int); v4l2_ctrl_g_ctrl()
2949 get_ctrl(ctrl, &c); v4l2_ctrl_g_ctrl()
2954 s64 v4l2_ctrl_g_ctrl_int64(struct v4l2_ctrl *ctrl) v4l2_ctrl_g_ctrl_int64() argument
2959 WARN_ON(ctrl->is_ptr || ctrl->type != V4L2_CTRL_TYPE_INTEGER64); v4l2_ctrl_g_ctrl_int64()
2961 get_ctrl(ctrl, &c); v4l2_ctrl_g_ctrl_int64()
2969 Must be called with ctrl->handler->lock held. */ try_or_set_cluster()
2982 struct v4l2_ctrl *ctrl = master->cluster[i]; try_or_set_cluster() local
2984 if (ctrl == NULL) try_or_set_cluster()
2987 if (!ctrl->is_new) { try_or_set_cluster()
2988 cur_to_new(ctrl); try_or_set_cluster()
2993 if (set && (ctrl->flags & V4L2_CTRL_FLAG_GRABBED)) try_or_set_cluster()
3023 struct v4l2_ctrl *ctrl = helpers[i].ctrl; validate_ctrls() local
3028 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) validate_ctrls()
3036 if (set && (ctrl->flags & V4L2_CTRL_FLAG_GRABBED)) validate_ctrls()
3042 if (ctrl->is_ptr) validate_ctrls()
3044 if (ctrl->type == V4L2_CTRL_TYPE_INTEGER64) validate_ctrls()
3048 ret = validate_new(ctrl, p_new); validate_ctrls()
3107 master = helpers[i].mref->ctrl; try_set_ext_ctrls()
3130 if (helpers[tmp_idx].ctrl == master) try_set_ext_ctrls()
3143 struct v4l2_ctrl *ctrl = helpers[idx].ctrl; try_set_ext_ctrls() local
3145 ret = user_to_new(cs->controls + idx, ctrl); try_set_ext_ctrls()
3146 if (!ret && ctrl->is_ptr) try_set_ext_ctrls()
3147 ret = validate_new(ctrl, ctrl->p_new); try_set_ext_ctrls()
3159 helpers[idx].ctrl); try_set_ext_ctrls()
3197 static int set_ctrl(struct v4l2_fh *fh, struct v4l2_ctrl *ctrl, u32 ch_flags) set_ctrl() argument
3199 struct v4l2_ctrl *master = ctrl->cluster[0]; set_ctrl()
3208 ret = validate_new(ctrl, ctrl->p_new); set_ctrl()
3215 if (master->is_auto && master->has_volatiles && ctrl == master && set_ctrl()
3216 !is_cur_manual(master) && ctrl->val == master->manual_mode_value) set_ctrl()
3219 ctrl->is_new = 1; set_ctrl()
3224 static int set_ctrl_lock(struct v4l2_fh *fh, struct v4l2_ctrl *ctrl, set_ctrl_lock() argument
3229 v4l2_ctrl_lock(ctrl); set_ctrl_lock()
3230 user_to_new(c, ctrl); set_ctrl_lock()
3231 ret = set_ctrl(fh, ctrl, 0); set_ctrl_lock()
3233 cur_to_user(c, ctrl); set_ctrl_lock()
3234 v4l2_ctrl_unlock(ctrl); set_ctrl_lock()
3241 struct v4l2_ctrl *ctrl = v4l2_ctrl_find(hdl, control->id); v4l2_s_ctrl() local
3245 if (ctrl == NULL || !ctrl->is_int) v4l2_s_ctrl()
3248 if (ctrl->flags & V4L2_CTRL_FLAG_READ_ONLY) v4l2_s_ctrl()
3252 ret = set_ctrl_lock(fh, ctrl, &c); v4l2_s_ctrl()
3264 int __v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val) __v4l2_ctrl_s_ctrl() argument
3266 lockdep_assert_held(ctrl->handler->lock); __v4l2_ctrl_s_ctrl()
3269 WARN_ON(!ctrl->is_int); __v4l2_ctrl_s_ctrl()
3270 ctrl->val = val; __v4l2_ctrl_s_ctrl()
3271 return set_ctrl(NULL, ctrl, 0); __v4l2_ctrl_s_ctrl()
3275 int __v4l2_ctrl_s_ctrl_int64(struct v4l2_ctrl *ctrl, s64 val) __v4l2_ctrl_s_ctrl_int64() argument
3277 lockdep_assert_held(ctrl->handler->lock); __v4l2_ctrl_s_ctrl_int64()
3280 WARN_ON(ctrl->is_ptr || ctrl->type != V4L2_CTRL_TYPE_INTEGER64); __v4l2_ctrl_s_ctrl_int64()
3281 *ctrl->p_new.p_s64 = val; __v4l2_ctrl_s_ctrl_int64()
3282 return set_ctrl(NULL, ctrl, 0); __v4l2_ctrl_s_ctrl_int64()
3286 int __v4l2_ctrl_s_ctrl_string(struct v4l2_ctrl *ctrl, const char *s) __v4l2_ctrl_s_ctrl_string() argument
3288 lockdep_assert_held(ctrl->handler->lock); __v4l2_ctrl_s_ctrl_string()
3291 WARN_ON(ctrl->type != V4L2_CTRL_TYPE_STRING); __v4l2_ctrl_s_ctrl_string()
3292 strlcpy(ctrl->p_new.p_char, s, ctrl->maximum + 1); __v4l2_ctrl_s_ctrl_string()
3293 return set_ctrl(NULL, ctrl, 0); __v4l2_ctrl_s_ctrl_string()
3297 void v4l2_ctrl_notify(struct v4l2_ctrl *ctrl, v4l2_ctrl_notify_fnc notify, void *priv) v4l2_ctrl_notify() argument
3299 if (ctrl == NULL) v4l2_ctrl_notify()
3302 ctrl->call_notify = 0; v4l2_ctrl_notify()
3305 if (WARN_ON(ctrl->handler->notify && ctrl->handler->notify != notify)) v4l2_ctrl_notify()
3307 ctrl->handler->notify = notify; v4l2_ctrl_notify()
3308 ctrl->handler->notify_priv = priv; v4l2_ctrl_notify()
3309 ctrl->call_notify = 1; v4l2_ctrl_notify()
3313 int __v4l2_ctrl_modify_range(struct v4l2_ctrl *ctrl, __v4l2_ctrl_modify_range() argument
3319 lockdep_assert_held(ctrl->handler->lock); __v4l2_ctrl_modify_range()
3321 switch (ctrl->type) { __v4l2_ctrl_modify_range()
3331 if (ctrl->is_array) __v4l2_ctrl_modify_range()
3333 ret = check_range(ctrl->type, min, max, step, def); __v4l2_ctrl_modify_range()
3340 ctrl->minimum = min; __v4l2_ctrl_modify_range()
3341 ctrl->maximum = max; __v4l2_ctrl_modify_range()
3342 ctrl->step = step; __v4l2_ctrl_modify_range()
3343 ctrl->default_value = def; __v4l2_ctrl_modify_range()
3344 cur_to_new(ctrl); __v4l2_ctrl_modify_range()
3345 if (validate_new(ctrl, ctrl->p_new)) { __v4l2_ctrl_modify_range()
3346 if (ctrl->type == V4L2_CTRL_TYPE_INTEGER64) __v4l2_ctrl_modify_range()
3347 *ctrl->p_new.p_s64 = def; __v4l2_ctrl_modify_range()
3349 *ctrl->p_new.p_s32 = def; __v4l2_ctrl_modify_range()
3352 if (ctrl->type == V4L2_CTRL_TYPE_INTEGER64) __v4l2_ctrl_modify_range()
3353 changed = *ctrl->p_new.p_s64 != *ctrl->p_cur.p_s64; __v4l2_ctrl_modify_range()
3355 changed = *ctrl->p_new.p_s32 != *ctrl->p_cur.p_s32; __v4l2_ctrl_modify_range()
3357 ret = set_ctrl(NULL, ctrl, V4L2_EVENT_CTRL_CH_RANGE); __v4l2_ctrl_modify_range()
3359 send_event(NULL, ctrl, V4L2_EVENT_CTRL_CH_RANGE); __v4l2_ctrl_modify_range()
3366 struct v4l2_ctrl *ctrl = v4l2_ctrl_find(sev->fh->ctrl_handler, sev->id); v4l2_ctrl_add_event() local
3368 if (ctrl == NULL) v4l2_ctrl_add_event()
3371 v4l2_ctrl_lock(ctrl); v4l2_ctrl_add_event()
3372 list_add_tail(&sev->node, &ctrl->ev_subs); v4l2_ctrl_add_event()
3373 if (ctrl->type != V4L2_CTRL_TYPE_CTRL_CLASS && v4l2_ctrl_add_event()
3378 if (!(ctrl->flags & V4L2_CTRL_FLAG_WRITE_ONLY)) v4l2_ctrl_add_event()
3380 fill_event(&ev, ctrl, changes); v4l2_ctrl_add_event()
3386 v4l2_ctrl_unlock(ctrl); v4l2_ctrl_add_event()
3392 struct v4l2_ctrl *ctrl = v4l2_ctrl_find(sev->fh->ctrl_handler, sev->id); v4l2_ctrl_del_event() local
3394 v4l2_ctrl_lock(ctrl); v4l2_ctrl_del_event()
3396 v4l2_ctrl_unlock(ctrl); v4l2_ctrl_del_event()
3401 u32 old_changes = old->u.ctrl.changes; v4l2_ctrl_replace()
3403 old->u.ctrl = new->u.ctrl; v4l2_ctrl_replace()
3404 old->u.ctrl.changes |= old_changes; v4l2_ctrl_replace()
3410 new->u.ctrl.changes |= old->u.ctrl.changes; v4l2_ctrl_merge()
1449 ptr_to_user(struct v4l2_ext_control *c, struct v4l2_ctrl *ctrl, union v4l2_ctrl_ptr ptr) ptr_to_user() argument
1479 cur_to_user(struct v4l2_ext_control *c, struct v4l2_ctrl *ctrl) cur_to_user() argument
1486 new_to_user(struct v4l2_ext_control *c, struct v4l2_ctrl *ctrl) new_to_user() argument
1493 user_to_ptr(struct v4l2_ext_control *c, struct v4l2_ctrl *ctrl, union v4l2_ctrl_ptr ptr) user_to_ptr() argument
1541 user_to_new(struct v4l2_ext_control *c, struct v4l2_ctrl *ctrl) user_to_new() argument
1841 handler_new_ref(struct v4l2_ctrl_handler *hdl, struct v4l2_ctrl *ctrl) handler_new_ref() argument
2217 v4l2_ctrl_add_ctrl(struct v4l2_ctrl_handler *hdl, struct v4l2_ctrl *ctrl) v4l2_ctrl_add_ctrl() argument
2233 v4l2_ctrl_add_handler(struct v4l2_ctrl_handler *hdl, struct v4l2_ctrl_handler *add, bool (*filter)(const struct v4l2_ctrl *ctrl)) v4l2_ctrl_add_handler() argument
|
| /linux-4.1.27/arch/arm/kernel/ |
| H A D | unwind.c | 223 static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl) unwind_get_byte() argument
227 if (ctrl->entries <= 0) { unwind_get_byte()
232 ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; unwind_get_byte()
234 if (ctrl->byte == 0) { unwind_get_byte()
235 ctrl->insn++; unwind_get_byte()
236 ctrl->entries--; unwind_get_byte()
237 ctrl->byte = 3; unwind_get_byte()
239 ctrl->byte--; unwind_get_byte()
245 static int unwind_pop_register(struct unwind_ctrl_block *ctrl, unwind_pop_register() argument
248 if (unlikely(ctrl->check_each_pop)) unwind_pop_register()
249 if (*vsp >= (unsigned long *)ctrl->sp_high) unwind_pop_register()
252 ctrl->vrs[reg] = *(*vsp)++; unwind_pop_register()
257 static int unwind_exec_pop_subset_r4_to_r13(struct unwind_ctrl_block *ctrl, unwind_exec_pop_subset_r4_to_r13() argument
260 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; unwind_exec_pop_subset_r4_to_r13()
266 if (unwind_pop_register(ctrl, &vsp, reg)) unwind_exec_pop_subset_r4_to_r13()
272 ctrl->vrs[SP] = (unsigned long)vsp; unwind_exec_pop_subset_r4_to_r13()
277 static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl, unwind_exec_pop_r4_to_rN() argument
280 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; unwind_exec_pop_r4_to_rN()
285 if (unwind_pop_register(ctrl, &vsp, reg)) unwind_exec_pop_r4_to_rN()
289 if (unwind_pop_register(ctrl, &vsp, 14)) unwind_exec_pop_r4_to_rN()
292 ctrl->vrs[SP] = (unsigned long)vsp; unwind_exec_pop_r4_to_rN()
297 static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, unwind_exec_pop_subset_r0_to_r3() argument
300 unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; unwind_exec_pop_subset_r0_to_r3()
306 if (unwind_pop_register(ctrl, &vsp, reg)) unwind_exec_pop_subset_r0_to_r3()
311 ctrl->vrs[SP] = (unsigned long)vsp; unwind_exec_pop_subset_r0_to_r3()
319 static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) unwind_exec_insn() argument
321 unsigned long insn = unwind_get_byte(ctrl); unwind_exec_insn()
327 ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; unwind_exec_insn()
329 ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; unwind_exec_insn()
333 insn = (insn << 8) | unwind_get_byte(ctrl); unwind_exec_insn()
341 ret = unwind_exec_pop_subset_r4_to_r13(ctrl, mask); unwind_exec_insn()
346 ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; unwind_exec_insn()
348 ret = unwind_exec_pop_r4_to_rN(ctrl, insn); unwind_exec_insn()
352 if (ctrl->vrs[PC] == 0) unwind_exec_insn()
353 ctrl->vrs[PC] = ctrl->vrs[LR]; unwind_exec_insn()
355 ctrl->entries = 0; unwind_exec_insn()
357 unsigned long mask = unwind_get_byte(ctrl); unwind_exec_insn()
365 ret = unwind_exec_pop_subset_r0_to_r3(ctrl, mask); unwind_exec_insn()
369 unsigned long uleb128 = unwind_get_byte(ctrl); unwind_exec_insn()
371 ctrl->vrs[SP] += 0x204 + (uleb128 << 2); unwind_exec_insn()
378 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); unwind_exec_insn()
392 struct unwind_ctrl_block ctrl; unwind_frame() local
396 ctrl.sp_high = ALIGN(low, THREAD_SIZE); unwind_frame()
410 ctrl.vrs[FP] = frame->fp; unwind_frame()
411 ctrl.vrs[SP] = frame->sp; unwind_frame()
412 ctrl.vrs[LR] = frame->lr; unwind_frame()
413 ctrl.vrs[PC] = 0; unwind_frame()
420 ctrl.insn = (unsigned long *)prel31_to_addr(&idx->insn); unwind_frame()
423 ctrl.insn = &idx->insn; unwind_frame()
431 if ((*ctrl.insn & 0xff000000) == 0x80000000) { unwind_frame()
432 ctrl.byte = 2; unwind_frame()
433 ctrl.entries = 1; unwind_frame()
434 } else if ((*ctrl.insn & 0xff000000) == 0x81000000) { unwind_frame()
435 ctrl.byte = 1; unwind_frame()
436 ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16); unwind_frame()
439 *ctrl.insn, ctrl.insn); unwind_frame()
443 ctrl.check_each_pop = 0; unwind_frame()
445 while (ctrl.entries > 0) { unwind_frame()
447 if ((ctrl.sp_high - ctrl.vrs[SP]) < sizeof(ctrl.vrs)) unwind_frame()
448 ctrl.check_each_pop = 1; unwind_frame()
449 urc = unwind_exec_insn(&ctrl); unwind_frame()
452 if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= ctrl.sp_high) unwind_frame()
456 if (ctrl.vrs[PC] == 0) unwind_frame()
457 ctrl.vrs[PC] = ctrl.vrs[LR]; unwind_frame()
460 if (frame->pc == ctrl.vrs[PC]) unwind_frame()
463 frame->fp = ctrl.vrs[FP]; unwind_frame()
464 frame->sp = ctrl.vrs[SP]; unwind_frame()
465 frame->lr = ctrl.vrs[LR]; unwind_frame()
466 frame->pc = ctrl.vrs[PC]; unwind_frame()
|
| H A D | hw_breakpoint.c | 307 struct arch_hw_breakpoint_ctrl ctrl; get_max_wp_len() local
313 memset(&ctrl, 0, sizeof(ctrl)); get_max_wp_len()
314 ctrl.len = ARM_BREAKPOINT_LEN_8; get_max_wp_len()
315 ctrl_reg = encode_ctrl_reg(ctrl); get_max_wp_len()
339 u32 addr, ctrl; arch_install_hw_breakpoint() local
342 ctrl = encode_ctrl_reg(info->ctrl) | 0x1; arch_install_hw_breakpoint()
344 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { arch_install_hw_breakpoint()
375 ctrl = encode_ctrl_reg(info->step_ctrl); arch_install_hw_breakpoint()
376 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) { arch_install_hw_breakpoint()
387 write_wb_reg(ctrl_base + i, ctrl); arch_install_hw_breakpoint()
397 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { arch_uninstall_hw_breakpoint()
425 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE && arch_uninstall_hw_breakpoint()
467 len = get_hbp_len(info->ctrl.len); arch_check_bp_in_kernelspace()
477 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, arch_bp_generic_fields() argument
481 switch (ctrl.type) { arch_bp_generic_fields()
499 switch (ctrl.len) { arch_bp_generic_fields()
529 info->ctrl.type = ARM_BREAKPOINT_EXECUTE; arch_build_bp_info()
532 info->ctrl.type = ARM_BREAKPOINT_LOAD; arch_build_bp_info()
535 info->ctrl.type = ARM_BREAKPOINT_STORE; arch_build_bp_info()
538 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; arch_build_bp_info()
547 info->ctrl.len = ARM_BREAKPOINT_LEN_1; arch_build_bp_info()
550 info->ctrl.len = ARM_BREAKPOINT_LEN_2; arch_build_bp_info()
553 info->ctrl.len = ARM_BREAKPOINT_LEN_4; arch_build_bp_info()
556 info->ctrl.len = ARM_BREAKPOINT_LEN_8; arch_build_bp_info()
557 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE) arch_build_bp_info()
570 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE && arch_build_bp_info()
571 info->ctrl.len != ARM_BREAKPOINT_LEN_2 && arch_build_bp_info()
572 info->ctrl.len != ARM_BREAKPOINT_LEN_4) arch_build_bp_info()
579 info->ctrl.privilege = ARM_BREAKPOINT_USER; arch_build_bp_info()
581 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV; arch_build_bp_info()
584 info->ctrl.enabled = !bp->attr.disabled; arch_build_bp_info()
587 info->ctrl.mismatch = 0; arch_build_bp_info()
611 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) arch_validate_hwbkpt_settings()
621 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) arch_validate_hwbkpt_settings()
625 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) arch_validate_hwbkpt_settings()
633 info->ctrl.len <<= offset; arch_validate_hwbkpt_settings()
659 (info->ctrl.type == ARM_BREAKPOINT_LOAD || arch_validate_hwbkpt_settings()
660 info->ctrl.type == ARM_BREAKPOINT_STORE)) arch_validate_hwbkpt_settings()
679 info->step_ctrl.privilege = info->ctrl.privilege; enable_single_step()
699 struct arch_hw_breakpoint_ctrl ctrl; watchpoint_handler() local
722 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) watchpoint_handler()
734 decode_ctrl_reg(ctrl_reg, &ctrl); watchpoint_handler()
735 if (!((1 << (addr & alignment_mask)) & ctrl.len)) watchpoint_handler()
804 struct arch_hw_breakpoint_ctrl ctrl; breakpoint_handler() local
829 decode_ctrl_reg(ctrl_reg, &ctrl); breakpoint_handler()
830 if ((1 << (addr & 0x3)) & ctrl.len) { breakpoint_handler()
|
| /linux-4.1.27/drivers/spmi/ |
| H A D | spmi.c | 40 struct spmi_controller *ctrl = to_spmi_controller(dev); spmi_ctrl_release() local
41 ida_simple_remove(&ctrl_ida, ctrl->nr); spmi_ctrl_release()
42 kfree(ctrl); spmi_ctrl_release()
67 struct spmi_controller *ctrl = sdev->ctrl; spmi_device_add() local
70 dev_set_name(&sdev->dev, "%d-%02x", ctrl->nr, sdev->usid); spmi_device_add()
97 spmi_cmd(struct spmi_controller *ctrl, u8 opcode, u8 sid) spmi_cmd() argument
99 if (!ctrl || !ctrl->cmd || ctrl->dev.type != &spmi_ctrl_type) spmi_cmd()
102 return ctrl->cmd(ctrl, opcode, sid); spmi_cmd()
105 static inline int spmi_read_cmd(struct spmi_controller *ctrl, u8 opcode, spmi_read_cmd() argument
108 if (!ctrl || !ctrl->read_cmd || ctrl->dev.type != &spmi_ctrl_type) spmi_read_cmd()
111 return ctrl->read_cmd(ctrl, opcode, sid, addr, buf, len); spmi_read_cmd()
114 static inline int spmi_write_cmd(struct spmi_controller *ctrl, u8 opcode, spmi_write_cmd() argument
117 if (!ctrl || !ctrl->write_cmd || ctrl->dev.type != &spmi_ctrl_type) spmi_write_cmd()
120 return ctrl->write_cmd(ctrl, opcode, sid, addr, buf, len); spmi_write_cmd()
137 return spmi_read_cmd(sdev->ctrl, SPMI_CMD_READ, sdev->usid, addr, spmi_register_read()
159 return spmi_read_cmd(sdev->ctrl, SPMI_CMD_EXT_READ, sdev->usid, addr, spmi_ext_register_read()
181 return spmi_read_cmd(sdev->ctrl, SPMI_CMD_EXT_READL, sdev->usid, addr, spmi_ext_register_readl()
200 return spmi_write_cmd(sdev->ctrl, SPMI_CMD_WRITE, sdev->usid, addr, spmi_register_write()
214 return spmi_write_cmd(sdev->ctrl, SPMI_CMD_ZERO_WRITE, sdev->usid, 0, spmi_register_zero_write()
236 return spmi_write_cmd(sdev->ctrl, SPMI_CMD_EXT_WRITE, sdev->usid, addr, spmi_ext_register_write()
258 return spmi_write_cmd(sdev->ctrl, SPMI_CMD_EXT_WRITEL, sdev->usid, spmi_ext_register_writel()
273 return spmi_cmd(sdev->ctrl, SPMI_CMD_RESET, sdev->usid); spmi_command_reset()
285 return spmi_cmd(sdev->ctrl, SPMI_CMD_SLEEP, sdev->usid); spmi_command_sleep()
298 return spmi_cmd(sdev->ctrl, SPMI_CMD_WAKEUP, sdev->usid); spmi_command_wakeup()
310 return spmi_cmd(sdev->ctrl, SPMI_CMD_SHUTDOWN, sdev->usid); spmi_command_shutdown()
360 * @ctrl: associated controller
365 struct spmi_device *spmi_device_alloc(struct spmi_controller *ctrl) spmi_device_alloc() argument
373 sdev->ctrl = ctrl; spmi_device_alloc()
375 sdev->dev.parent = &ctrl->dev; spmi_device_alloc()
395 struct spmi_controller *ctrl; spmi_controller_alloc() local
401 ctrl = kzalloc(sizeof(*ctrl) + size, GFP_KERNEL); spmi_controller_alloc()
402 if (!ctrl) spmi_controller_alloc()
405 device_initialize(&ctrl->dev); spmi_controller_alloc()
406 ctrl->dev.type = &spmi_ctrl_type; spmi_controller_alloc()
407 ctrl->dev.bus = &spmi_bus_type; spmi_controller_alloc()
408 ctrl->dev.parent = parent; spmi_controller_alloc()
409 ctrl->dev.of_node = parent->of_node; spmi_controller_alloc()
410 spmi_controller_set_drvdata(ctrl, &ctrl[1]); spmi_controller_alloc()
416 spmi_controller_put(ctrl); spmi_controller_alloc()
420 ctrl->nr = id; spmi_controller_alloc()
421 dev_set_name(&ctrl->dev, "spmi-%d", id); spmi_controller_alloc()
423 dev_dbg(&ctrl->dev, "allocated controller 0x%p id %d\n", ctrl, id); spmi_controller_alloc()
424 return ctrl; spmi_controller_alloc()
428 static void of_spmi_register_devices(struct spmi_controller *ctrl) of_spmi_register_devices() argument
433 if (!ctrl->dev.of_node) of_spmi_register_devices()
436 for_each_available_child_of_node(ctrl->dev.of_node, node) { of_spmi_register_devices()
440 dev_dbg(&ctrl->dev, "adding child %s\n", node->full_name); of_spmi_register_devices()
444 dev_err(&ctrl->dev, of_spmi_register_devices()
451 dev_err(&ctrl->dev, of_spmi_register_devices()
458 dev_err(&ctrl->dev, of_spmi_register_devices()
464 dev_dbg(&ctrl->dev, "read usid %02x\n", reg[0]); of_spmi_register_devices()
466 sdev = spmi_device_alloc(ctrl); of_spmi_register_devices()
484 * @ctrl: controller to be registered.
489 int spmi_controller_add(struct spmi_controller *ctrl) spmi_controller_add() argument
497 ret = device_add(&ctrl->dev); spmi_controller_add()
502 of_spmi_register_devices(ctrl); spmi_controller_add()
504 dev_dbg(&ctrl->dev, "spmi-%d registered: dev:%p\n", spmi_controller_add()
505 ctrl->nr, &ctrl->dev); spmi_controller_add()
522 * @ctrl: controller to remove
527 void spmi_controller_remove(struct spmi_controller *ctrl) spmi_controller_remove() argument
531 if (!ctrl) spmi_controller_remove()
534 dummy = device_for_each_child(&ctrl->dev, NULL, spmi_controller_remove()
536 device_del(&ctrl->dev); spmi_controller_remove()
|
| H A D | spmi-pmic-arb.c | 163 int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
214 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, pmic_arb_wait_for_done() argument
217 struct spmi_pmic_arb_dev *dev = spmi_controller_get_drvdata(ctrl); pmic_arb_wait_for_done()
227 dev_err(&ctrl->dev, pmic_arb_wait_for_done()
234 dev_err(&ctrl->dev, pmic_arb_wait_for_done()
241 dev_err(&ctrl->dev, pmic_arb_wait_for_done()
252 dev_err(&ctrl->dev, pmic_arb_wait_for_done()
259 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) pmic_arb_non_data_cmd_v1() argument
261 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); pmic_arb_non_data_cmd_v1()
271 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0); pmic_arb_non_data_cmd_v1()
278 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) pmic_arb_non_data_cmd_v2() argument
284 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) pmic_arb_cmd() argument
286 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); pmic_arb_cmd()
288 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); pmic_arb_cmd()
294 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); pmic_arb_cmd()
297 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, pmic_arb_read_cmd() argument
300 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); pmic_arb_read_cmd()
308 dev_err(&ctrl->dev, pmic_arb_read_cmd()
328 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr); pmic_arb_read_cmd()
344 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, pmic_arb_write_cmd() argument
347 struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); pmic_arb_write_cmd()
355 dev_err(&ctrl->dev, pmic_arb_write_cmd()
385 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr); pmic_arb_write_cmd()
784 struct spmi_controller *ctrl; spmi_pmic_arb_probe() local
791 ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa)); spmi_pmic_arb_probe()
792 if (!ctrl) spmi_pmic_arb_probe()
795 pa = spmi_controller_get_drvdata(ctrl); spmi_pmic_arb_probe()
796 pa->spmic = ctrl; spmi_pmic_arb_probe()
799 core = devm_ioremap_resource(&ctrl->dev, res); spmi_pmic_arb_probe()
808 dev_info(&ctrl->dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), spmi_pmic_arb_probe()
824 pa->rd_base = devm_ioremap_resource(&ctrl->dev, res); spmi_pmic_arb_probe()
832 pa->wr_base = devm_ioremap_resource(&ctrl->dev, res); spmi_pmic_arb_probe()
838 pa->ppid_to_chan = devm_kzalloc(&ctrl->dev, spmi_pmic_arb_probe()
859 pa->intr = devm_ioremap_resource(&ctrl->dev, res); spmi_pmic_arb_probe()
866 pa->cnfg = devm_ioremap_resource(&ctrl->dev, res); spmi_pmic_arb_probe()
915 platform_set_drvdata(pdev, ctrl); spmi_pmic_arb_probe()
918 ctrl->cmd = pmic_arb_cmd; spmi_pmic_arb_probe()
919 ctrl->read_cmd = pmic_arb_read_cmd; spmi_pmic_arb_probe()
920 ctrl->write_cmd = pmic_arb_write_cmd; spmi_pmic_arb_probe()
934 err = spmi_controller_add(ctrl); spmi_pmic_arb_probe()
945 spmi_controller_put(ctrl); spmi_pmic_arb_probe()
951 struct spmi_controller *ctrl = platform_get_drvdata(pdev); spmi_pmic_arb_remove() local
952 struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl); spmi_pmic_arb_remove()
953 spmi_controller_remove(ctrl); spmi_pmic_arb_remove()
957 spmi_controller_put(ctrl); spmi_pmic_arb_remove()
|
| /linux-4.1.27/arch/arm/include/asm/ |
| H A D | hw_breakpoint.h | 24 struct arch_hw_breakpoint_ctrl ctrl; member in struct:arch_hw_breakpoint
27 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) encode_ctrl_reg() argument
29 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) | encode_ctrl_reg()
30 (ctrl.privilege << 1) | ctrl.enabled; encode_ctrl_reg()
34 struct arch_hw_breakpoint_ctrl *ctrl) decode_ctrl_reg()
36 ctrl->enabled = reg & 0x1; decode_ctrl_reg()
38 ctrl->privilege = reg & 0x3; decode_ctrl_reg()
40 ctrl->type = reg & 0x3; decode_ctrl_reg()
42 ctrl->len = reg & 0xff; decode_ctrl_reg()
44 ctrl->mismatch = reg & 0x1; decode_ctrl_reg()
118 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
33 decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl *ctrl) decode_ctrl_reg() argument
|
| /linux-4.1.27/drivers/media/usb/uvc/ |
| H A D | uvc_ctrl.c | 747 static inline __u8 *uvc_ctrl_data(struct uvc_control *ctrl, int id) uvc_ctrl_data() argument
749 return ctrl->uvc_data + id * ctrl->info.size; uvc_ctrl_data()
863 struct uvc_control *ctrl; __uvc_find_control() local
871 ctrl = &entity->controls[i]; __uvc_find_control()
872 if (!ctrl->initialized) __uvc_find_control()
875 list_for_each_entry(map, &ctrl->info.mappings, list) { __uvc_find_control()
877 *control = ctrl; __uvc_find_control()
884 *control = ctrl; __uvc_find_control()
894 struct uvc_control *ctrl = NULL; uvc_find_control() local
905 __uvc_find_control(entity, v4l2_id, mapping, &ctrl, next); uvc_find_control()
906 if (ctrl && !next) uvc_find_control()
907 return ctrl; uvc_find_control()
910 if (ctrl == NULL && !next) uvc_find_control()
914 return ctrl; uvc_find_control()
918 struct uvc_control *ctrl) uvc_ctrl_populate_cache()
922 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_DEF) { uvc_ctrl_populate_cache()
923 ret = uvc_query_ctrl(chain->dev, UVC_GET_DEF, ctrl->entity->id, uvc_ctrl_populate_cache()
924 chain->dev->intfnum, ctrl->info.selector, uvc_ctrl_populate_cache()
925 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_DEF), uvc_ctrl_populate_cache()
926 ctrl->info.size); uvc_ctrl_populate_cache()
931 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MIN) { uvc_ctrl_populate_cache()
932 ret = uvc_query_ctrl(chain->dev, UVC_GET_MIN, ctrl->entity->id, uvc_ctrl_populate_cache()
933 chain->dev->intfnum, ctrl->info.selector, uvc_ctrl_populate_cache()
934 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MIN), uvc_ctrl_populate_cache()
935 ctrl->info.size); uvc_ctrl_populate_cache()
939 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MAX) { uvc_ctrl_populate_cache()
940 ret = uvc_query_ctrl(chain->dev, UVC_GET_MAX, ctrl->entity->id, uvc_ctrl_populate_cache()
941 chain->dev->intfnum, ctrl->info.selector, uvc_ctrl_populate_cache()
942 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MAX), uvc_ctrl_populate_cache()
943 ctrl->info.size); uvc_ctrl_populate_cache()
947 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES) { uvc_ctrl_populate_cache()
948 ret = uvc_query_ctrl(chain->dev, UVC_GET_RES, ctrl->entity->id, uvc_ctrl_populate_cache()
949 chain->dev->intfnum, ctrl->info.selector, uvc_ctrl_populate_cache()
950 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES), uvc_ctrl_populate_cache()
951 ctrl->info.size); uvc_ctrl_populate_cache()
953 if (UVC_ENTITY_TYPE(ctrl->entity) != uvc_ctrl_populate_cache()
964 memset(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES), 0, uvc_ctrl_populate_cache()
965 ctrl->info.size); uvc_ctrl_populate_cache()
969 ctrl->cached = 1; uvc_ctrl_populate_cache()
974 struct uvc_control *ctrl, struct uvc_control_mapping *mapping, __uvc_ctrl_get()
981 if ((ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0) __uvc_ctrl_get()
984 if (!ctrl->loaded) { __uvc_ctrl_get()
985 ret = uvc_query_ctrl(chain->dev, UVC_GET_CUR, ctrl->entity->id, __uvc_ctrl_get()
986 chain->dev->intfnum, ctrl->info.selector, __uvc_ctrl_get()
987 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), __uvc_ctrl_get()
988 ctrl->info.size); __uvc_ctrl_get()
992 ctrl->loaded = 1; __uvc_ctrl_get()
996 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT)); __uvc_ctrl_get()
1012 struct uvc_control *ctrl, __uvc_query_v4l2_ctrl()
1027 if (!(ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR)) __uvc_query_v4l2_ctrl()
1029 if (!(ctrl->info.flags & UVC_CTRL_FLAG_SET_CUR)) __uvc_query_v4l2_ctrl()
1033 __uvc_find_control(ctrl->entity, mapping->master_id, __uvc_query_v4l2_ctrl()
1045 if (!ctrl->cached) { __uvc_query_v4l2_ctrl()
1046 int ret = uvc_ctrl_populate_cache(chain, ctrl); __uvc_query_v4l2_ctrl()
1051 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_DEF) { __uvc_query_v4l2_ctrl()
1053 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_DEF)); __uvc_query_v4l2_ctrl()
1088 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MIN) __uvc_query_v4l2_ctrl()
1090 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MIN)); __uvc_query_v4l2_ctrl()
1092 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MAX) __uvc_query_v4l2_ctrl()
1094 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MAX)); __uvc_query_v4l2_ctrl()
1096 if (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES) __uvc_query_v4l2_ctrl()
1098 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES)); __uvc_query_v4l2_ctrl()
1106 struct uvc_control *ctrl; uvc_query_v4l2_ctrl() local
1114 ctrl = uvc_find_control(chain, v4l2_ctrl->id, &mapping); uvc_query_v4l2_ctrl()
1115 if (ctrl == NULL) { uvc_query_v4l2_ctrl()
1120 ret = __uvc_query_v4l2_ctrl(chain, ctrl, mapping, v4l2_ctrl); uvc_query_v4l2_ctrl()
1140 struct uvc_control *ctrl; uvc_query_v4l2_menu() local
1153 ctrl = uvc_find_control(chain, query_menu->id, &mapping); uvc_query_v4l2_menu()
1154 if (ctrl == NULL || mapping->v4l2_type != V4L2_CTRL_TYPE_MENU) { uvc_query_v4l2_menu()
1167 (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES)) { uvc_query_v4l2_menu()
1170 if (!ctrl->cached) { uvc_query_v4l2_menu()
1171 ret = uvc_ctrl_populate_cache(chain, ctrl); uvc_query_v4l2_menu()
1177 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES)); uvc_query_v4l2_menu()
1197 struct uvc_control *ctrl, uvc_ctrl_fill_event()
1203 __uvc_query_v4l2_ctrl(chain, ctrl, mapping, &v4l2_ctrl); uvc_ctrl_fill_event()
1208 ev->u.ctrl.value = value; uvc_ctrl_fill_event()
1209 ev->u.ctrl.changes = changes; uvc_ctrl_fill_event()
1210 ev->u.ctrl.type = v4l2_ctrl.type; uvc_ctrl_fill_event()
1211 ev->u.ctrl.flags = v4l2_ctrl.flags; uvc_ctrl_fill_event()
1212 ev->u.ctrl.minimum = v4l2_ctrl.minimum; uvc_ctrl_fill_event()
1213 ev->u.ctrl.maximum = v4l2_ctrl.maximum; uvc_ctrl_fill_event()
1214 ev->u.ctrl.step = v4l2_ctrl.step; uvc_ctrl_fill_event()
1215 ev->u.ctrl.default_value = v4l2_ctrl.default_value; uvc_ctrl_fill_event()
1219 struct uvc_control *ctrl, struct uvc_control_mapping *mapping, uvc_ctrl_send_event()
1228 uvc_ctrl_fill_event(handle->chain, &ev, ctrl, mapping, value, changes); uvc_ctrl_send_event()
1243 struct uvc_control *ctrl = NULL; uvc_ctrl_send_slave_event() local
1257 __uvc_find_control(master->entity, slave_id, &mapping, &ctrl, 0); uvc_ctrl_send_slave_event()
1258 if (ctrl == NULL) uvc_ctrl_send_slave_event()
1261 if (__uvc_ctrl_get(handle->chain, ctrl, mapping, &val) == 0) uvc_ctrl_send_slave_event()
1264 uvc_ctrl_send_event(handle, ctrl, mapping, val, changes); uvc_ctrl_send_slave_event()
1271 struct uvc_control *ctrl; uvc_ctrl_send_events() local
1277 ctrl = uvc_find_control(handle->chain, xctrls[i].id, &mapping); uvc_ctrl_send_events()
1282 uvc_ctrl_send_slave_event(handle, ctrl, uvc_ctrl_send_events()
1300 uvc_ctrl_send_event(handle, ctrl, mapping, xctrls[i].value, uvc_ctrl_send_events()
1309 struct uvc_control *ctrl; uvc_ctrl_add_event() local
1316 ctrl = uvc_find_control(handle->chain, sev->id, &mapping); uvc_ctrl_add_event()
1317 if (ctrl == NULL) { uvc_ctrl_add_event()
1328 if (__uvc_ctrl_get(handle->chain, ctrl, mapping, &val) == 0) uvc_ctrl_add_event()
1331 uvc_ctrl_fill_event(handle->chain, &ev, ctrl, mapping, val, uvc_ctrl_add_event()
1392 struct uvc_control *ctrl; uvc_ctrl_commit_entity() local
1400 ctrl = &entity->controls[i]; uvc_ctrl_commit_entity()
1401 if (!ctrl->initialized) uvc_ctrl_commit_entity()
1410 if (ctrl->info.flags & UVC_CTRL_FLAG_AUTO_UPDATE || uvc_ctrl_commit_entity()
1411 !(ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR)) uvc_ctrl_commit_entity()
1412 ctrl->loaded = 0; uvc_ctrl_commit_entity()
1414 if (!ctrl->dirty) uvc_ctrl_commit_entity()
1418 ret = uvc_query_ctrl(dev, UVC_SET_CUR, ctrl->entity->id, uvc_ctrl_commit_entity()
1419 dev->intfnum, ctrl->info.selector, uvc_ctrl_commit_entity()
1420 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), uvc_ctrl_commit_entity()
1421 ctrl->info.size); uvc_ctrl_commit_entity()
1426 memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), uvc_ctrl_commit_entity()
1427 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP), uvc_ctrl_commit_entity()
1428 ctrl->info.size); uvc_ctrl_commit_entity()
1430 ctrl->dirty = 0; uvc_ctrl_commit_entity()
1464 struct uvc_control *ctrl; uvc_ctrl_get() local
1467 ctrl = uvc_find_control(chain, xctrl->id, &mapping); uvc_ctrl_get()
1468 if (ctrl == NULL) uvc_ctrl_get()
1471 return __uvc_ctrl_get(chain, ctrl, mapping, &xctrl->value); uvc_ctrl_get()
1477 struct uvc_control *ctrl; uvc_ctrl_set() local
1485 ctrl = uvc_find_control(chain, xctrl->id, &mapping); uvc_ctrl_set()
1486 if (ctrl == NULL) uvc_ctrl_set()
1488 if (!(ctrl->info.flags & UVC_CTRL_FLAG_SET_CUR)) uvc_ctrl_set()
1494 if (!ctrl->cached) { uvc_ctrl_set()
1495 ret = uvc_ctrl_populate_cache(chain, ctrl); uvc_ctrl_set()
1501 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MIN)); uvc_ctrl_set()
1503 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MAX)); uvc_ctrl_set()
1505 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES)); uvc_ctrl_set()
1532 (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES)) { uvc_ctrl_set()
1533 if (!ctrl->cached) { uvc_ctrl_set()
1534 ret = uvc_ctrl_populate_cache(chain, ctrl); uvc_ctrl_set()
1540 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES)); uvc_ctrl_set()
1556 if (!ctrl->loaded && (ctrl->info.size * 8) != mapping->size) { uvc_ctrl_set()
1557 if ((ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0) { uvc_ctrl_set()
1558 memset(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), uvc_ctrl_set()
1559 0, ctrl->info.size); uvc_ctrl_set()
1562 ctrl->entity->id, chain->dev->intfnum, uvc_ctrl_set()
1563 ctrl->info.selector, uvc_ctrl_set()
1564 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), uvc_ctrl_set()
1565 ctrl->info.size); uvc_ctrl_set()
1570 ctrl->loaded = 1; uvc_ctrl_set()
1574 if (!ctrl->dirty) { uvc_ctrl_set()
1575 memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP), uvc_ctrl_set()
1576 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT), uvc_ctrl_set()
1577 ctrl->info.size); uvc_ctrl_set()
1581 uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT)); uvc_ctrl_set()
1583 ctrl->dirty = 1; uvc_ctrl_set()
1584 ctrl->modified = 1; uvc_ctrl_set()
1593 const struct uvc_control *ctrl, struct uvc_control_info *info) uvc_ctrl_fixup_xu_info()
1623 if (fixups[i].entity == ctrl->entity->id && uvc_ctrl_fixup_xu_info()
1635 const struct uvc_control *ctrl, struct uvc_control_info *info) uvc_ctrl_fill_xu_info()
1644 memcpy(info->entity, ctrl->entity->extension.guidExtensionCode, uvc_ctrl_fill_xu_info()
1646 info->index = ctrl->index; uvc_ctrl_fill_xu_info()
1647 info->selector = ctrl->index + 1; uvc_ctrl_fill_xu_info()
1650 ret = uvc_query_ctrl(dev, UVC_GET_LEN, ctrl->entity->id, dev->intfnum, uvc_ctrl_fill_xu_info()
1662 ret = uvc_query_ctrl(dev, UVC_GET_INFO, ctrl->entity->id, dev->intfnum, uvc_ctrl_fill_xu_info()
1680 uvc_ctrl_fixup_xu_info(dev, ctrl, info); uvc_ctrl_fill_xu_info()
1694 static int uvc_ctrl_add_info(struct uvc_device *dev, struct uvc_control *ctrl,
1698 struct uvc_control *ctrl) uvc_ctrl_init_xu_ctrl()
1703 if (ctrl->initialized) uvc_ctrl_init_xu_ctrl()
1706 ret = uvc_ctrl_fill_xu_info(dev, ctrl, &info); uvc_ctrl_init_xu_ctrl()
1710 ret = uvc_ctrl_add_info(dev, ctrl, &info); uvc_ctrl_init_xu_ctrl()
1714 info.selector, dev->udev->devpath, ctrl->entity->id); uvc_ctrl_init_xu_ctrl()
1723 struct uvc_control *ctrl; uvc_xu_ctrl_query() local
1745 ctrl = &entity->controls[i]; uvc_xu_ctrl_query()
1746 if (ctrl->index == xqry->selector - 1) { uvc_xu_ctrl_query()
1761 ret = uvc_ctrl_init_xu_ctrl(chain->dev, ctrl); uvc_xu_ctrl_query()
1769 size = ctrl->info.size; uvc_xu_ctrl_query()
1806 if (reqflags && !(ctrl->info.flags & reqflags)) { uvc_xu_ctrl_query()
1852 struct uvc_control *ctrl; uvc_ctrl_restore_values() local
1861 ctrl = &entity->controls[i]; uvc_ctrl_restore_values()
1863 if (!ctrl->initialized || !ctrl->modified || uvc_ctrl_restore_values()
1864 (ctrl->info.flags & UVC_CTRL_FLAG_RESTORE) == 0) uvc_ctrl_restore_values()
1868 ctrl->info.entity, ctrl->info.index, uvc_ctrl_restore_values()
1869 ctrl->info.selector); uvc_ctrl_restore_values()
1870 ctrl->dirty = 1; uvc_ctrl_restore_values()
1888 static int uvc_ctrl_add_info(struct uvc_device *dev, struct uvc_control *ctrl, uvc_ctrl_add_info() argument
1893 ctrl->info = *info; uvc_ctrl_add_info()
1894 INIT_LIST_HEAD(&ctrl->info.mappings); uvc_ctrl_add_info()
1897 ctrl->uvc_data = kzalloc(ctrl->info.size * UVC_CTRL_DATA_LAST + 1, uvc_ctrl_add_info()
1899 if (ctrl->uvc_data == NULL) { uvc_ctrl_add_info()
1904 ctrl->initialized = 1; uvc_ctrl_add_info()
1907 "entity %u\n", ctrl->info.entity, ctrl->info.selector, uvc_ctrl_add_info()
1908 dev->udev->devpath, ctrl->entity->id); uvc_ctrl_add_info()
1912 kfree(ctrl->uvc_data); uvc_ctrl_add_info()
1920 struct uvc_control *ctrl, const struct uvc_control_mapping *mapping) __uvc_ctrl_add_mapping()
1947 list_add_tail(&map->list, &ctrl->info.mappings); __uvc_ctrl_add_mapping()
1950 map->name, ctrl->info.entity, ctrl->info.selector); __uvc_ctrl_add_mapping()
1961 struct uvc_control *ctrl; uvc_ctrl_add_mapping() local
1981 ctrl = &entity->controls[i]; uvc_ctrl_add_mapping()
1982 if (ctrl->index == mapping->selector - 1) { uvc_ctrl_add_mapping()
1998 ret = uvc_ctrl_init_xu_ctrl(dev, ctrl); uvc_ctrl_add_mapping()
2004 list_for_each_entry(map, &ctrl->info.mappings, list) { uvc_ctrl_add_mapping()
2024 ret = __uvc_ctrl_add_mapping(dev, ctrl, mapping); uvc_ctrl_add_mapping()
2099 static void uvc_ctrl_init_ctrl(struct uvc_device *dev, struct uvc_control *ctrl) uvc_ctrl_init_ctrl() argument
2112 if (UVC_ENTITY_TYPE(ctrl->entity) == UVC_VC_EXTENSION_UNIT) uvc_ctrl_init_ctrl()
2116 if (uvc_entity_match_guid(ctrl->entity, info->entity) && uvc_ctrl_init_ctrl()
2117 ctrl->index == info->index) { uvc_ctrl_init_ctrl()
2118 uvc_ctrl_add_info(dev, ctrl, info); uvc_ctrl_init_ctrl()
2123 if (!ctrl->initialized) uvc_ctrl_init_ctrl()
2127 if (uvc_entity_match_guid(ctrl->entity, mapping->entity) && uvc_ctrl_init_ctrl()
2128 ctrl->info.selector == mapping->selector) uvc_ctrl_init_ctrl()
2129 __uvc_ctrl_add_mapping(dev, ctrl, mapping); uvc_ctrl_init_ctrl()
2143 struct uvc_control *ctrl; uvc_ctrl_init_device() local
2166 entity->controls = kcalloc(ncontrols, sizeof(*ctrl), uvc_ctrl_init_device()
2173 ctrl = entity->controls; uvc_ctrl_init_device()
2178 ctrl->entity = entity; uvc_ctrl_init_device()
2179 ctrl->index = i; uvc_ctrl_init_device()
2181 uvc_ctrl_init_ctrl(dev, ctrl); uvc_ctrl_init_device()
2182 ctrl++; uvc_ctrl_init_device()
2193 struct uvc_control *ctrl) uvc_ctrl_cleanup_mappings()
2197 list_for_each_entry_safe(mapping, nm, &ctrl->info.mappings, list) { uvc_ctrl_cleanup_mappings()
2212 struct uvc_control *ctrl = &entity->controls[i]; uvc_ctrl_cleanup_device() local
2214 if (!ctrl->initialized) uvc_ctrl_cleanup_device()
2217 uvc_ctrl_cleanup_mappings(dev, ctrl); uvc_ctrl_cleanup_device()
2218 kfree(ctrl->uvc_data); uvc_ctrl_cleanup_device()
917 uvc_ctrl_populate_cache(struct uvc_video_chain *chain, struct uvc_control *ctrl) uvc_ctrl_populate_cache() argument
973 __uvc_ctrl_get(struct uvc_video_chain *chain, struct uvc_control *ctrl, struct uvc_control_mapping *mapping, s32 *value) __uvc_ctrl_get() argument
1011 __uvc_query_v4l2_ctrl(struct uvc_video_chain *chain, struct uvc_control *ctrl, struct uvc_control_mapping *mapping, struct v4l2_queryctrl *v4l2_ctrl) __uvc_query_v4l2_ctrl() argument
1195 uvc_ctrl_fill_event(struct uvc_video_chain *chain, struct v4l2_event *ev, struct uvc_control *ctrl, struct uvc_control_mapping *mapping, s32 value, u32 changes) uvc_ctrl_fill_event() argument
1218 uvc_ctrl_send_event(struct uvc_fh *handle, struct uvc_control *ctrl, struct uvc_control_mapping *mapping, s32 value, u32 changes) uvc_ctrl_send_event() argument
1592 uvc_ctrl_fixup_xu_info(struct uvc_device *dev, const struct uvc_control *ctrl, struct uvc_control_info *info) uvc_ctrl_fixup_xu_info() argument
1634 uvc_ctrl_fill_xu_info(struct uvc_device *dev, const struct uvc_control *ctrl, struct uvc_control_info *info) uvc_ctrl_fill_xu_info() argument
1697 uvc_ctrl_init_xu_ctrl(struct uvc_device *dev, struct uvc_control *ctrl) uvc_ctrl_init_xu_ctrl() argument
1919 __uvc_ctrl_add_mapping(struct uvc_device *dev, struct uvc_control *ctrl, const struct uvc_control_mapping *mapping) __uvc_ctrl_add_mapping() argument
2192 uvc_ctrl_cleanup_mappings(struct uvc_device *dev, struct uvc_control *ctrl) uvc_ctrl_cleanup_mappings() argument
|
| /linux-4.1.27/drivers/scsi/be2iscsi/ |
| H A D | be_cmds.c | 109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; be_mcc_notify()
121 if (phba->ctrl.mcc_tag_available) { alloc_mcc_tag()
122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; alloc_mcc_tag()
123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; alloc_mcc_tag()
124 phba->ctrl.mcc_numtag[tag] = 0; alloc_mcc_tag()
127 phba->ctrl.mcc_tag_available--; alloc_mcc_tag()
128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1)) alloc_mcc_tag()
129 phba->ctrl.mcc_alloc_index = 0; alloc_mcc_tag()
131 phba->ctrl.mcc_alloc_index++; alloc_mcc_tag()
159 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; beiscsi_mccq_compl()
162 free_mcc_tag(&phba->ctrl, tag); beiscsi_mccq_compl()
167 spin_lock(&phba->ctrl.mbox_lock); beiscsi_mccq_compl()
168 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_RUNNING; beiscsi_mccq_compl()
169 spin_unlock(&phba->ctrl.mbox_lock); beiscsi_mccq_compl()
173 phba->ctrl.mcc_wait[tag], beiscsi_mccq_compl()
174 phba->ctrl.mcc_numtag[tag], beiscsi_mccq_compl()
181 spin_lock(&phba->ctrl.mbox_lock); beiscsi_mccq_compl()
182 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_TIMEOUT; beiscsi_mccq_compl()
183 spin_unlock(&phba->ctrl.mbox_lock); beiscsi_mccq_compl()
186 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state; beiscsi_mccq_compl()
202 spin_lock(&phba->ctrl.mbox_lock); beiscsi_mccq_compl()
203 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED; beiscsi_mccq_compl()
204 spin_unlock(&phba->ctrl.mbox_lock); beiscsi_mccq_compl()
207 mcc_tag_response = phba->ctrl.mcc_numtag[tag]; beiscsi_mccq_compl()
253 free_mcc_tag(&phba->ctrl, tag); beiscsi_mccq_compl()
258 void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag) free_mcc_tag() argument
260 spin_lock(&ctrl->mbox_lock); free_mcc_tag()
262 ctrl->mcc_tag[ctrl->mcc_free_index] = tag; free_mcc_tag()
263 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1)) free_mcc_tag()
264 ctrl->mcc_free_index = 0; free_mcc_tag()
266 ctrl->mcc_free_index++; free_mcc_tag()
267 ctrl->mcc_tag_available++; free_mcc_tag()
268 spin_unlock(&ctrl->mbox_lock); free_mcc_tag()
308 * @ctrl: Function specific MBX data structure
317 static int be_mcc_compl_process(struct be_ctrl_info *ctrl, be_mcc_compl_process() argument
321 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_mcc_compl_process()
322 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_mcc_compl_process()
352 int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl, be_mcc_compl_process_isr() argument
355 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_mcc_compl_process_isr()
363 /* The ctrl.mcc_numtag[tag] is filled with be_mcc_compl_process_isr()
371 ctrl->mcc_numtag[tag] = 0x80000000; be_mcc_compl_process_isr()
372 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000); be_mcc_compl_process_isr()
373 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8; be_mcc_compl_process_isr()
374 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF); be_mcc_compl_process_isr()
376 if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_RUNNING) { be_mcc_compl_process_isr()
377 wake_up_interruptible(&ctrl->mcc_wait[tag]); be_mcc_compl_process_isr()
378 } else if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_TIMEOUT) { be_mcc_compl_process_isr()
380 tag_mem = &ctrl->ptag_state[tag].tag_mem_state; be_mcc_compl_process_isr()
389 pci_free_consistent(ctrl->pdev, tag_mem->size, be_mcc_compl_process_isr()
393 spin_lock(&phba->ctrl.mbox_lock); be_mcc_compl_process_isr()
394 ctrl->ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED; be_mcc_compl_process_isr()
395 spin_unlock(&phba->ctrl.mbox_lock); be_mcc_compl_process_isr()
398 free_mcc_tag(ctrl, tag); be_mcc_compl_process_isr()
406 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq; be_mcc_compl_get()
467 struct be_ctrl_info *ctrl = &phba->ctrl; beiscsi_process_mcc() local
469 spin_lock_bh(&phba->ctrl.mcc_cq_lock); beiscsi_process_mcc()
506 status = be_mcc_compl_process(ctrl, compl); beiscsi_process_mcc()
507 atomic_dec(&phba->ctrl.mcc_obj.q.used); beiscsi_process_mcc()
514 hwi_ring_cq_db(phba, phba->ctrl.mcc_obj.cq.id, num, 1, 0); beiscsi_process_mcc()
516 spin_unlock_bh(&phba->ctrl.mcc_cq_lock); beiscsi_process_mcc()
542 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0) be_mcc_wait_compl()
575 * @ctrl: Function specific MBX data structure
584 static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl) be_mbox_db_ready_wait() argument
587 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; be_mbox_db_ready_wait()
588 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_mbox_db_ready_wait()
631 * @ctrl: Function specific MBX data structure
640 int be_mbox_notify(struct be_ctrl_info *ctrl) be_mbox_notify() argument
644 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; be_mbox_notify()
645 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; be_mbox_notify()
648 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_mbox_notify()
650 status = be_mbox_db_ready_wait(ctrl); be_mbox_notify()
659 status = be_mbox_db_ready_wait(ctrl); be_mbox_notify()
669 status = be_mbox_db_ready_wait(ctrl); be_mbox_notify()
674 status = be_mcc_compl_process(ctrl, &mbox->compl); be_mbox_notify()
701 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET; be_mbox_notify_wait()
702 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem; be_mbox_notify_wait()
705 struct be_ctrl_info *ctrl = &phba->ctrl; be_mbox_notify_wait() local
707 status = be_mbox_db_ready_wait(ctrl); be_mbox_notify_wait()
717 status = be_mbox_db_ready_wait(ctrl); be_mbox_notify_wait()
726 status = be_mbox_db_ready_wait(ctrl); be_mbox_notify_wait()
732 status = be_mcc_compl_process(ctrl, &mbox->compl); be_mbox_notify_wait()
810 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; wrb_from_mccq()
823 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, beiscsi_cmd_eq_create() argument
826 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); beiscsi_cmd_eq_create()
832 spin_lock(&ctrl->mbox_lock); beiscsi_cmd_eq_create()
843 PCI_FUNC(ctrl->pdev->devfn)); beiscsi_cmd_eq_create()
854 status = be_mbox_notify(ctrl); beiscsi_cmd_eq_create()
859 spin_unlock(&ctrl->mbox_lock); beiscsi_cmd_eq_create()
865 * @ctrl: Pointer to function control structure
873 int be_cmd_fw_initialize(struct be_ctrl_info *ctrl) be_cmd_fw_initialize() argument
875 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_cmd_fw_initialize()
876 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_cmd_fw_initialize()
880 spin_lock(&ctrl->mbox_lock); be_cmd_fw_initialize()
894 status = be_mbox_notify(ctrl); be_cmd_fw_initialize()
899 spin_unlock(&ctrl->mbox_lock); be_cmd_fw_initialize()
905 * @ctrl: Pointer to function control structure
913 int be_cmd_fw_uninit(struct be_ctrl_info *ctrl) be_cmd_fw_uninit() argument
915 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_cmd_fw_uninit()
916 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_cmd_fw_uninit()
920 spin_lock(&ctrl->mbox_lock); be_cmd_fw_uninit()
935 status = be_mbox_notify(ctrl); be_cmd_fw_uninit()
940 spin_unlock(&ctrl->mbox_lock); be_cmd_fw_uninit()
944 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, beiscsi_cmd_cq_create() argument
948 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); beiscsi_cmd_cq_create()
951 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); beiscsi_cmd_cq_create()
956 spin_lock(&ctrl->mbox_lock); beiscsi_cmd_cq_create()
977 PCI_FUNC(ctrl->pdev->devfn)); beiscsi_cmd_cq_create()
997 status = be_mbox_notify(ctrl); beiscsi_cmd_cq_create()
1006 spin_unlock(&ctrl->mbox_lock); beiscsi_cmd_cq_create()
1026 struct be_ctrl_info *ctrl; beiscsi_cmd_mccq_create() local
1030 spin_lock(&phba->ctrl.mbox_lock); beiscsi_cmd_mccq_create()
1031 ctrl = &phba->ctrl; beiscsi_cmd_mccq_create()
1032 wrb = wrb_from_mbox(&ctrl->mbox_mem); beiscsi_cmd_mccq_create()
1061 spin_unlock(&phba->ctrl.mbox_lock); beiscsi_cmd_mccq_create()
1066 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, beiscsi_cmd_q_destroy() argument
1069 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); beiscsi_cmd_q_destroy()
1071 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); beiscsi_cmd_q_destroy()
1079 spin_lock(&ctrl->mbox_lock); beiscsi_cmd_q_destroy()
1109 spin_unlock(&ctrl->mbox_lock); beiscsi_cmd_q_destroy()
1117 status = be_mbox_notify(ctrl); beiscsi_cmd_q_destroy()
1119 spin_unlock(&ctrl->mbox_lock); beiscsi_cmd_q_destroy()
1125 * @ctrl: ptr to ctrl_info
1141 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, be_cmd_create_default_pdu_queue() argument
1147 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_cmd_create_default_pdu_queue()
1150 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_cmd_create_default_pdu_queue()
1154 spin_lock(&ctrl->mbox_lock); be_cmd_create_default_pdu_queue()
1175 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn)); be_cmd_create_default_pdu_queue()
1203 status = be_mbox_notify(ctrl); be_cmd_create_default_pdu_queue()
1226 spin_unlock(&ctrl->mbox_lock); be_cmd_create_default_pdu_queue()
1233 * @ctrl: ptr to ctrl_info
1242 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, be_cmd_wrbq_create() argument
1248 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_cmd_wrbq_create()
1251 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_cmd_wrbq_create()
1254 spin_lock(&ctrl->mbox_lock); be_cmd_wrbq_create()
1271 status = be_mbox_notify(ctrl); be_cmd_wrbq_create()
1285 spin_unlock(&ctrl->mbox_lock); be_cmd_wrbq_create()
1289 int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl, be_cmd_iscsi_post_template_hdr() argument
1292 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_cmd_iscsi_post_template_hdr()
1296 spin_lock(&ctrl->mbox_lock); be_cmd_iscsi_post_template_hdr()
1308 status = be_mbox_notify(ctrl); be_cmd_iscsi_post_template_hdr()
1309 spin_unlock(&ctrl->mbox_lock); be_cmd_iscsi_post_template_hdr()
1313 int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl) be_cmd_iscsi_remove_template_hdr() argument
1315 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_cmd_iscsi_remove_template_hdr()
1319 spin_lock(&ctrl->mbox_lock); be_cmd_iscsi_remove_template_hdr()
1329 status = be_mbox_notify(ctrl); be_cmd_iscsi_remove_template_hdr()
1330 spin_unlock(&ctrl->mbox_lock); be_cmd_iscsi_remove_template_hdr()
1334 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl, be_cmd_iscsi_post_sgl_pages() argument
1338 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); be_cmd_iscsi_post_sgl_pages()
1340 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); be_cmd_iscsi_post_sgl_pages()
1349 spin_lock(&ctrl->mbox_lock); be_cmd_iscsi_post_sgl_pages()
1369 status = be_mbox_notify(ctrl); be_cmd_iscsi_post_sgl_pages()
1378 spin_unlock(&ctrl->mbox_lock); be_cmd_iscsi_post_sgl_pages()
1380 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); be_cmd_iscsi_post_sgl_pages()
1386 struct be_ctrl_info *ctrl = &phba->ctrl; beiscsi_cmd_reset_function() local
1387 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); beiscsi_cmd_reset_function()
1391 spin_lock(&ctrl->mbox_lock); beiscsi_cmd_reset_function()
1399 spin_unlock(&ctrl->mbox_lock); beiscsi_cmd_reset_function()
1419 struct be_ctrl_info *ctrl = &phba->ctrl; be_cmd_set_vlan() local
1421 spin_lock(&ctrl->mbox_lock); be_cmd_set_vlan()
1424 spin_unlock(&ctrl->mbox_lock); be_cmd_set_vlan()
1440 spin_unlock(&ctrl->mbox_lock); be_cmd_set_vlan()
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| H A D | be_mgmt.c | 161 struct be_ctrl_info *ctrl = &phba->ctrl; be_cmd_modify_eq_delay() local
167 spin_lock(&ctrl->mbox_lock); be_cmd_modify_eq_delay()
170 spin_unlock(&ctrl->mbox_lock); be_cmd_modify_eq_delay()
191 spin_unlock(&ctrl->mbox_lock); be_cmd_modify_eq_delay()
209 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_reopen_session() local
218 spin_lock(&ctrl->mbox_lock); mgmt_reopen_session()
221 spin_unlock(&ctrl->mbox_lock); mgmt_reopen_session()
238 spin_unlock(&ctrl->mbox_lock); mgmt_reopen_session()
244 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_get_boot_target() local
253 spin_lock(&ctrl->mbox_lock); mgmt_get_boot_target()
256 spin_unlock(&ctrl->mbox_lock); mgmt_get_boot_target()
269 spin_unlock(&ctrl->mbox_lock); mgmt_get_boot_target()
277 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_get_session_info() local
288 spin_lock(&ctrl->mbox_lock); mgmt_get_session_info()
291 spin_unlock(&ctrl->mbox_lock); mgmt_get_session_info()
314 spin_unlock(&ctrl->mbox_lock); mgmt_get_session_info()
320 * @ctrl: ptr to Ctrl Info
330 int mgmt_get_fw_config(struct be_ctrl_info *ctrl, mgmt_get_fw_config() argument
333 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); mgmt_get_fw_config()
337 spin_lock(&ctrl->mbox_lock); mgmt_get_fw_config()
345 status = be_mbox_notify(ctrl); mgmt_get_fw_config()
418 spin_unlock(&ctrl->mbox_lock); mgmt_get_fw_config()
422 int mgmt_check_supported_fw(struct be_ctrl_info *ctrl, mgmt_check_supported_fw() argument
426 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); mgmt_check_supported_fw()
431 nonemb_cmd.va = pci_alloc_consistent(ctrl->pdev, mgmt_check_supported_fw()
443 spin_lock(&ctrl->mbox_lock); mgmt_check_supported_fw()
451 status = be_mbox_notify(ctrl); mgmt_check_supported_fw()
473 spin_unlock(&ctrl->mbox_lock); mgmt_check_supported_fw()
475 pci_free_consistent(ctrl->pdev, nonemb_cmd.size, mgmt_check_supported_fw()
481 unsigned int mgmt_vendor_specific_fw_cmd(struct be_ctrl_info *ctrl, mgmt_vendor_specific_fw_cmd() argument
504 spin_lock(&ctrl->mbox_lock); mgmt_vendor_specific_fw_cmd()
524 spin_unlock(&ctrl->mbox_lock); mgmt_vendor_specific_fw_cmd()
530 spin_unlock(&ctrl->mbox_lock); mgmt_vendor_specific_fw_cmd()
545 spin_unlock(&ctrl->mbox_lock); mgmt_vendor_specific_fw_cmd()
560 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_epfw_cleanup() local
565 spin_lock(&ctrl->mbox_lock); mgmt_epfw_cleanup()
579 spin_unlock(&ctrl->mbox_lock); mgmt_epfw_cleanup()
589 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_invalidate_icds() local
595 spin_lock(&ctrl->mbox_lock); mgmt_invalidate_icds()
598 spin_unlock(&ctrl->mbox_lock); mgmt_invalidate_icds()
625 spin_unlock(&ctrl->mbox_lock); mgmt_invalidate_icds()
635 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_invalidate_connection() local
640 spin_lock(&ctrl->mbox_lock); mgmt_invalidate_connection()
643 spin_unlock(&ctrl->mbox_lock); mgmt_invalidate_connection()
662 spin_unlock(&ctrl->mbox_lock); mgmt_invalidate_connection()
669 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_upload_connection() local
674 spin_lock(&ctrl->mbox_lock); mgmt_upload_connection()
677 spin_unlock(&ctrl->mbox_lock); mgmt_upload_connection()
690 spin_unlock(&ctrl->mbox_lock); mgmt_upload_connection()
713 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_open_connection() local
735 spin_lock(&ctrl->mbox_lock); mgmt_open_connection()
738 spin_unlock(&ctrl->mbox_lock); mgmt_open_connection()
776 spin_unlock(&ctrl->mbox_lock); mgmt_open_connection()
777 free_mcc_tag(&phba->ctrl, tag); mgmt_open_connection()
805 spin_unlock(&ctrl->mbox_lock); mgmt_open_connection()
811 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_get_all_if_id() local
812 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); mgmt_get_all_if_id()
819 spin_lock(&ctrl->mbox_lock); mgmt_get_all_if_id()
825 status = be_mbox_notify(ctrl); mgmt_get_all_if_id()
832 spin_unlock(&ctrl->mbox_lock); mgmt_get_all_if_id()
849 struct be_ctrl_info *ctrl = &phba->ctrl; mgmt_exec_nonemb_cmd() local
855 spin_lock(&ctrl->mbox_lock); mgmt_exec_nonemb_cmd()
858 spin_unlock(&ctrl->mbox_lock); mgmt_exec_nonemb_cmd()
873 spin_unlock(&ctrl->mbox_lock); mgmt_exec_nonemb_cmd()
895 pci_free_consistent(ctrl->pdev, nonemb_cmd->size, mgmt_exec_nonemb_cmd()
903 cmd->va = pci_zalloc_consistent(phba->ctrl.pdev, size, &cmd->dma); mgmt_alloc_cmd_data()
1198 pci_free_consistent(phba->ctrl.pdev, mgmt_get_if_info()
1217 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, mgmt_get_if_info()
1251 struct be_ctrl_info *ctrl = &phba->ctrl; be_cmd_get_initname() local
1253 spin_lock(&ctrl->mbox_lock); be_cmd_get_initname()
1256 spin_unlock(&ctrl->mbox_lock); be_cmd_get_initname()
1269 spin_unlock(&ctrl->mbox_lock); be_cmd_get_initname()
1278 struct be_ctrl_info *ctrl = &phba->ctrl; be_cmd_get_port_speed() local
1280 spin_lock(&ctrl->mbox_lock); be_cmd_get_port_speed()
1283 spin_unlock(&ctrl->mbox_lock); be_cmd_get_port_speed()
1296 spin_unlock(&ctrl->mbox_lock); be_cmd_get_port_speed()
|
| /linux-4.1.27/net/bluetooth/ |
| H A D | amp.c | 23 void amp_ctrl_get(struct amp_ctrl *ctrl) amp_ctrl_get() argument
25 BT_DBG("ctrl %p orig refcnt %d", ctrl, amp_ctrl_get()
26 atomic_read(&ctrl->kref.refcount)); amp_ctrl_get()
28 kref_get(&ctrl->kref); amp_ctrl_get()
33 struct amp_ctrl *ctrl = container_of(kref, struct amp_ctrl, kref); amp_ctrl_destroy() local
35 BT_DBG("ctrl %p", ctrl); amp_ctrl_destroy()
37 kfree(ctrl->assoc); amp_ctrl_destroy()
38 kfree(ctrl); amp_ctrl_destroy()
41 int amp_ctrl_put(struct amp_ctrl *ctrl) amp_ctrl_put() argument
43 BT_DBG("ctrl %p orig refcnt %d", ctrl, amp_ctrl_put()
44 atomic_read(&ctrl->kref.refcount)); amp_ctrl_put()
46 return kref_put(&ctrl->kref, &_ctrl_destroy); amp_ctrl_put()
51 struct amp_ctrl *ctrl; amp_ctrl_add() local
53 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); amp_ctrl_add()
54 if (!ctrl) amp_ctrl_add()
57 kref_init(&ctrl->kref); amp_ctrl_add()
58 ctrl->id = id; amp_ctrl_add()
61 list_add(&ctrl->list, &mgr->amp_ctrls); amp_ctrl_add()
64 BT_DBG("mgr %p ctrl %p", mgr, ctrl); amp_ctrl_add()
66 return ctrl; amp_ctrl_add()
71 struct amp_ctrl *ctrl, *n; amp_ctrl_list_flush() local
76 list_for_each_entry_safe(ctrl, n, &mgr->amp_ctrls, list) { amp_ctrl_list_flush()
77 list_del(&ctrl->list); amp_ctrl_list_flush()
78 amp_ctrl_put(ctrl); amp_ctrl_list_flush()
85 struct amp_ctrl *ctrl; amp_ctrl_lookup() local
90 list_for_each_entry(ctrl, &mgr->amp_ctrls, list) { amp_ctrl_lookup()
91 if (ctrl->id == id) { amp_ctrl_lookup()
92 amp_ctrl_get(ctrl); amp_ctrl_lookup()
94 return ctrl; amp_ctrl_lookup()
272 struct amp_ctrl *ctrl; amp_write_rem_assoc_frag() local
275 ctrl = amp_ctrl_lookup(mgr, hcon->remote_id); amp_write_rem_assoc_frag()
276 if (!ctrl) amp_write_rem_assoc_frag()
279 if (!ctrl->assoc_rem_len) { amp_write_rem_assoc_frag()
281 ctrl->assoc_rem_len = ctrl->assoc_len; amp_write_rem_assoc_frag()
282 ctrl->assoc_len_so_far = 0; amp_write_rem_assoc_frag()
284 amp_ctrl_put(ctrl); amp_write_rem_assoc_frag()
288 frag_len = min_t(u16, 248, ctrl->assoc_rem_len); amp_write_rem_assoc_frag()
293 amp_ctrl_put(ctrl); amp_write_rem_assoc_frag()
297 BT_DBG("hcon %p ctrl %p frag_len %u assoc_len %u rem_len %u", amp_write_rem_assoc_frag()
298 hcon, ctrl, frag_len, ctrl->assoc_len, ctrl->assoc_rem_len); amp_write_rem_assoc_frag()
301 cp->len_so_far = cpu_to_le16(ctrl->assoc_len_so_far); amp_write_rem_assoc_frag()
302 cp->rem_len = cpu_to_le16(ctrl->assoc_rem_len); amp_write_rem_assoc_frag()
303 memcpy(cp->frag, ctrl->assoc, frag_len); amp_write_rem_assoc_frag()
305 ctrl->assoc_len_so_far += frag_len; amp_write_rem_assoc_frag()
306 ctrl->assoc_rem_len -= frag_len; amp_write_rem_assoc_frag()
308 amp_ctrl_put(ctrl); amp_write_rem_assoc_frag()
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| H A D | a2mp.c | 329 struct amp_ctrl *ctrl; a2mp_getinfo_rsp() local
339 ctrl = amp_ctrl_add(mgr, rsp->id); a2mp_getinfo_rsp()
340 if (!ctrl) a2mp_getinfo_rsp()
400 struct amp_ctrl *ctrl; a2mp_getampassoc_rsp() local
416 ctrl = amp_ctrl_lookup(mgr, rsp->id); a2mp_getampassoc_rsp()
417 if (ctrl) { a2mp_getampassoc_rsp()
422 amp_ctrl_put(ctrl); a2mp_getampassoc_rsp()
426 ctrl->assoc = assoc; a2mp_getampassoc_rsp()
427 ctrl->assoc_len = assoc_len; a2mp_getampassoc_rsp()
428 ctrl->assoc_rem_len = assoc_len; a2mp_getampassoc_rsp()
429 ctrl->assoc_len_so_far = 0; a2mp_getampassoc_rsp()
431 amp_ctrl_put(ctrl); a2mp_getampassoc_rsp()
463 struct amp_ctrl *ctrl; a2mp_createphyslink_req() local
479 ctrl = amp_ctrl_lookup(mgr, rsp.remote_id); a2mp_createphyslink_req()
480 if (!ctrl) { a2mp_createphyslink_req()
481 ctrl = amp_ctrl_add(mgr, rsp.remote_id); a2mp_createphyslink_req()
482 if (ctrl) { a2mp_createphyslink_req()
483 amp_ctrl_get(ctrl); a2mp_createphyslink_req()
490 if (ctrl) { a2mp_createphyslink_req()
496 amp_ctrl_put(ctrl); a2mp_createphyslink_req()
500 ctrl->assoc = assoc; a2mp_createphyslink_req()
501 ctrl->assoc_len = assoc_len; a2mp_createphyslink_req()
502 ctrl->assoc_rem_len = assoc_len; a2mp_createphyslink_req()
503 ctrl->assoc_len_so_far = 0; a2mp_createphyslink_req()
505 amp_ctrl_put(ctrl); a2mp_createphyslink_req()
852 /* Remote AMP ctrl list initialization */ amp_mgr_create()
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| /linux-4.1.27/drivers/net/ethernet/cisco/enic/ |
| H A D | vnic_cq.c | 32 cq->ctrl = NULL; vnic_cq_free()
43 cq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_CQ, index); vnic_cq_alloc()
44 if (!cq->ctrl) { vnic_cq_alloc()
65 writeq(paddr, &cq->ctrl->ring_base); vnic_cq_init()
66 iowrite32(cq->ring.desc_count, &cq->ctrl->ring_size); vnic_cq_init()
67 iowrite32(flow_control_enable, &cq->ctrl->flow_control_enable); vnic_cq_init()
68 iowrite32(color_enable, &cq->ctrl->color_enable); vnic_cq_init()
69 iowrite32(cq_head, &cq->ctrl->cq_head); vnic_cq_init()
70 iowrite32(cq_tail, &cq->ctrl->cq_tail); vnic_cq_init()
71 iowrite32(cq_tail_color, &cq->ctrl->cq_tail_color); vnic_cq_init()
72 iowrite32(interrupt_enable, &cq->ctrl->interrupt_enable); vnic_cq_init()
73 iowrite32(cq_entry_enable, &cq->ctrl->cq_entry_enable); vnic_cq_init()
74 iowrite32(cq_message_enable, &cq->ctrl->cq_message_enable); vnic_cq_init()
75 iowrite32(interrupt_offset, &cq->ctrl->interrupt_offset); vnic_cq_init()
76 writeq(cq_message_addr, &cq->ctrl->cq_message_addr); vnic_cq_init()
86 iowrite32(0, &cq->ctrl->cq_head); vnic_cq_clean()
87 iowrite32(0, &cq->ctrl->cq_tail); vnic_cq_clean()
88 iowrite32(1, &cq->ctrl->cq_tail_color); vnic_cq_clean()
|
| H A D | vnic_intr.c | 31 intr->ctrl = NULL; vnic_intr_free()
40 intr->ctrl = vnic_dev_get_res(vdev, RES_TYPE_INTR_CTRL, index); vnic_intr_alloc()
41 if (!intr->ctrl) { vnic_intr_alloc()
42 pr_err("Failed to hook INTR[%d].ctrl resource\n", index); vnic_intr_alloc()
53 iowrite32(coalescing_type, &intr->ctrl->coalescing_type); vnic_intr_init()
54 iowrite32(mask_on_assertion, &intr->ctrl->mask_on_assertion); vnic_intr_init()
55 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_init()
62 coalescing_timer), &intr->ctrl->coalescing_timer); vnic_intr_coalescing_timer_set()
67 iowrite32(0, &intr->ctrl->int_credits); vnic_intr_clean()
|
| H A D | vnic_rq.c | 81 rq->ctrl = NULL; vnic_rq_free()
92 rq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_RQ, index); vnic_rq_alloc()
93 if (!rq->ctrl) { vnic_rq_alloc()
122 writeq(paddr, &rq->ctrl->ring_base); vnic_rq_init_start()
123 iowrite32(count, &rq->ctrl->ring_size); vnic_rq_init_start()
124 iowrite32(cq_index, &rq->ctrl->cq_index); vnic_rq_init_start()
125 iowrite32(error_interrupt_enable, &rq->ctrl->error_interrupt_enable); vnic_rq_init_start()
126 iowrite32(error_interrupt_offset, &rq->ctrl->error_interrupt_offset); vnic_rq_init_start()
127 iowrite32(0, &rq->ctrl->dropped_packet_count); vnic_rq_init_start()
128 iowrite32(0, &rq->ctrl->error_status); vnic_rq_init_start()
129 iowrite32(fetch_index, &rq->ctrl->fetch_index); vnic_rq_init_start()
130 iowrite32(posted_index, &rq->ctrl->posted_index); vnic_rq_init_start()
144 fetch_index = ioread32(&rq->ctrl->fetch_index); vnic_rq_init()
159 return ioread32(&rq->ctrl->error_status); vnic_rq_error_status()
164 iowrite32(1, &rq->ctrl->enable); vnic_rq_enable()
171 iowrite32(0, &rq->ctrl->enable); vnic_rq_disable()
175 if (!(ioread32(&rq->ctrl->running))) vnic_rq_disable()
202 fetch_index = ioread32(&rq->ctrl->fetch_index); vnic_rq_clean()
211 iowrite32(fetch_index, &rq->ctrl->posted_index); vnic_rq_clean()
|
| H A D | vnic_wq.c | 84 wq->ctrl = NULL; vnic_wq_free()
95 wq->ctrl = vnic_dev_get_res(vdev, RES_TYPE_WQ, index); vnic_wq_alloc()
96 if (!wq->ctrl) { vnic_wq_alloc()
125 writeq(paddr, &wq->ctrl->ring_base); vnic_wq_init_start()
126 iowrite32(count, &wq->ctrl->ring_size); vnic_wq_init_start()
127 iowrite32(fetch_index, &wq->ctrl->fetch_index); vnic_wq_init_start()
128 iowrite32(posted_index, &wq->ctrl->posted_index); vnic_wq_init_start()
129 iowrite32(cq_index, &wq->ctrl->cq_index); vnic_wq_init_start()
130 iowrite32(error_interrupt_enable, &wq->ctrl->error_interrupt_enable); vnic_wq_init_start()
131 iowrite32(error_interrupt_offset, &wq->ctrl->error_interrupt_offset); vnic_wq_init_start()
132 iowrite32(0, &wq->ctrl->error_status); vnic_wq_init_start()
150 return ioread32(&wq->ctrl->error_status); vnic_wq_error_status()
155 iowrite32(1, &wq->ctrl->enable); vnic_wq_enable()
162 iowrite32(0, &wq->ctrl->enable); vnic_wq_disable()
166 if (!(ioread32(&wq->ctrl->running))) vnic_wq_disable()
193 iowrite32(0, &wq->ctrl->fetch_index); vnic_wq_clean()
194 iowrite32(0, &wq->ctrl->posted_index); vnic_wq_clean()
195 iowrite32(0, &wq->ctrl->error_status); vnic_wq_clean()
|
| H A D | vnic_intr.h | 51 struct vnic_intr_ctrl __iomem *ctrl; /* memory-mapped */ member in struct:vnic_intr
56 iowrite32(0, &intr->ctrl->mask); vnic_intr_unmask()
61 iowrite32(1, &intr->ctrl->mask); vnic_intr_mask()
66 return ioread32(&intr->ctrl->mask); vnic_intr_masked()
79 iowrite32(int_credit_return, &intr->ctrl->int_credit_return); vnic_intr_return_credits()
84 return ioread32(&intr->ctrl->int_credits); vnic_intr_credits()
|
| /linux-4.1.27/drivers/isdn/hysdn/ |
| H A D | hycapi.c | 47 static u16 hycapi_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
65 hycapi_reset_ctr(struct capi_ctr *ctrl) hycapi_reset_ctr() argument
67 hycapictrl_info *cinfo = ctrl->driverdata; hycapi_reset_ctr()
73 capi_ctr_down(ctrl); hycapi_reset_ctr()
81 hycapi_remove_ctr(struct capi_ctr *ctrl) hycapi_remove_ctr() argument
89 cinfo = (hycapictrl_info *)(ctrl->driverdata); hycapi_remove_ctr()
95 capi_ctr_suspend_output(ctrl); hycapi_remove_ctr()
97 if (hycapi_applications[i].listen_req[ctrl->cnr - 1]) { hycapi_remove_ctr()
98 kfree_skb(hycapi_applications[i].listen_req[ctrl->cnr - 1]); hycapi_remove_ctr()
99 hycapi_applications[i].listen_req[ctrl->cnr - 1] = NULL; hycapi_remove_ctr()
102 detach_capi_ctr(ctrl); hycapi_remove_ctr()
103 ctrl->driverdata = NULL; hycapi_remove_ctr()
117 hycapi_sendmsg_internal(struct capi_ctr *ctrl, struct sk_buff *skb) hycapi_sendmsg_internal() argument
119 hycapictrl_info *cinfo = (hycapictrl_info *)(ctrl->driverdata); hycapi_sendmsg_internal()
134 capi_ctr_suspend_output(ctrl); hycapi_sendmsg_internal()
151 hycapi_register_internal(struct capi_ctr *ctrl, __u16 appl, hycapi_register_internal() argument
155 hycapictrl_info *cinfo = (hycapictrl_info *)(ctrl->driverdata); hycapi_register_internal()
184 hycapi_applications[appl - 1].ctrl_mask |= (1 << (ctrl->cnr - 1)); hycapi_register_internal()
185 hycapi_send_message(ctrl, skb); hycapi_register_internal()
196 static void hycapi_restart_internal(struct capi_ctr *ctrl) hycapi_restart_internal() argument
204 if (_hycapi_appCheck(i + 1, ctrl->cnr) == 1) { hycapi_restart_internal()
205 hycapi_register_internal(ctrl, i + 1, hycapi_restart_internal()
207 if (hycapi_applications[i].listen_req[ctrl->cnr - 1]) { hycapi_restart_internal()
208 skb = skb_copy(hycapi_applications[i].listen_req[ctrl->cnr - 1], GFP_ATOMIC); hycapi_restart_internal()
209 hycapi_sendmsg_internal(ctrl, skb); hycapi_restart_internal()
223 hycapi_register_appl(struct capi_ctr *ctrl, __u16 appl, hycapi_register_appl() argument
227 hycapictrl_info *cinfo = (hycapictrl_info *)(ctrl->driverdata); hycapi_register_appl()
229 int chk = _hycapi_appCheck(appl, ctrl->cnr); hycapi_register_appl()
262 static void hycapi_release_internal(struct capi_ctr *ctrl, __u16 appl) hycapi_release_internal() argument
264 hycapictrl_info *cinfo = (hycapictrl_info *)(ctrl->driverdata); hycapi_release_internal()
287 hycapi_send_message(ctrl, skb); hycapi_release_internal()
288 hycapi_applications[appl - 1].ctrl_mask &= ~(1 << (ctrl->cnr - 1)); hycapi_release_internal()
299 hycapi_release_appl(struct capi_ctr *ctrl, __u16 appl) hycapi_release_appl() argument
303 chk = _hycapi_appCheck(appl, ctrl->cnr); hycapi_release_appl()
305 printk(KERN_ERR "HYCAPI: Releasing invalid appl %d on controller %d\n", appl, ctrl->cnr); hycapi_release_appl()
308 if (hycapi_applications[appl - 1].listen_req[ctrl->cnr - 1]) { hycapi_release_appl()
309 kfree_skb(hycapi_applications[appl - 1].listen_req[ctrl->cnr - 1]); hycapi_release_appl()
310 hycapi_applications[appl - 1].listen_req[ctrl->cnr - 1] = NULL; hycapi_release_appl()
314 hycapi_release_internal(ctrl, appl); hycapi_release_appl()
326 struct capi_ctr *ctrl; hycapi_capi_release() local
331 ctrl = &cinfo->capi_ctrl; hycapi_capi_release()
332 hycapi_remove_ctr(ctrl); hycapi_capi_release()
346 struct capi_ctr *ctrl; hycapi_capi_stop() local
351 ctrl = &cinfo->capi_ctrl; hycapi_capi_stop()
352 /* ctrl->suspend_output(ctrl); */ hycapi_capi_stop()
353 capi_ctr_down(ctrl); hycapi_capi_stop()
371 static u16 hycapi_send_message(struct capi_ctr *ctrl, struct sk_buff *skb) hycapi_send_message() argument
376 hycapictrl_info *cinfo = ctrl->driverdata; hycapi_send_message()
380 switch (_hycapi_appCheck(appl_id, ctrl->cnr)) hycapi_send_message()
384 hycapi_register_internal(ctrl, hycapi_send_message()
416 if (hycapi_applications[appl_id - 1].listen_req[ctrl->cnr - 1]) hycapi_send_message()
418 kfree_skb(hycapi_applications[appl_id - 1].listen_req[ctrl->cnr - 1]); hycapi_send_message()
419 hycapi_applications[appl_id - 1].listen_req[ctrl->cnr - 1] = NULL; hycapi_send_message()
421 if (!(hycapi_applications[appl_id -1].listen_req[ctrl->cnr - 1] = skb_copy(skb, GFP_ATOMIC))) hycapi_send_message()
431 hycapi_sendmsg_internal(ctrl, skb); hycapi_send_message()
440 struct capi_ctr *ctrl = m->private; hycapi_proc_show() local
441 hycapictrl_info *cinfo = (hycapictrl_info *)(ctrl->driverdata); hycapi_proc_show()
491 static int hycapi_load_firmware(struct capi_ctr *ctrl, capiloaddata *data) hycapi_load_firmware() argument
500 static char *hycapi_procinfo(struct capi_ctr *ctrl) hycapi_procinfo() argument
502 hycapictrl_info *cinfo = (hycapictrl_info *)(ctrl->driverdata); hycapi_procinfo()
532 struct capi_ctr *ctrl; hycapi_rx_capipkt() local
543 ctrl = &cinfo->capi_ctrl; hycapi_rx_capipkt()
622 capi_ctr_handle_message(ctrl, ApplId, skb); hycapi_rx_capipkt()
705 Attach the card with its capi-ctrl.
711 struct capi_ctr *ctrl = NULL; hycapi_fill_profile() local
714 ctrl = &cinfo->capi_ctrl; hycapi_fill_profile()
715 strcpy(ctrl->manu, "Hypercope"); hycapi_fill_profile()
716 ctrl->version.majorversion = 2; hycapi_fill_profile()
717 ctrl->version.minorversion = 0; hycapi_fill_profile()
718 ctrl->version.majormanuversion = 3; hycapi_fill_profile()
719 ctrl->version.minormanuversion = 2; hycapi_fill_profile()
720 ctrl->profile.ncontroller = card->myid; hycapi_fill_profile()
721 ctrl->profile.nbchannel = card->bchans; hycapi_fill_profile()
722 ctrl->profile.goptions = GLOBAL_OPTION_INTERNAL_CONTROLLER | hycapi_fill_profile()
724 ctrl->profile.support1 = B1_PROT_64KBIT_HDLC | hycapi_fill_profile()
727 ctrl->profile.support2 = B2_PROT_ISO7776 | hycapi_fill_profile()
730 ctrl->profile.support3 = B3_PROT_TRANSPARENT | hycapi_fill_profile()
741 struct capi_ctr *ctrl = NULL; hycapi_capi_create() local
752 printk(KERN_WARNING "HYSDN: no memory for capi-ctrl.\n"); hycapi_capi_create()
769 ctrl = &cinfo->capi_ctrl; hycapi_capi_create()
770 ctrl->driver_name = "hycapi"; hycapi_capi_create()
771 ctrl->driverdata = cinfo; hycapi_capi_create()
772 ctrl->register_appl = hycapi_register_appl; hycapi_capi_create()
773 ctrl->release_appl = hycapi_release_appl; hycapi_capi_create()
774 ctrl->send_message = hycapi_send_message; hycapi_capi_create()
775 ctrl->load_firmware = hycapi_load_firmware; hycapi_capi_create()
776 ctrl->reset_ctr = hycapi_reset_ctr; hycapi_capi_create()
777 ctrl->procinfo = hycapi_procinfo; hycapi_capi_create()
778 ctrl->proc_fops = &hycapi_proc_fops; hycapi_capi_create()
779 strcpy(ctrl->name, cinfo->cardname); hycapi_capi_create()
780 ctrl->owner = THIS_MODULE; hycapi_capi_create()
782 retval = attach_capi_ctr(ctrl); hycapi_capi_create()
789 capi_ctr_ready(ctrl); hycapi_capi_create()
791 /* resume output on stopped ctrl */ hycapi_capi_create()
792 ctrl = &card->hyctrlinfo->capi_ctrl; hycapi_capi_create()
794 capi_ctr_ready(ctrl); hycapi_capi_create()
795 hycapi_restart_internal(ctrl); hycapi_capi_create()
796 /* ctrl->resume_output(ctrl); */ hycapi_capi_create()
|
| /linux-4.1.27/drivers/pwm/ |
| H A D | pwm-lpss.c | 62 u32 ctrl; pwm_lpss_config() local
82 ctrl = readl(lpwm->regs + PWM); pwm_lpss_config()
83 ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK); pwm_lpss_config()
84 ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT; pwm_lpss_config()
85 ctrl |= on_time_div; pwm_lpss_config()
87 ctrl |= PWM_SW_UPDATE; pwm_lpss_config()
88 writel(ctrl, lpwm->regs + PWM); pwm_lpss_config()
96 u32 ctrl; pwm_lpss_enable() local
98 ctrl = readl(lpwm->regs + PWM); pwm_lpss_enable()
99 writel(ctrl | PWM_ENABLE, lpwm->regs + PWM); pwm_lpss_enable()
107 u32 ctrl; pwm_lpss_disable() local
109 ctrl = readl(lpwm->regs + PWM); pwm_lpss_disable()
110 writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); pwm_lpss_disable()
152 u32 ctrl; pwm_lpss_remove() local
154 ctrl = readl(lpwm->regs + PWM); pwm_lpss_remove()
155 writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); pwm_lpss_remove()
|
| H A D | pwm-jz4740.c | 90 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm); jz4740_pwm_enable() local
92 ctrl |= JZ_TIMER_CTRL_PWM_ENABLE; jz4740_pwm_enable()
93 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); jz4740_pwm_enable()
101 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm); jz4740_pwm_disable() local
103 ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE; jz4740_pwm_disable()
105 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); jz4740_pwm_disable()
115 uint16_t ctrl; jz4740_pwm_config() local
145 ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT | jz4740_pwm_config()
148 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl); jz4740_pwm_config()
|
| /linux-4.1.27/net/bluetooth/cmtp/ |
| H A D | capi.c | 188 struct capi_ctr *ctrl = &session->ctrl; cmtp_recv_interopmsg() local
242 if (!info && ctrl) { cmtp_recv_interopmsg()
243 memcpy(&ctrl->profile, cmtp_recv_interopmsg()
247 capi_ctr_ready(ctrl); cmtp_recv_interopmsg()
256 if (!info && ctrl) { cmtp_recv_interopmsg()
260 memset(ctrl->manu, 0, CAPI_MANUFACTURER_LEN); cmtp_recv_interopmsg()
261 strncpy(ctrl->manu, cmtp_recv_interopmsg()
271 if (!info && ctrl) { cmtp_recv_interopmsg()
272 ctrl->version.majorversion = CAPIMSG_U32(skb->data, CAPI_MSG_BASELEN + 16); cmtp_recv_interopmsg()
273 ctrl->version.minorversion = CAPIMSG_U32(skb->data, CAPI_MSG_BASELEN + 20); cmtp_recv_interopmsg()
274 ctrl->version.majormanuversion = CAPIMSG_U32(skb->data, CAPI_MSG_BASELEN + 24); cmtp_recv_interopmsg()
275 ctrl->version.minormanuversion = CAPIMSG_U32(skb->data, CAPI_MSG_BASELEN + 28); cmtp_recv_interopmsg()
284 if (!info && ctrl) { cmtp_recv_interopmsg()
288 memset(ctrl->serial, 0, CAPI_SERIAL_LEN); cmtp_recv_interopmsg()
289 strncpy(ctrl->serial, cmtp_recv_interopmsg()
321 struct capi_ctr *ctrl = &session->ctrl; cmtp_recv_capimsg() local
359 capi_ctr_handle_message(ctrl, appl, skb); cmtp_recv_capimsg()
362 static int cmtp_load_firmware(struct capi_ctr *ctrl, capiloaddata *data) cmtp_load_firmware() argument
364 BT_DBG("ctrl %p data %p", ctrl, data); cmtp_load_firmware()
369 static void cmtp_reset_ctr(struct capi_ctr *ctrl) cmtp_reset_ctr() argument
371 struct cmtp_session *session = ctrl->driverdata; cmtp_reset_ctr()
373 BT_DBG("ctrl %p", ctrl); cmtp_reset_ctr()
375 capi_ctr_down(ctrl); cmtp_reset_ctr()
381 static void cmtp_register_appl(struct capi_ctr *ctrl, __u16 appl, capi_register_params *rp) cmtp_register_appl() argument
384 struct cmtp_session *session = ctrl->driverdata; cmtp_register_appl()
390 BT_DBG("ctrl %p appl %d level3cnt %d datablkcnt %d datablklen %d", cmtp_register_appl()
391 ctrl, appl, rp->level3cnt, rp->datablkcnt, rp->datablklen); cmtp_register_appl()
400 nconn = ctrl->profile.nbchannel * -want; cmtp_register_appl()
405 nconn = ctrl->profile.nbchannel; cmtp_register_appl()
450 static void cmtp_release_appl(struct capi_ctr *ctrl, __u16 appl) cmtp_release_appl() argument
452 struct cmtp_session *session = ctrl->driverdata; cmtp_release_appl()
455 BT_DBG("ctrl %p appl %d", ctrl, appl); cmtp_release_appl()
474 static u16 cmtp_send_message(struct capi_ctr *ctrl, struct sk_buff *skb) cmtp_send_message() argument
476 struct cmtp_session *session = ctrl->driverdata; cmtp_send_message()
481 BT_DBG("ctrl %p skb %p", ctrl, skb); cmtp_send_message()
504 static char *cmtp_procinfo(struct capi_ctr *ctrl) cmtp_procinfo() argument
511 struct capi_ctr *ctrl = m->private; cmtp_proc_show() local
512 struct cmtp_session *session = ctrl->driverdata; cmtp_proc_show()
516 seq_printf(m, "%s\n\n", cmtp_procinfo(ctrl)); cmtp_proc_show()
518 seq_printf(m, "ctrl %d\n", session->num); cmtp_proc_show()
567 session->ctrl.owner = THIS_MODULE; cmtp_attach_device()
568 session->ctrl.driverdata = session; cmtp_attach_device()
569 strcpy(session->ctrl.name, session->name); cmtp_attach_device()
571 session->ctrl.driver_name = "cmtp"; cmtp_attach_device()
572 session->ctrl.load_firmware = cmtp_load_firmware; cmtp_attach_device()
573 session->ctrl.reset_ctr = cmtp_reset_ctr; cmtp_attach_device()
574 session->ctrl.register_appl = cmtp_register_appl; cmtp_attach_device()
575 session->ctrl.release_appl = cmtp_release_appl; cmtp_attach_device()
576 session->ctrl.send_message = cmtp_send_message; cmtp_attach_device()
578 session->ctrl.procinfo = cmtp_procinfo; cmtp_attach_device()
579 session->ctrl.proc_fops = &cmtp_proc_fops; cmtp_attach_device()
581 if (attach_capi_ctr(&session->ctrl) < 0) { cmtp_attach_device()
586 session->num = session->ctrl.cnr; cmtp_attach_device()
611 detach_capi_ctr(&session->ctrl); cmtp_detach_device()
|
| /linux-4.1.27/arch/mips/kernel/ |
| H A D | cevt-gt641xx.c | 51 u32 ctrl; gt641xx_timer0_set_next_event() local
55 ctrl = GT_READ(GT_TC_CONTROL_OFS); gt641xx_timer0_set_next_event()
56 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); gt641xx_timer0_set_next_event()
57 ctrl |= GT_TC_CONTROL_ENTC0_MSK; gt641xx_timer0_set_next_event()
60 GT_WRITE(GT_TC_CONTROL_OFS, ctrl); gt641xx_timer0_set_next_event()
70 u32 ctrl; gt641xx_timer0_set_mode() local
74 ctrl = GT_READ(GT_TC_CONTROL_OFS); gt641xx_timer0_set_mode()
75 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); gt641xx_timer0_set_mode()
79 ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK; gt641xx_timer0_set_mode()
82 ctrl |= GT_TC_CONTROL_ENTC0_MSK; gt641xx_timer0_set_mode()
88 GT_WRITE(GT_TC_CONTROL_OFS, ctrl); gt641xx_timer0_set_mode()
|
| /linux-4.1.27/arch/mips/lib/ |
| H A D | iomap-pci.c | 16 struct pci_controller *ctrl = dev->bus->sysdata; __pci_ioport_map() local
17 unsigned long base = ctrl->io_map_base; __pci_ioport_map()
20 if (unlikely(!ctrl->io_map_base)) { __pci_ioport_map()
27 ctrl->io_map_base = base = mips_io_port_base; __pci_ioport_map()
40 return (void __iomem *) (ctrl->io_map_base + port); __pci_ioport_map()
|
| /linux-4.1.27/include/linux/ |
| H A D | mdio-bitbang.h | 16 void (*set_mdc)(struct mdiobb_ctrl *ctrl, int level);
21 void (*set_mdio_dir)(struct mdiobb_ctrl *ctrl, int output);
27 void (*set_mdio_data)(struct mdiobb_ctrl *ctrl, int value);
30 int (*get_mdio_data)(struct mdiobb_ctrl *ctrl);
40 struct mii_bus *alloc_mdio_bitbang(struct mdiobb_ctrl *ctrl);
|
| H A D | spmi.h | 44 * @ctrl: SPMI controller managing the bus hosting this device.
49 struct spmi_controller *ctrl; member in struct:spmi_device
68 struct spmi_device *spmi_device_alloc(struct spmi_controller *ctrl);
91 int (*cmd)(struct spmi_controller *ctrl, u8 opcode, u8 sid);
92 int (*read_cmd)(struct spmi_controller *ctrl, u8 opcode,
94 int (*write_cmd)(struct spmi_controller *ctrl, u8 opcode,
104 void *spmi_controller_get_drvdata(const struct spmi_controller *ctrl) spmi_controller_get_drvdata() argument
106 return dev_get_drvdata(&ctrl->dev); spmi_controller_get_drvdata()
109 static inline void spmi_controller_set_drvdata(struct spmi_controller *ctrl, spmi_controller_set_drvdata() argument
112 dev_set_drvdata(&ctrl->dev, data); spmi_controller_set_drvdata()
120 * @ctrl SPMI controller.
122 static inline void spmi_controller_put(struct spmi_controller *ctrl) spmi_controller_put() argument
124 if (ctrl) spmi_controller_put()
125 put_device(&ctrl->dev); spmi_controller_put()
128 int spmi_controller_add(struct spmi_controller *ctrl);
129 void spmi_controller_remove(struct spmi_controller *ctrl);
|
| H A D | gpio-fan.h | 26 unsigned *ctrl; /* fan control GPIOs. */ member in struct:gpio_fan_platform_data
|
| /linux-4.1.27/drivers/isdn/hardware/eicon/ |
| H A D | capimain.c | 82 struct capi_ctr *ctrl = m->private; diva_ctl_proc_show() local
83 diva_card *card = (diva_card *) ctrl->driverdata; diva_ctl_proc_show()
85 seq_printf(m, "%s\n", ctrl->name); diva_ctl_proc_show()
86 seq_printf(m, "Serial No. : %s\n", ctrl->serial); diva_ctl_proc_show()
109 void diva_os_set_controller_struct(struct capi_ctr *ctrl) diva_os_set_controller_struct() argument
111 ctrl->driver_name = DRIVERLNAME; diva_os_set_controller_struct()
112 ctrl->load_firmware = NULL; diva_os_set_controller_struct()
113 ctrl->reset_ctr = NULL; diva_os_set_controller_struct()
114 ctrl->proc_fops = &diva_ctl_proc_fops; diva_os_set_controller_struct()
115 ctrl->owner = THIS_MODULE; diva_os_set_controller_struct()
|
| H A D | capifunc.c | 88 static char *diva_procinfo(struct capi_ctr *ctrl) diva_procinfo() argument
90 return (ctrl->serial); diva_procinfo()
117 byte ctrl = Controller & 0x7f; /* mask external controller bit off */ MapController() local
120 if (ctrl == ControllerMap[i]) { MapController()
126 ControllerMap[0] = ctrl; MapController()
138 byte ctrl = MappedController & 0x7f; /* mask external controller bit off */ UnMapController() local
140 if (ctrl <= max_adapter) { UnMapController()
141 Controller = ControllerMap[ctrl]; UnMapController()
491 struct capi_ctr *ctrl = NULL; diva_add_card() local
509 ctrl = &card->capi_ctrl; diva_add_card()
510 strcpy(ctrl->name, card->name); diva_add_card()
511 ctrl->register_appl = diva_register_appl; diva_add_card()
512 ctrl->release_appl = diva_release_appl; diva_add_card()
513 ctrl->send_message = diva_send_message; diva_add_card()
514 ctrl->procinfo = diva_procinfo; diva_add_card()
515 ctrl->driverdata = card; diva_add_card()
516 diva_os_set_controller_struct(ctrl); diva_add_card()
518 if (attach_capi_ctr(ctrl)) { diva_add_card()
528 strlcpy(ctrl->manu, M_COMPANY, sizeof(ctrl->manu)); diva_add_card()
529 ctrl->version.majorversion = 2; diva_add_card()
530 ctrl->version.minorversion = 0; diva_add_card()
531 ctrl->version.majormanuversion = DRRELMAJOR; diva_add_card()
532 ctrl->version.minormanuversion = DRRELMINOR; diva_add_card()
544 strlcpy(ctrl->serial, serial, sizeof(ctrl->serial)); diva_add_card()
549 ControllerMap[card->Id] = (byte) (ctrl->cnr); diva_add_card()
551 DBG_TRC(("AddAdapterMap (%d) -> (%d)", ctrl->cnr, card->Id)) diva_add_card()
703 PUT_WORD(&ctrl->profile.nbchannel, card->d.channels); diva_add_card()
704 ctrl->profile.goptions = a->profile.Global_Options; diva_add_card()
705 ctrl->profile.support1 = a->profile.B1_Protocols; diva_add_card()
706 ctrl->profile.support2 = a->profile.B2_Protocols; diva_add_card()
707 ctrl->profile.support3 = a->profile.B3_Protocols; diva_add_card()
709 ctrl->profile.manu[0] = a->man_profile.private_options; diva_add_card()
710 ctrl->profile.manu[1] = a->man_profile.rtp_primary_payloads; diva_add_card()
711 ctrl->profile.manu[2] = a->man_profile.rtp_additional_payloads; diva_add_card()
712 ctrl->profile.manu[3] = 0; diva_add_card()
713 ctrl->profile.manu[4] = 0; diva_add_card()
715 capi_ctr_ready(ctrl); diva_add_card()
724 static void diva_register_appl(struct capi_ctr *ctrl, __u16 appl, diva_register_appl() argument
751 nconn = ctrl->profile.nbchannel * -nconn; diva_register_appl()
754 nconn = ctrl->profile.nbchannel; diva_register_appl()
848 static void diva_release_appl(struct capi_ctr *ctrl, __u16 appl) diva_release_appl() argument
878 static u16 diva_send_message(struct capi_ctr *ctrl, diva_send_message() argument
886 diva_card *card = ctrl->driverdata; diva_send_message()
|
| /linux-4.1.27/drivers/video/fbdev/mmp/hw/ |
| H A D | mmp_ctrl.c | 45 struct mmphw_ctrl *ctrl = (struct mmphw_ctrl *)dev_id; ctrl_handle_irq() local
48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); ctrl_handle_irq()
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); ctrl_handle_irq()
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); ctrl_handle_irq()
55 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); ctrl_handle_irq()
56 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask); ctrl_handle_irq()
295 /* vsync ctrl */ path_set_mode()
327 static void ctrl_set_default(struct mmphw_ctrl *ctrl) ctrl_set_default() argument
335 tmp = readl_relaxed(ctrl->reg_base + LCD_TOP_CTRL); ctrl_set_default()
337 writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL); ctrl_set_default()
343 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); ctrl_set_default()
346 writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA); ctrl_set_default()
402 struct mmphw_ctrl *ctrl = path_plat->ctrl; path_init() local
406 dev_info(ctrl->dev, "%s: %s\n", __func__, config->name); path_init()
411 dev_err(ctrl->dev, "%s: unable to alloc path_info for %s\n", path_init()
417 path_info->dev = ctrl->dev; path_init()
453 struct mmphw_ctrl *ctrl = NULL; mmphw_probe() local
481 ctrl = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); mmphw_probe()
482 if (!ctrl) { mmphw_probe()
487 ctrl->name = mi->name; mmphw_probe()
488 ctrl->path_num = mi->path_num; mmphw_probe()
489 ctrl->dev = &pdev->dev; mmphw_probe()
490 ctrl->irq = irq; mmphw_probe()
491 platform_set_drvdata(pdev, ctrl); mmphw_probe()
492 mutex_init(&ctrl->access_ok); mmphw_probe()
495 if (!devm_request_mem_region(ctrl->dev, res->start, mmphw_probe()
496 resource_size(res), ctrl->name)) { mmphw_probe()
497 dev_err(ctrl->dev, mmphw_probe()
503 ctrl->reg_base = devm_ioremap_nocache(ctrl->dev, mmphw_probe()
505 if (ctrl->reg_base == NULL) { mmphw_probe()
506 dev_err(ctrl->dev, "%s: res %x - %x map failed\n", __func__, mmphw_probe()
513 ret = devm_request_irq(ctrl->dev, ctrl->irq, ctrl_handle_irq, mmphw_probe()
514 IRQF_SHARED, "lcd_controller", ctrl); mmphw_probe()
516 dev_err(ctrl->dev, "%s unable to request IRQ %d\n", mmphw_probe()
517 __func__, ctrl->irq); mmphw_probe()
523 ctrl->clk = devm_clk_get(ctrl->dev, mi->clk_name); mmphw_probe()
524 if (IS_ERR(ctrl->clk)) { mmphw_probe()
525 dev_err(ctrl->dev, "unable to get clk %s\n", mi->clk_name); mmphw_probe()
529 clk_prepare_enable(ctrl->clk); mmphw_probe()
532 ctrl_set_default(ctrl); mmphw_probe()
535 for (i = 0; i < ctrl->path_num; i++) { mmphw_probe()
537 path_plat = &ctrl->path_plats[i]; mmphw_probe()
539 path_plat->ctrl = ctrl; mmphw_probe()
549 ret = lcd_spi_register(ctrl); mmphw_probe()
554 dev_info(ctrl->dev, "device init done\n"); mmphw_probe()
559 for (i = 0; i < ctrl->path_num; i++) { mmphw_probe()
560 path_plat = &ctrl->path_plats[i]; mmphw_probe()
564 clk_disable_unprepare(ctrl->clk); mmphw_probe()
|
| /linux-4.1.27/drivers/mmc/host/ |
| H A D | sdhci_f_sdh30.c | 55 u32 ctrl = 0; sdhci_f_sdh30_soft_voltage_switch() local
58 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); sdhci_f_sdh30_soft_voltage_switch()
59 ctrl |= F_SDH30_CRES_O_DN; sdhci_f_sdh30_soft_voltage_switch()
60 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); sdhci_f_sdh30_soft_voltage_switch()
61 ctrl |= F_SDH30_MSEL_O_1_8; sdhci_f_sdh30_soft_voltage_switch()
62 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); sdhci_f_sdh30_soft_voltage_switch()
64 ctrl &= ~F_SDH30_CRES_O_DN; sdhci_f_sdh30_soft_voltage_switch()
65 sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2); sdhci_f_sdh30_soft_voltage_switch()
70 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); sdhci_f_sdh30_soft_voltage_switch()
71 ctrl |= priv->vendor_hs200; sdhci_f_sdh30_soft_voltage_switch()
72 sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL); sdhci_f_sdh30_soft_voltage_switch()
75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); sdhci_f_sdh30_soft_voltage_switch()
76 ctrl |= F_SDH30_CMD_CHK_DIS; sdhci_f_sdh30_soft_voltage_switch()
77 sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING); sdhci_f_sdh30_soft_voltage_switch()
107 int irq, ctrl = 0, ret = 0; sdhci_f_sdh30_probe() local
169 ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG); sdhci_f_sdh30_probe()
170 ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 | sdhci_f_sdh30_probe()
172 ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN); sdhci_f_sdh30_probe()
173 sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG); sdhci_f_sdh30_probe()
|
| H A D | sdhci-sirf.c | 28 u8 ctrl; sdhci_sirf_set_bus_width() local
30 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); sdhci_sirf_set_bus_width()
31 ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS); sdhci_sirf_set_bus_width()
39 ctrl |= SDHCI_SIRF_8BITBUS; sdhci_sirf_set_bus_width()
41 ctrl |= SDHCI_CTRL_4BITBUS; sdhci_sirf_set_bus_width()
43 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); sdhci_sirf_set_bus_width()
|
| /linux-4.1.27/drivers/mtd/nand/ |
| H A D | plat_nand.c | 69 data->chip.cmd_ctrl = pdata->ctrl.cmd_ctrl; plat_nand_probe()
70 data->chip.dev_ready = pdata->ctrl.dev_ready; plat_nand_probe()
71 data->chip.select_chip = pdata->ctrl.select_chip; plat_nand_probe()
72 data->chip.write_buf = pdata->ctrl.write_buf; plat_nand_probe()
73 data->chip.read_buf = pdata->ctrl.read_buf; plat_nand_probe()
74 data->chip.read_byte = pdata->ctrl.read_byte; plat_nand_probe()
79 data->chip.ecc.hwctl = pdata->ctrl.hwcontrol; plat_nand_probe()
86 if (pdata->ctrl.probe) { plat_nand_probe()
87 err = pdata->ctrl.probe(pdev); plat_nand_probe()
110 if (pdata->ctrl.remove) plat_nand_probe()
111 pdata->ctrl.remove(pdev); plat_nand_probe()
124 if (pdata->ctrl.remove) plat_nand_remove()
125 pdata->ctrl.remove(pdev); plat_nand_remove()
|
| H A D | fsl_ifc_nand.c | 45 struct fsl_ifc_ctrl *ctrl; member in struct:fsl_ifc_mtd
235 struct fsl_ifc_ctrl *ctrl = priv->ctrl; set_addr() local
236 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; set_addr()
279 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, check_read_ecc() argument
297 struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_run_command() local
299 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_run_command()
313 ctrl->nand_stat = 0; fsl_ifc_run_command()
319 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, fsl_ifc_run_command()
322 /* ctrl->nand_stat will be updated from IRQ context */ fsl_ifc_run_command()
323 if (!ctrl->nand_stat) fsl_ifc_run_command()
325 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER) fsl_ifc_run_command()
327 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER) fsl_ifc_run_command()
342 errors = check_read_ecc(mtd, ctrl, eccstat, i); fsl_ifc_run_command()
354 ctrl->nand_stat |= fsl_ifc_run_command()
374 struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_do_read() local
375 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_do_read()
414 struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_cmdfunc() local
415 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_cmdfunc()
724 struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_wait() local
725 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_wait()
753 struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_read_page() local
760 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) fsl_ifc_read_page()
763 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) fsl_ifc_read_page()
826 struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_sram_init() local
827 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_sram_init()
862 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat, fsl_ifc_sram_init()
865 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC) fsl_ifc_sram_init()
875 struct fsl_ifc_ctrl *ctrl = priv->ctrl; fsl_ifc_chip_init() local
876 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_chip_init()
986 if (ctrl->version == FSL_IFC_VERSION_1_1_0) fsl_ifc_chip_init()
1083 priv->ctrl = fsl_ifc_ctrl_dev; fsl_ifc_nand_probe()
|
| H A D | jz4740_nand.c | 85 uint32_t ctrl; jz_nand_select_chip() local
88 ctrl = readl(nand->base + JZ_REG_NAND_CTRL); jz_nand_select_chip()
89 ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK; jz_nand_select_chip()
98 writel(ctrl, nand->base + JZ_REG_NAND_CTRL); jz_nand_select_chip()
103 static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) jz_nand_cmd_ctrl() argument
112 if (ctrl & NAND_CTRL_CHANGE) { jz_nand_cmd_ctrl()
113 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE)); jz_nand_cmd_ctrl()
114 if (ctrl & NAND_ALE) jz_nand_cmd_ctrl()
116 else if (ctrl & NAND_CLE) jz_nand_cmd_ctrl()
121 if (ctrl & NAND_NCE) jz_nand_cmd_ctrl()
335 uint32_t ctrl; jz_nand_detect_bank() local
360 ctrl = readl(nand->base + JZ_REG_NAND_CTRL); jz_nand_detect_bank()
361 ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1); jz_nand_detect_bank()
362 writel(ctrl, nand->base + JZ_REG_NAND_CTRL); jz_nand_detect_bank()
397 ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1)); jz_nand_detect_bank()
398 writel(ctrl, nand->base + JZ_REG_NAND_CTRL); jz_nand_detect_bank()
|
| H A D | fsl_elbc_nand.c | 53 struct fsl_lbc_ctrl *ctrl; member in struct:fsl_elbc_mtd
149 struct fsl_lbc_ctrl *ctrl = priv->ctrl; set_addr() local
150 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; set_addr()
151 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; set_addr()
200 struct fsl_lbc_ctrl *ctrl = priv->ctrl; fsl_elbc_run_command() local
201 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; fsl_elbc_run_command()
202 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_elbc_run_command()
218 ctrl->irq_status = 0; fsl_elbc_run_command()
223 wait_event_timeout(ctrl->irq_wait, ctrl->irq_status, fsl_elbc_run_command()
225 elbc_fcm_ctrl->status = ctrl->irq_status; fsl_elbc_run_command()
272 struct fsl_lbc_ctrl *ctrl = priv->ctrl; fsl_elbc_do_read() local
273 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_elbc_do_read()
305 struct fsl_lbc_ctrl *ctrl = priv->ctrl; fsl_elbc_cmdfunc() local
306 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; fsl_elbc_cmdfunc()
307 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_elbc_cmdfunc()
530 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; fsl_elbc_write_buf()
568 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; fsl_elbc_read_byte()
585 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; fsl_elbc_read_buf()
609 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; fsl_elbc_wait()
624 struct fsl_lbc_ctrl *ctrl = priv->ctrl; fsl_elbc_chip_init_tail() local
625 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_elbc_chip_init_tail()
701 struct fsl_lbc_ctrl *ctrl = priv->ctrl; fsl_elbc_read_page() local
702 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; fsl_elbc_read_page()
741 struct fsl_lbc_ctrl *ctrl = priv->ctrl; fsl_elbc_chip_init() local
742 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_elbc_chip_init()
743 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = ctrl->nand; fsl_elbc_chip_init()
799 struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl = priv->ctrl->nand; fsl_elbc_chip_remove()
879 priv->ctrl = fsl_lbc_ctrl_dev; fsl_elbc_nand_probe()
|
| /linux-4.1.27/drivers/media/i2c/s5c73m3/ |
| H A D | s5c73m3-ctrls.c | 39 static int s5c73m3_get_af_status(struct s5c73m3 *state, struct v4l2_ctrl *ctrl) s5c73m3_get_af_status() argument
49 ctrl->val = V4L2_AUTO_FOCUS_STATUS_BUSY; s5c73m3_get_af_status()
53 ctrl->val = V4L2_AUTO_FOCUS_STATUS_REACHED; s5c73m3_get_af_status()
61 ctrl->val = V4L2_AUTO_FOCUS_STATUS_FAILED; s5c73m3_get_af_status()
68 static int s5c73m3_g_volatile_ctrl(struct v4l2_ctrl *ctrl) s5c73m3_g_volatile_ctrl() argument
70 struct v4l2_subdev *sd = ctrl_to_sensor_sd(ctrl); s5c73m3_g_volatile_ctrl()
77 switch (ctrl->id) { s5c73m3_g_volatile_ctrl()
191 static int s5c73m3_3a_lock(struct s5c73m3 *state, struct v4l2_ctrl *ctrl) s5c73m3_3a_lock() argument
193 bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; s5c73m3_3a_lock()
194 bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; s5c73m3_3a_lock()
195 bool af_lock = ctrl->val & V4L2_LOCK_FOCUS; s5c73m3_3a_lock()
198 if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) { s5c73m3_3a_lock()
205 if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE) s5c73m3_3a_lock()
213 if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_FOCUS) s5c73m3_3a_lock()
345 static int s5c73m3_s_ctrl(struct v4l2_ctrl *ctrl) s5c73m3_s_ctrl() argument
347 struct v4l2_subdev *sd = ctrl_to_sensor_sd(ctrl); s5c73m3_s_ctrl()
352 ctrl->name, ctrl->val); s5c73m3_s_ctrl()
363 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) { s5c73m3_s_ctrl()
368 switch (ctrl->id) { s5c73m3_s_ctrl()
370 ret = s5c73m3_3a_lock(state, ctrl); s5c73m3_s_ctrl()
374 ret = s5c73m3_set_white_balance(state, ctrl->val); s5c73m3_s_ctrl()
378 ret = s5c73m3_set_contrast(state, ctrl->val); s5c73m3_s_ctrl()
382 ret = s5c73m3_set_colorfx(state, ctrl->val); s5c73m3_s_ctrl()
386 ret = s5c73m3_set_exposure(state, ctrl->val); s5c73m3_s_ctrl()
390 ret = s5c73m3_set_auto_focus(state, ctrl->val); s5c73m3_s_ctrl()
394 ret = s5c73m3_set_stabilization(state, ctrl->val); s5c73m3_s_ctrl()
398 ret = s5c73m3_set_iso(state, ctrl->val); s5c73m3_s_ctrl()
402 ret = s5c73m3_set_jpeg_quality(state, ctrl->val); s5c73m3_s_ctrl()
406 ret = s5c73m3_set_power_line_freq(state, ctrl->val); s5c73m3_s_ctrl()
410 ret = s5c73m3_set_saturation(state, ctrl->val); s5c73m3_s_ctrl()
414 ret = s5c73m3_set_scene_program(state, ctrl->val); s5c73m3_s_ctrl()
418 ret = s5c73m3_set_sharpness(state, ctrl->val); s5c73m3_s_ctrl()
422 ret = s5c73m3_isp_command(state, COMM_WDR, !!ctrl->val); s5c73m3_s_ctrl()
426 ret = s5c73m3_isp_command(state, COMM_ZOOM_STEP, ctrl->val); s5c73m3_s_ctrl()
|
| /linux-4.1.27/drivers/clocksource/ |
| H A D | dw_apb_timer.c | 65 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL); apbt_disable_int() local
67 ctrl |= APBTMR_CONTROL_INT; apbt_disable_int()
68 apbt_writel(timer, ctrl, APBTMR_N_CONTROL); apbt_disable_int()
106 unsigned long ctrl = apbt_readl(timer, APBTMR_N_CONTROL); apbt_enable_int() local
109 ctrl &= ~APBTMR_CONTROL_INT; apbt_enable_int()
110 apbt_writel(timer, ctrl, APBTMR_N_CONTROL); apbt_enable_int()
116 unsigned long ctrl; apbt_set_mode() local
127 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); apbt_set_mode()
128 ctrl |= APBTMR_CONTROL_MODE_PERIODIC; apbt_set_mode()
129 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_set_mode()
134 ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_set_mode()
135 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_set_mode()
139 ctrl |= APBTMR_CONTROL_ENABLE; apbt_set_mode()
140 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_set_mode()
144 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); apbt_set_mode()
150 ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_set_mode()
151 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; apbt_set_mode()
153 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_set_mode()
155 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_set_mode()
162 ctrl &= ~APBTMR_CONTROL_INT; apbt_set_mode()
163 ctrl |= APBTMR_CONTROL_ENABLE; apbt_set_mode()
164 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_set_mode()
169 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); apbt_set_mode()
170 ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_set_mode()
171 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_set_mode()
183 unsigned long ctrl; apbt_next_event() local
187 ctrl = apbt_readl(&dw_ced->timer, APBTMR_N_CONTROL); apbt_next_event()
188 ctrl &= ~APBTMR_CONTROL_ENABLE; apbt_next_event()
189 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_next_event()
192 ctrl |= APBTMR_CONTROL_ENABLE; apbt_next_event()
193 apbt_writel(&dw_ced->timer, ctrl, APBTMR_N_CONTROL); apbt_next_event()
306 unsigned long ctrl = apbt_readl(&dw_cs->timer, APBTMR_N_CONTROL); dw_apb_clocksource_start() local
308 ctrl &= ~APBTMR_CONTROL_ENABLE; dw_apb_clocksource_start()
309 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL); dw_apb_clocksource_start()
312 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC; dw_apb_clocksource_start()
313 ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT); dw_apb_clocksource_start()
314 apbt_writel(&dw_cs->timer, ctrl, APBTMR_N_CONTROL); dw_apb_clocksource_start()
|
| H A D | timer-integrator-ap.c | 41 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC; integrator_clocksource_init() local
46 ctrl |= TIMER_CTRL_DIV16; integrator_clocksource_init()
50 writel(ctrl, base + TIMER_CTRL); integrator_clocksource_init()
79 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE; clkevt_set_mode() local
82 writel(ctrl, clkevt_base + TIMER_CTRL); clkevt_set_mode()
88 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE; clkevt_set_mode()
89 writel(ctrl, clkevt_base + TIMER_CTRL); clkevt_set_mode()
93 ctrl &= ~TIMER_CTRL_PERIODIC; clkevt_set_mode()
94 writel(ctrl, clkevt_base + TIMER_CTRL); clkevt_set_mode()
108 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL); clkevt_set_next_event() local
110 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); clkevt_set_next_event()
112 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); clkevt_set_next_event()
136 unsigned int ctrl = 0; integrator_clockevent_init() local
142 ctrl |= TIMER_CTRL_DIV256; integrator_clockevent_init()
145 ctrl |= TIMER_CTRL_DIV16; integrator_clockevent_init()
148 writel(ctrl, clkevt_base + TIMER_CTRL); integrator_clockevent_init()
|
| H A D | qcom-timer.c | 53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); msm_timer_interrupt() local
54 ctrl &= ~TIMER_ENABLE_EN; msm_timer_interrupt()
55 writel_relaxed(ctrl, event_base + TIMER_ENABLE); msm_timer_interrupt()
64 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); msm_timer_set_next_event() local
66 ctrl &= ~TIMER_ENABLE_EN; msm_timer_set_next_event()
67 writel_relaxed(ctrl, event_base + TIMER_ENABLE); msm_timer_set_next_event()
69 writel_relaxed(ctrl, event_base + TIMER_CLEAR); msm_timer_set_next_event()
76 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); msm_timer_set_next_event()
83 u32 ctrl; msm_timer_set_mode() local
85 ctrl = readl_relaxed(event_base + TIMER_ENABLE); msm_timer_set_mode()
86 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN); msm_timer_set_mode()
99 writel_relaxed(ctrl, event_base + TIMER_ENABLE); msm_timer_set_mode()
|
| H A D | arm_global_timer.c | 93 unsigned long ctrl; gt_compare_set() local
96 ctrl = GT_CONTROL_TIMER_ENABLE; gt_compare_set()
97 writel(ctrl, gt_base + GT_CONTROL); gt_compare_set()
103 ctrl |= GT_CONTROL_AUTO_INC; gt_compare_set()
106 ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE; gt_compare_set()
107 writel(ctrl, gt_base + GT_CONTROL); gt_compare_set()
113 unsigned long ctrl; gt_clockevent_set_mode() local
122 ctrl = readl(gt_base + GT_CONTROL); gt_clockevent_set_mode()
123 ctrl &= ~(GT_CONTROL_COMP_ENABLE | gt_clockevent_set_mode()
125 writel(ctrl, gt_base + GT_CONTROL); gt_clockevent_set_mode()
|
| /linux-4.1.27/drivers/media/common/ |
| H A D | cx2341x.c | 279 struct v4l2_ext_control *ctrl) cx2341x_get_ctrl()
281 switch (ctrl->id) { cx2341x_get_ctrl()
283 ctrl->value = params->audio_sampling_freq; cx2341x_get_ctrl()
286 ctrl->value = params->audio_encoding; cx2341x_get_ctrl()
289 ctrl->value = params->audio_l2_bitrate; cx2341x_get_ctrl()
292 ctrl->value = params->audio_ac3_bitrate; cx2341x_get_ctrl()
295 ctrl->value = params->audio_mode; cx2341x_get_ctrl()
298 ctrl->value = params->audio_mode_extension; cx2341x_get_ctrl()
301 ctrl->value = params->audio_emphasis; cx2341x_get_ctrl()
304 ctrl->value = params->audio_crc; cx2341x_get_ctrl()
307 ctrl->value = params->audio_mute; cx2341x_get_ctrl()
310 ctrl->value = params->video_encoding; cx2341x_get_ctrl()
313 ctrl->value = params->video_aspect; cx2341x_get_ctrl()
316 ctrl->value = params->video_b_frames; cx2341x_get_ctrl()
319 ctrl->value = params->video_gop_size; cx2341x_get_ctrl()
322 ctrl->value = params->video_gop_closure; cx2341x_get_ctrl()
325 ctrl->value = params->video_bitrate_mode; cx2341x_get_ctrl()
328 ctrl->value = params->video_bitrate; cx2341x_get_ctrl()
331 ctrl->value = params->video_bitrate_peak; cx2341x_get_ctrl()
334 ctrl->value = params->video_temporal_decimation; cx2341x_get_ctrl()
337 ctrl->value = params->video_mute; cx2341x_get_ctrl()
340 ctrl->value = params->video_mute_yuv; cx2341x_get_ctrl()
343 ctrl->value = params->stream_type; cx2341x_get_ctrl()
346 ctrl->value = params->stream_vbi_fmt; cx2341x_get_ctrl()
349 ctrl->value = params->video_spatial_filter_mode; cx2341x_get_ctrl()
352 ctrl->value = params->video_spatial_filter; cx2341x_get_ctrl()
355 ctrl->value = params->video_luma_spatial_filter_type; cx2341x_get_ctrl()
358 ctrl->value = params->video_chroma_spatial_filter_type; cx2341x_get_ctrl()
361 ctrl->value = params->video_temporal_filter_mode; cx2341x_get_ctrl()
364 ctrl->value = params->video_temporal_filter; cx2341x_get_ctrl()
367 ctrl->value = params->video_median_filter_type; cx2341x_get_ctrl()
370 ctrl->value = params->video_luma_median_filter_top; cx2341x_get_ctrl()
373 ctrl->value = params->video_luma_median_filter_bottom; cx2341x_get_ctrl()
376 ctrl->value = params->video_chroma_median_filter_top; cx2341x_get_ctrl()
379 ctrl->value = params->video_chroma_median_filter_bottom; cx2341x_get_ctrl()
382 ctrl->value = params->stream_insert_nav_packets; cx2341x_get_ctrl()
393 struct v4l2_ext_control *ctrl) cx2341x_set_ctrl()
395 switch (ctrl->id) { cx2341x_set_ctrl()
399 params->audio_sampling_freq = ctrl->value; cx2341x_set_ctrl()
405 if (ctrl->value != V4L2_MPEG_AUDIO_ENCODING_LAYER_2 && cx2341x_set_ctrl()
406 ctrl->value != V4L2_MPEG_AUDIO_ENCODING_AC3) cx2341x_set_ctrl()
408 params->audio_encoding = ctrl->value; cx2341x_set_ctrl()
413 params->audio_l2_bitrate = ctrl->value; cx2341x_set_ctrl()
420 params->audio_ac3_bitrate = ctrl->value; cx2341x_set_ctrl()
423 params->audio_mode = ctrl->value; cx2341x_set_ctrl()
426 params->audio_mode_extension = ctrl->value; cx2341x_set_ctrl()
429 params->audio_emphasis = ctrl->value; cx2341x_set_ctrl()
432 params->audio_crc = ctrl->value; cx2341x_set_ctrl()
435 params->audio_mute = ctrl->value; cx2341x_set_ctrl()
438 params->video_aspect = ctrl->value; cx2341x_set_ctrl()
441 int b = ctrl->value + 1; cx2341x_set_ctrl()
443 params->video_b_frames = ctrl->value; cx2341x_set_ctrl()
452 int gop = ctrl->value; cx2341x_set_ctrl()
457 ctrl->value = params->video_gop_size; cx2341x_set_ctrl()
461 params->video_gop_closure = ctrl->value; cx2341x_set_ctrl()
468 ctrl->value != V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) cx2341x_set_ctrl()
470 params->video_bitrate_mode = ctrl->value; cx2341x_set_ctrl()
475 params->video_bitrate = ctrl->value; cx2341x_set_ctrl()
480 params->video_bitrate_peak = ctrl->value; cx2341x_set_ctrl()
483 params->video_temporal_decimation = ctrl->value; cx2341x_set_ctrl()
486 params->video_mute = (ctrl->value != 0); cx2341x_set_ctrl()
489 params->video_mute_yuv = ctrl->value; cx2341x_set_ctrl()
494 params->stream_type = ctrl->value; cx2341x_set_ctrl()
506 params->stream_vbi_fmt = ctrl->value; cx2341x_set_ctrl()
509 params->video_spatial_filter_mode = ctrl->value; cx2341x_set_ctrl()
512 params->video_spatial_filter = ctrl->value; cx2341x_set_ctrl()
515 params->video_luma_spatial_filter_type = ctrl->value; cx2341x_set_ctrl()
518 params->video_chroma_spatial_filter_type = ctrl->value; cx2341x_set_ctrl()
521 params->video_temporal_filter_mode = ctrl->value; cx2341x_set_ctrl()
524 params->video_temporal_filter = ctrl->value; cx2341x_set_ctrl()
527 params->video_median_filter_type = ctrl->value; cx2341x_set_ctrl()
530 params->video_luma_median_filter_top = ctrl->value; cx2341x_set_ctrl()
533 params->video_luma_median_filter_bottom = ctrl->value; cx2341x_set_ctrl()
536 params->video_chroma_median_filter_top = ctrl->value; cx2341x_set_ctrl()
539 params->video_chroma_median_filter_bottom = ctrl->value; cx2341x_set_ctrl()
542 params->stream_insert_nav_packets = ctrl->value; cx2341x_set_ctrl()
934 /* Check for correctness of the ctrl's value based on the data from
937 static int v4l2_ctrl_check(struct v4l2_ext_control *ctrl, struct v4l2_queryctrl *qctrl, v4l2_ctrl_check() argument
950 if (ctrl->value < qctrl->minimum || ctrl->value > qctrl->maximum) v4l2_ctrl_check()
953 if (menu_items[ctrl->value] == NULL || v4l2_ctrl_check()
954 menu_items[ctrl->value][0] == '\0') v4l2_ctrl_check()
958 (ctrl->value & ~qctrl->maximum)) v4l2_ctrl_check()
971 struct v4l2_ext_control *ctrl = ctrls->controls + i; cx2341x_ext_ctrls() local
973 err = cx2341x_get_ctrl(params, ctrl); cx2341x_ext_ctrls()
982 struct v4l2_ext_control *ctrl = ctrls->controls + i; cx2341x_ext_ctrls() local
986 qctrl.id = ctrl->id; cx2341x_ext_ctrls()
992 err = v4l2_ctrl_check(ctrl, &qctrl, menu_items); cx2341x_ext_ctrls()
995 err = cx2341x_set_ctrl(params, busy, ctrl); cx2341x_ext_ctrls()
1168 struct v4l2_ext_control ctrl; cx2341x_menu_item() local
1172 ctrl.id = id; cx2341x_menu_item()
1173 if (cx2341x_get_ctrl(p, &ctrl)) cx2341x_menu_item()
1175 while (ctrl.value-- && *menu) menu++; cx2341x_menu_item()
1273 static inline struct cx2341x_handler *to_cxhdl(struct v4l2_ctrl *ctrl) to_cxhdl() argument
1275 return container_of(ctrl->handler, struct cx2341x_handler, hdl); to_cxhdl()
1293 /* ctrl->handler->lock is held, so it is safe to access cur.val */ cx2341x_neq()
1294 static inline int cx2341x_neq(struct v4l2_ctrl *ctrl) cx2341x_neq() argument
1296 return ctrl && ctrl->val != ctrl->cur.val; cx2341x_neq()
1299 static int cx2341x_try_ctrl(struct v4l2_ctrl *ctrl) cx2341x_try_ctrl() argument
1301 struct cx2341x_handler *hdl = to_cxhdl(ctrl); cx2341x_try_ctrl()
1302 s32 val = ctrl->val; cx2341x_try_ctrl()
1304 switch (ctrl->id) { cx2341x_try_ctrl()
1339 static int cx2341x_s_ctrl(struct v4l2_ctrl *ctrl) cx2341x_s_ctrl() argument
1349 struct cx2341x_handler *hdl = to_cxhdl(ctrl); cx2341x_s_ctrl()
1350 s32 val = ctrl->val; cx2341x_s_ctrl()
1354 switch (ctrl->id) { cx2341x_s_ctrl()
278 cx2341x_get_ctrl(const struct cx2341x_mpeg_params *params, struct v4l2_ext_control *ctrl) cx2341x_get_ctrl() argument
392 cx2341x_set_ctrl(struct cx2341x_mpeg_params *params, int busy, struct v4l2_ext_control *ctrl) cx2341x_set_ctrl() argument
|
| /linux-4.1.27/arch/arm64/include/asm/ |
| H A D | hw_breakpoint.h | 32 struct arch_hw_breakpoint_ctrl ctrl; member in struct:arch_hw_breakpoint
35 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) encode_ctrl_reg() argument
37 return (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | encode_ctrl_reg()
38 ctrl.enabled; encode_ctrl_reg()
42 struct arch_hw_breakpoint_ctrl *ctrl) decode_ctrl_reg()
44 ctrl->enabled = reg & 0x1; decode_ctrl_reg()
46 ctrl->privilege = reg & 0x3; decode_ctrl_reg()
48 ctrl->type = reg & 0x3; decode_ctrl_reg()
50 ctrl->len = reg & 0xff; decode_ctrl_reg()
109 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
41 decode_ctrl_reg(u32 reg, struct arch_hw_breakpoint_ctrl *ctrl) decode_ctrl_reg() argument
|
| /linux-4.1.27/drivers/media/i2c/ |
| H A D | tw2804.c | 147 static inline struct tw2804 *to_state_from_ctrl(struct v4l2_ctrl *ctrl) to_state_from_ctrl() argument
149 return container_of(ctrl->handler, struct tw2804, hdl); to_state_from_ctrl()
176 static int tw2804_g_volatile_ctrl(struct v4l2_ctrl *ctrl) tw2804_g_volatile_ctrl() argument
178 struct tw2804 *state = to_state_from_ctrl(ctrl); tw2804_g_volatile_ctrl()
181 switch (ctrl->id) { tw2804_g_volatile_ctrl()
183 ctrl->val = read_reg(client, TW2804_REG_GAIN, 0); tw2804_g_volatile_ctrl()
187 ctrl->val = read_reg(client, TW2804_REG_CHROMA_GAIN, 0); tw2804_g_volatile_ctrl()
191 ctrl->val = read_reg(client, TW2804_REG_BLUE_BALANCE, 0); tw2804_g_volatile_ctrl()
195 ctrl->val = read_reg(client, TW2804_REG_RED_BALANCE, 0); tw2804_g_volatile_ctrl()
201 static int tw2804_s_ctrl(struct v4l2_ctrl *ctrl) tw2804_s_ctrl() argument
203 struct tw2804 *state = to_state_from_ctrl(ctrl); tw2804_s_ctrl()
208 switch (ctrl->id) { tw2804_s_ctrl()
214 if (ctrl->val == 0) tw2804_s_ctrl()
225 reg = (reg & ~(0x03)) | (ctrl->val == 0 ? 0x02 : 0x03); tw2804_s_ctrl()
229 return write_reg(client, TW2804_REG_GAIN, ctrl->val, 0); tw2804_s_ctrl()
232 return write_reg(client, TW2804_REG_CHROMA_GAIN, ctrl->val, 0); tw2804_s_ctrl()
235 return write_reg(client, TW2804_REG_BLUE_BALANCE, ctrl->val, 0); tw2804_s_ctrl()
238 return write_reg(client, TW2804_REG_RED_BALANCE, ctrl->val, 0); tw2804_s_ctrl()
242 ctrl->val, state->channel); tw2804_s_ctrl()
246 ctrl->val, state->channel); tw2804_s_ctrl()
250 ctrl->val, state->channel); tw2804_s_ctrl()
254 ctrl->val, state->channel); tw2804_s_ctrl()
364 struct v4l2_ctrl *ctrl; tw2804_probe() local
391 ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops, tw2804_probe()
393 if (ctrl) tw2804_probe()
394 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; tw2804_probe()
395 ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops, tw2804_probe()
397 if (ctrl) tw2804_probe()
398 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; tw2804_probe()
399 ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops, tw2804_probe()
401 if (ctrl) tw2804_probe()
402 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; tw2804_probe()
403 ctrl = v4l2_ctrl_new_std(&state->hdl, &tw2804_ctrl_ops, tw2804_probe()
405 if (ctrl) tw2804_probe()
406 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; tw2804_probe()
|
| H A D | lm3646.c | 102 static int lm3646_get_ctrl(struct v4l2_ctrl *ctrl) lm3646_get_ctrl() argument
104 struct lm3646_flash *flash = to_lm3646_flash(ctrl); lm3646_get_ctrl()
108 if (ctrl->id != V4L2_CID_FLASH_FAULT) lm3646_get_ctrl()
115 ctrl->val = 0; lm3646_get_ctrl()
117 ctrl->val |= V4L2_FLASH_FAULT_TIMEOUT; lm3646_get_ctrl()
119 ctrl->val |= V4L2_FLASH_FAULT_SHORT_CIRCUIT; lm3646_get_ctrl()
121 ctrl->val |= V4L2_FLASH_FAULT_UNDER_VOLTAGE; lm3646_get_ctrl()
123 ctrl->val |= V4L2_FLASH_FAULT_INPUT_VOLTAGE; lm3646_get_ctrl()
125 ctrl->val |= V4L2_FLASH_FAULT_OVER_CURRENT; lm3646_get_ctrl()
127 ctrl->val |= V4L2_FLASH_FAULT_OVER_TEMPERATURE; lm3646_get_ctrl()
129 ctrl->val |= V4L2_FLASH_FAULT_LED_OVER_TEMPERATURE; lm3646_get_ctrl()
131 ctrl->val |= V4L2_FLASH_FAULT_OVER_VOLTAGE; lm3646_get_ctrl()
136 static int lm3646_set_ctrl(struct v4l2_ctrl *ctrl) lm3646_set_ctrl() argument
138 struct lm3646_flash *flash = to_lm3646_flash(ctrl); lm3646_set_ctrl()
142 switch (ctrl->id) { lm3646_set_ctrl()
145 if (ctrl->val != V4L2_FLASH_LED_MODE_FLASH) lm3646_set_ctrl()
146 return lm3646_mode_ctrl(flash, ctrl->val); lm3646_set_ctrl()
153 (ctrl->val) << 7); lm3646_set_ctrl()
183 (ctrl->val)); lm3646_set_ctrl()
189 (ctrl->val)); lm3646_set_ctrl()
195 (ctrl->val) << 4); lm3646_set_ctrl()
|
| H A D | lm3560.c | 167 static int lm3560_get_ctrl(struct v4l2_ctrl *ctrl, enum lm3560_led_id led_no) lm3560_get_ctrl() argument
169 struct lm3560_flash *flash = to_lm3560_flash(ctrl, led_no); lm3560_get_ctrl()
174 if (ctrl->id == V4L2_CID_FLASH_FAULT) { lm3560_get_ctrl()
186 ctrl->cur.val = fault; lm3560_get_ctrl()
194 static int lm3560_set_ctrl(struct v4l2_ctrl *ctrl, enum lm3560_led_id led_no) lm3560_set_ctrl() argument
196 struct lm3560_flash *flash = to_lm3560_flash(ctrl, led_no); lm3560_set_ctrl()
202 switch (ctrl->id) { lm3560_set_ctrl()
204 flash->led_mode = ctrl->val; lm3560_set_ctrl()
211 REG_CONFIG1, 0x04, (ctrl->val) << 2); lm3560_set_ctrl()
235 tout_bits = LM3560_FLASH_TOUT_ms_TO_REG(ctrl->val); lm3560_set_ctrl()
241 rval = lm3560_flash_brt_ctrl(flash, led_no, ctrl->val); lm3560_set_ctrl()
245 rval = lm3560_torch_brt_ctrl(flash, led_no, ctrl->val); lm3560_set_ctrl()
254 static int lm3560_led1_get_ctrl(struct v4l2_ctrl *ctrl) lm3560_led1_get_ctrl() argument
256 return lm3560_get_ctrl(ctrl, LM3560_LED1); lm3560_led1_get_ctrl()
259 static int lm3560_led1_set_ctrl(struct v4l2_ctrl *ctrl) lm3560_led1_set_ctrl() argument
261 return lm3560_set_ctrl(ctrl, LM3560_LED1); lm3560_led1_set_ctrl()
264 static int lm3560_led0_get_ctrl(struct v4l2_ctrl *ctrl) lm3560_led0_get_ctrl() argument
266 return lm3560_get_ctrl(ctrl, LM3560_LED0); lm3560_led0_get_ctrl()
269 static int lm3560_led0_set_ctrl(struct v4l2_ctrl *ctrl) lm3560_led0_set_ctrl() argument
271 return lm3560_set_ctrl(ctrl, LM3560_LED0); lm3560_led0_set_ctrl()
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| H A D | as3645a.c | 324 static int as3645a_get_ctrl(struct v4l2_ctrl *ctrl) as3645a_get_ctrl() argument
327 container_of(ctrl->handler, struct as3645a, ctrls); as3645a_get_ctrl()
331 switch (ctrl->id) { as3645a_get_ctrl()
337 ctrl->cur.val = 0; as3645a_get_ctrl()
339 ctrl->cur.val |= V4L2_FLASH_FAULT_SHORT_CIRCUIT; as3645a_get_ctrl()
341 ctrl->cur.val |= V4L2_FLASH_FAULT_OVER_TEMPERATURE; as3645a_get_ctrl()
343 ctrl->cur.val |= V4L2_FLASH_FAULT_TIMEOUT; as3645a_get_ctrl()
345 ctrl->cur.val |= V4L2_FLASH_FAULT_OVER_VOLTAGE; as3645a_get_ctrl()
347 ctrl->cur.val |= V4L2_FLASH_FAULT_OVER_CURRENT; as3645a_get_ctrl()
349 ctrl->cur.val |= V4L2_FLASH_FAULT_INDICATOR; as3645a_get_ctrl()
354 ctrl->cur.val = 0; as3645a_get_ctrl()
362 ctrl->cur.val = value; as3645a_get_ctrl()
366 dev_dbg(&client->dev, "G_CTRL %08x:%d\n", ctrl->id, ctrl->cur.val); as3645a_get_ctrl()
371 static int as3645a_set_ctrl(struct v4l2_ctrl *ctrl) as3645a_set_ctrl() argument
374 container_of(ctrl->handler, struct as3645a, ctrls); as3645a_set_ctrl()
378 dev_dbg(&client->dev, "S_CTRL %08x:%d\n", ctrl->id, ctrl->val); as3645a_set_ctrl()
386 switch (ctrl->id) { as3645a_set_ctrl()
395 flash->led_mode = ctrl->val; as3645a_set_ctrl()
399 flash->strobe_source = ctrl->val; as3645a_set_ctrl()
420 flash->timeout = ctrl->val; as3645a_set_ctrl()
429 flash->flash_current = (ctrl->val - AS3645A_FLASH_INTENSITY_MIN) as3645a_set_ctrl()
440 (ctrl->val - AS3645A_TORCH_INTENSITY_MIN) as3645a_set_ctrl()
454 (ctrl->val - AS3645A_INDICATOR_INTENSITY_MIN) as3645a_set_ctrl()
461 if ((ctrl->val == 0) == (ctrl->cur.val == 0)) as3645a_set_ctrl()
719 struct v4l2_ctrl *ctrl; as3645a_init_controls() local
747 ctrl = v4l2_ctrl_new_std(&flash->ctrls, &as3645a_ctrl_ops, as3645a_init_controls()
749 if (ctrl != NULL) as3645a_init_controls()
750 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; as3645a_init_controls()
793 ctrl = v4l2_ctrl_new_std(&flash->ctrls, &as3645a_ctrl_ops, as3645a_init_controls()
799 if (ctrl != NULL) as3645a_init_controls()
800 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; as3645a_init_controls()
|
| H A D | cs5345.c | 49 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) to_sd() argument
51 return &container_of(ctrl->handler, struct cs5345_state, hdl)->sd; to_sd()
82 static int cs5345_s_ctrl(struct v4l2_ctrl *ctrl) cs5345_s_ctrl() argument
84 struct v4l2_subdev *sd = to_sd(ctrl); cs5345_s_ctrl()
86 switch (ctrl->id) { cs5345_s_ctrl()
88 cs5345_write(sd, 0x04, ctrl->val ? 0x80 : 0); cs5345_s_ctrl()
91 cs5345_write(sd, 0x07, ((u8)ctrl->val) & 0x3f); cs5345_s_ctrl()
92 cs5345_write(sd, 0x08, ((u8)ctrl->val) & 0x3f); cs5345_s_ctrl()
|
| H A D | adv7183_regs.h | 64 #define ADV7183_GEMSTAR_CTRL_1 0x48 /* Gemstar ctrl 1 */
65 #define ADV7183_GEMSTAR_CTRL_2 0x49 /* Gemstar ctrl 2 */
66 #define ADV7183_GEMSTAR_CTRL_3 0x4A /* Gemstar ctrl 3 */
67 #define ADV7183_GEMSTAR_CTRL_4 0x4B /* Gemstar ctrl 4 */
68 #define ADV7183_GEMSTAR_CTRL_5 0x4C /* Gemstar ctrl 5 */
69 #define ADV7183_CTI_DNR_CTRL_1 0x4D /* CTI DNR ctrl 1 */
70 #define ADV7183_CTI_DNR_CTRL_2 0x4E /* CTI DNR ctrl 2 */
71 #define ADV7183_CTI_DNR_CTRL_4 0x50 /* CTI DNR ctrl 4 */
|
| H A D | ml86v7667.c | 100 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) to_sd() argument
102 return &container_of(ctrl->handler, struct ml86v7667_priv, hdl)->sd; to_sd()
116 static int ml86v7667_s_ctrl(struct v4l2_ctrl *ctrl) ml86v7667_s_ctrl() argument
118 struct v4l2_subdev *sd = to_sd(ctrl); ml86v7667_s_ctrl()
122 switch (ctrl->id) { ml86v7667_s_ctrl()
125 SSEPL_LUMINANCE_MASK, ctrl->val); ml86v7667_s_ctrl()
129 CLC_CONTRAST_MASK, ctrl->val); ml86v7667_s_ctrl()
133 ctrl->val << ACCRC_CHROMA_SHIFT); ml86v7667_s_ctrl()
136 ret = ml86v7667_mask_set(client, HUE_REG, ~0, ctrl->val); ml86v7667_s_ctrl()
141 ctrl->val << ACCC_CHROMA_CR_SHIFT); ml86v7667_s_ctrl()
146 ctrl->val << ACCC_CHROMA_CB_SHIFT); ml86v7667_s_ctrl()
151 ctrl->val << LUMC_ONOFF_SHIFT); ml86v7667_s_ctrl()
156 ctrl->val << CHRCA_MODE_SHIFT); ml86v7667_s_ctrl()
|
| H A D | adp1653.c | 151 static int adp1653_get_ctrl(struct v4l2_ctrl *ctrl) adp1653_get_ctrl() argument
154 container_of(ctrl->handler, struct adp1653_flash, ctrls); adp1653_get_ctrl()
161 ctrl->cur.val = 0; adp1653_get_ctrl()
164 ctrl->cur.val |= V4L2_FLASH_FAULT_SHORT_CIRCUIT; adp1653_get_ctrl()
166 ctrl->cur.val |= V4L2_FLASH_FAULT_OVER_TEMPERATURE; adp1653_get_ctrl()
168 ctrl->cur.val |= V4L2_FLASH_FAULT_TIMEOUT; adp1653_get_ctrl()
170 ctrl->cur.val |= V4L2_FLASH_FAULT_OVER_VOLTAGE; adp1653_get_ctrl()
177 static int adp1653_set_ctrl(struct v4l2_ctrl *ctrl) adp1653_set_ctrl() argument
180 container_of(ctrl->handler, struct adp1653_flash, ctrls); adp1653_set_ctrl()
189 (ctrl->id == V4L2_CID_FLASH_STROBE || adp1653_set_ctrl()
190 ctrl->id == V4L2_CID_FLASH_TORCH_INTENSITY || adp1653_set_ctrl()
191 ctrl->id == V4L2_CID_FLASH_LED_MODE)) adp1653_set_ctrl()
194 switch (ctrl->id) { adp1653_set_ctrl()
|
| H A D | tlv320aic23b.c | 53 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) to_sd() argument
55 return &container_of(ctrl->handler, struct tlv320aic23b_state, hdl)->sd; to_sd()
94 static int tlv320aic23b_s_ctrl(struct v4l2_ctrl *ctrl) tlv320aic23b_s_ctrl() argument
96 struct v4l2_subdev *sd = to_sd(ctrl); tlv320aic23b_s_ctrl()
98 switch (ctrl->id) { tlv320aic23b_s_ctrl()
102 if (!ctrl->val) tlv320aic23b_s_ctrl()
|
| H A D | tw9906.c | 121 static int tw9906_s_ctrl(struct v4l2_ctrl *ctrl) tw9906_s_ctrl() argument
123 struct tw9906 *dec = container_of(ctrl->handler, struct tw9906, hdl); tw9906_s_ctrl()
126 switch (ctrl->id) { tw9906_s_ctrl()
128 write_reg(sd, 0x10, ctrl->val); tw9906_s_ctrl()
131 write_reg(sd, 0x11, ctrl->val); tw9906_s_ctrl()
134 write_reg(sd, 0x15, ctrl->val); tw9906_s_ctrl()
|
| /linux-4.1.27/drivers/memory/ |
| H A D | fsl_ifc.c | 75 static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl) fsl_ifc_ctrl_init() argument
77 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_ctrl_init()
98 struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev); fsl_ifc_ctrl_remove() local
100 free_irq(ctrl->nand_irq, ctrl); fsl_ifc_ctrl_remove()
101 free_irq(ctrl->irq, ctrl); fsl_ifc_ctrl_remove()
103 irq_dispose_mapping(ctrl->nand_irq); fsl_ifc_ctrl_remove()
104 irq_dispose_mapping(ctrl->irq); fsl_ifc_ctrl_remove()
106 iounmap(ctrl->regs); fsl_ifc_ctrl_remove()
109 kfree(ctrl); fsl_ifc_ctrl_remove()
122 static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl) check_nand_stat() argument
124 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; check_nand_stat()
133 ctrl->nand_stat = stat; check_nand_stat()
134 wake_up(&ctrl->nand_wait); check_nand_stat()
144 struct fsl_ifc_ctrl *ctrl = data; fsl_ifc_nand_irq() local
146 if (check_nand_stat(ctrl)) fsl_ifc_nand_irq()
158 struct fsl_ifc_ctrl *ctrl = data; fsl_ifc_ctrl_irq() local
159 struct fsl_ifc_regs __iomem *ifc = ctrl->regs; fsl_ifc_ctrl_irq()
166 dev_err(ctrl->dev, "transaction sent to IFC is not mapped to" fsl_ifc_ctrl_irq()
176 dev_err(ctrl->dev, "Read transaction error" fsl_ifc_ctrl_irq()
179 dev_err(ctrl->dev, "Write transaction error" fsl_ifc_ctrl_irq()
184 dev_err(ctrl->dev, "AXI ID of the error" fsl_ifc_ctrl_irq()
189 dev_err(ctrl->dev, "SRC ID of the error" fsl_ifc_ctrl_irq()
192 dev_err(ctrl->dev, "Transaction Address corresponding to error" fsl_ifc_ctrl_irq()
198 if (check_nand_stat(ctrl)) fsl_ifc_ctrl_irq()
|
| /linux-4.1.27/drivers/crypto/caam/ |
| H A D | Makefile | 14 caam-objs := ctrl.o
|
| H A D | ctrl.c | 83 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl; run_descriptor_deco0() local
91 setbits32(&ctrl->deco_rsr, DECORSR_JR0); run_descriptor_deco0()
93 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) && run_descriptor_deco0()
100 setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); run_descriptor_deco0()
102 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) && run_descriptor_deco0()
108 clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); run_descriptor_deco0()
143 clrbits32(&ctrl->deco_rsr, DECORSR_JR0); run_descriptor_deco0()
146 clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE); run_descriptor_deco0()
177 struct caam_ctrl __iomem *ctrl; instantiate_rng() local
181 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; instantiate_rng()
209 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; instantiate_rng()
281 struct caam_ctrl __iomem *ctrl; caam_remove() local
286 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; caam_remove()
304 iounmap(&ctrl); caam_remove()
319 struct caam_ctrl __iomem *ctrl; kick_trng() local
323 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl; kick_trng()
324 r4tst = &ctrl->r4tst[0]; kick_trng()
391 struct caam_ctrl __iomem *ctrl; caam_probe() local
413 ctrl = of_iomap(nprop, 0); caam_probe()
414 if (ctrl == NULL) { caam_probe()
419 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms); caam_probe()
430 ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl; caam_probe()
432 ((uint8_t *)ctrl + caam_probe()
436 ((uint8_t *)ctrl + caam_probe()
447 setbits32(&ctrl->mcr, MCFGR_WDENABLE | caam_probe()
454 scfgr = rd_reg32(&ctrl->scfgr); caam_probe()
472 setbits32(&ctrl->jrstart, JRSTART_JR0_START | caam_probe()
499 iounmap(&ctrl); caam_probe()
516 ((uint8_t *)ctrl + for_each_available_child_of_node()
526 !!(rd_reg32(&ctrl->perfmon.comp_parms_ms) &
530 ((uint8_t *)ctrl +
544 cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
552 rd_reg32(&ctrl->r4tst[0].rdsta);
563 rd_reg32(&ctrl->r4tst[0].rdsta) &
608 setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
613 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
614 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
628 perfmon = (struct caam_perfmon __force *)&ctrl->perfmon;
678 ctrlpriv->ctl_kek_wrap.data = &ctrlpriv->ctrl->kek[0];
686 ctrlpriv->ctl_tkek_wrap.data = &ctrlpriv->ctrl->tkek[0];
694 ctrlpriv->ctl_tdsk_wrap.data = &ctrlpriv->ctrl->tdsk[0];
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/ |
| H A D | nouveau_sysfs.h | 7 struct nvif_object ctrl; member in struct:nouveau_sysfs
|
| H A D | nouveau_sysfs.c | 56 ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_INFO, nouveau_sysfs_pstate_get()
69 ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_ATTR, nouveau_sysfs_pstate_get()
84 ret = nvif_mthd(&sysfs->ctrl, nouveau_sysfs_pstate_get()
149 ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_USER, nouveau_sysfs_pstate_set()
167 if (sysfs && sysfs->ctrl.priv) { nouveau_sysfs_fini()
169 nvif_object_fini(&sysfs->ctrl); nouveau_sysfs_fini()
193 &sysfs->ctrl); nouveau_sysfs_init()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | nv40.h | 7 u32 ctrl; member in struct:nv40_ram
|
| /linux-4.1.27/arch/mips/oprofile/ |
| H A D | op_model_loongson2.c | 37 unsigned int ctrl; member in struct:loongson2_register_config
54 unsigned int ctrl = 0; loongson2_reg_setup() local
60 * Compute the performance counter ctrl word. loongson2_reg_setup()
64 ctrl |= LOONGSON2_PERFCTRL_EVENT(0, cfg[0].event); loongson2_reg_setup()
69 ctrl |= LOONGSON2_PERFCTRL_EVENT(1, cfg[1].event); loongson2_reg_setup()
74 ctrl |= LOONGSON2_PERFCTRL_EXL | LOONGSON2_PERFCTRL_ENABLE; loongson2_reg_setup()
76 ctrl |= LOONGSON2_PERFCTRL_KERNEL; loongson2_reg_setup()
78 ctrl |= LOONGSON2_PERFCTRL_USER; loongson2_reg_setup()
81 reg.ctrl = ctrl; loongson2_reg_setup()
96 write_c0_perfctrl(reg.ctrl); loongson2_cpu_start()
|
| /linux-4.1.27/arch/arm/mach-ks8695/ |
| H A D | irq.c | 69 unsigned long ctrl, mode; ks8695_irq_set_type() local
72 ctrl = __raw_readl(KS8695_GPIO_VA + KS8695_IOPC); ks8695_irq_set_type()
98 ctrl &= ~IOPC_IOEINT0TM; ks8695_irq_set_type()
99 ctrl |= IOPC_IOEINT0_MODE(mode); ks8695_irq_set_type()
102 ctrl &= ~IOPC_IOEINT1TM; ks8695_irq_set_type()
103 ctrl |= IOPC_IOEINT1_MODE(mode); ks8695_irq_set_type()
106 ctrl &= ~IOPC_IOEINT2TM; ks8695_irq_set_type()
107 ctrl |= IOPC_IOEINT2_MODE(mode); ks8695_irq_set_type()
110 ctrl &= ~IOPC_IOEINT3TM; ks8695_irq_set_type()
111 ctrl |= IOPC_IOEINT3_MODE(mode); ks8695_irq_set_type()
126 __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); ks8695_irq_set_type()
|
| /linux-4.1.27/drivers/clk/mvebu/ |
| H A D | common.c | 204 static struct clk_gating_ctrl *ctrl; variable in typeref:struct:clk_gating_ctrl
214 for (n = 0; n < ctrl->num_gates; n++) { clk_gating_get_src()
216 to_clk_gate(__clk_get_hw(ctrl->gates[n])); clk_gating_get_src()
218 return ctrl->gates[n]; clk_gating_get_src()
225 ctrl->saved_reg = readl(ctrl->base); mvebu_clk_gating_suspend()
231 writel(ctrl->saved_reg, ctrl->base); mvebu_clk_gating_resume()
247 if (ctrl) { mvebu_clk_gating_setup()
262 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); mvebu_clk_gating_setup()
263 if (WARN_ON(!ctrl)) mvebu_clk_gating_setup()
267 ctrl->lock = &ctrl_gating_lock; mvebu_clk_gating_setup()
269 ctrl->base = base; mvebu_clk_gating_setup()
275 ctrl->num_gates = n; mvebu_clk_gating_setup()
276 ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *), mvebu_clk_gating_setup()
278 if (WARN_ON(!ctrl->gates)) mvebu_clk_gating_setup()
281 for (n = 0; n < ctrl->num_gates; n++) { mvebu_clk_gating_setup()
284 ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent, mvebu_clk_gating_setup()
286 0, ctrl->lock); mvebu_clk_gating_setup()
287 WARN_ON(IS_ERR(ctrl->gates[n])); mvebu_clk_gating_setup()
290 of_clk_add_provider(np, clk_gating_get_src, ctrl); mvebu_clk_gating_setup()
296 kfree(ctrl); mvebu_clk_gating_setup()
|
| H A D | kirkwood.c | 264 struct clk_muxing_ctrl *ctrl = (struct clk_muxing_ctrl *)data; clk_muxing_get_src() local
270 for (n = 0; n < ctrl->num_muxes; n++) { clk_muxing_get_src()
272 to_clk_mux(__clk_get_hw(ctrl->muxes[n])); clk_muxing_get_src()
274 return ctrl->muxes[n]; clk_muxing_get_src()
282 struct clk_muxing_ctrl *ctrl; kirkwood_clk_muxing_setup() local
290 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL); kirkwood_clk_muxing_setup()
291 if (WARN_ON(!ctrl)) kirkwood_clk_muxing_setup()
295 ctrl->lock = &ctrl_gating_lock; kirkwood_clk_muxing_setup()
301 ctrl->num_muxes = n; kirkwood_clk_muxing_setup()
302 ctrl->muxes = kcalloc(ctrl->num_muxes, sizeof(struct clk *), kirkwood_clk_muxing_setup()
304 if (WARN_ON(!ctrl->muxes)) kirkwood_clk_muxing_setup()
307 for (n = 0; n < ctrl->num_muxes; n++) { kirkwood_clk_muxing_setup()
308 ctrl->muxes[n] = clk_register_mux(NULL, desc[n].name, kirkwood_clk_muxing_setup()
311 desc[n].width, desc[n].flags, ctrl->lock); kirkwood_clk_muxing_setup()
312 WARN_ON(IS_ERR(ctrl->muxes[n])); kirkwood_clk_muxing_setup()
315 of_clk_add_provider(np, clk_muxing_get_src, ctrl); kirkwood_clk_muxing_setup()
319 kfree(ctrl); kirkwood_clk_muxing_setup()
|
| /linux-4.1.27/arch/mips/jz4740/ |
| H A D | setup.c | 34 u32 ctrl, bus, bank, rows, cols; jz4740_detect_mem() local
38 ctrl = readl(jz_emc_base + JZ4740_EMC_SDRAM_CTRL); jz4740_detect_mem()
39 bus = 2 - ((ctrl >> 31) & 1); jz4740_detect_mem()
40 bank = 1 + ((ctrl >> 19) & 1); jz4740_detect_mem()
41 cols = 8 + ((ctrl >> 26) & 7); jz4740_detect_mem()
42 rows = 11 + ((ctrl >> 20) & 3); jz4740_detect_mem()
|
| H A D | time.c | 116 uint16_t ctrl; plat_time_init() local
139 ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT; plat_time_init()
141 jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl); plat_time_init()
142 jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl); plat_time_init()
|
| H A D | reset.c | 70 uint32_t ctrl; jz4740_rtc_wait_ready() local
73 ctrl = readl(rtc_base + JZ_REG_RTC_CTRL); jz4740_rtc_wait_ready()
74 } while (!(ctrl & JZ_RTC_CTRL_WRDY)); jz4740_rtc_wait_ready()
|
| /linux-4.1.27/drivers/net/ethernet/freescale/fs_enet/ |
| H A D | mii-bitbang.c | 31 struct mdiobb_ctrl ctrl; member in struct:bb_info
58 static inline void mdio_dir(struct mdiobb_ctrl *ctrl, int dir) mdio_dir() argument
60 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); mdio_dir()
71 static inline int mdio_read(struct mdiobb_ctrl *ctrl) mdio_read() argument
73 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); mdio_read()
77 static inline void mdio(struct mdiobb_ctrl *ctrl, int what) mdio() argument
79 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); mdio()
90 static inline void mdc(struct mdiobb_ctrl *ctrl, int what) mdc() argument
92 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); mdc()
162 bitbang->ctrl.ops = &bb_ops; fs_enet_mdio_probe()
164 new_bus = alloc_mdio_bitbang(&bitbang->ctrl); fs_enet_mdio_probe()
|
| /linux-4.1.27/sound/soc/codecs/ |
| H A D | sigmadsp.c | 108 struct sigmadsp_control *ctrl = (void *)kcontrol->private_value; sigmadsp_ctrl_info() local
111 info->count = ctrl->num_bytes; sigmadsp_ctrl_info()
117 struct sigmadsp_control *ctrl, void *data) sigmadsp_ctrl_write()
120 if (ctrl->num_bytes > 4 && ctrl->num_bytes <= 20 && sigmadsp->ops && sigmadsp_ctrl_write()
122 return sigmadsp->ops->safeload(sigmadsp, ctrl->addr, data, sigmadsp_ctrl_write()
123 ctrl->num_bytes); sigmadsp_ctrl_write()
125 return sigmadsp_write(sigmadsp, ctrl->addr, data, sigmadsp_ctrl_write()
126 ctrl->num_bytes); sigmadsp_ctrl_write()
132 struct sigmadsp_control *ctrl = (void *)kcontrol->private_value; sigmadsp_ctrl_put() local
142 ret = sigmadsp_ctrl_write(sigmadsp, ctrl, data); sigmadsp_ctrl_put()
145 memcpy(ctrl->cache, data, ctrl->num_bytes); sigmadsp_ctrl_put()
146 ctrl->cached = true; sigmadsp_ctrl_put()
157 struct sigmadsp_control *ctrl = (void *)kcontrol->private_value; sigmadsp_ctrl_get() local
163 if (!ctrl->cached) { sigmadsp_ctrl_get()
164 ret = sigmadsp_read(sigmadsp, ctrl->addr, ctrl->cache, sigmadsp_ctrl_get()
165 ctrl->num_bytes); sigmadsp_ctrl_get()
169 ctrl->cached = true; sigmadsp_ctrl_get()
170 memcpy(ucontrol->value.bytes.data, ctrl->cache, sigmadsp_ctrl_get()
171 ctrl->num_bytes); sigmadsp_ctrl_get()
181 struct sigmadsp_control *ctrl = (void *)kcontrol->private_value; sigmadsp_control_free() local
183 ctrl->kcontrol = NULL; sigmadsp_control_free()
203 struct sigmadsp_control *ctrl; sigma_fw_load_control() local
223 ctrl = kzalloc(sizeof(*ctrl) + num_bytes, GFP_KERNEL); sigma_fw_load_control()
224 if (!ctrl) sigma_fw_load_control()
234 ctrl->name = name; sigma_fw_load_control()
236 ctrl->addr = le16_to_cpu(ctrl_chunk->addr); sigma_fw_load_control()
237 ctrl->num_bytes = num_bytes; sigma_fw_load_control()
238 ctrl->samplerates = le32_to_cpu(chunk->samplerates); sigma_fw_load_control()
240 list_add_tail(&ctrl->head, &sigmadsp->ctrl_list); sigma_fw_load_control()
245 kfree(ctrl); sigma_fw_load_control()
457 struct sigmadsp_control *ctrl, *_ctrl; sigmadsp_firmware_release() local
460 list_for_each_entry_safe(ctrl, _ctrl, &sigmadsp->ctrl_list, head) { sigmadsp_firmware_release()
461 kfree(ctrl->name); sigmadsp_firmware_release()
462 kfree(ctrl); sigmadsp_firmware_release()
632 struct sigmadsp_control *ctrl, unsigned int samplerate_mask) sigmadsp_alloc_control()
639 template.name = ctrl->name; sigmadsp_alloc_control()
643 template.private_value = (unsigned long)ctrl; sigmadsp_alloc_control()
645 if (!sigmadsp_samplerate_valid(ctrl->samplerates, samplerate_mask)) sigmadsp_alloc_control()
653 ctrl->kcontrol = kcontrol; sigmadsp_alloc_control()
659 struct sigmadsp_control *ctrl, unsigned int samplerate_mask) sigmadsp_activate_ctrl()
667 active = sigmadsp_samplerate_valid(ctrl->samplerates, samplerate_mask); sigmadsp_activate_ctrl()
670 if (!ctrl->kcontrol) { sigmadsp_activate_ctrl()
675 id = ctrl->kcontrol->id; sigmadsp_activate_ctrl()
676 vd = &ctrl->kcontrol->vd[0]; sigmadsp_activate_ctrl()
685 if (ctrl->cached) sigmadsp_activate_ctrl()
686 sigmadsp_ctrl_write(sigmadsp, ctrl, ctrl->cache); sigmadsp_activate_ctrl()
708 struct sigmadsp_control *ctrl; sigmadsp_attach() local
717 list_for_each_entry(ctrl, &sigmadsp->ctrl_list, head) { sigmadsp_attach()
718 ret = sigmadsp_alloc_control(sigmadsp, ctrl, samplerate_mask); sigmadsp_attach()
740 struct sigmadsp_control *ctrl; sigmadsp_setup() local
762 list_for_each_entry(ctrl, &sigmadsp->ctrl_list, head) sigmadsp_setup()
763 sigmadsp_activate_ctrl(sigmadsp, ctrl, samplerate_mask); sigmadsp_setup()
784 struct sigmadsp_control *ctrl; sigmadsp_reset() local
786 list_for_each_entry(ctrl, &sigmadsp->ctrl_list, head) sigmadsp_reset()
787 sigmadsp_activate_ctrl(sigmadsp, ctrl, false); sigmadsp_reset()
116 sigmadsp_ctrl_write(struct sigmadsp *sigmadsp, struct sigmadsp_control *ctrl, void *data) sigmadsp_ctrl_write() argument
631 sigmadsp_alloc_control(struct sigmadsp *sigmadsp, struct sigmadsp_control *ctrl, unsigned int samplerate_mask) sigmadsp_alloc_control() argument
658 sigmadsp_activate_ctrl(struct sigmadsp *sigmadsp, struct sigmadsp_control *ctrl, unsigned int samplerate_mask) sigmadsp_activate_ctrl() argument
|
| /linux-4.1.27/drivers/macintosh/ |
| H A D | windfarm_smu_controls.c | 50 struct wf_control ctrl; member in struct:smu_fan_control
52 #define to_smu_fan(c) container_of(c, struct smu_fan_control, ctrl)
168 fct->ctrl.ops = &smu_fan_ops; smu_fan_create()
174 fct->ctrl.type = pwm_fan ? WF_CONTROL_PWM_FAN : WF_CONTROL_RPM_FAN; smu_fan_create()
185 fct->ctrl.name = NULL; smu_fan_create()
191 fct->ctrl.name = "cpu-rear-fan-0"; smu_fan_create()
194 fct->ctrl.name = "cpu-rear-fan-1"; smu_fan_create()
198 fct->ctrl.name = "cpu-front-fan-0"; smu_fan_create()
201 fct->ctrl.name = "cpu-front-fan-1"; smu_fan_create()
203 fct->ctrl.name = "cpu-pump-0"; smu_fan_create()
205 fct->ctrl.name = "cpu-pump-1"; smu_fan_create()
208 fct->ctrl.name = "slots-fan"; smu_fan_create()
211 fct->ctrl.name = "drive-bay-fan"; smu_fan_create()
213 fct->ctrl.name = "backside-fan"; smu_fan_create()
217 fct->ctrl.name = "system-fan"; smu_fan_create()
219 fct->ctrl.name = "cpu-fan"; smu_fan_create()
221 fct->ctrl.name = "drive-bay-fan"; smu_fan_create()
223 fct->ctrl.name = "hard-drive-fan"; smu_fan_create()
225 fct->ctrl.name = "optical-drive-fan"; smu_fan_create()
228 if (fct->ctrl.name == NULL) smu_fan_create()
247 if (wf_register_control(&fct->ctrl)) smu_fan_create()
317 wf_unregister_control(&fct->ctrl); smu_controls_exit()
|
| H A D | macio-adb.c | 31 struct preg ctrl; member in struct:adb_regs
50 /* Bits in ctrl register */
110 out_8(&adb->ctrl.r, 0); macio_init()
153 out_8(&adb->ctrl.r, in_8(&adb->ctrl.r) | ADB_RST); macio_adb_reset_bus()
154 while ((in_8(&adb->ctrl.r) & ADB_RST) != 0) { macio_adb_reset_bus()
156 out_8(&adb->ctrl.r, in_8(&adb->ctrl.r) & ~ADB_RST); macio_adb_reset_bus()
189 out_8(&adb->ctrl.r, in_8(&adb->ctrl.r) | TAR); macio_send_request()
221 out_8(&adb->ctrl.r, DTB + CRE); macio_adb_interrupt()
223 out_8(&adb->ctrl.r, DTB); macio_adb_interrupt()
227 out_8(&adb->ctrl.r, in_8(&adb->ctrl.r) | TAR); macio_adb_interrupt()
247 out_8(&adb->ctrl.r, in_8(&adb->ctrl.r) | TAR); macio_adb_interrupt()
|
| H A D | windfarm_fcu_controls.c | 69 struct wf_control ctrl; member in struct:wf_fcu_fan
317 fan->ctrl.name, pump_min, pump_max); wf_fcu_get_pump_minmax()
331 if (mpu0 && !strcmp(fan->ctrl.name, "cpu-front-fan-0")) { wf_fcu_get_rpmfan_minmax()
336 if (mpu1 && !strcmp(fan->ctrl.name, "cpu-front-fan-1")) { wf_fcu_get_rpmfan_minmax()
341 if (mpu0 && !strcmp(fan->ctrl.name, "cpu-rear-fan-0")) { wf_fcu_get_rpmfan_minmax()
346 if (mpu1 && !strcmp(fan->ctrl.name, "cpu-rear-fan-1")) { wf_fcu_get_rpmfan_minmax()
352 if (!strncmp(fan->ctrl.name, "cpu-fan", 7)) { wf_fcu_get_rpmfan_minmax()
359 fan->ctrl.name, fan->min, fan->max); wf_fcu_get_rpmfan_minmax()
372 fan->ctrl.name = name; wf_fcu_add_fan()
373 fan->ctrl.priv = fan; wf_fcu_add_fan()
383 fan->ctrl.type = WF_CONTROL_RPM_FAN; wf_fcu_add_fan()
384 fan->ctrl.ops = &wf_fcu_fan_rpm_ops; wf_fcu_add_fan()
388 fan->ctrl.type = WF_CONTROL_PWM_FAN; wf_fcu_add_fan()
389 fan->ctrl.ops = &wf_fcu_fan_pwm_ops; wf_fcu_add_fan()
392 if (wf_register_control(&fan->ctrl)) { wf_fcu_add_fan()
574 wf_unregister_control(&fan->ctrl); wf_fcu_remove()
|
| /linux-4.1.27/drivers/hwmon/ |
| H A D | lm73.c | 60 u8 ctrl; /* control register value */ member in struct:lm73_data
124 data->ctrl &= LM73_CTRL_TO_MASK; set_convrate()
125 data->ctrl |= res << LM73_CTRL_RES_SHIFT; set_convrate()
127 data->ctrl); set_convrate()
142 res = (data->ctrl & LM73_CTRL_RES_MASK) >> LM73_CTRL_RES_SHIFT; show_convrate()
151 s32 ctrl; show_maxmin_alarm() local
154 ctrl = i2c_smbus_read_byte_data(data->client, LM73_REG_CTRL); show_maxmin_alarm()
155 if (ctrl < 0) show_maxmin_alarm()
157 data->ctrl = ctrl; show_maxmin_alarm()
160 return scnprintf(buf, PAGE_SIZE, "%d\n", (ctrl >> attr->index) & 1); show_maxmin_alarm()
164 return ctrl; show_maxmin_alarm()
205 int ctrl; lm73_probe() local
214 ctrl = i2c_smbus_read_byte_data(client, LM73_REG_CTRL); lm73_probe()
215 if (ctrl < 0) lm73_probe()
216 return ctrl; lm73_probe()
217 data->ctrl = ctrl; lm73_probe()
240 int id, ctrl, conf; lm73_detect() local
250 ctrl = i2c_smbus_read_byte_data(new_client, LM73_REG_CTRL); lm73_detect()
251 if (ctrl < 0 || (ctrl & 0x10)) lm73_detect()
|
| H A D | gpio-fan.c | 46 unsigned *ctrl; member in struct:gpio_fan_data
137 gpio_set_value_cansleep(fan_data->ctrl[i], (ctrl_val >> i) & 1); __set_fan_ctrl()
148 value = gpio_get_value_cansleep(fan_data->ctrl[i]); __get_fan_ctrl()
333 if (index > 0 && !data->ctrl) gpio_fan_is_visible()
366 unsigned *ctrl = pdata->ctrl; fan_ctrl_init() local
370 err = devm_gpio_request(&pdev->dev, ctrl[i], fan_ctrl_init()
375 err = gpio_direction_output(ctrl[i], fan_ctrl_init()
376 gpio_get_value_cansleep(ctrl[i])); fan_ctrl_init()
382 fan_data->ctrl = ctrl; fan_ctrl_init()
444 unsigned *ctrl; gpio_fan_get_of_pdata() local
480 ctrl = devm_kzalloc(dev, pdata->num_ctrl * sizeof(unsigned), gpio_fan_get_of_pdata()
482 if (!ctrl) gpio_fan_get_of_pdata()
490 ctrl[i] = val; gpio_fan_get_of_pdata()
492 pdata->ctrl = ctrl; gpio_fan_get_of_pdata()
579 if (pdata->ctrl && pdata->num_ctrl > 0) { gpio_fan_probe()
618 if (fan_data->ctrl) gpio_fan_remove()
634 if (fan_data->ctrl) { gpio_fan_suspend()
646 if (fan_data->ctrl) gpio_fan_resume()
|
| /linux-4.1.27/drivers/media/platform/vivid/ |
| H A D | vivid-ctrls.c | 104 static int vivid_user_gen_s_ctrl(struct v4l2_ctrl *ctrl) vivid_user_gen_s_ctrl() argument
106 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_user_gen); vivid_user_gen_s_ctrl()
108 switch (ctrl->id) { vivid_user_gen_s_ctrl()
283 static int vivid_user_vid_g_volatile_ctrl(struct v4l2_ctrl *ctrl) vivid_user_vid_g_volatile_ctrl() argument
285 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_user_vid); vivid_user_vid_g_volatile_ctrl()
287 switch (ctrl->id) { vivid_user_vid_g_volatile_ctrl()
295 static int vivid_user_vid_s_ctrl(struct v4l2_ctrl *ctrl) vivid_user_vid_s_ctrl() argument
297 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_user_vid); vivid_user_vid_s_ctrl()
299 switch (ctrl->id) { vivid_user_vid_s_ctrl()
301 dev->input_brightness[dev->input] = ctrl->val - dev->input * 128; vivid_user_vid_s_ctrl()
305 tpg_s_contrast(&dev->tpg, ctrl->val); vivid_user_vid_s_ctrl()
308 tpg_s_saturation(&dev->tpg, ctrl->val); vivid_user_vid_s_ctrl()
311 tpg_s_hue(&dev->tpg, ctrl->val); vivid_user_vid_s_ctrl()
314 dev->hflip = ctrl->val; vivid_user_vid_s_ctrl()
318 dev->vflip = ctrl->val; vivid_user_vid_s_ctrl()
322 tpg_s_alpha_component(&dev->tpg, ctrl->val); vivid_user_vid_s_ctrl()
336 static int vivid_vid_cap_s_ctrl(struct v4l2_ctrl *ctrl) vivid_vid_cap_s_ctrl() argument
348 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_vid_cap); vivid_vid_cap_s_ctrl()
351 switch (ctrl->id) { vivid_vid_cap_s_ctrl()
354 tpg_s_pattern(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
357 tpg_s_colorspace(&dev->tpg, colorspaces[ctrl->val]); vivid_vid_cap_s_ctrl()
364 tpg_s_ycbcr_enc(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
371 tpg_s_quantization(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
380 tpg_s_rgb_range(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
383 tpg_s_real_rgb_range(&dev->tpg, ctrl->val ? vivid_vid_cap_s_ctrl()
387 tpg_s_alpha_mode(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
390 tpg_s_mv_hor_mode(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
393 tpg_s_mv_vert_mode(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
396 dev->osd_mode = ctrl->val; vivid_vid_cap_s_ctrl()
399 tpg_s_perc_fill(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
401 dev->must_blank[i] = ctrl->val < 100; vivid_vid_cap_s_ctrl()
404 tpg_s_insert_sav(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
407 tpg_s_insert_eav(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
410 dev->sensor_hflip = ctrl->val; vivid_vid_cap_s_ctrl()
414 dev->sensor_vflip = ctrl->val; vivid_vid_cap_s_ctrl()
418 dev->has_crop_cap = ctrl->val; vivid_vid_cap_s_ctrl()
422 dev->has_compose_cap = ctrl->val; vivid_vid_cap_s_ctrl()
426 dev->has_scaler_cap = ctrl->val; vivid_vid_cap_s_ctrl()
430 tpg_s_show_border(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
433 tpg_s_show_square(&dev->tpg, ctrl->val); vivid_vid_cap_s_ctrl()
436 dev->std_aspect_ratio = ctrl->val; vivid_vid_cap_s_ctrl()
449 dev->dv_timings_aspect_ratio = ctrl->val; vivid_vid_cap_s_ctrl()
453 dev->tstamp_src_is_soe = ctrl->val; vivid_vid_cap_s_ctrl()
459 dev->edid_max_blocks = ctrl->val; vivid_vid_cap_s_ctrl()
771 static int vivid_vbi_cap_s_ctrl(struct v4l2_ctrl *ctrl) vivid_vbi_cap_s_ctrl() argument
773 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_vbi_cap); vivid_vbi_cap_s_ctrl()
775 switch (ctrl->id) { vivid_vbi_cap_s_ctrl()
777 dev->vbi_cap_interlaced = ctrl->val; vivid_vbi_cap_s_ctrl()
799 static int vivid_vid_out_s_ctrl(struct v4l2_ctrl *ctrl) vivid_vid_out_s_ctrl() argument
801 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_vid_out); vivid_vid_out_s_ctrl()
804 switch (ctrl->id) { vivid_vid_out_s_ctrl()
806 dev->has_crop_out = ctrl->val; vivid_vid_out_s_ctrl()
810 dev->has_compose_out = ctrl->val; vivid_vid_out_s_ctrl()
814 dev->has_scaler_out = ctrl->val; vivid_vid_out_s_ctrl()
818 dev->dvi_d_out = ctrl->val == V4L2_DV_TX_MODE_DVI_D; vivid_vid_out_s_ctrl()
877 static int vivid_streaming_s_ctrl(struct v4l2_ctrl *ctrl) vivid_streaming_s_ctrl() argument
879 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_streaming); vivid_streaming_s_ctrl()
882 switch (ctrl->id) { vivid_streaming_s_ctrl()
887 dev->perc_dropped_buffers = ctrl->val; vivid_streaming_s_ctrl()
911 dev->seq_wrap = ctrl->val; vivid_streaming_s_ctrl()
914 dev->time_wrap = ctrl->val; vivid_streaming_s_ctrl()
915 if (ctrl->val == 0) { vivid_streaming_s_ctrl()
996 static int vivid_sdtv_cap_s_ctrl(struct v4l2_ctrl *ctrl) vivid_sdtv_cap_s_ctrl() argument
998 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_sdtv_cap); vivid_sdtv_cap_s_ctrl()
1000 switch (ctrl->id) { vivid_sdtv_cap_s_ctrl()
1051 static int vivid_radio_rx_s_ctrl(struct v4l2_ctrl *ctrl) vivid_radio_rx_s_ctrl() argument
1053 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_radio_rx); vivid_radio_rx_s_ctrl()
1055 switch (ctrl->id) { vivid_radio_rx_s_ctrl()
1057 dev->radio_rx_hw_seek_mode = ctrl->val; vivid_radio_rx_s_ctrl()
1060 dev->radio_rx_hw_seek_prog_lim = ctrl->val; vivid_radio_rx_s_ctrl()
1063 dev->rds_gen.use_rbds = ctrl->val; vivid_radio_rx_s_ctrl()
1066 dev->radio_rx_rds_controls = ctrl->val; vivid_radio_rx_s_ctrl()
1086 dev->radio_rx_rds_enabled = ctrl->val; vivid_radio_rx_s_ctrl()
1148 static int vivid_radio_tx_s_ctrl(struct v4l2_ctrl *ctrl) vivid_radio_tx_s_ctrl() argument
1150 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_radio_tx); vivid_radio_tx_s_ctrl()
1152 switch (ctrl->id) { vivid_radio_tx_s_ctrl()
1154 dev->radio_tx_rds_controls = ctrl->val; vivid_radio_tx_s_ctrl()
1161 v4l2_ctrl_s_ctrl(dev->radio_rx_rds_pty, ctrl->val); vivid_radio_tx_s_ctrl()
1165 v4l2_ctrl_s_ctrl_string(dev->radio_rx_rds_psname, ctrl->p_new.p_char); vivid_radio_tx_s_ctrl()
1169 v4l2_ctrl_s_ctrl_string(dev->radio_rx_rds_radiotext, ctrl->p_new.p_char); vivid_radio_tx_s_ctrl()
1173 v4l2_ctrl_s_ctrl(dev->radio_rx_rds_ta, ctrl->val); vivid_radio_tx_s_ctrl()
1177 v4l2_ctrl_s_ctrl(dev->radio_rx_rds_tp, ctrl->val); vivid_radio_tx_s_ctrl()
1181 v4l2_ctrl_s_ctrl(dev->radio_rx_rds_ms, ctrl->val); vivid_radio_tx_s_ctrl()
1205 static int vivid_loop_out_s_ctrl(struct v4l2_ctrl *ctrl) vivid_loop_out_s_ctrl() argument
1207 struct vivid_dev *dev = container_of(ctrl->handler, struct vivid_dev, ctrl_hdl_loop_out); vivid_loop_out_s_ctrl()
1209 switch (ctrl->id) { vivid_loop_out_s_ctrl()
1211 dev->loop_video = ctrl->val; vivid_loop_out_s_ctrl()
|
| /linux-4.1.27/drivers/dma/ |
| H A D | moxart-dma.c | 190 u32 ctrl; moxart_terminate_all() local
201 ctrl = readl(ch->base + REG_OFF_CTRL); moxart_terminate_all()
202 ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); moxart_terminate_all()
203 writel(ctrl, ch->base + REG_OFF_CTRL); moxart_terminate_all()
216 u32 ctrl; moxart_slave_config() local
220 ctrl = readl(ch->base + REG_OFF_CTRL); moxart_slave_config()
221 ctrl |= APB_DMA_BURST_MODE; moxart_slave_config()
222 ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK); moxart_slave_config()
223 ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK); moxart_slave_config()
227 ctrl |= APB_DMA_DATA_WIDTH_1; moxart_slave_config()
229 ctrl |= APB_DMA_DEST_INC_1_4; moxart_slave_config()
231 ctrl |= APB_DMA_SOURCE_INC_1_4; moxart_slave_config()
234 ctrl |= APB_DMA_DATA_WIDTH_2; moxart_slave_config()
236 ctrl |= APB_DMA_DEST_INC_2_8; moxart_slave_config()
238 ctrl |= APB_DMA_SOURCE_INC_2_8; moxart_slave_config()
241 ctrl &= ~APB_DMA_DATA_WIDTH; moxart_slave_config()
243 ctrl |= APB_DMA_DEST_INC_4_16; moxart_slave_config()
245 ctrl |= APB_DMA_SOURCE_INC_4_16; moxart_slave_config()
252 ctrl &= ~APB_DMA_DEST_SELECT; moxart_slave_config()
253 ctrl |= APB_DMA_SOURCE_SELECT; moxart_slave_config()
254 ctrl |= (ch->line_reqno << 16 & moxart_slave_config()
257 ctrl |= APB_DMA_DEST_SELECT; moxart_slave_config()
258 ctrl &= ~APB_DMA_SOURCE_SELECT; moxart_slave_config()
259 ctrl |= (ch->line_reqno << 24 & moxart_slave_config()
263 writel(ctrl, ch->base + REG_OFF_CTRL); moxart_slave_config()
396 u32 ctrl; moxart_start_dma() local
398 ctrl = readl(ch->base + REG_OFF_CTRL); moxart_start_dma()
399 ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); moxart_start_dma()
400 writel(ctrl, ch->base + REG_OFF_CTRL); moxart_start_dma()
527 u32 ctrl; moxart_dma_interrupt() local
535 ctrl = readl(ch->base + REG_OFF_CTRL); moxart_dma_interrupt()
537 dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n", moxart_dma_interrupt()
538 __func__, ch, ch->base, ctrl); moxart_dma_interrupt() local
540 if (ctrl & APB_DMA_FIN_INT_STS) { moxart_dma_interrupt()
541 ctrl &= ~APB_DMA_FIN_INT_STS; moxart_dma_interrupt()
554 if (ctrl & APB_DMA_ERR_INT_STS) { moxart_dma_interrupt()
555 ctrl &= ~APB_DMA_ERR_INT_STS; moxart_dma_interrupt()
559 writel(ctrl, ch->base + REG_OFF_CTRL); moxart_dma_interrupt()
|
| H A D | coh901318.h | 90 * @ctrl_chained: ctrl for chained lli
91 * @ctrl_last: ctrl for the last lli
107 * @ctrl_chained: ctrl for chained lli
108 * @ctrl_last: ctrl for the last lli
126 * @ctrl_chained: ctrl for chained lli
127 * @ctrl: ctrl of middle lli
128 * @ctrl_last: ctrl for the last lli
130 * @ctrl_irq_mask: ctrl mask for CPU interrupt
138 u32 ctrl, u32 ctrl_last,
|
| /linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/ |
| H A D | sxgbe_core.c | 190 u32 ctrl; sxgbe_set_eee_mode() local
197 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_set_eee_mode()
198 ctrl |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_TXA; sxgbe_set_eee_mode()
199 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_set_eee_mode()
204 u32 ctrl; sxgbe_reset_eee_mode() local
206 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_reset_eee_mode()
207 ctrl &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_TXA); sxgbe_reset_eee_mode()
208 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_reset_eee_mode()
213 u32 ctrl; sxgbe_set_eee_pls() local
215 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_set_eee_pls()
219 ctrl |= LPI_CTRL_STATUS_PLS; sxgbe_set_eee_pls()
221 ctrl &= ~LPI_CTRL_STATUS_PLS; sxgbe_set_eee_pls()
223 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_set_eee_pls()
243 u32 ctrl; sxgbe_enable_rx_csum() local
245 ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_enable_rx_csum()
246 ctrl |= SXGBE_RX_CSUMOFFLOAD_ENABLE; sxgbe_enable_rx_csum()
247 writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_enable_rx_csum()
252 u32 ctrl; sxgbe_disable_rx_csum() local
254 ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_disable_rx_csum()
255 ctrl &= ~SXGBE_RX_CSUMOFFLOAD_ENABLE; sxgbe_disable_rx_csum()
256 writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_disable_rx_csum()
|
| /linux-4.1.27/drivers/staging/comedi/drivers/ |
| H A D | comedi_parport.c | 99 unsigned int ctrl; parport_data_reg_insn_config() local
106 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_data_reg_insn_config()
108 ctrl &= ~PARPORT_CTRL_BIDIR_ENA; parport_data_reg_insn_config()
110 ctrl |= PARPORT_CTRL_BIDIR_ENA; parport_data_reg_insn_config()
111 outb(ctrl, dev->iobase + PARPORT_CTRL_REG); parport_data_reg_insn_config()
131 unsigned int ctrl; parport_ctrl_reg_insn_bits() local
134 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_ctrl_reg_insn_bits()
135 ctrl &= (PARPORT_CTRL_IRQ_ENA | PARPORT_CTRL_BIDIR_ENA); parport_ctrl_reg_insn_bits()
136 ctrl |= s->state; parport_ctrl_reg_insn_bits()
137 outb(ctrl, dev->iobase + PARPORT_CTRL_REG); parport_ctrl_reg_insn_bits()
196 unsigned int ctrl; parport_intr_cmd() local
198 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_intr_cmd()
199 ctrl |= PARPORT_CTRL_IRQ_ENA; parport_intr_cmd()
200 outb(ctrl, dev->iobase + PARPORT_CTRL_REG); parport_intr_cmd()
208 unsigned int ctrl; parport_intr_cancel() local
210 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_intr_cancel()
211 ctrl &= ~PARPORT_CTRL_IRQ_ENA; parport_intr_cancel()
212 outb(ctrl, dev->iobase + PARPORT_CTRL_REG); parport_intr_cancel()
221 unsigned int ctrl; parport_interrupt() local
223 ctrl = inb(dev->iobase + PARPORT_CTRL_REG); parport_interrupt()
224 if (!(ctrl & PARPORT_CTRL_IRQ_ENA)) parport_interrupt()
|
| H A D | addi_apci_1032.c | 95 unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */ member in struct:apci1032_private
127 devpriv->ctrl = 0; apci1032_cos_insn_config()
133 if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA | apci1032_cos_insn_config()
136 devpriv->ctrl = APCI1032_CTRL_INT_ENA | apci1032_cos_insn_config()
151 if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA | apci1032_cos_insn_config()
154 devpriv->ctrl = APCI1032_CTRL_INT_ENA | apci1032_cos_insn_config()
238 if (!devpriv->ctrl) { apci1032_cos_cmd()
246 outl(devpriv->ctrl, dev->iobase + APCI1032_CTRL_REG); apci1032_cos_cmd()
262 unsigned int ctrl; apci1032_interrupt() local
270 ctrl = inl(dev->iobase + APCI1032_CTRL_REG); apci1032_interrupt()
271 if ((ctrl & APCI1032_CTRL_INT_ENA) == 0) apci1032_interrupt()
275 outl(ctrl & ~APCI1032_CTRL_INT_ENA, dev->iobase + APCI1032_CTRL_REG); apci1032_interrupt()
282 outl(ctrl, dev->iobase + APCI1032_CTRL_REG); apci1032_interrupt()
|
| /linux-4.1.27/arch/powerpc/sysdev/ |
| H A D | fsl_lbc.c | 188 static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl, fsl_lbc_ctrl_init() argument
191 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_lbc_ctrl_init()
214 struct fsl_lbc_ctrl *ctrl = data; fsl_lbc_ctrl_irq() local
215 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_lbc_ctrl_irq()
229 ctrl->irq_status = status; fsl_lbc_ctrl_irq()
232 dev_err(ctrl->dev, "Local bus monitor time-out: " fsl_lbc_ctrl_irq()
235 dev_err(ctrl->dev, "Write protect error: " fsl_lbc_ctrl_irq()
238 dev_err(ctrl->dev, "Atomic write error: " fsl_lbc_ctrl_irq()
241 dev_err(ctrl->dev, "Atomic read error: " fsl_lbc_ctrl_irq()
244 dev_err(ctrl->dev, "Chip select error: " fsl_lbc_ctrl_irq()
249 dev_err(ctrl->dev, "FCM command time-out: " fsl_lbc_ctrl_irq()
252 wake_up(&ctrl->irq_wait); fsl_lbc_ctrl_irq()
255 dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: " fsl_lbc_ctrl_irq()
258 wake_up(&ctrl->irq_wait); fsl_lbc_ctrl_irq()
262 wake_up(&ctrl->irq_wait); fsl_lbc_ctrl_irq()
265 dev_err(ctrl->dev, "Unknown error: " fsl_lbc_ctrl_irq()
359 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev); fsl_lbc_suspend() local
360 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_lbc_suspend()
362 ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL); fsl_lbc_suspend()
363 if (!ctrl->saved_regs) fsl_lbc_suspend()
366 _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs)); fsl_lbc_suspend()
373 struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev); fsl_lbc_resume() local
374 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; fsl_lbc_resume()
376 if (ctrl->saved_regs) { fsl_lbc_resume()
377 _memcpy_toio(lbc, ctrl->saved_regs, fsl_lbc_resume()
379 kfree(ctrl->saved_regs); fsl_lbc_resume()
380 ctrl->saved_regs = NULL; fsl_lbc_resume()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| H A D | nv50.c | 34 pwm_info(struct nvkm_therm *therm, int *line, int *ctrl, int *indx) pwm_info() argument
37 *ctrl = 0x00e100; pwm_info()
42 *ctrl = 0x00e100; pwm_info()
47 *ctrl = 0x00e28c; pwm_info()
51 nv_error(therm, "unknown pwm ctrl for gpio %d\n", *line); pwm_info()
62 int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); nv50_fan_pwm_ctrl() local
64 nv_mask(therm, ctrl, 0x00010001 << line, data << line); nv50_fan_pwm_ctrl()
71 int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); nv50_fan_pwm_get() local
75 if (nv_rd32(therm, ctrl) & (1 << line)) { nv50_fan_pwm_get()
87 int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); nv50_fan_pwm_set() local
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| H A D | hdmig84.c | 38 u32 ctrl; g84_hdmi_ctrl() local
41 nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); g84_hdmi_ctrl()
43 nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " g84_hdmi_ctrl()
49 ctrl = 0x40000000 * !!args->v0.state; g84_hdmi_ctrl()
50 ctrl |= args->v0.max_ac_packet << 16; g84_hdmi_ctrl()
51 ctrl |= args->v0.rekey; g84_hdmi_ctrl()
52 ctrl |= 0x1f000000; /* ??? */ g84_hdmi_ctrl()
56 if (!(ctrl & 0x40000000)) { g84_hdmi_ctrl()
89 nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, ctrl); g84_hdmi_ctrl()
|
| H A D | hdmigt215.c | 39 u32 ctrl; gt215_hdmi_ctrl() local
42 nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); gt215_hdmi_ctrl()
44 nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " gt215_hdmi_ctrl()
50 ctrl = 0x40000000 * !!args->v0.state; gt215_hdmi_ctrl()
51 ctrl |= args->v0.max_ac_packet << 16; gt215_hdmi_ctrl()
52 ctrl |= args->v0.rekey; gt215_hdmi_ctrl()
53 ctrl |= 0x1f000000; /* ??? */ gt215_hdmi_ctrl()
57 if (!(ctrl & 0x40000000)) { gt215_hdmi_ctrl()
90 nv_mask(priv, 0x61c5a4 + soff, 0x5f1f007f, ctrl); gt215_hdmi_ctrl()
|
| H A D | hdmigf110.c | 38 u32 ctrl; gf110_hdmi_ctrl() local
41 nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); gf110_hdmi_ctrl()
43 nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " gf110_hdmi_ctrl()
49 ctrl = 0x40000000 * !!args->v0.state; gf110_hdmi_ctrl()
50 ctrl |= args->v0.max_ac_packet << 16; gf110_hdmi_ctrl()
51 ctrl |= args->v0.rekey; gf110_hdmi_ctrl()
55 if (!(ctrl & 0x40000000)) { gf110_hdmi_ctrl()
77 nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); gf110_hdmi_ctrl()
|
| H A D | hdmigk104.c | 39 u32 ctrl; gk104_hdmi_ctrl() local
42 nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); gk104_hdmi_ctrl()
44 nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " gk104_hdmi_ctrl()
50 ctrl = 0x40000000 * !!args->v0.state; gk104_hdmi_ctrl()
51 ctrl |= args->v0.max_ac_packet << 16; gk104_hdmi_ctrl()
52 ctrl |= args->v0.rekey; gk104_hdmi_ctrl()
56 if (!(ctrl & 0x40000000)) { gk104_hdmi_ctrl()
81 nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); gk104_hdmi_ctrl()
|
| /linux-4.1.27/net/caif/ |
| H A D | cfctrl.c | 22 static int handle_loop(struct cfctrl *ctrl, handle_loop() argument
27 static int handle_loop(struct cfctrl *ctrl,
31 static void cfctrl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl,
49 sprintf(this->serv.layer.name, "ctrl"); cfctrl_create()
63 struct cfctrl *ctrl = container_obj(layer); cfctrl_remove() local
65 spin_lock_bh(&ctrl->info_list_lock); cfctrl_remove()
66 list_for_each_entry_safe(p, tmp, &ctrl->list, list) { cfctrl_remove()
70 spin_unlock_bh(&ctrl->info_list_lock); cfctrl_remove()
129 static void cfctrl_insert_req(struct cfctrl *ctrl, cfctrl_insert_req() argument
132 spin_lock_bh(&ctrl->info_list_lock); cfctrl_insert_req()
133 atomic_inc(&ctrl->req_seq_no); cfctrl_insert_req()
134 req->sequence_no = atomic_read(&ctrl->req_seq_no); cfctrl_insert_req()
135 list_add_tail(&req->list, &ctrl->list); cfctrl_insert_req()
136 spin_unlock_bh(&ctrl->info_list_lock); cfctrl_insert_req()
140 static struct cfctrl_request_info *cfctrl_remove_req(struct cfctrl *ctrl, cfctrl_remove_req() argument
145 first = list_first_entry(&ctrl->list, struct cfctrl_request_info, list); cfctrl_remove_req()
147 list_for_each_entry_safe(p, tmp, &ctrl->list, list) { cfctrl_remove_req()
152 atomic_set(&ctrl->rsp_seq_no, cfctrl_remove_req()
334 struct cfctrl *ctrl = container_obj(layr); cfctrl_cancel_req() local
336 spin_lock_bh(&ctrl->info_list_lock); cfctrl_cancel_req()
338 list_for_each_entry_safe(p, tmp, &ctrl->list, list) { cfctrl_cancel_req()
346 spin_unlock_bh(&ctrl->info_list_lock); cfctrl_cancel_req()
557 static void cfctrl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl, cfctrl_ctrlcmd() argument
561 switch (ctrl) { cfctrl_ctrlcmd()
592 static int handle_loop(struct cfctrl *ctrl, int cmd, struct cfpkt *pkt) handle_loop() argument
599 spin_lock_bh(&ctrl->loop_linkid_lock); handle_loop()
602 if (!ctrl->loop_linkused[linkid]) handle_loop()
607 if (!ctrl->loop_linkused[linkid]) handle_loop()
609 spin_unlock_bh(&ctrl->loop_linkid_lock); handle_loop()
615 if (!ctrl->loop_linkused[linkid]) handle_loop()
616 ctrl->loop_linkused[linkid] = 1; handle_loop()
621 spin_unlock_bh(&ctrl->loop_linkid_lock); handle_loop()
631 spin_lock_bh(&ctrl->loop_linkid_lock); handle_loop()
633 ctrl->loop_linkused[linkid] = 0; handle_loop()
634 spin_unlock_bh(&ctrl->loop_linkid_lock); handle_loop()
|
| H A D | cfsrvl.c | 28 static void cfservl_ctrlcmd(struct cflayer *layr, enum caif_ctrlcmd ctrl, cfservl_ctrlcmd() argument
36 switch (ctrl) { cfservl_ctrlcmd()
39 layr->up->ctrlcmd(layr->up, ctrl, phyid); cfservl_ctrlcmd()
44 layr->up->ctrlcmd(layr->up, ctrl, phyid); cfservl_ctrlcmd()
84 layr->up->ctrlcmd(layr->up, ctrl, phyid); cfservl_ctrlcmd()
87 pr_warn("Unexpected ctrl in cfsrvl (%d)\n", ctrl); cfservl_ctrlcmd()
89 layr->up->ctrlcmd(layr->up, ctrl, phyid); cfservl_ctrlcmd()
95 static int cfservl_modemcmd(struct cflayer *layr, enum caif_modemcmd ctrl) cfservl_modemcmd() argument
106 switch (ctrl) { cfservl_modemcmd()
|
| /linux-4.1.27/drivers/rtc/ |
| H A D | rtc-ds1305.c | 98 u8 ctrl[DS1305_CONTROL_LEN]; member in struct:ds1305
150 buf[1] = ds1305->ctrl[0]; ds1305_alarm_irq_enable()
153 if (ds1305->ctrl[0] & DS1305_AEI0) ds1305_alarm_irq_enable()
163 ds1305->ctrl[0] = buf[1]; ds1305_alarm_irq_enable()
273 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
290 ds1305->ctrl, sizeof(ds1305->ctrl)); ds1305_get_alarm()
294 alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0); ds1305_get_alarm()
295 alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0); ds1305_get_alarm()
332 * Context: caller holds rtc->ops_lock (to protect ds1305->ctrl)
363 if (ds1305->ctrl[0] & DS1305_AEI0) { ds1305_set_alarm()
364 ds1305->ctrl[0] &= ~DS1305_AEI0; ds1305_set_alarm()
367 buf[1] = ds1305->ctrl[0]; ds1305_set_alarm()
390 ds1305->ctrl[0] |= DS1305_AEI0; ds1305_set_alarm()
393 buf[1] = ds1305->ctrl[0]; ds1305_set_alarm()
408 /* ctrl[2] is treated as read-only; no locking needed */ ds1305_proc()
409 if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) { ds1305_proc()
410 switch (ds1305->ctrl[2] & 0x0c) { ds1305_proc()
420 switch (ds1305->ctrl[2] & 0x03) { ds1305_proc()
463 /* lock to protect ds1305->ctrl */ ds1305_work()
470 ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0); ds1305_work()
471 ds1305->ctrl[1] = 0; ds1305_work()
474 buf[1] = ds1305->ctrl[0]; ds1305_work()
492 * mutex locking for ds1305->ctrl ... unlike I2C, we could issue async
631 ds1305->ctrl, sizeof(ds1305->ctrl)); ds1305_probe()
638 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl); ds1305_probe()
645 if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) { ds1305_probe()
649 if (ds1305->ctrl[2] == 0) ds1305_probe()
655 if (ds1305->ctrl[0] & DS1305_WP) { ds1305_probe()
658 ds1305->ctrl[0] &= ~DS1305_WP; ds1305_probe()
661 buf[1] = ds1305->ctrl[0]; ds1305_probe()
672 if (ds1305->ctrl[0] & DS1305_nEOSC) { ds1305_probe()
673 ds1305->ctrl[0] &= ~DS1305_nEOSC; ds1305_probe()
679 if (ds1305->ctrl[1]) { ds1305_probe()
680 ds1305->ctrl[1] = 0; ds1305_probe()
687 if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) { ds1305_probe()
688 ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC ds1305_probe()
696 if (!(ds1305->ctrl[0] & DS1306_1HZ)) { ds1305_probe()
697 ds1305->ctrl[0] |= DS1306_1HZ; ds1305_probe()
701 if (ds1305->ctrl[0] & DS1306_1HZ) { ds1305_probe()
702 ds1305->ctrl[0] &= ~DS1306_1HZ; ds1305_probe()
713 buf[1] = ds1305->ctrl[0]; ds1305_probe()
714 buf[2] = ds1305->ctrl[1]; ds1305_probe()
715 buf[3] = ds1305->ctrl[2]; ds1305_probe()
723 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl); ds1305_probe()
739 /* register RTC ... from here on, ds1305->ctrl needs locking */ ds1305_probe()
|
| H A D | rtc-jz4740.c | 57 uint32_t ctrl; jz4740_rtc_wait_write_ready() local
61 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); jz4740_rtc_wait_write_ready()
62 } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout); jz4740_rtc_wait_write_ready()
83 uint32_t ctrl; jz4740_rtc_ctrl_set_bits() local
87 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); jz4740_rtc_ctrl_set_bits()
90 ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF; jz4740_rtc_ctrl_set_bits()
93 ctrl |= mask; jz4740_rtc_ctrl_set_bits()
95 ctrl &= ~mask; jz4740_rtc_ctrl_set_bits()
97 ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl); jz4740_rtc_ctrl_set_bits()
141 uint32_t ctrl; jz4740_rtc_read_alarm() local
145 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); jz4740_rtc_read_alarm()
147 alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE); jz4740_rtc_read_alarm()
148 alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF); jz4740_rtc_read_alarm()
188 uint32_t ctrl; jz4740_rtc_irq() local
191 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL); jz4740_rtc_irq()
193 if (ctrl & JZ_RTC_CTRL_1HZ) jz4740_rtc_irq()
196 if (ctrl & JZ_RTC_CTRL_AF) jz4740_rtc_irq()
|
| H A D | rtc-pcf8583.c | 32 unsigned char ctrl; member in struct:pcf8583
46 #define get_ctrl(x) ((struct pcf8583 *)i2c_get_clientdata(x))->ctrl
118 static int pcf8583_get_ctrl(struct i2c_client *client, unsigned char *ctrl) pcf8583_get_ctrl() argument
120 *ctrl = get_ctrl(client); pcf8583_get_ctrl()
124 static int pcf8583_set_ctrl(struct i2c_client *client, unsigned char *ctrl) pcf8583_set_ctrl() argument
129 buf[1] = *ctrl; pcf8583_set_ctrl()
130 set_ctrl(client, *ctrl); pcf8583_set_ctrl()
178 unsigned char ctrl, year[2]; pcf8583_rtc_read_time() local
189 pcf8583_get_ctrl(client, &ctrl); pcf8583_rtc_read_time()
190 if (ctrl & (CTRL_STOP | CTRL_HOLD)) { pcf8583_rtc_read_time()
191 unsigned char new_ctrl = ctrl & ~(CTRL_STOP | CTRL_HOLD); pcf8583_rtc_read_time()
194 ctrl, new_ctrl); pcf8583_rtc_read_time()
|
| /linux-4.1.27/drivers/media/i2c/m5mols/ |
| H A D | m5mols_controls.c | 189 static int m5mols_3a_lock(struct m5mols_info *info, struct v4l2_ctrl *ctrl) m5mols_3a_lock() argument
191 bool af_lock = ctrl->val & V4L2_LOCK_FOCUS; m5mols_3a_lock()
194 if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE) { m5mols_3a_lock()
195 bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; m5mols_3a_lock()
203 if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE) m5mols_3a_lock()
205 bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; m5mols_3a_lock()
216 if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_FOCUS) m5mols_3a_lock()
403 static int m5mols_g_volatile_ctrl(struct v4l2_ctrl *ctrl) m5mols_g_volatile_ctrl() argument
405 struct v4l2_subdev *sd = to_sd(ctrl); m5mols_g_volatile_ctrl()
410 v4l2_dbg(1, m5mols_debug, sd, "%s: ctrl: %s (%d)\n", m5mols_g_volatile_ctrl()
411 __func__, ctrl->name, info->isp_ready); m5mols_g_volatile_ctrl()
416 switch (ctrl->id) { m5mols_g_volatile_ctrl()
420 ctrl->val = !status; m5mols_g_volatile_ctrl()
426 ctrl->val &= ~0x7; m5mols_g_volatile_ctrl()
449 static int m5mols_s_ctrl(struct v4l2_ctrl *ctrl) m5mols_s_ctrl() argument
451 unsigned int ctrl_mode = m5mols_get_ctrl_mode(ctrl); m5mols_s_ctrl()
452 struct v4l2_subdev *sd = to_sd(ctrl); m5mols_s_ctrl()
467 __func__, ctrl->name, ctrl->val, ctrl->priv); m5mols_s_ctrl()
475 switch (ctrl->id) { m5mols_s_ctrl()
477 ret = m5mols_3a_lock(info, ctrl); m5mols_s_ctrl()
481 ret = m5mols_write(sd, MON_ZOOM, ctrl->val); m5mols_s_ctrl()
485 ret = m5mols_set_exposure(info, ctrl->val); m5mols_s_ctrl()
489 ret = m5mols_set_iso(info, ctrl->val); m5mols_s_ctrl()
493 ret = m5mols_set_white_balance(info, ctrl->val); m5mols_s_ctrl()
497 ret = m5mols_set_saturation(info, ctrl->val); m5mols_s_ctrl()
501 ret = m5mols_set_color_effect(info, ctrl->val); m5mols_s_ctrl()
505 ret = m5mols_set_wdr(info, ctrl->val); m5mols_s_ctrl()
509 ret = m5mols_set_stabilization(info, ctrl->val); m5mols_s_ctrl()
513 ret = m5mols_write(sd, CAPP_JPEG_RATIO, ctrl->val); m5mols_s_ctrl()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/ |
| H A D | g94.c | 71 u32 ctrl, timeout; auxch_init() local
76 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); auxch_init()
79 AUX_ERR("begin idle timeout 0x%08x\n", ctrl); auxch_init()
82 } while (ctrl & 0x03010000); auxch_init()
88 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); auxch_init()
91 AUX_ERR("magic wait 0x%08x\n", ctrl); auxch_init()
95 } while ((ctrl & 0x03000000) != urep); auxch_init()
106 u32 ctrl, stat, timeout, retries; g94_aux() local
132 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); g94_aux()
133 ctrl &= ~0x0001f0ff; g94_aux()
134 ctrl |= type << 12; g94_aux()
135 ctrl |= size - 1; g94_aux()
141 nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl); g94_aux()
142 nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl); g94_aux()
147 nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl); g94_aux()
151 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); g94_aux()
154 AUX_ERR("tx req timeout 0x%08x\n", ctrl); g94_aux()
158 } while (ctrl & 0x00010000); g94_aux()
171 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat); g94_aux()
|
| H A D | gm204.c | 41 u32 ctrl, timeout; auxch_init() local
46 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); auxch_init()
49 AUX_ERR("begin idle timeout 0x%08x\n", ctrl); auxch_init()
52 } while (ctrl & 0x03010000); auxch_init()
58 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); auxch_init()
61 AUX_ERR("magic wait 0x%08x\n", ctrl); auxch_init()
65 } while ((ctrl & 0x03000000) != urep); auxch_init()
76 u32 ctrl, stat, timeout, retries; gm204_aux() local
102 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); gm204_aux()
103 ctrl &= ~0x0001f0ff; gm204_aux()
104 ctrl |= type << 12; gm204_aux()
105 ctrl |= size - 1; gm204_aux()
111 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x80000000 | ctrl); gm204_aux()
112 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00000000 | ctrl); gm204_aux()
117 nv_wr32(aux, 0x00d954 + (ch * 0x50), 0x00010000 | ctrl); gm204_aux()
121 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); gm204_aux()
124 AUX_ERR("tx req timeout 0x%08x\n", ctrl); gm204_aux()
128 } while (ctrl & 0x00010000); gm204_aux()
141 AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat); gm204_aux()
|
| H A D | anx9805.c | 29 u32 ctrl; member in struct:anx9805_i2c_port
75 tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04; anx9805_aux()
76 nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04); anx9805_aux()
77 nv_wri2cr(mast, chan->ctrl, 0x07, tmp); anx9805_aux()
78 nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01); anx9805_aux()
100 if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) { anx9805_aux()
114 nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01); anx9805_aux()
144 chan->ctrl = 0x39; anx9805_aux_chan_ctor()
148 chan->ctrl = 0x3b; anx9805_aux_chan_ctor()
180 tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10; anx9805_xfer()
181 nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10); anx9805_xfer()
182 nv_wri2cr(mast, port->ctrl, 0x07, tmp); anx9805_xfer()
259 port->ctrl = 0x39; anx9805_ddc_port_ctor()
263 port->ctrl = 0x3b; anx9805_ddc_port_ctor()
|
| /linux-4.1.27/include/uapi/linux/netfilter_bridge/ |
| H A D | ebt_802_3.h | 28 /* ui has one byte ctrl, ni has two */
32 __u8 ctrl; member in struct:hdr_ui
40 __be16 ctrl; member in struct:hdr_ni
|
| /linux-4.1.27/arch/arm/mach-omap1/ |
| H A D | board-nand.c | 23 void omap1_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl) omap1_nand_cmd_ctl() argument
31 mask = (ctrl & NAND_CLE) ? 0x02 : 0; omap1_nand_cmd_ctl()
32 if (ctrl & NAND_ALE) omap1_nand_cmd_ctl()
|
| /linux-4.1.27/drivers/net/can/c_can/ |
| H A D | c_can_platform.c | 79 u32 ctrl = 0; c_can_hw_raminit_wait_syscon() local
87 regmap_read(raminit->syscon, raminit->reg, &ctrl); c_can_hw_raminit_wait_syscon()
92 } while ((ctrl & mask) != val); c_can_hw_raminit_wait_syscon()
98 u32 ctrl = 0; c_can_hw_raminit_syscon() local
104 regmap_read(raminit->syscon, raminit->reg, &ctrl); c_can_hw_raminit_syscon()
113 ctrl &= ~mask; /* START = 0, DONE = 0 */ c_can_hw_raminit_syscon()
114 regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); c_can_hw_raminit_syscon()
119 c_can_hw_raminit_wait_syscon(priv, 1 << raminit->bits.start, ctrl); c_can_hw_raminit_syscon()
123 ctrl |= 1 << raminit->bits.start; c_can_hw_raminit_syscon()
125 ctrl |= 1 << raminit->bits.done; c_can_hw_raminit_syscon()
126 regmap_update_bits(raminit->syscon, raminit->reg, mask, ctrl); c_can_hw_raminit_syscon()
128 ctrl &= ~(1 << raminit->bits.done); c_can_hw_raminit_syscon()
131 ctrl &= ~(1 << raminit->bits.start); c_can_hw_raminit_syscon()
133 mask, ctrl); c_can_hw_raminit_syscon()
136 ctrl |= 1 << raminit->bits.done; c_can_hw_raminit_syscon()
137 c_can_hw_raminit_wait_syscon(priv, mask, ctrl); c_can_hw_raminit_syscon()
178 u32 ctrl; c_can_hw_raminit() local
180 ctrl = priv->read_reg32(priv, C_CAN_FUNCTION_REG); c_can_hw_raminit()
181 ctrl &= ~DCAN_RAM_INIT_BIT; c_can_hw_raminit()
182 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); c_can_hw_raminit()
183 c_can_hw_raminit_wait(priv, ctrl); c_can_hw_raminit()
186 ctrl |= DCAN_RAM_INIT_BIT; c_can_hw_raminit()
187 priv->write_reg32(priv, C_CAN_FUNCTION_REG, ctrl); c_can_hw_raminit()
188 c_can_hw_raminit_wait(priv, ctrl); c_can_hw_raminit()
|
| /linux-4.1.27/drivers/isdn/hisax/ |
| H A D | hisax_fcpcipnp.h | 34 u_int ctrl; member in union:fritz_bcs::__anon5294
36 } ctrl; member in struct:fritz_bcs
|
| H A D | st5481_usb.c | 31 struct st5481_ctrl *ctrl = &adapter->ctrl; usb_next_ctrl_msg() local
34 if (test_and_set_bit(0, &ctrl->busy)) { usb_next_ctrl_msg()
38 if ((r_index = fifo_remove(&ctrl->msg_fifo.f)) < 0) { usb_next_ctrl_msg()
39 test_and_clear_bit(0, &ctrl->busy); usb_next_ctrl_msg()
43 (unsigned char *)&ctrl->msg_fifo.data[r_index]; usb_next_ctrl_msg()
64 struct st5481_ctrl *ctrl = &adapter->ctrl; usb_ctrl_msg() local
68 if ((w_index = fifo_add(&ctrl->msg_fifo.f)) < 0) { usb_ctrl_msg()
72 ctrl_msg = &ctrl->msg_fifo.data[w_index]; usb_ctrl_msg()
82 usb_next_ctrl_msg(ctrl->urb, adapter); usb_ctrl_msg()
131 struct st5481_ctrl *ctrl = &adapter->ctrl; usb_ctrl_complete() local
158 clear_bit(0, &ctrl->busy); usb_ctrl_complete()
241 struct st5481_ctrl *ctrl = &adapter->ctrl; st5481_setup_usb() local
284 ctrl->urb = urb; st5481_setup_usb()
292 fifo_init(&ctrl->msg_fifo.f, ARRAY_SIZE(ctrl->msg_fifo.data)); st5481_setup_usb()
320 usb_free_urb(ctrl->urb); st5481_setup_usb()
321 ctrl->urb = NULL; st5481_setup_usb()
333 struct st5481_ctrl *ctrl = &adapter->ctrl; st5481_release_usb() local
338 usb_kill_urb(ctrl->urb); st5481_release_usb()
339 kfree(ctrl->urb->transfer_buffer); st5481_release_usb()
340 usb_free_urb(ctrl->urb); st5481_release_usb()
341 ctrl->urb = NULL; st5481_release_usb()
|
| H A D | hisax_fcpcipnp.c | 228 DBG(0x40, "hdlc %c wr%x ctrl %x", __fcpci_write_ctrl()
229 'A' + bcs->channel, which, bcs->ctrl.ctrl); __fcpci_write_ctrl()
232 outl(bcs->ctrl.ctrl, adapter->io + AVM_DATA + HDLC_CTRL); __fcpci_write_ctrl()
318 DBG(0x40, "hdlc %c wr%x ctrl %x", fcpci2_write_ctrl()
319 'A' + bcs->channel, which, bcs->ctrl.ctrl); fcpci2_write_ctrl()
321 outl(bcs->ctrl.ctrl, adapter->io + offset); fcpci2_write_ctrl()
347 DBG(0x40, "hdlc %c wr%x ctrl %x", __fcpnp_write_ctrl()
348 'A' + bcs->channel, which, bcs->ctrl.ctrl); __fcpnp_write_ctrl()
352 outb(bcs->ctrl.sr.mode, __fcpnp_write_ctrl()
355 outb(bcs->ctrl.sr.xml, __fcpnp_write_ctrl()
358 outb(bcs->ctrl.sr.cmd, __fcpnp_write_ctrl()
394 bcs->ctrl.sr.cmd &= ~HDLC_CMD_XME; hdlc_fill_fifo()
400 bcs->ctrl.sr.cmd |= HDLC_CMD_XME; hdlc_fill_fifo()
406 bcs->ctrl.sr.xml = ((count == bcs->fifo_size) ? 0 : count); hdlc_fill_fifo()
476 bcs->ctrl.sr.xml = 0; hdlc_rpr_irq()
477 bcs->ctrl.sr.cmd |= HDLC_CMD_RRS; hdlc_rpr_irq()
479 bcs->ctrl.sr.cmd &= ~HDLC_CMD_RRS; hdlc_rpr_irq()
520 bcs->ctrl.sr.xml = 0; hdlc_xdu_irq()
521 bcs->ctrl.sr.cmd |= HDLC_CMD_XRS; hdlc_xdu_irq()
523 bcs->ctrl.sr.cmd &= ~HDLC_CMD_XRS; hdlc_xdu_irq()
598 bcs->ctrl.ctrl = 0; modehdlc()
599 bcs->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; modehdlc()
602 bcs->ctrl.sr.mode = HDLC_MODE_TRANS; modehdlc()
611 bcs->ctrl.sr.mode = HDLC_MODE_TRANS; modehdlc()
613 bcs->ctrl.sr.mode = HDLC_MODE_ITF_FLG; modehdlc()
616 bcs->ctrl.sr.cmd = HDLC_CMD_XRS; modehdlc()
618 bcs->ctrl.sr.cmd = 0; modehdlc()
|
| /linux-4.1.27/include/linux/platform_data/ |
| H A D | max197.h | 19 * @convert: Function used to start a conversion with control byte ctrl.
23 int (*convert)(u8 ctrl);
|
| /linux-4.1.27/arch/nios2/kernel/ |
| H A D | time.c | 112 u16 ctrl; nios2_timer_start() local
114 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); nios2_timer_start()
115 ctrl |= ALTERA_TIMER_CONTROL_START_MSK; nios2_timer_start()
116 timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG); nios2_timer_start()
121 u16 ctrl; nios2_timer_stop() local
123 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); nios2_timer_stop()
124 ctrl |= ALTERA_TIMER_CONTROL_STOP_MSK; nios2_timer_stop()
125 timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG); nios2_timer_stop()
131 u16 ctrl; nios2_timer_config() local
137 ctrl = timer_readw(timer, ALTERA_TIMER_CONTROL_REG); nios2_timer_config()
139 timer_writew(timer, ctrl | ALTERA_TIMER_CONTROL_STOP_MSK, nios2_timer_config()
146 ctrl |= ALTERA_TIMER_CONTROL_START_MSK | ALTERA_TIMER_CONTROL_ITO_MSK; nios2_timer_config()
148 ctrl |= ALTERA_TIMER_CONTROL_CONT_MSK; nios2_timer_config()
150 ctrl &= ~ALTERA_TIMER_CONTROL_CONT_MSK; nios2_timer_config()
151 timer_writew(timer, ctrl, ALTERA_TIMER_CONTROL_REG); nios2_timer_config()
252 unsigned int ctrl; nios2_clocksource_init() local
267 ctrl = ALTERA_TIMER_CONTROL_CONT_MSK | ALTERA_TIMER_CONTROL_START_MSK; nios2_clocksource_init()
268 timer_writew(&nios2_cs.timer, ctrl, ALTERA_TIMER_CONTROL_REG); nios2_clocksource_init()
|
| /linux-4.1.27/arch/blackfin/include/asm/ |
| H A D | cplb.h | 113 u32 ctrl = bfin_read32(mmr) & ~mask; _disable_cplb() local
116 bfin_write32(mmr, ctrl); _disable_cplb()
121 u32 ctrl = bfin_read32(mmr) & ~mask; disable_cplb() local
123 bfin_write32(mmr, ctrl); disable_cplb()
133 u32 ctrl = bfin_read32(mmr) | mask; _enable_cplb() local
136 bfin_write32(mmr, ctrl); _enable_cplb()
141 u32 ctrl = bfin_read32(mmr) | mask; enable_cplb() local
143 bfin_write32(mmr, ctrl); enable_cplb()
|
| /linux-4.1.27/arch/cris/arch-v10/lib/ |
| H A D | dmacopy.c | 25 indma.ctrl = d_eol | d_eop; dma_memcpy()
26 outdma.ctrl = d_eol; dma_memcpy()
|
| /linux-4.1.27/arch/arm64/kernel/ |
| H A D | hw_breakpoint.c | 234 enum debug_el dbg_el = debug_exception_level(info->ctrl.privilege); hw_breakpoint_control()
235 u32 ctrl; hw_breakpoint_control() local
237 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { hw_breakpoint_control()
271 ctrl = encode_ctrl_reg(info->ctrl); hw_breakpoint_control()
273 reg_enable ? ctrl | 0x1 : ctrl & ~0x1); hw_breakpoint_control()
335 len = get_hbp_len(info->ctrl.len); arch_check_bp_in_kernelspace()
345 int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, arch_bp_generic_fields() argument
349 switch (ctrl.type) { arch_bp_generic_fields()
367 switch (ctrl.len) { arch_bp_generic_fields()
397 info->ctrl.type = ARM_BREAKPOINT_EXECUTE; arch_build_bp_info()
400 info->ctrl.type = ARM_BREAKPOINT_LOAD; arch_build_bp_info()
403 info->ctrl.type = ARM_BREAKPOINT_STORE; arch_build_bp_info()
406 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; arch_build_bp_info()
415 info->ctrl.len = ARM_BREAKPOINT_LEN_1; arch_build_bp_info()
418 info->ctrl.len = ARM_BREAKPOINT_LEN_2; arch_build_bp_info()
421 info->ctrl.len = ARM_BREAKPOINT_LEN_4; arch_build_bp_info()
424 info->ctrl.len = ARM_BREAKPOINT_LEN_8; arch_build_bp_info()
435 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { arch_build_bp_info()
437 if (info->ctrl.len != ARM_BREAKPOINT_LEN_2 && arch_build_bp_info()
438 info->ctrl.len != ARM_BREAKPOINT_LEN_4) arch_build_bp_info()
440 } else if (info->ctrl.len != ARM_BREAKPOINT_LEN_4) { arch_build_bp_info()
447 info->ctrl.len = ARM_BREAKPOINT_LEN_4; arch_build_bp_info()
460 info->ctrl.privilege = AARCH64_BREAKPOINT_EL1; arch_build_bp_info()
462 info->ctrl.privilege = AARCH64_BREAKPOINT_EL0; arch_build_bp_info()
465 info->ctrl.enabled = !bp->attr.disabled; arch_build_bp_info()
494 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) arch_validate_hwbkpt_settings()
505 if (info->ctrl.len == ARM_BREAKPOINT_LEN_1) arch_validate_hwbkpt_settings()
509 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2) arch_validate_hwbkpt_settings()
516 info->ctrl.len <<= offset; arch_validate_hwbkpt_settings()
518 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) arch_validate_hwbkpt_settings()
530 if (info->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target) arch_validate_hwbkpt_settings()
544 u32 ctrl; toggle_bp_registers() local
564 privilege = counter_arch_bp(slots[i])->ctrl.privilege; toggle_bp_registers()
568 ctrl = read_wb_reg(reg, i); toggle_bp_registers()
570 ctrl |= 0x1; toggle_bp_registers()
572 ctrl &= ~0x1; toggle_bp_registers()
573 write_wb_reg(reg, i, ctrl); toggle_bp_registers()
588 struct arch_hw_breakpoint_ctrl ctrl; breakpoint_handler() local
609 decode_ctrl_reg(ctrl_reg, &ctrl); breakpoint_handler()
610 if (!((1 << (addr & 0x3)) & ctrl.len)) breakpoint_handler()
665 struct arch_hw_breakpoint_ctrl ctrl; watchpoint_handler() local
681 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) watchpoint_handler()
696 decode_ctrl_reg(ctrl_reg, &ctrl); watchpoint_handler()
697 if (!((1 << (addr & alignment_mask)) & ctrl.len)) watchpoint_handler()
|
| /linux-4.1.27/drivers/char/hw_random/ |
| H A D | mxc-rnga.c | 88 u32 ctrl; mxc_rnga_data_read() local
100 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); mxc_rnga_data_read()
101 __raw_writel(ctrl | RNGA_CONTROL_CLEAR_INT, mxc_rnga_data_read()
110 u32 ctrl, osc; mxc_rnga_init() local
114 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); mxc_rnga_init()
115 __raw_writel(ctrl & ~RNGA_CONTROL_SLEEP, mxc_rng->mem + RNGA_CONTROL); mxc_rnga_init()
125 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); mxc_rnga_init()
126 __raw_writel(ctrl | RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL); mxc_rnga_init()
133 u32 ctrl; mxc_rnga_cleanup() local
136 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); mxc_rnga_cleanup()
139 __raw_writel(ctrl & ~RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL); mxc_rnga_cleanup()
|
| H A D | ppc4xx-rng.c | 56 struct device_node *ctrl; ppc4xx_rng_enable() local
62 ctrl = of_find_compatible_node(NULL, NULL, "amcc,ppc4xx-crypto"); ppc4xx_rng_enable()
63 if (!ctrl) ppc4xx_rng_enable()
66 ctrl_reg = of_iomap(ctrl, 0); ppc4xx_rng_enable()
83 of_node_put(ctrl); ppc4xx_rng_enable()
|
| /linux-4.1.27/drivers/i2c/busses/ |
| H A D | i2c-kempld.c | 236 u8 ctrl; kempld_i2c_device_init() local
241 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); kempld_i2c_device_init()
242 ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); kempld_i2c_device_init()
243 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); kempld_i2c_device_init()
274 ctrl |= I2C_CTRL_EN; kempld_i2c_device_init()
275 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); kempld_i2c_device_init()
304 u8 ctrl; kempld_i2c_probe() local
318 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); kempld_i2c_probe()
320 if (ctrl & I2C_CTRL_EN) kempld_i2c_probe()
343 u8 ctrl; kempld_i2c_remove() local
351 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); kempld_i2c_remove()
352 ctrl &= ~I2C_CTRL_EN; kempld_i2c_remove()
353 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); kempld_i2c_remove()
367 u8 ctrl; kempld_i2c_suspend() local
370 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL); kempld_i2c_suspend()
371 ctrl &= ~I2C_CTRL_EN; kempld_i2c_suspend()
372 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl); kempld_i2c_suspend()
|
| /linux-4.1.27/arch/arm/mach-lpc32xx/ |
| H A D | irq.c | 212 unsigned int reg, ctrl, mask; lpc32xx_mask_irq() local
214 get_controller(d->hwirq, &ctrl, &mask); lpc32xx_mask_irq()
216 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; lpc32xx_mask_irq()
217 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); lpc32xx_mask_irq()
222 unsigned int reg, ctrl, mask; lpc32xx_unmask_irq() local
224 get_controller(d->hwirq, &ctrl, &mask); lpc32xx_unmask_irq()
226 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; lpc32xx_unmask_irq()
227 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); lpc32xx_unmask_irq()
232 unsigned int ctrl, mask; lpc32xx_ack_irq() local
234 get_controller(d->hwirq, &ctrl, &mask); lpc32xx_ack_irq()
236 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); lpc32xx_ack_irq()
247 unsigned int reg, ctrl, mask; __lpc32xx_set_irq_type() local
249 get_controller(irq, &ctrl, &mask); __lpc32xx_set_irq_type()
252 reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl)); __lpc32xx_set_irq_type()
257 __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl)); __lpc32xx_set_irq_type()
260 reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl)); __lpc32xx_set_irq_type()
265 __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl)); __lpc32xx_set_irq_type()
|
| /linux-4.1.27/drivers/media/pci/cx23885/ |
| H A D | cx23885-i2c.c | 82 u32 wdata, addr, ctrl; i2c_sendbytes() local
108 ctrl = bus->i2c_period | (1 << 12) | (1 << 2); i2c_sendbytes()
111 ctrl |= I2C_NOSTOP | I2C_EXTEND; i2c_sendbytes()
113 ctrl |= I2C_NOSTOP; i2c_sendbytes()
117 cx_write(bus->reg_ctrl, ctrl); i2c_sendbytes()
123 if (!(ctrl & I2C_NOSTOP)) i2c_sendbytes()
130 ctrl = bus->i2c_period | (1 << 12) | (1 << 2); i2c_sendbytes()
133 ctrl |= I2C_NOSTOP | I2C_EXTEND; i2c_sendbytes()
135 ctrl |= I2C_NOSTOP; i2c_sendbytes()
139 cx_write(bus->reg_ctrl, ctrl); i2c_sendbytes()
145 if (!(ctrl & I2C_NOSTOP)) i2c_sendbytes()
163 u32 ctrl, cnt; i2c_readbytes() local
193 ctrl = bus->i2c_period | (1 << 12) | (1 << 2) | 1; i2c_readbytes()
196 ctrl |= I2C_NOSTOP | I2C_EXTEND; i2c_readbytes()
199 cx_write(bus->reg_ctrl, ctrl); i2c_readbytes()
206 if (!(ctrl & I2C_NOSTOP)) i2c_readbytes()
|
| /linux-4.1.27/drivers/media/pci/cx25821/ |
| H A D | cx25821-i2c.c | 85 u32 wdata, addr, ctrl; i2c_sendbytes() local
113 ctrl = bus->i2c_period | (1 << 12) | (1 << 2); i2c_sendbytes()
116 ctrl |= I2C_NOSTOP | I2C_EXTEND; i2c_sendbytes()
118 ctrl |= I2C_NOSTOP; i2c_sendbytes()
122 cx_write(bus->reg_ctrl, ctrl); i2c_sendbytes()
132 if (!(ctrl & I2C_NOSTOP)) i2c_sendbytes()
139 ctrl = bus->i2c_period | (1 << 12) | (1 << 2); i2c_sendbytes()
142 ctrl |= I2C_NOSTOP | I2C_EXTEND; i2c_sendbytes()
144 ctrl |= I2C_NOSTOP; i2c_sendbytes()
148 cx_write(bus->reg_ctrl, ctrl); i2c_sendbytes()
159 if (!(ctrl & I2C_NOSTOP)) i2c_sendbytes()
179 u32 ctrl, cnt; i2c_readbytes() local
207 ctrl = bus->i2c_period | (1 << 12) | (1 << 2) | 1; i2c_readbytes()
210 ctrl |= I2C_NOSTOP | I2C_EXTEND; i2c_readbytes()
213 cx_write(bus->reg_ctrl, ctrl); i2c_readbytes()
224 if (!(ctrl & I2C_NOSTOP)) i2c_readbytes()
|
| /linux-4.1.27/drivers/spi/ |
| H A D | spi-sc18is602.c | 43 u8 ctrl; member in struct:sc18is602
137 u8 ctrl = 0; sc18is602_setup_transfer() local
141 ctrl |= SC18IS602_MODE_CPHA; sc18is602_setup_transfer()
143 ctrl |= SC18IS602_MODE_CPOL; sc18is602_setup_transfer()
145 ctrl |= SC18IS602_MODE_LSB_FIRST; sc18is602_setup_transfer()
149 ctrl |= SC18IS602_MODE_CLOCK_DIV_4; sc18is602_setup_transfer()
152 ctrl |= SC18IS602_MODE_CLOCK_DIV_16; sc18is602_setup_transfer()
155 ctrl |= SC18IS602_MODE_CLOCK_DIV_64; sc18is602_setup_transfer()
158 ctrl |= SC18IS602_MODE_CLOCK_DIV_128; sc18is602_setup_transfer()
164 * value of 0xff for hw->ctrl ensures that the correct mode will be set sc18is602_setup_transfer()
167 if (ctrl == hw->ctrl) sc18is602_setup_transfer()
170 ret = i2c_smbus_write_byte_data(hw->client, 0xf0, ctrl); sc18is602_setup_transfer()
174 hw->ctrl = ctrl; sc18is602_setup_transfer()
263 hw->ctrl = 0xff; sc18is602_probe()
|
| /linux-4.1.27/drivers/isdn/hardware/avm/ |
| H A D | b1.c | 278 int b1_load_firmware(struct capi_ctr *ctrl, capiloaddata *data) b1_load_firmware() argument
280 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1_load_firmware()
316 b1_put_word(port, ctrl->cnr - 1); b1_load_firmware()
322 void b1_reset_ctr(struct capi_ctr *ctrl) b1_reset_ctr() argument
324 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1_reset_ctr()
336 capi_ctr_down(ctrl); b1_reset_ctr()
339 void b1_register_appl(struct capi_ctr *ctrl, b1_register_appl() argument
343 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1_register_appl()
350 else nconn = ctrl->profile.nbchannel * -want; b1_register_appl()
351 if (nconn == 0) nconn = ctrl->profile.nbchannel; b1_register_appl()
363 void b1_release_appl(struct capi_ctr *ctrl, u16 appl) b1_release_appl() argument
365 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1_release_appl()
377 u16 b1_send_message(struct capi_ctr *ctrl, struct sk_buff *skb) b1_send_message() argument
379 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1_send_message()
418 struct capi_ctr *ctrl = &cinfo->capi_ctrl; b1_parse_version() local
432 strlcpy(ctrl->serial, cinfo->version[VER_SERIAL], sizeof(ctrl->serial)); b1_parse_version()
433 memcpy(&ctrl->profile, cinfo->version[VER_PROFILE], sizeof(capi_profile)); b1_parse_version()
434 strlcpy(ctrl->manu, "AVM GmbH", sizeof(ctrl->manu)); b1_parse_version()
436 ctrl->version.majorversion = 2; b1_parse_version()
437 ctrl->version.minorversion = 0; b1_parse_version()
438 ctrl->version.majormanuversion = (((dversion[0] - '0') & 0xf) << 4); b1_parse_version()
439 ctrl->version.majormanuversion |= ((dversion[2] - '0') & 0xf); b1_parse_version()
440 ctrl->version.minormanuversion = (dversion[3] - '0') << 4; b1_parse_version()
441 ctrl->version.minormanuversion |= b1_parse_version()
444 profp = &ctrl->profile; b1_parse_version()
460 card->name, ctrl->cnr, cinfo->cardname); b1_parse_version()
466 ctrl->cnr, b1_parse_version()
480 ctrl->cnr, b1_parse_version()
494 struct capi_ctr *ctrl = &cinfo->capi_ctrl; b1_interrupt() local
534 capi_ctr_handle_message(ctrl, ApplId, skb); b1_interrupt()
553 capi_ctr_handle_message(ctrl, ApplId, skb); b1_interrupt()
578 capi_ctr_resume_output(ctrl); b1_interrupt()
583 capi_ctr_suspend_output(ctrl); b1_interrupt()
595 capi_ctr_ready(ctrl); b1_interrupt()
642 struct capi_ctr *ctrl = m->private; b1ctl_proc_show() local
643 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1ctl_proc_show()
674 flag = ((u8 *)(ctrl->profile.manu))[3]; b1ctl_proc_show()
688 flag = ((u8 *)(ctrl->profile.manu))[5]; b1ctl_proc_show()
|
| H A D | t1isa.c | 139 struct capi_ctr *ctrl = &cinfo->capi_ctrl; t1isa_interrupt() local
176 capi_ctr_handle_message(ctrl, ApplId, skb); t1isa_interrupt()
195 capi_ctr_handle_message(ctrl, ApplId, skb); t1isa_interrupt()
220 capi_ctr_resume_output(ctrl); t1isa_interrupt()
225 capi_ctr_suspend_output(ctrl); t1isa_interrupt()
237 capi_ctr_ready(ctrl); t1isa_interrupt()
285 static int t1isa_load_firmware(struct capi_ctr *ctrl, capiloaddata *data) t1isa_load_firmware() argument
287 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); t1isa_load_firmware()
322 b1_put_word(port, ctrl->cnr - 1); t1isa_load_firmware()
328 static void t1isa_reset_ctr(struct capi_ctr *ctrl) t1isa_reset_ctr() argument
330 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); t1isa_reset_ctr()
343 capi_ctr_down(ctrl); t1isa_reset_ctr()
369 static u16 t1isa_send_message(struct capi_ctr *ctrl, struct sk_buff *skb);
370 static char *t1isa_procinfo(struct capi_ctr *ctrl);
458 static u16 t1isa_send_message(struct capi_ctr *ctrl, struct sk_buff *skb) t1isa_send_message() argument
460 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); t1isa_send_message()
494 static char *t1isa_procinfo(struct capi_ctr *ctrl) t1isa_procinfo() argument
496 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); t1isa_procinfo()
|
| H A D | b1pcmcia.c | 40 static void b1pcmcia_remove_ctr(struct capi_ctr *ctrl) b1pcmcia_remove_ctr() argument
42 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1pcmcia_remove_ctr()
49 detach_capi_ctr(ctrl); b1pcmcia_remove_ctr()
58 static char *b1pcmcia_procinfo(struct capi_ctr *ctrl);
141 static char *b1pcmcia_procinfo(struct capi_ctr *ctrl) b1pcmcia_procinfo() argument
143 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1pcmcia_procinfo()
|
| H A D | b1dma.c | 451 struct capi_ctr *ctrl = &cinfo->capi_ctrl; b1dma_handle_rx() local
479 capi_ctr_handle_message(ctrl, ApplId, skb); b1dma_handle_rx()
499 capi_ctr_handle_message(ctrl, ApplId, skb); b1dma_handle_rx()
531 capi_ctr_resume_output(ctrl); b1dma_handle_rx()
535 capi_ctr_suspend_output(ctrl); b1dma_handle_rx()
546 capi_ctr_ready(ctrl); b1dma_handle_rx()
704 int b1dma_load_firmware(struct capi_ctr *ctrl, capiloaddata *data) b1dma_load_firmware() argument
706 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1dma_load_firmware()
753 void b1dma_reset_ctr(struct capi_ctr *ctrl) b1dma_reset_ctr() argument
755 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1dma_reset_ctr()
765 capi_ctr_down(ctrl); b1dma_reset_ctr()
770 void b1dma_register_appl(struct capi_ctr *ctrl, b1dma_register_appl() argument
774 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1dma_register_appl()
782 else nconn = ctrl->profile.nbchannel * -want; b1dma_register_appl()
783 if (nconn == 0) nconn = ctrl->profile.nbchannel; b1dma_register_appl()
807 void b1dma_release_appl(struct capi_ctr *ctrl, u16 appl) b1dma_release_appl() argument
809 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1dma_release_appl()
838 u16 b1dma_send_message(struct capi_ctr *ctrl, struct sk_buff *skb) b1dma_send_message() argument
840 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1dma_send_message()
863 struct capi_ctr *ctrl = m->private; b1dmactl_proc_show() local
864 avmctrl_info *cinfo = (avmctrl_info *)(ctrl->driverdata); b1dmactl_proc_show()
896 flag = ((u8 *)(ctrl->profile.manu))[3]; b1dmactl_proc_show()
910 flag = ((u8 *)(ctrl->profile.manu))[5]; b1dmactl_proc_show()
|
| /linux-4.1.27/sound/soc/spear/ |
| H A D | spdif_out.c | 94 u32 divider, ctrl; spdif_out_clock() local
99 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); spdif_out_clock()
100 ctrl &= ~SPDIF_DIVIDER_MASK; spdif_out_clock()
101 ctrl |= (divider << SPDIF_DIVIDER_SHIFT) & SPDIF_DIVIDER_MASK; spdif_out_clock()
102 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); spdif_out_clock()
155 u32 ctrl; spdif_out_trigger() local
165 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); spdif_out_trigger()
166 ctrl &= ~SPDIF_OPMODE_MASK; spdif_out_trigger()
168 ctrl |= SPDIF_OPMODE_AUD_DATA | spdif_out_trigger()
171 ctrl |= SPDIF_OPMODE_MUTE_PCM; spdif_out_trigger()
172 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); spdif_out_trigger()
178 ctrl = readl(host->io_base + SPDIF_OUT_CTRL); spdif_out_trigger()
179 ctrl &= ~SPDIF_OPMODE_MASK; spdif_out_trigger()
180 ctrl |= SPDIF_OPMODE_OFF; spdif_out_trigger()
181 writel(ctrl, host->io_base + SPDIF_OUT_CTRL); spdif_out_trigger()
|
| H A D | spdif_in.c | 48 u32 ctrl = SPDIF_IN_PRTYEN | SPDIF_IN_STATEN | SPDIF_IN_USREN | spdif_in_configure() local
50 ctrl |= SPDIF_MODE_16BIT | SPDIF_FIFO_THRES_16; spdif_in_configure()
52 writel(ctrl, host->io_base + SPDIF_IN_CTRL); spdif_in_configure()
79 u32 ctrl = readl(host->io_base + SPDIF_IN_CTRL); spdif_in_format() local
83 ctrl |= SPDIF_XTRACT_16BIT; spdif_in_format()
87 ctrl &= ~SPDIF_XTRACT_16BIT; spdif_in_format()
91 writel(ctrl, host->io_base + SPDIF_IN_CTRL); spdif_in_format()
114 u32 ctrl; spdif_in_trigger() local
128 ctrl = readl(host->io_base + SPDIF_IN_CTRL); spdif_in_trigger()
129 ctrl |= SPDIF_IN_SAMPLE | SPDIF_IN_ENB; spdif_in_trigger()
130 writel(ctrl, host->io_base + SPDIF_IN_CTRL); spdif_in_trigger()
137 ctrl = readl(host->io_base + SPDIF_IN_CTRL); spdif_in_trigger()
138 ctrl &= ~(SPDIF_IN_SAMPLE | SPDIF_IN_ENB); spdif_in_trigger()
139 writel(ctrl, host->io_base + SPDIF_IN_CTRL); spdif_in_trigger()
|
| /linux-4.1.27/drivers/media/platform/s5p-mfc/ |
| H A D | s5p_mfc_enc.c | 1391 static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl) s5p_mfc_enc_s_ctrl() argument
1393 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl); s5p_mfc_enc_s_ctrl()
1398 switch (ctrl->id) { s5p_mfc_enc_s_ctrl()
1400 p->gop_size = ctrl->val; s5p_mfc_enc_s_ctrl()
1403 p->slice_mode = ctrl->val; s5p_mfc_enc_s_ctrl()
1406 p->slice_mb = ctrl->val; s5p_mfc_enc_s_ctrl()
1409 p->slice_bit = ctrl->val * 8; s5p_mfc_enc_s_ctrl()
1412 p->intra_refresh_mb = ctrl->val; s5p_mfc_enc_s_ctrl()
1415 p->pad = ctrl->val; s5p_mfc_enc_s_ctrl()
1418 p->pad_luma = (ctrl->val >> 16) & 0xff; s5p_mfc_enc_s_ctrl()
1419 p->pad_cb = (ctrl->val >> 8) & 0xff; s5p_mfc_enc_s_ctrl()
1420 p->pad_cr = (ctrl->val >> 0) & 0xff; s5p_mfc_enc_s_ctrl()
1423 p->rc_frame = ctrl->val; s5p_mfc_enc_s_ctrl()
1426 p->rc_bitrate = ctrl->val; s5p_mfc_enc_s_ctrl()
1429 p->rc_reaction_coeff = ctrl->val; s5p_mfc_enc_s_ctrl()
1432 ctx->force_frame_type = ctrl->val; s5p_mfc_enc_s_ctrl()
1435 p->vbv_size = ctrl->val; s5p_mfc_enc_s_ctrl()
1438 p->mv_h_range = ctrl->val; s5p_mfc_enc_s_ctrl()
1441 p->mv_v_range = ctrl->val; s5p_mfc_enc_s_ctrl()
1444 p->codec.h264.cpb_size = ctrl->val; s5p_mfc_enc_s_ctrl()
1447 p->seq_hdr_mode = ctrl->val; s5p_mfc_enc_s_ctrl()
1450 p->frame_skip_mode = ctrl->val; s5p_mfc_enc_s_ctrl()
1453 p->fixed_target_bit = ctrl->val; s5p_mfc_enc_s_ctrl()
1456 p->num_b_frame = ctrl->val; s5p_mfc_enc_s_ctrl()
1459 switch (ctrl->val) { s5p_mfc_enc_s_ctrl()
1484 p->codec.h264.level_v4l2 = ctrl->val; s5p_mfc_enc_s_ctrl()
1485 p->codec.h264.level = h264_level(ctrl->val); s5p_mfc_enc_s_ctrl()
1492 p->codec.mpeg4.level_v4l2 = ctrl->val; s5p_mfc_enc_s_ctrl()
1493 p->codec.mpeg4.level = mpeg4_level(ctrl->val); s5p_mfc_enc_s_ctrl()
1500 p->codec.h264.loop_filter_mode = ctrl->val; s5p_mfc_enc_s_ctrl()
1503 p->codec.h264.loop_filter_alpha = ctrl->val; s5p_mfc_enc_s_ctrl()
1506 p->codec.h264.loop_filter_beta = ctrl->val; s5p_mfc_enc_s_ctrl()
1509 p->codec.h264.entropy_mode = ctrl->val; s5p_mfc_enc_s_ctrl()
1512 p->codec.h264.num_ref_pic_4p = ctrl->val; s5p_mfc_enc_s_ctrl()
1515 p->codec.h264._8x8_transform = ctrl->val; s5p_mfc_enc_s_ctrl()
1518 p->rc_mb = ctrl->val; s5p_mfc_enc_s_ctrl()
1521 p->codec.h264.rc_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1524 p->codec.h264.rc_min_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1527 p->codec.h264.rc_max_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1530 p->codec.h264.rc_p_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1533 p->codec.h264.rc_b_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1537 p->codec.mpeg4.rc_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1541 p->codec.mpeg4.rc_min_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1545 p->codec.mpeg4.rc_max_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1549 p->codec.mpeg4.rc_p_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1553 p->codec.mpeg4.rc_b_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1556 p->codec.h264.rc_mb_dark = ctrl->val; s5p_mfc_enc_s_ctrl()
1559 p->codec.h264.rc_mb_smooth = ctrl->val; s5p_mfc_enc_s_ctrl()
1562 p->codec.h264.rc_mb_static = ctrl->val; s5p_mfc_enc_s_ctrl()
1565 p->codec.h264.rc_mb_activity = ctrl->val; s5p_mfc_enc_s_ctrl()
1568 p->codec.h264.vui_sar = ctrl->val; s5p_mfc_enc_s_ctrl()
1571 p->codec.h264.vui_sar_idc = vui_sar_idc(ctrl->val); s5p_mfc_enc_s_ctrl()
1574 p->codec.h264.vui_ext_sar_width = ctrl->val; s5p_mfc_enc_s_ctrl()
1577 p->codec.h264.vui_ext_sar_height = ctrl->val; s5p_mfc_enc_s_ctrl()
1580 p->codec.h264.open_gop = !ctrl->val; s5p_mfc_enc_s_ctrl()
1583 p->codec.h264.open_gop_size = ctrl->val; s5p_mfc_enc_s_ctrl()
1586 switch (ctrl->val) { s5p_mfc_enc_s_ctrl()
1600 p->codec.mpeg4.quarter_pixel = ctrl->val; s5p_mfc_enc_s_ctrl()
1603 p->codec.vp8.num_partitions = ctrl->val; s5p_mfc_enc_s_ctrl()
1606 p->codec.vp8.imd_4x4 = ctrl->val; s5p_mfc_enc_s_ctrl()
1609 p->codec.vp8.num_ref = ctrl->val; s5p_mfc_enc_s_ctrl()
1612 p->codec.vp8.filter_level = ctrl->val; s5p_mfc_enc_s_ctrl()
1615 p->codec.vp8.filter_sharpness = ctrl->val; s5p_mfc_enc_s_ctrl()
1618 p->codec.vp8.golden_frame_ref_period = ctrl->val; s5p_mfc_enc_s_ctrl()
1621 p->codec.vp8.golden_frame_sel = ctrl->val; s5p_mfc_enc_s_ctrl()
1624 p->codec.vp8.rc_min_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1627 p->codec.vp8.rc_max_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1630 p->codec.vp8.rc_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1633 p->codec.vp8.rc_p_frame_qp = ctrl->val; s5p_mfc_enc_s_ctrl()
1636 p->codec.vp8.profile = ctrl->val; s5p_mfc_enc_s_ctrl()
1640 ctrl->id, ctrl->val); s5p_mfc_enc_s_ctrl()
1646 static int s5p_mfc_enc_g_v_ctrl(struct v4l2_ctrl *ctrl) s5p_mfc_enc_g_v_ctrl() argument
1648 struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl); s5p_mfc_enc_g_v_ctrl()
1651 switch (ctrl->id) { s5p_mfc_enc_g_v_ctrl()
1655 ctrl->val = ctx->pb_count; s5p_mfc_enc_g_v_ctrl()
1666 ctrl->val = ctx->pb_count; s5p_mfc_enc_g_v_ctrl()
|
| /linux-4.1.27/drivers/media/tuners/ |
| H A D | tea5767.c | 29 struct tea5767_ctrl ctrl; member in struct:tea5767_priv
150 switch (priv->ctrl.xtal_freq) { tea5767_status_dump()
201 if (priv->ctrl.port1) set_radio_freq()
214 if (priv->ctrl.port2) set_radio_freq()
217 if (priv->ctrl.high_cut) set_radio_freq()
220 if (priv->ctrl.st_noise) set_radio_freq()
223 if (priv->ctrl.soft_mute) set_radio_freq()
226 if (priv->ctrl.japan_band) set_radio_freq()
231 if (priv->ctrl.deemph_75) set_radio_freq()
234 if (priv->ctrl.pllref) set_radio_freq()
241 switch (priv->ctrl.xtal_freq) { set_radio_freq()
421 memcpy(&priv->ctrl, priv_cfg, sizeof(priv->ctrl)); tea5767_set_config()
455 priv->ctrl.xtal_freq = TEA5767_HIGH_LO_32768; tea5767_attach()
456 priv->ctrl.port1 = 1; tea5767_attach()
457 priv->ctrl.port2 = 1; tea5767_attach()
458 priv->ctrl.high_cut = 1; tea5767_attach()
459 priv->ctrl.st_noise = 1; tea5767_attach()
460 priv->ctrl.japan_band = 1; tea5767_attach()
|
| H A D | tuner-xc2028.c | 119 struct xc2028_ctrl ctrl; member in struct:xc2028_data
132 if (priv->ctrl.msleep) \
133 msleep(priv->ctrl.msleep); \
144 if (priv->ctrl.msleep) \
145 msleep(priv->ctrl.msleep); \
156 } else if (priv->ctrl.msleep) \
157 msleep(priv->ctrl.msleep); \
547 if (priv->ctrl.max_len > sizeof(buf)) load_firmware()
548 priv->ctrl.max_len = sizeof(buf); load_firmware()
626 int len = (size < priv->ctrl.max_len - 1) ? load_firmware()
627 size : priv->ctrl.max_len - 1; load_firmware()
730 if (priv->ctrl.mts && !(type & FM)) check_firmware()
737 new_fw.scode_table = SCODE | priv->ctrl.scode_table; check_firmware()
748 dump_firm_type(priv->ctrl.scode_table); check_firmware()
749 printk("(%x), ", priv->ctrl.scode_table); check_firmware()
846 if (priv->ctrl.read_not_reliable) check_firmware()
851 if (!priv->ctrl.read_not_reliable) { check_firmware()
1130 if (priv->ctrl.msleep) generic_set_freq()
1131 msleep(priv->ctrl.msleep); generic_set_freq()
1169 if (priv->ctrl.input1) xc2028_set_analog_freq()
1217 switch (priv->ctrl.type) { xc2028_set_params()
1227 if (priv->ctrl.demod == XC3028_FE_ZARLINK456) xc2028_set_params()
1244 priv->ctrl.vhfbw7 = 0; xc2028_set_params()
1245 priv->ctrl.uhfbw8 = 0; xc2028_set_params()
1248 priv->ctrl.vhfbw7 = 1; xc2028_set_params()
1250 priv->ctrl.uhfbw8 = 0; xc2028_set_params()
1251 type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV7; xc2028_set_params()
1255 priv->ctrl.vhfbw7 = 0; xc2028_set_params()
1257 priv->ctrl.uhfbw8 = 1; xc2028_set_params()
1258 type |= (priv->ctrl.vhfbw7 && priv->ctrl.uhfbw8) ? DTV78 : DTV8; xc2028_set_params()
1263 if (priv->ctrl.demod) { xc2028_set_params()
1264 demod = priv->ctrl.demod; xc2028_set_params()
1302 if (no_poweroff || priv->ctrl.disable_power_mgmt) xc2028_sleep()
1337 kfree(priv->ctrl.fname); xc2028_dvb_release()
1338 priv->ctrl.fname = NULL; xc2028_dvb_release()
1405 kfree(priv->ctrl.fname); xc2028_set_config()
1406 memcpy(&priv->ctrl, p, sizeof(priv->ctrl)); xc2028_set_config()
1408 priv->ctrl.fname = kstrdup(p->fname, GFP_KERNEL); xc2028_set_config()
1409 if (priv->ctrl.fname == NULL) xc2028_set_config()
1421 if (priv->ctrl.max_len < 9) xc2028_set_config()
1422 priv->ctrl.max_len = 13; xc2028_set_config()
1426 priv->fname = priv->ctrl.fname; xc2028_set_config()
1494 priv->ctrl.max_len = 13; xc2028_attach()
1511 if (cfg->ctrl) xc2028_attach()
1512 xc2028_set_config(fe, cfg->ctrl); xc2028_attach()
|
| /linux-4.1.27/drivers/usb/gadget/function/ |
| H A D | f_uac1.c | 383 const struct usb_ctrlrequest *ctrl) audio_set_intf_req()
388 u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); audio_set_intf_req()
389 u16 len = le16_to_cpu(ctrl->wLength); audio_set_intf_req()
390 u16 w_value = le16_to_cpu(ctrl->wValue); audio_set_intf_req()
392 u8 cmd = (ctrl->bRequest & 0x0F); audio_set_intf_req()
397 ctrl->bRequest, w_value, len, id); audio_set_intf_req()
419 const struct usb_ctrlrequest *ctrl) audio_get_intf_req()
425 u8 id = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); audio_get_intf_req()
426 u16 len = le16_to_cpu(ctrl->wLength); audio_get_intf_req()
427 u16 w_value = le16_to_cpu(ctrl->wValue); audio_get_intf_req()
429 u8 cmd = (ctrl->bRequest & 0x0F); audio_get_intf_req()
434 ctrl->bRequest, w_value, len, id); audio_get_intf_req()
457 const struct usb_ctrlrequest *ctrl) audio_set_endpoint_req()
461 u16 ep = le16_to_cpu(ctrl->wIndex); audio_set_endpoint_req()
462 u16 len = le16_to_cpu(ctrl->wLength); audio_set_endpoint_req()
463 u16 w_value = le16_to_cpu(ctrl->wValue); audio_set_endpoint_req()
466 ctrl->bRequest, w_value, len, ep); audio_set_endpoint_req()
468 switch (ctrl->bRequest) { audio_set_endpoint_req()
493 const struct usb_ctrlrequest *ctrl) audio_get_endpoint_req()
497 u8 ep = ((le16_to_cpu(ctrl->wIndex) >> 8) & 0xFF); audio_get_endpoint_req()
498 u16 len = le16_to_cpu(ctrl->wLength); audio_get_endpoint_req()
499 u16 w_value = le16_to_cpu(ctrl->wValue); audio_get_endpoint_req()
502 ctrl->bRequest, w_value, len, ep); audio_get_endpoint_req()
504 switch (ctrl->bRequest) { audio_get_endpoint_req()
521 f_audio_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) f_audio_setup() argument
526 u16 w_index = le16_to_cpu(ctrl->wIndex); f_audio_setup()
527 u16 w_value = le16_to_cpu(ctrl->wValue); f_audio_setup()
528 u16 w_length = le16_to_cpu(ctrl->wLength); f_audio_setup()
533 switch (ctrl->bRequestType) { f_audio_setup()
535 value = audio_set_intf_req(f, ctrl); f_audio_setup()
539 value = audio_get_intf_req(f, ctrl); f_audio_setup()
543 value = audio_set_endpoint_req(f, ctrl); f_audio_setup()
547 value = audio_get_endpoint_req(f, ctrl); f_audio_setup()
552 ctrl->bRequestType, ctrl->bRequest, f_audio_setup()
559 ctrl->bRequestType, ctrl->bRequest, f_audio_setup()
382 audio_set_intf_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) audio_set_intf_req() argument
418 audio_get_intf_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) audio_get_intf_req() argument
456 audio_set_endpoint_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) audio_set_endpoint_req() argument
492 audio_get_endpoint_req(struct usb_function *f, const struct usb_ctrlrequest *ctrl) audio_get_endpoint_req() argument
|
| /linux-4.1.27/drivers/mfd/ |
| H A D | ti_am335x_tscadc.c | 146 int err, ctrl; ti_tscadc_probe() local
242 ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID; ti_tscadc_probe()
243 tscadc_writel(tscadc, REG_CTRL, ctrl); ti_tscadc_probe()
249 ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB; ti_tscadc_probe()
251 ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB; ti_tscadc_probe()
256 ctrl |= CNTRLREG_TSCSSENB; ti_tscadc_probe()
257 tscadc_writel(tscadc, REG_CTRL, ctrl); ti_tscadc_probe()
327 u32 ctrl; tscadc_resume() local
332 ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID; tscadc_resume()
333 tscadc_writel(tscadc_dev, REG_CTRL, ctrl); tscadc_resume()
337 ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB; tscadc_resume()
339 ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB; tscadc_resume()
342 ctrl |= CNTRLREG_TSCSSENB; tscadc_resume()
343 tscadc_writel(tscadc_dev, REG_CTRL, ctrl); tscadc_resume()
|
| /linux-4.1.27/drivers/usb/dwc3/ |
| H A D | trace.h | 83 TP_PROTO(struct usb_ctrlrequest *ctrl),
84 TP_ARGS(ctrl),
93 __entry->bRequestType = ctrl->bRequestType;
94 __entry->bRequest = ctrl->bRequest;
95 __entry->wValue = ctrl->wValue;
96 __entry->wIndex = ctrl->wIndex;
97 __entry->wLength = ctrl->wLength;
107 TP_PROTO(struct usb_ctrlrequest *ctrl),
108 TP_ARGS(ctrl)
221 __field(u32, ctrl)
229 __entry->ctrl = trb->ctrl;
231 TP_printk("%s: trb %p bph %08x bpl %08x size %08x ctrl %08x",
233 __entry->size, __entry->ctrl
|
| H A D | ep0.c | 78 trb->ctrl = type; dwc3_ep0_start_trans()
80 trb->ctrl |= (DWC3_TRB_CTRL_HWO dwc3_ep0_start_trans()
333 struct usb_ctrlrequest *ctrl) dwc3_ep0_handle_status()
341 recip = ctrl->bRequestType & USB_RECIP_MASK; dwc3_ep0_handle_status()
367 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); dwc3_ep0_handle_status()
391 struct usb_ctrlrequest *ctrl, int set) dwc3_ep0_handle_feature()
401 wValue = le16_to_cpu(ctrl->wValue); dwc3_ep0_handle_feature()
402 wIndex = le16_to_cpu(ctrl->wIndex); dwc3_ep0_handle_feature()
403 recip = ctrl->bRequestType & USB_RECIP_MASK; dwc3_ep0_handle_feature()
500 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dwc3_ep0_set_address() argument
506 addr = le16_to_cpu(ctrl->wValue); dwc3_ep0_set_address()
531 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dwc3_ep0_delegate_req() argument
536 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); dwc3_ep0_delegate_req()
541 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dwc3_ep0_set_config() argument
548 cfg = le16_to_cpu(ctrl->wValue); dwc3_ep0_set_config()
555 ret = dwc3_ep0_delegate_req(dwc, ctrl); dwc3_ep0_set_config()
583 ret = dwc3_ep0_delegate_req(dwc, ctrl); dwc3_ep0_set_config()
638 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dwc3_ep0_set_sel() argument
648 wValue = le16_to_cpu(ctrl->wValue); dwc3_ep0_set_sel()
649 wLength = le16_to_cpu(ctrl->wLength); dwc3_ep0_set_sel()
674 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dwc3_ep0_set_isoch_delay() argument
680 wValue = le16_to_cpu(ctrl->wValue); dwc3_ep0_set_isoch_delay()
681 wLength = le16_to_cpu(ctrl->wLength); dwc3_ep0_set_isoch_delay()
682 wIndex = le16_to_cpu(ctrl->wIndex); dwc3_ep0_set_isoch_delay()
696 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dwc3_ep0_std_request() argument
700 switch (ctrl->bRequest) { dwc3_ep0_std_request()
703 ret = dwc3_ep0_handle_status(dwc, ctrl); dwc3_ep0_std_request()
707 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); dwc3_ep0_std_request()
711 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); dwc3_ep0_std_request()
715 ret = dwc3_ep0_set_address(dwc, ctrl); dwc3_ep0_std_request()
719 ret = dwc3_ep0_set_config(dwc, ctrl); dwc3_ep0_std_request()
723 ret = dwc3_ep0_set_sel(dwc, ctrl); dwc3_ep0_std_request()
727 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); dwc3_ep0_std_request()
731 ret = dwc3_ep0_delegate_req(dwc, ctrl); dwc3_ep0_std_request()
741 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; dwc3_ep0_inspect_setup() local
748 trace_dwc3_ctrl_req(ctrl); dwc3_ep0_inspect_setup()
750 len = le16_to_cpu(ctrl->wLength); dwc3_ep0_inspect_setup()
757 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); dwc3_ep0_inspect_setup()
761 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) dwc3_ep0_inspect_setup()
762 ret = dwc3_ep0_std_request(dwc, ctrl); dwc3_ep0_inspect_setup()
764 ret = dwc3_ep0_delegate_req(dwc, ctrl); dwc3_ep0_inspect_setup()
332 dwc3_ep0_handle_status(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) dwc3_ep0_handle_status() argument
390 dwc3_ep0_handle_feature(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl, int set) dwc3_ep0_handle_feature() argument
|
| /linux-4.1.27/drivers/net/ethernet/micrel/ |
| H A D | ks8695net.c | 595 u32 ctrl; ks8695_link_irq() local
597 ctrl = readl(ksp->phyiface_regs + KS8695_WMC); ks8695_link_irq()
598 if (ctrl & WMC_WLS) { ks8695_link_irq()
604 (ctrl & WMC_WSS) ? "0" : "", ks8695_link_irq()
605 (ctrl & WMC_WDS) ? "Full" : "Half"); ks8695_link_irq()
666 u32 ctrl; ks8695_shutdown() local
670 ctrl = ks8695_readreg(ksp, KS8695_DTXC); ks8695_shutdown()
671 ks8695_writereg(ksp, KS8695_DTXC, ctrl & ~DTXC_TE); ks8695_shutdown()
674 ctrl = ks8695_readreg(ksp, KS8695_DRXC); ks8695_shutdown()
675 ks8695_writereg(ksp, KS8695_DRXC, ctrl & ~DRXC_RE); ks8695_shutdown()
757 u32 ctrl; ks8695_init_net() local
787 ctrl = ks8695_readreg(ksp, KS8695_DTXC); ks8695_init_net()
789 ks8695_writereg(ksp, KS8695_DTXC, ctrl | DTXC_TE); ks8695_init_net()
792 ctrl = ks8695_readreg(ksp, KS8695_DRXC); ks8695_init_net()
794 ks8695_writereg(ksp, KS8695_DRXC, ctrl | DRXC_RE); ks8695_init_net()
866 u32 ctrl; ks8695_wan_get_settings() local
879 ctrl = readl(ksp->phyiface_regs + KS8695_WMC); ks8695_wan_get_settings()
880 if ((ctrl & WMC_WAND) == 0) { ks8695_wan_get_settings()
883 if (ctrl & WMC_WANA100F) ks8695_wan_get_settings()
885 if (ctrl & WMC_WANA100H) ks8695_wan_get_settings()
887 if (ctrl & WMC_WANA10F) ks8695_wan_get_settings()
889 if (ctrl & WMC_WANA10H) ks8695_wan_get_settings()
891 if (ctrl & WMC_WANAP) ks8695_wan_get_settings()
896 (ctrl & WMC_WSS) ? SPEED_100 : SPEED_10); ks8695_wan_get_settings()
897 cmd->duplex = (ctrl & WMC_WDS) ? ks8695_wan_get_settings()
903 ethtool_cmd_speed_set(cmd, ((ctrl & WMC_WANF100) ? ks8695_wan_get_settings()
905 cmd->duplex = (ctrl & WMC_WANFF) ? ks8695_wan_get_settings()
921 u32 ctrl; ks8695_wan_set_settings() local
942 ctrl = readl(ksp->phyiface_regs + KS8695_WMC); ks8695_wan_set_settings()
944 ctrl &= ~(WMC_WAND | WMC_WANA100F | WMC_WANA100H | ks8695_wan_set_settings()
947 ctrl |= WMC_WANA100F; ks8695_wan_set_settings()
949 ctrl |= WMC_WANA100H; ks8695_wan_set_settings()
951 ctrl |= WMC_WANA10F; ks8695_wan_set_settings()
953 ctrl |= WMC_WANA10H; ks8695_wan_set_settings()
956 ctrl |= WMC_WANR; ks8695_wan_set_settings()
957 writel(ctrl, ksp->phyiface_regs + KS8695_WMC); ks8695_wan_set_settings()
959 ctrl = readl(ksp->phyiface_regs + KS8695_WMC); ks8695_wan_set_settings()
962 ctrl |= WMC_WAND; ks8695_wan_set_settings()
963 ctrl &= ~(WMC_WANF100 | WMC_WANFF); ks8695_wan_set_settings()
966 ctrl |= WMC_WANF100; ks8695_wan_set_settings()
968 ctrl |= WMC_WANFF; ks8695_wan_set_settings()
970 writel(ctrl, ksp->phyiface_regs + KS8695_WMC); ks8695_wan_set_settings()
984 u32 ctrl; ks8695_wan_nwayreset() local
986 ctrl = readl(ksp->phyiface_regs + KS8695_WMC); ks8695_wan_nwayreset()
988 if ((ctrl & WMC_WAND) == 0) ks8695_wan_nwayreset()
989 writel(ctrl | WMC_WANR, ks8695_wan_nwayreset()
1007 u32 ctrl; ks8695_wan_get_pause() local
1009 ctrl = readl(ksp->phyiface_regs + KS8695_WMC); ks8695_wan_get_pause()
1012 param->autoneg = (ctrl & WMC_WANAP); ks8695_wan_get_pause()
1015 ctrl = ks8695_readreg(ksp, KS8695_DRXC); ks8695_wan_get_pause()
1016 param->rx_pause = (ctrl & DRXC_RFCE); ks8695_wan_get_pause()
1019 ctrl = ks8695_readreg(ksp, KS8695_DTXC); ks8695_wan_get_pause()
1020 param->tx_pause = (ctrl & DTXC_TFCE); ks8695_wan_get_pause()
1091 u32 ctrl; ks8695_set_multicast() local
1093 ctrl = ks8695_readreg(ksp, KS8695_DRXC); ks8695_set_multicast()
1097 ctrl |= DRXC_RA; ks8695_set_multicast()
1100 ctrl &= ~DRXC_RA; ks8695_set_multicast()
1105 ctrl |= DRXC_RM; ks8695_set_multicast()
1110 ctrl |= DRXC_RM; ks8695_set_multicast()
1113 ctrl &= ~DRXC_RM; ks8695_set_multicast()
1117 ks8695_writereg(ksp, KS8695_DRXC, ctrl); ks8695_set_multicast()
1279 u32 ctrl; ks8695_init_switch() local
1282 ctrl = 0x40819e00; ks8695_init_switch()
1285 ctrl &= ~(SEC0_LLED1S | SEC0_LLED0S); ks8695_init_switch()
1286 ctrl |= (LLED0S_LINK | LLED1S_LINK_ACTIVITY); ks8695_init_switch()
1289 ctrl |= SEC0_ENABLE; ks8695_init_switch()
1291 writel(ctrl, ksp->phyiface_regs + KS8695_SEC0); ks8695_init_switch()
1307 u32 ctrl; ks8695_init_wan_phy() local
1310 ctrl = (WMC_WANAP | WMC_WANA100F | WMC_WANA100H | ks8695_init_wan_phy()
1314 ctrl |= (WLED0S_ACTIVITY | WLED1S_LINK); ks8695_init_wan_phy()
1317 ctrl |= WMC_WANR; ks8695_init_wan_phy()
1319 writel(ctrl, ksp->phyiface_regs + KS8695_WMC); ks8695_init_wan_phy()
|
| /linux-4.1.27/sound/soc/jz4740/ |
| H A D | jz4740-i2s.c | 135 uint32_t conf, ctrl; jz4740_i2s_startup() local
140 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); jz4740_i2s_startup()
141 ctrl |= JZ_AIC_CTRL_FLUSH; jz4740_i2s_startup()
142 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); jz4740_i2s_startup()
174 uint32_t ctrl; jz4740_i2s_trigger() local
182 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); jz4740_i2s_trigger()
188 ctrl |= mask; jz4740_i2s_trigger()
193 ctrl &= ~mask; jz4740_i2s_trigger()
199 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); jz4740_i2s_trigger()
260 uint32_t ctrl, div_reg; jz4740_i2s_hw_params() local
263 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL); jz4740_i2s_hw_params()
280 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK; jz4740_i2s_hw_params()
281 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET; jz4740_i2s_hw_params()
283 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO; jz4740_i2s_hw_params()
285 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO; jz4740_i2s_hw_params()
290 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK; jz4740_i2s_hw_params()
291 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET; jz4740_i2s_hw_params()
302 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl); jz4740_i2s_hw_params()
|
| /linux-4.1.27/sound/soc/fsl/ |
| H A D | fsl_spdif.c | 145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; spdif_irq_uqrx_full() local
152 pos = &ctrl->upos; spdif_irq_uqrx_full()
157 pos = &ctrl->qpos; spdif_irq_uqrx_full()
176 ctrl->subcode[*pos++] = val >> 16; spdif_irq_uqrx_full()
177 ctrl->subcode[*pos++] = val >> 8; spdif_irq_uqrx_full()
178 ctrl->subcode[*pos++] = val; spdif_irq_uqrx_full()
184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; spdif_irq_uq_sync() local
190 if (ctrl->qpos == 0) spdif_irq_uq_sync()
194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; spdif_irq_uq_sync()
200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; spdif_irq_uq_err() local
212 ctrl->ready_buf = 0; spdif_irq_uq_err()
213 ctrl->upos = 0; spdif_irq_uq_err()
214 ctrl->qpos = 0; spdif_irq_uq_err()
319 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, spdif_set_cstatus() argument
322 ctrl->ch_status[3] &= ~mask; spdif_set_cstatus()
323 ctrl->ch_status[3] |= cstatus & mask; spdif_set_cstatus()
328 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; spdif_write_channel_status() local
333 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | spdif_write_channel_status()
334 (bitrev8(ctrl->ch_status[1]) << 8) | spdif_write_channel_status()
335 bitrev8(ctrl->ch_status[2]); spdif_write_channel_status()
340 ch_status = bitrev8(ctrl->ch_status[3]) << 16; spdif_write_channel_status()
368 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; spdif_set_sample_rate() local
437 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); spdif_set_sample_rate()
546 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; fsl_spdif_hw_params() local
558 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, fsl_spdif_hw_params()
631 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; fsl_spdif_pb_get() local
633 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; fsl_spdif_pb_get()
634 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; fsl_spdif_pb_get()
635 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; fsl_spdif_pb_get()
636 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; fsl_spdif_pb_get()
646 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; fsl_spdif_pb_put() local
648 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; fsl_spdif_pb_put()
649 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; fsl_spdif_pb_put()
650 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; fsl_spdif_pb_put()
651 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; fsl_spdif_pb_put()
696 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; fsl_spdif_subcode_get() local
700 spin_lock_irqsave(&ctrl->ctl_lock, flags); fsl_spdif_subcode_get()
701 if (ctrl->ready_buf) { fsl_spdif_subcode_get()
702 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; fsl_spdif_subcode_get()
704 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); fsl_spdif_subcode_get()
707 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); fsl_spdif_subcode_get()
728 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; fsl_spdif_qget() local
732 spin_lock_irqsave(&ctrl->ctl_lock, flags); fsl_spdif_qget()
733 if (ctrl->ready_buf) { fsl_spdif_qget()
734 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; fsl_spdif_qget()
736 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); fsl_spdif_qget()
739 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); fsl_spdif_qget()
1159 struct spdif_mixer_control *ctrl; fsl_spdif_probe() local
1232 ctrl = &spdif_priv->fsl_spdif_control; fsl_spdif_probe()
1233 spin_lock_init(&ctrl->ctl_lock); fsl_spdif_probe()
1236 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | fsl_spdif_probe()
1238 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; fsl_spdif_probe()
1239 ctrl->ch_status[2] = 0x00; fsl_spdif_probe()
1240 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | fsl_spdif_probe()
|
| /linux-4.1.27/arch/mips/sgi-ip32/ |
| H A D | ip32-reset.c | 75 unsigned long led = mace->perif.ctrl.misc ^ MACEISA_LED_RED; blink_timeout()
76 mace->perif.ctrl.misc = led; blink_timeout()
120 led = mace->perif.ctrl.misc | MACEISA_LED_GREEN; panic_event()
121 mace->perif.ctrl.misc = led; panic_event()
136 unsigned long led = mace->perif.ctrl.misc; ip32_reboot_setup()
139 mace->perif.ctrl.misc = led; ip32_reboot_setup()
|
| /linux-4.1.27/arch/arm/mach-ep93xx/ |
| H A D | snappercl15.c | 50 unsigned int ctrl) snappercl15_nand_cmd_ctrl()
56 if (ctrl & NAND_CTRL_CHANGE) { snappercl15_nand_cmd_ctrl()
59 if (ctrl & NAND_NCE) snappercl15_nand_cmd_ctrl()
61 if (ctrl & NAND_CLE) snappercl15_nand_cmd_ctrl()
63 if (ctrl & NAND_ALE) snappercl15_nand_cmd_ctrl()
104 .ctrl = {
49 snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) snappercl15_nand_cmd_ctrl() argument
|
| H A D | ts72xx.c | 75 int cmd, unsigned int ctrl) ts72xx_nand_hwcontrol()
79 if (ctrl & NAND_CTRL_CHANGE) { ts72xx_nand_hwcontrol()
86 bits |= (ctrl & NAND_NCE) << 2; /* bit 0 -> bit 2 */ ts72xx_nand_hwcontrol()
87 bits |= (ctrl & NAND_CLE); /* bit 1 -> bit 1 */ ts72xx_nand_hwcontrol()
88 bits |= (ctrl & NAND_ALE) >> 2; /* bit 2 -> bit 0 */ ts72xx_nand_hwcontrol()
137 .ctrl = {
74 ts72xx_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) ts72xx_nand_hwcontrol() argument
|
| /linux-4.1.27/drivers/usb/early/ |
| H A D | ehci-dbgp.c | 163 u32 ctrl; dbgp_wait_until_complete() local
167 ctrl = readl(&ehci_debug->control); dbgp_wait_until_complete()
169 if (ctrl & DBGP_DONE) dbgp_wait_until_complete()
181 writel(ctrl | DBGP_DONE, &ehci_debug->control); dbgp_wait_until_complete()
182 return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl); dbgp_wait_until_complete()
200 static int dbgp_wait_until_done(unsigned ctrl, int loop) dbgp_wait_until_done() argument
206 writel(ctrl | DBGP_GO, &ehci_debug->control); dbgp_wait_until_done()
275 u32 pids, ctrl; dbgp_bulk_write() local
285 ctrl = readl(&ehci_debug->control); dbgp_bulk_write()
286 ctrl = dbgp_len_update(ctrl, size); dbgp_bulk_write()
287 ctrl |= DBGP_OUT; dbgp_bulk_write()
288 ctrl |= DBGP_GO; dbgp_bulk_write()
293 ret = dbgp_wait_until_done(ctrl, DBGP_LOOPS); dbgp_bulk_write()
301 u32 pids, addr, ctrl; dbgp_bulk_read() local
312 ctrl = readl(&ehci_debug->control); dbgp_bulk_read()
313 ctrl = dbgp_len_update(ctrl, size); dbgp_bulk_read()
314 ctrl &= ~DBGP_OUT; dbgp_bulk_read()
315 ctrl |= DBGP_GO; dbgp_bulk_read()
319 ret = dbgp_wait_until_done(ctrl, loops); dbgp_bulk_read()
332 u32 pids, addr, ctrl; dbgp_control_msg() local
351 ctrl = readl(&ehci_debug->control); dbgp_control_msg()
352 ctrl = dbgp_len_update(ctrl, sizeof(req)); dbgp_control_msg()
353 ctrl |= DBGP_OUT; dbgp_control_msg()
354 ctrl |= DBGP_GO; dbgp_control_msg()
360 ret = dbgp_wait_until_done(ctrl, DBGP_LOOPS); dbgp_control_msg()
433 u32 ctrl, cmd, status; dbgp_ehci_startup() local
437 ctrl = readl(&ehci_debug->control); dbgp_ehci_startup()
438 ctrl |= DBGP_OWNER; dbgp_ehci_startup()
439 ctrl &= ~(DBGP_ENABLED | DBGP_INUSE); dbgp_ehci_startup()
440 writel(ctrl, &ehci_debug->control); dbgp_ehci_startup()
500 u32 ctrl, portsc, cmd; _dbgp_external_startup() local
539 ctrl = readl(&ehci_debug->control); _dbgp_external_startup()
540 ctrl |= DBGP_CLAIM; _dbgp_external_startup()
541 writel(ctrl, &ehci_debug->control); _dbgp_external_startup()
542 ctrl = readl(&ehci_debug->control); _dbgp_external_startup()
543 if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) { _dbgp_external_startup()
545 writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control); _dbgp_external_startup()
759 u32 ctrl, portsc, hcs_params; ehci_setup() local
809 ctrl = readl(&ehci_debug->control); ehci_setup()
810 ctrl &= ~(DBGP_CLAIM | DBGP_OUT); ehci_setup()
811 writel(ctrl, &ehci_debug->control); ehci_setup()
919 u32 cmd, ctrl; early_dbgp_write() local
930 ctrl = readl(&ehci_debug->control); early_dbgp_write()
931 if (!(ctrl & DBGP_ENABLED)) { early_dbgp_write()
977 u32 ctrl; dbgp_reset_prep() local
993 ctrl = readl(&ehci_debug->control); dbgp_reset_prep()
994 if (ctrl & DBGP_ENABLED) { dbgp_reset_prep()
995 ctrl &= ~(DBGP_CLAIM); dbgp_reset_prep()
996 writel(ctrl, &ehci_debug->control); dbgp_reset_prep()
|
| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | nv40.c | 33 u32 ctrl; member in struct:nv40_clk_priv
52 u32 ctrl = nv_rd32(priv, reg + 0x00); read_pll_1() local
53 int P = (ctrl & 0x00070000) >> 16; read_pll_1()
54 int N = (ctrl & 0x0000ff00) >> 8; read_pll_1()
55 int M = (ctrl & 0x000000ff) >> 0; read_pll_1()
58 if (ctrl & 0x80000000) read_pll_1()
67 u32 ctrl = nv_rd32(priv, reg + 0x00); read_pll_2() local
73 int P = (ctrl & 0x00070000) >> 16; read_pll_2()
76 if ((ctrl & 0x80000000) && M1) { read_pll_2()
78 if ((ctrl & 0x40000100) == 0x40000000) { read_pll_2()
182 priv->ctrl = 0x00000223; nv40_clk_calc()
185 priv->ctrl = 0x00000333; nv40_clk_calc()
200 nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl); nv40_clk_prog()
|
| /linux-4.1.27/arch/cris/arch-v32/kernel/ |
| H A D | time.c | 151 reg_clkgen_rw_clk_ctrl ctrl = handle_watchdog_bite() local
153 ctrl.pll = 0; handle_watchdog_bite()
154 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl); handle_watchdog_bite()
178 reg_timer_rw_tmr0_ctrl ctrl = { crisv32_clkevt_mode() local
183 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_clkevt_mode()
189 reg_timer_rw_tmr0_ctrl ctrl = { crisv32_clkevt_next_event() local
195 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_clkevt_next_event()
197 ctrl.op = regk_timer_run; crisv32_clkevt_next_event()
198 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_clkevt_next_event()
206 reg_timer_rw_tmr0_ctrl ctrl = { crisv32_timer_interrupt() local
217 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_timer_interrupt()
254 reg_timer_rw_tmr0_ctrl ctrl = { crisv32_timer_init() local
259 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_timer_init()
|
| /linux-4.1.27/drivers/mtd/maps/ |
| H A D | scx200_docflash.c | 79 unsigned ctrl; init_scx200_docflash() local
99 pci_read_config_dword(bridge, SCx200_DOCCS_CTRL, &ctrl); init_scx200_docflash()
105 || (ctrl & 0x07000000) != 0x07000000 init_scx200_docflash()
106 || (ctrl & 0x0007ffff) == 0) init_scx200_docflash()
109 size = ((ctrl&0x1fff)<<13) + (1<<13); init_scx200_docflash()
150 ctrl = 0x07000000 | ((size-1) >> 13); init_scx200_docflash()
152 printk(KERN_INFO "DOCCS BASE=0x%08lx, CTRL=0x%08lx\n", (long)docmem.start, (long)ctrl); init_scx200_docflash()
155 pci_write_config_dword(bridge, SCx200_DOCCS_CTRL, ctrl); init_scx200_docflash()
|
| /linux-4.1.27/arch/arm/mach-s3c64xx/ |
| H A D | setup-ide.c | 41 /* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */ s3c64xx_ide_setup_gpio()
|
| /linux-4.1.27/include/media/ |
| H A D | v4l2-ctrls.h | 67 * ctrl->handler->lock is held when these ops are called, so no
71 int (*g_volatile_ctrl)(struct v4l2_ctrl *ctrl);
72 int (*try_ctrl)(struct v4l2_ctrl *ctrl);
73 int (*s_ctrl)(struct v4l2_ctrl *ctrl);
83 bool (*equal)(const struct v4l2_ctrl *ctrl, u32 idx,
86 void (*init)(const struct v4l2_ctrl *ctrl, u32 idx,
88 void (*log)(const struct v4l2_ctrl *ctrl);
89 int (*validate)(const struct v4l2_ctrl *ctrl, u32 idx,
93 typedef void (*v4l2_ctrl_notify_fnc)(struct v4l2_ctrl *ctrl, void *priv);
115 * uses ctrl->val).
216 * @ctrl: The actual control information.
226 struct v4l2_ctrl *ctrl; member in struct:v4l2_ctrl_ref
374 * @ctrl: The control to lock.
376 static inline void v4l2_ctrl_lock(struct v4l2_ctrl *ctrl) v4l2_ctrl_lock() argument
378 mutex_lock(ctrl->handler->lock); v4l2_ctrl_lock()
383 * @ctrl: The control to unlock.
385 static inline void v4l2_ctrl_unlock(struct v4l2_ctrl *ctrl) v4l2_ctrl_unlock() argument
387 mutex_unlock(ctrl->handler->lock); v4l2_ctrl_unlock()
511 * @ctrl: The control to add.
515 * nothing and just return @ctrl.
518 struct v4l2_ctrl *ctrl);
535 bool (*filter)(const struct v4l2_ctrl *ctrl));
538 * @ctrl: The control that is filtered.
546 bool v4l2_ctrl_radio_filter(const struct v4l2_ctrl *ctrl);
598 * @ctrl: The control to (de)activate.
602 * Does nothing if @ctrl == NULL.
608 void v4l2_ctrl_activate(struct v4l2_ctrl *ctrl, bool active);
611 * @ctrl: The control to (de)activate.
615 * Does nothing if @ctrl == NULL.
623 void v4l2_ctrl_grab(struct v4l2_ctrl *ctrl, bool grabbed);
627 int __v4l2_ctrl_modify_range(struct v4l2_ctrl *ctrl,
631 * @ctrl: The control to update.
647 static inline int v4l2_ctrl_modify_range(struct v4l2_ctrl *ctrl, v4l2_ctrl_modify_range() argument
652 v4l2_ctrl_lock(ctrl); v4l2_ctrl_modify_range()
653 rval = __v4l2_ctrl_modify_range(ctrl, min, max, step, def); v4l2_ctrl_modify_range()
654 v4l2_ctrl_unlock(ctrl); v4l2_ctrl_modify_range()
660 * @ctrl: The control.
664 * This function sets a callback function for the control. If @ctrl is NULL,
671 void v4l2_ctrl_notify(struct v4l2_ctrl *ctrl, v4l2_ctrl_notify_fnc notify, void *priv);
699 * @ctrl: The control.
707 s32 v4l2_ctrl_g_ctrl(struct v4l2_ctrl *ctrl);
710 int __v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val);
712 * @ctrl: The control.
721 static inline int v4l2_ctrl_s_ctrl(struct v4l2_ctrl *ctrl, s32 val) v4l2_ctrl_s_ctrl() argument
725 v4l2_ctrl_lock(ctrl); v4l2_ctrl_s_ctrl()
726 rval = __v4l2_ctrl_s_ctrl(ctrl, val); v4l2_ctrl_s_ctrl()
727 v4l2_ctrl_unlock(ctrl); v4l2_ctrl_s_ctrl()
733 * @ctrl: The control.
741 s64 v4l2_ctrl_g_ctrl_int64(struct v4l2_ctrl *ctrl);
744 int __v4l2_ctrl_s_ctrl_int64(struct v4l2_ctrl *ctrl, s64 val);
747 * @ctrl: The control.
756 static inline int v4l2_ctrl_s_ctrl_int64(struct v4l2_ctrl *ctrl, s64 val) v4l2_ctrl_s_ctrl_int64() argument
760 v4l2_ctrl_lock(ctrl); v4l2_ctrl_s_ctrl_int64()
761 rval = __v4l2_ctrl_s_ctrl_int64(ctrl, val); v4l2_ctrl_s_ctrl_int64()
762 v4l2_ctrl_unlock(ctrl); v4l2_ctrl_s_ctrl_int64()
768 int __v4l2_ctrl_s_ctrl_string(struct v4l2_ctrl *ctrl, const char *s);
771 * @ctrl: The control.
780 static inline int v4l2_ctrl_s_ctrl_string(struct v4l2_ctrl *ctrl, const char *s) v4l2_ctrl_s_ctrl_string() argument
784 v4l2_ctrl_lock(ctrl); v4l2_ctrl_s_ctrl_string()
785 rval = __v4l2_ctrl_s_ctrl_string(ctrl, s); v4l2_ctrl_s_ctrl_string()
786 v4l2_ctrl_unlock(ctrl); v4l2_ctrl_s_ctrl_string()
812 int v4l2_g_ctrl(struct v4l2_ctrl_handler *hdl, struct v4l2_control *ctrl);
814 struct v4l2_control *ctrl);
827 int v4l2_subdev_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl);
828 int v4l2_subdev_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl);
|
| /linux-4.1.27/drivers/pci/ |
| H A D | ats.c | 60 u16 ctrl; pci_enable_ats() local
89 ctrl = PCI_ATS_CTRL_ENABLE; pci_enable_ats()
91 ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU); pci_enable_ats()
92 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl); pci_enable_ats()
106 u16 ctrl; pci_disable_ats() local
110 pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl); pci_disable_ats()
111 ctrl &= ~PCI_ATS_CTRL_ENABLE; pci_disable_ats()
112 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl); pci_disable_ats()
133 u16 ctrl; pci_restore_ats_state() local
140 ctrl = PCI_ATS_CTRL_ENABLE; pci_restore_ats_state()
142 ctrl |= PCI_ATS_CTRL_STU(dev->ats->stu - PCI_ATS_MIN_STU); pci_restore_ats_state()
144 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl); pci_restore_ats_state()
|
| /linux-4.1.27/arch/blackfin/mach-common/ |
| H A D | cache-c.c | 45 u32 ctrl; bfin_cache_init() local
48 ctrl = bfin_read32(mem_control) | (1 << RDCHK); bfin_cache_init()
50 bfin_write32(mem_control, ctrl); bfin_cache_init()
|
| /linux-4.1.27/drivers/video/fbdev/omap/ |
| H A D | omapfb_main.c | 167 r = fbdev->ctrl->init(fbdev, 0, &fbdev->mem_desc); ctrl_init()
188 fbdev->ctrl->cleanup(); ctrl_cleanup()
203 if (fbdev->ctrl->sync) ctrl_change_mode()
204 fbdev->ctrl->sync(); ctrl_change_mode()
205 r = fbdev->ctrl->setup_plane(plane->idx, plane->info.channel_out, ctrl_change_mode()
212 if (fbdev->ctrl->set_rotate != NULL) { ctrl_change_mode()
213 r = fbdev->ctrl->set_rotate(var->rotate); ctrl_change_mode()
218 if (fbdev->ctrl->set_scale != NULL) ctrl_change_mode()
219 r = fbdev->ctrl->set_scale(plane->idx, ctrl_change_mode()
270 if (fbdev->ctrl->setcolreg) _setcolreg()
271 r = fbdev->ctrl->setcolreg(regno, red, green, blue, _setcolreg()
343 if (fbdev->ctrl->resume) omapfb_blank()
344 fbdev->ctrl->resume(); omapfb_blank()
347 if (fbdev->ctrl->get_update_mode() == omapfb_blank()
355 if (fbdev->ctrl->suspend) omapfb_blank()
356 fbdev->ctrl->suspend(); omapfb_blank()
377 if (fbdev->ctrl->sync) omapfb_sync()
378 fbdev->ctrl->sync(); omapfb_sync()
685 if (fbdev->ctrl->sync != NULL) omapfb_check_var()
686 fbdev->ctrl->sync(); omapfb_check_var()
740 if (!fbdev->ctrl->update_window || omapfb_update_window_async()
741 fbdev->ctrl->get_update_mode() != OMAPFB_MANUAL_UPDATE) omapfb_update_window_async()
755 return fbdev->ctrl->update_window(fbi, win, callback, callback_data); omapfb_update_window_async()
779 if (!fbdev->ctrl->update_window || omapfb_update_full_screen()
780 fbdev->ctrl->get_update_mode() != OMAPFB_MANUAL_UPDATE) omapfb_update_full_screen()
794 r = fbdev->ctrl->update_window(fbi, &win, NULL, NULL); omapfb_update_full_screen()
830 r = fbdev->ctrl->enable_plane(plane->idx, pi->enabled); omapfb_setup_plane()
856 if (fbdev->ctrl->setup_mem == NULL) omapfb_setup_mem()
890 if (fbdev->ctrl->sync) omapfb_setup_mem()
891 fbdev->ctrl->sync(); omapfb_setup_mem()
892 r = fbdev->ctrl->setup_mem(plane->idx, size, mi->type, &paddr); omapfb_setup_mem()
943 if (!fbdev->ctrl->set_color_key) omapfb_set_color_key()
947 r = fbdev->ctrl->set_color_key(ck); omapfb_set_color_key()
958 if (!fbdev->ctrl->get_color_key) omapfb_get_color_key()
962 r = fbdev->ctrl->get_color_key(ck); omapfb_get_color_key()
1002 omapfb_dev->ctrl && omapfb_dev->ctrl->bind_client) { omapfb_register_client()
1003 omapfb_dev->ctrl->bind_client(omapfb_nb); omapfb_register_client()
1037 r = fbdev->ctrl->set_update_mode(mode); omapfb_set_update_mode()
1048 r = fbdev->ctrl->get_update_mode(); omapfb_get_update_mode()
1058 fbdev->ctrl->get_caps(plane, caps); omapfb_get_caps()
1059 caps->ctrl |= fbdev->panel->get_caps(fbdev->panel); omapfb_get_caps()
1067 if (fbdev->ctrl->get_update_mode() == OMAPFB_MANUAL_UPDATE) { omapfb_write_first_pixel()
1075 fbdev->ctrl->update_window(fbdev->fb_info[0], &win, NULL, NULL); omapfb_write_first_pixel()
1220 if (!fbdev->ctrl->run_test) { omapfb_ioctl()
1224 r = fbdev->ctrl->run_test(test_num); omapfb_ioctl()
1241 r = fbdev->ctrl->mmap(info, vma); omapfb_mmap()
1288 plane, caps.ctrl, caps.plane_color, caps.wnd_color); omapfb_show_caps_num()
1311 if (ctrl_caps[i].flag & caps.ctrl) omapfb_show_caps_text()
1416 /* ctrl sysfs entries */ omapfb_show_ctrl_name()
1422 return snprintf(buf, PAGE_SIZE, "%s\n", fbdev->ctrl->name); omapfb_show_ctrl_name()
1434 .name = "ctrl",
1607 fbdev->ctrl = NULL; omapfb_find_ctrl()
1613 fbdev->ctrl = fbdev->int_ctrl; omapfb_find_ctrl()
1618 dev_dbg(fbdev->dev, "ctrl %s\n", ctrls[i]->name); omapfb_find_ctrl()
1620 fbdev->ctrl = ctrls[i]; omapfb_find_ctrl()
1625 if (fbdev->ctrl == NULL) { omapfb_find_ctrl()
1626 dev_dbg(fbdev->dev, "ctrl %s not supported\n", name); omapfb_find_ctrl()
1635 #define _C(x) (fbdev->ctrl->x != NULL) check_required_callbacks()
1637 BUG_ON(fbdev->ctrl == NULL || fbdev->panel == NULL); check_required_callbacks()
1724 if (fbdev->ctrl->mmap != NULL) omapfb_do_probe()
1747 r = fbdev->ctrl->enable_plane(OMAPFB_PLANE_GFX, 1); omapfb_do_probe()
|
| /linux-4.1.27/drivers/pinctrl/mvebu/ |
| H A D | pinctrl-mvebu.c | 41 struct mvebu_mpp_ctrl *ctrl; member in struct:mvebu_pinctrl_group
146 if (!grp->ctrl) mvebu_pinconf_group_get()
149 return grp->ctrl->mpp_get(grp->pins[0], config); mvebu_pinconf_group_get()
160 if (!grp->ctrl) mvebu_pinconf_group_set()
164 ret = grp->ctrl->mpp_set(grp->pins[0], configs[i]); mvebu_pinconf_group_set()
304 if (grp->ctrl->mpp_gpio_req) mvebu_pinmux_gpio_request_enable()
305 return grp->ctrl->mpp_gpio_req(offset); mvebu_pinmux_gpio_request_enable()
327 if (grp->ctrl->mpp_gpio_dir) mvebu_pinmux_gpio_set_direction()
328 return grp->ctrl->mpp_gpio_dir(offset, input); mvebu_pinmux_gpio_set_direction()
585 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; mvebu_pinctrl_probe() local
587 pctl->desc.npins += ctrl->npins; mvebu_pinctrl_probe()
589 for (k = 0; k < ctrl->npins; k++) mvebu_pinctrl_probe()
590 ctrl->pins[k] = ctrl->pid + k; mvebu_pinctrl_probe()
597 if (!ctrl->name) { mvebu_pinctrl_probe()
598 pctl->num_groups += ctrl->npins; mvebu_pinctrl_probe()
599 noname += ctrl->npins; mvebu_pinctrl_probe()
631 struct mvebu_mpp_ctrl *ctrl = &soc->controls[n]; mvebu_pinctrl_probe() local
633 pctl->groups[gid].ctrl = ctrl; mvebu_pinctrl_probe()
634 pctl->groups[gid].name = ctrl->name; mvebu_pinctrl_probe()
635 pctl->groups[gid].pins = ctrl->pins; mvebu_pinctrl_probe()
636 pctl->groups[gid].npins = ctrl->npins; mvebu_pinctrl_probe()
643 if (!ctrl->name) { mvebu_pinctrl_probe()
646 sprintf(noname_buf, "mpp%d", ctrl->pid+0); mvebu_pinctrl_probe()
649 for (k = 1; k < ctrl->npins; k++) { mvebu_pinctrl_probe()
652 pctl->groups[gid].ctrl = ctrl; mvebu_pinctrl_probe()
654 pctl->groups[gid].pins = &ctrl->pins[k]; mvebu_pinctrl_probe()
656 sprintf(noname_buf, "mpp%d", ctrl->pid+k); mvebu_pinctrl_probe()
|
| /linux-4.1.27/drivers/media/platform/exynos4-is/ |
| H A D | fimc-isp.c | 472 struct v4l2_ctrl *ctrl) __ctrl_set_aewb_lock()
474 bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; __ctrl_set_aewb_lock()
475 bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; __ctrl_set_aewb_lock()
591 static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl) fimc_is_s_ctrl() argument
593 struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl); fimc_is_s_ctrl()
598 switch (ctrl->id) { fimc_is_s_ctrl()
601 ctrl->val); fimc_is_s_ctrl()
606 ctrl->val); fimc_is_s_ctrl()
611 ctrl->val); fimc_is_s_ctrl()
616 ctrl->val); fimc_is_s_ctrl()
621 ctrl->val); fimc_is_s_ctrl()
626 ctrl->val); fimc_is_s_ctrl()
630 ret = __ctrl_set_metering(is, ctrl->val); fimc_is_s_ctrl()
634 ret = __ctrl_set_white_balance(is, ctrl->val); fimc_is_s_ctrl()
638 ret = __ctrl_set_aewb_lock(is, ctrl); fimc_is_s_ctrl()
643 ret = __ctrl_set_iso(is, ctrl->val); fimc_is_s_ctrl()
647 ret = __ctrl_set_afc(is, ctrl->val); fimc_is_s_ctrl()
651 __ctrl_set_image_effect(is, ctrl->val); fimc_is_s_ctrl()
661 ctrl->name, ctrl->val); fimc_is_s_ctrl()
471 __ctrl_set_aewb_lock(struct fimc_is *is, struct v4l2_ctrl *ctrl) __ctrl_set_aewb_lock() argument
|
| /linux-4.1.27/arch/sparc/kernel/ |
| H A D | leon_kernel.c | 185 /* Used by external level sensitive IRQ handlers on the LEON: ACK IRQ ctrl */ leon_eoi_irq()
264 u32 rld, val, ctrl, off; leon_cycles_offset() local
268 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); leon_cycles_offset()
269 if (LEON3_GPTIMER_CTRL_ISPENDING(ctrl)) { leon_cycles_offset()
314 u32 ctrl; leon_init_timers() local
387 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); leon_init_timers()
388 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, leon_init_timers()
389 ctrl | LEON3_GPTIMER_CTRL_PENDING); leon_init_timers()
390 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); leon_init_timers()
392 if ((ctrl & LEON3_GPTIMER_CTRL_PENDING) != 0) leon_init_timers()
401 &leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, 0); leon_init_timers()
461 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, leon_init_timers()
475 u32 ctrl; leon_clear_clock_irq() local
477 ctrl = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl); leon_clear_clock_irq()
478 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, leon_clear_clock_irq()
479 ctrl & leon3_gptimer_ackmask); leon_clear_clock_irq()
|
| /linux-4.1.27/arch/powerpc/platforms/cell/ |
| H A D | pervasive.c | 43 unsigned long ctrl, thread_switch_control; cbe_power_save() local
49 ctrl = mfspr(SPRN_CTRLF); cbe_power_save()
55 switch (ctrl & CTRL_CT) { cbe_power_save()
80 ctrl &= ~(CTRL_RUNLATCH | CTRL_TE); cbe_power_save()
81 mtspr(SPRN_CTRLT, ctrl); cbe_power_save()
|
| /linux-4.1.27/drivers/media/pci/saa7164/ |
| H A D | saa7164-encoder.c | 499 struct v4l2_ext_control *ctrl) saa7164_get_ctrl()
503 switch (ctrl->id) { saa7164_get_ctrl()
505 ctrl->value = params->bitrate; saa7164_get_ctrl()
508 ctrl->value = params->stream_type; saa7164_get_ctrl()
511 ctrl->value = params->ctl_mute; saa7164_get_ctrl()
514 ctrl->value = params->ctl_aspect; saa7164_get_ctrl()
517 ctrl->value = params->bitrate_mode; saa7164_get_ctrl()
520 ctrl->value = params->refdist; saa7164_get_ctrl()
523 ctrl->value = params->bitrate_peak; saa7164_get_ctrl()
526 ctrl->value = params->gop_size; saa7164_get_ctrl()
543 struct v4l2_ext_control *ctrl = ctrls->controls + i; vidioc_g_ext_ctrls() local
545 err = saa7164_get_ctrl(port, ctrl); vidioc_g_ext_ctrls()
558 static int saa7164_try_ctrl(struct v4l2_ext_control *ctrl, int ac3) saa7164_try_ctrl() argument
562 switch (ctrl->id) { saa7164_try_ctrl()
564 if ((ctrl->value >= ENCODER_MIN_BITRATE) && saa7164_try_ctrl()
565 (ctrl->value <= ENCODER_MAX_BITRATE)) saa7164_try_ctrl()
569 if ((ctrl->value == V4L2_MPEG_STREAM_TYPE_MPEG2_PS) || saa7164_try_ctrl()
570 (ctrl->value == V4L2_MPEG_STREAM_TYPE_MPEG2_TS)) saa7164_try_ctrl()
574 if ((ctrl->value >= 0) && saa7164_try_ctrl()
575 (ctrl->value <= 1)) saa7164_try_ctrl()
579 if ((ctrl->value >= V4L2_MPEG_VIDEO_ASPECT_1x1) && saa7164_try_ctrl()
580 (ctrl->value <= V4L2_MPEG_VIDEO_ASPECT_221x100)) saa7164_try_ctrl()
584 if ((ctrl->value >= 0) && saa7164_try_ctrl()
585 (ctrl->value <= 255)) saa7164_try_ctrl()
589 if ((ctrl->value == V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) || saa7164_try_ctrl()
590 (ctrl->value == V4L2_MPEG_VIDEO_BITRATE_MODE_CBR)) saa7164_try_ctrl()
594 if ((ctrl->value >= 1) && saa7164_try_ctrl()
595 (ctrl->value <= 3)) saa7164_try_ctrl()
599 if ((ctrl->value >= ENCODER_MIN_BITRATE) && saa7164_try_ctrl()
600 (ctrl->value <= ENCODER_MAX_BITRATE)) saa7164_try_ctrl()
617 struct v4l2_ext_control *ctrl = ctrls->controls + i; vidioc_try_ext_ctrls() local
619 err = saa7164_try_ctrl(ctrl, 0); vidioc_try_ext_ctrls()
632 struct v4l2_ext_control *ctrl) saa7164_set_ctrl()
637 switch (ctrl->id) { saa7164_set_ctrl()
639 params->bitrate = ctrl->value; saa7164_set_ctrl()
642 params->stream_type = ctrl->value; saa7164_set_ctrl()
645 params->ctl_mute = ctrl->value; saa7164_set_ctrl()
654 params->ctl_aspect = ctrl->value; saa7164_set_ctrl()
663 params->bitrate_mode = ctrl->value; saa7164_set_ctrl()
666 params->refdist = ctrl->value; saa7164_set_ctrl()
669 params->bitrate_peak = ctrl->value; saa7164_set_ctrl()
672 params->gop_size = ctrl->value; saa7164_set_ctrl()
692 struct v4l2_ext_control *ctrl = ctrls->controls + i; vidioc_s_ext_ctrls() local
694 err = saa7164_try_ctrl(ctrl, 0); vidioc_s_ext_ctrls()
699 err = saa7164_set_ctrl(port, ctrl); vidioc_s_ext_ctrls()
498 saa7164_get_ctrl(struct saa7164_port *port, struct v4l2_ext_control *ctrl) saa7164_get_ctrl() argument
631 saa7164_set_ctrl(struct saa7164_port *port, struct v4l2_ext_control *ctrl) saa7164_set_ctrl() argument
|
| /linux-4.1.27/drivers/input/misc/ |
| H A D | cma3000_d0x.c | 119 u8 ctrl, mode, range; cma3000_thread_irq() local
137 ctrl = CMA3000_READ(data, CMA3000_CTRL, "ctrl"); cma3000_thread_irq()
138 mode = (ctrl & CMA3000_MODEMASK) >> 1; cma3000_thread_irq()
139 range = (ctrl & CMA3000_GRANGEMASK) >> 7; cma3000_thread_irq()
187 u8 ctrl = 0; cma3000_poweron() local
191 ctrl = (data->mode << 1) | CMA3000_RANGE2G; cma3000_poweron()
193 ctrl = (data->mode << 1) | CMA3000_RANGE8G; cma3000_poweron()
197 ctrl = (data->mode << 1) | CMA3000_RANGE8G; cma3000_poweron()
200 ctrl |= data->bus_ops->ctrl_mod; cma3000_poweron()
208 ret = CMA3000_SET(data, CMA3000_CTRL, ctrl, "Mode setting"); cma3000_poweron()
|
| /linux-4.1.27/arch/cris/arch-v32/drivers/mach-a3/ |
| H A D | nandflash.c | 51 unsigned int ctrl) crisv32_hwcontrol()
60 if (ctrl & NAND_CTRL_CHANGE) { crisv32_hwcontrol()
62 dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1; crisv32_hwcontrol()
65 if (ctrl & NAND_ALE) { crisv32_hwcontrol()
69 } else if (ctrl & NAND_CLE) { crisv32_hwcontrol()
80 dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0; crisv32_hwcontrol()
81 dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0; crisv32_hwcontrol()
50 crisv32_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) crisv32_hwcontrol() argument
|
| /linux-4.1.27/drivers/media/usb/dvb-usb-v2/ |
| H A D | mxl111sf-tuner.c | 140 u8 ctrl; mxl1x1sf_tuner_set_if_output_freq() local
149 ctrl = state->cfg->invert_spectrum; mxl1x1sf_tuner_set_if_output_freq()
151 ctrl |= state->cfg->if_freq; mxl1x1sf_tuner_set_if_output_freq()
153 ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_SEL_REG, ctrl); mxl1x1sf_tuner_set_if_output_freq()
164 ctrl = 0x08; mxl1x1sf_tuner_set_if_output_freq()
167 ctrl = 0x08; mxl1x1sf_tuner_set_if_output_freq()
170 ctrl = 0; mxl1x1sf_tuner_set_if_output_freq()
174 ctrl |= (iffcw >> 8); mxl1x1sf_tuner_set_if_output_freq()
176 ret = mxl111sf_tuner_read_reg(state, V6_TUNER_IF_FCW_BYP_REG, &ctrl); mxl1x1sf_tuner_set_if_output_freq()
180 ctrl &= 0xf0; mxl1x1sf_tuner_set_if_output_freq()
181 ctrl |= 0x90; mxl1x1sf_tuner_set_if_output_freq()
183 ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_BYP_REG, ctrl); mxl1x1sf_tuner_set_if_output_freq()
188 ctrl = iffcw & 0x00ff; mxl1x1sf_tuner_set_if_output_freq()
190 ret = mxl111sf_tuner_write_reg(state, V6_TUNER_IF_FCW_REG, ctrl); mxl1x1sf_tuner_set_if_output_freq()
|
| /linux-4.1.27/drivers/media/radio/wl128x/ |
| H A D | fmdrv_v4l2.c | 211 static int fm_g_volatile_ctrl(struct v4l2_ctrl *ctrl) fm_g_volatile_ctrl() argument
213 struct fmdev *fmdev = container_of(ctrl->handler, fm_g_volatile_ctrl()
216 switch (ctrl->id) { fm_g_volatile_ctrl()
218 ctrl->val = fm_tx_get_tune_cap_val(fmdev); fm_g_volatile_ctrl()
221 fmwarn("%s: Unknown IOCTL: %d\n", __func__, ctrl->id); fm_g_volatile_ctrl()
228 static int fm_v4l2_s_ctrl(struct v4l2_ctrl *ctrl) fm_v4l2_s_ctrl() argument
230 struct fmdev *fmdev = container_of(ctrl->handler, fm_v4l2_s_ctrl()
233 switch (ctrl->id) { fm_v4l2_s_ctrl()
235 return fm_rx_set_volume(fmdev, (u16)ctrl->val); fm_v4l2_s_ctrl()
238 return fmc_set_mute_mode(fmdev, (u8)ctrl->val); fm_v4l2_s_ctrl()
242 return fm_tx_set_pwr_lvl(fmdev, (u8)ctrl->val); fm_v4l2_s_ctrl()
245 return fm_tx_set_preemph_filter(fmdev, (u8) ctrl->val); fm_v4l2_s_ctrl()
535 struct v4l2_ctrl *ctrl; fm_v4l2_init_video_device() local
562 /* Register to v4l2 ctrl handler framework */ fm_v4l2_init_video_device()
567 fmerr("(fmdev): Can't init ctrl handler\n"); fm_v4l2_init_video_device()
591 ctrl = v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops, fm_v4l2_init_video_device()
595 if (ctrl) fm_v4l2_init_video_device()
596 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; fm_v4l2_init_video_device()
608 /* Unregister to v4l2 ctrl handler framework*/ fm_v4l2_deinit_video_device()
|
| /linux-4.1.27/drivers/usb/renesas_usbhs/ |
| H A D | mod_gadget.c | 65 struct usb_ctrlrequest *ctrl);
67 struct usb_ctrlrequest *ctrl);
69 struct usb_ctrlrequest *ctrl);
223 struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_control_done()
236 struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_clear_endpoint()
247 usbhsg_recip_handler_std_control_done(priv, uep, ctrl); usbhsg_recip_handler_std_clear_endpoint()
266 struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_set_device()
268 switch (le16_to_cpu(ctrl->wValue)) { usbhsg_recip_handler_std_set_device()
270 usbhsg_recip_handler_std_control_done(priv, uep, ctrl); usbhsg_recip_handler_std_set_device()
272 usbhs_sys_set_test_mode(priv, le16_to_cpu(ctrl->wIndex >> 8)); usbhsg_recip_handler_std_set_device()
275 usbhsg_recip_handler_std_control_done(priv, uep, ctrl); usbhsg_recip_handler_std_set_device()
284 struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_set_endpoint()
290 usbhsg_recip_handler_std_control_done(priv, uep, ctrl); usbhsg_recip_handler_std_set_endpoint()
355 struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_get_device()
370 struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_get_interface()
382 struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_get_endpoint()
408 struct usb_ctrlrequest *ctrl) usbhsg_recip_run_handle()
414 int recip = ctrl->bRequestType & USB_RECIP_MASK; usbhsg_recip_run_handle()
415 int nth = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK; usbhsg_recip_run_handle()
418 struct usb_ctrlrequest *ctrl); usbhsg_recip_run_handle()
449 ret = func(priv, uep, ctrl); usbhsg_recip_run_handle()
482 struct usb_ctrlrequest ctrl; usbhsg_irq_ctrl_stage() local
518 usbhs_usbreq_get_val(priv, &ctrl); usbhsg_irq_ctrl_stage()
520 switch (ctrl.bRequestType & USB_TYPE_MASK) { usbhsg_irq_ctrl_stage()
522 switch (ctrl.bRequest) { usbhsg_irq_ctrl_stage()
539 ret = usbhsg_recip_run_handle(priv, recip_handler, &ctrl); usbhsg_irq_ctrl_stage()
541 ret = gpriv->driver->setup(&gpriv->gadget, &ctrl); usbhsg_irq_ctrl_stage()
221 usbhsg_recip_handler_std_control_done(struct usbhs_priv *priv, struct usbhsg_uep *uep, struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_control_done() argument
234 usbhsg_recip_handler_std_clear_endpoint(struct usbhs_priv *priv, struct usbhsg_uep *uep, struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_clear_endpoint() argument
264 usbhsg_recip_handler_std_set_device(struct usbhs_priv *priv, struct usbhsg_uep *uep, struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_set_device() argument
282 usbhsg_recip_handler_std_set_endpoint(struct usbhs_priv *priv, struct usbhsg_uep *uep, struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_set_endpoint() argument
353 usbhsg_recip_handler_std_get_device(struct usbhs_priv *priv, struct usbhsg_uep *uep, struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_get_device() argument
368 usbhsg_recip_handler_std_get_interface(struct usbhs_priv *priv, struct usbhsg_uep *uep, struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_get_interface() argument
380 usbhsg_recip_handler_std_get_endpoint(struct usbhs_priv *priv, struct usbhsg_uep *uep, struct usb_ctrlrequest *ctrl) usbhsg_recip_handler_std_get_endpoint() argument
406 usbhsg_recip_run_handle(struct usbhs_priv *priv, struct usbhsg_recip_handle *handler, struct usb_ctrlrequest *ctrl) usbhsg_recip_run_handle() argument
|
| /linux-4.1.27/drivers/mtd/onenand/ |
| H A D | omap2.c | 93 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr) wait_err() argument
95 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n", wait_err()
96 msg, state, ctrl, intr); wait_err()
99 static void wait_warn(char *msg, int state, unsigned int ctrl, wait_warn() argument
102 printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x " wait_warn()
103 "intr 0x%04x\n", msg, state, ctrl, intr); wait_warn()
111 unsigned int ctrl, ctrl_mask; omap2_onenand_wait() local
138 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); omap2_onenand_wait()
139 if (ctrl & ONENAND_CTRL_ERROR) { omap2_onenand_wait()
140 wait_err("controller error", state, ctrl, intr); omap2_onenand_wait()
165 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); omap2_onenand_wait()
167 wait_err("gpio error", state, ctrl, intr); omap2_onenand_wait()
179 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); omap2_onenand_wait()
180 if (ctrl & ONENAND_CTRL_ONGO && omap2_onenand_wait()
191 wait_err("timeout", state, ctrl, intr); omap2_onenand_wait()
196 wait_warn("timeout", state, ctrl, intr); omap2_onenand_wait()
215 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); omap2_onenand_wait()
216 if (ctrl & ONENAND_CTRL_ONGO) { omap2_onenand_wait()
234 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS); omap2_onenand_wait()
258 wait_err("timeout", state, ctrl, intr); omap2_onenand_wait()
262 if (ctrl & ONENAND_CTRL_ERROR) { omap2_onenand_wait()
263 wait_err("controller error", state, ctrl, intr); omap2_onenand_wait()
264 if (ctrl & ONENAND_CTRL_LOCK) omap2_onenand_wait()
274 if (ctrl & ctrl_mask) omap2_onenand_wait()
275 wait_warn("unexpected controller status", state, ctrl, intr); omap2_onenand_wait()
|
| /linux-4.1.27/drivers/media/pci/ivtv/ |
| H A D | ivtv-controls.c | 130 static int ivtv_g_volatile_ctrl(struct v4l2_ctrl *ctrl) ivtv_g_volatile_ctrl() argument
132 struct ivtv *itv = container_of(ctrl->handler, struct ivtv, cxhdl.hdl); ivtv_g_volatile_ctrl()
134 switch (ctrl->id) { ivtv_g_volatile_ctrl()
144 static int ivtv_s_ctrl(struct v4l2_ctrl *ctrl) ivtv_s_ctrl() argument
146 struct ivtv *itv = container_of(ctrl->handler, struct ivtv, cxhdl.hdl); ivtv_s_ctrl()
148 switch (ctrl->id) { ivtv_s_ctrl()
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| /linux-4.1.27/drivers/scsi/isci/ |
| H A D | probe_roms.c | 144 for (i = 0; i < ARRAY_SIZE(orom->ctrl); i++) isci_request_firmware()
145 for (j = 0; j < ARRAY_SIZE(orom->ctrl[i].phys); j++) { isci_request_firmware()
146 orom->ctrl[i].phys[j].afe_tx_amp_control0 = 0xe7c03; isci_request_firmware()
147 orom->ctrl[i].phys[j].afe_tx_amp_control1 = 0xe7c03; isci_request_firmware()
148 orom->ctrl[i].phys[j].afe_tx_amp_control2 = 0xe7c03; isci_request_firmware()
149 orom->ctrl[i].phys[j].afe_tx_amp_control3 = 0xe7c03; isci_request_firmware()
|
| /linux-4.1.27/drivers/parisc/ |
| H A D | gsc.c | 177 void *ctrl; member in struct:gsc_fixup_struct
188 gsc_fixup_irqs(padev, gf->ctrl, gf->choose_irq); gsc_fixup_irqs_callback()
189 gf->choose_irq(padev, gf->ctrl); gsc_fixup_irqs_callback()
194 void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl, gsc_fixup_irqs() argument
199 .ctrl = ctrl, gsc_fixup_irqs()
|
| /linux-4.1.27/drivers/w1/masters/ |
| H A D | mxc_w1.c | 61 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); mxc_w1_ds2_reset_bus() local
64 if (!(ctrl & MXC_W1_CONTROL_RPP)) mxc_w1_ds2_reset_bus()
65 return !(ctrl & MXC_W1_CONTROL_PST); mxc_w1_ds2_reset_bus()
89 u8 ctrl = readb(dev->regs + MXC_W1_CONTROL); mxc_w1_ds2_touch_bit() local
92 if (!(ctrl & MXC_W1_CONTROL_WR(bit))) mxc_w1_ds2_touch_bit()
93 return !!(ctrl & MXC_W1_CONTROL_RDST); mxc_w1_ds2_touch_bit()
|
| /linux-4.1.27/drivers/media/dvb-frontends/ |
| H A D | bcm3510.c | 378 c.ctl_dat[0].ctrl.size = BITS_8; bcm3510_tuner_cmd()
382 c.ctl_dat[1].ctrl.size = BITS_8; bcm3510_tuner_cmd()
386 c.ctl_dat[2].ctrl.size = BITS_3; bcm3510_tuner_cmd()
390 c.ctl_dat[3].ctrl.size = BITS_3; bcm3510_tuner_cmd()
391 c.ctl_dat[3].ctrl.clk_off = 1; bcm3510_tuner_cmd()
392 c.ctl_dat[3].ctrl.cs0 = 1; bcm3510_tuner_cmd()
396 c.ctl_dat[4].ctrl.size = BITS_8; bcm3510_tuner_cmd()
400 c.ctl_dat[5].ctrl.size = BITS_8; bcm3510_tuner_cmd()
404 c.ctl_dat[6].ctrl.size = BITS_3; bcm3510_tuner_cmd()
408 c.ctl_dat[7].ctrl.size = BITS_3; bcm3510_tuner_cmd()
409 c.ctl_dat[7].ctrl.clk_off = 1; bcm3510_tuner_cmd()
410 c.ctl_dat[7].ctrl.cs0 = 1; bcm3510_tuner_cmd()
414 c.ctl_dat[8].ctrl.size = BITS_8; bcm3510_tuner_cmd()
418 c.ctl_dat[9].ctrl.size = BITS_8; bcm3510_tuner_cmd()
422 c.ctl_dat[10].ctrl.size = BITS_3; bcm3510_tuner_cmd()
426 c.ctl_dat[11].ctrl.size = BITS_3; bcm3510_tuner_cmd()
427 c.ctl_dat[11].ctrl.clk_off = 1; bcm3510_tuner_cmd()
428 c.ctl_dat[11].ctrl.cs1 = 1; bcm3510_tuner_cmd()
432 c.ctl_dat[12].ctrl.size = BITS_8; bcm3510_tuner_cmd()
436 c.ctl_dat[13].ctrl.size = BITS_8; bcm3510_tuner_cmd()
440 c.ctl_dat[14].ctrl.size = BITS_3; bcm3510_tuner_cmd()
444 c.ctl_dat[15].ctrl.size = BITS_3; bcm3510_tuner_cmd()
445 c.ctl_dat[15].ctrl.clk_off = 1; bcm3510_tuner_cmd()
446 c.ctl_dat[15].ctrl.cs1 = 1; bcm3510_tuner_cmd()
|
| /linux-4.1.27/arch/cris/arch-v32/drivers/mach-fs/ |
| H A D | nandflash.c | 50 unsigned int ctrl) crisv32_hwcontrol()
59 if (ctrl & NAND_CTRL_CHANGE) { crisv32_hwcontrol()
68 dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT; crisv32_hwcontrol()
71 if (!(ctrl & NAND_NCE)) crisv32_hwcontrol()
73 if (ctrl & NAND_CLE) crisv32_hwcontrol()
75 if (ctrl & NAND_ALE) crisv32_hwcontrol()
49 crisv32_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) crisv32_hwcontrol() argument
|
| /linux-4.1.27/arch/arm/mach-ixp4xx/ |
| H A D | ixdp425-setup.c | 77 ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) ixdp425_flash_nand_cmd_ctrl() argument
82 if (ctrl & NAND_CTRL_CHANGE) { ixdp425_flash_nand_cmd_ctrl()
83 if (ctrl & NAND_NCE) { ixdp425_flash_nand_cmd_ctrl()
89 offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0; ixdp425_flash_nand_cmd_ctrl()
90 offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0; ixdp425_flash_nand_cmd_ctrl()
105 .ctrl = {
|
| /linux-4.1.27/drivers/reset/ |
| H A D | reset-berlin.c | 112 { .compatible = "marvell,berlin2-chip-ctrl" },
113 { .compatible = "marvell,berlin2cd-chip-ctrl" },
114 { .compatible = "marvell,berlin2q-chip-ctrl" },
|
| /linux-4.1.27/drivers/tty/hvc/ |
| H A D | hvsi_lib.c | 36 struct hvsi_control ctrl; hvsi_send_close() local
40 ctrl.hdr.type = VS_CONTROL_PACKET_HEADER; hvsi_send_close()
41 ctrl.hdr.len = sizeof(struct hvsi_control); hvsi_send_close()
42 ctrl.verb = cpu_to_be16(VSV_CLOSE_PROTOCOL); hvsi_send_close()
43 return hvsi_send_packet(pv, &ctrl.hdr); hvsi_send_close()
288 struct hvsi_control ctrl; hvsilib_write_mctrl() local
303 ctrl.hdr.type = VS_CONTROL_PACKET_HEADER, hvsilib_write_mctrl()
304 ctrl.hdr.len = sizeof(struct hvsi_control); hvsilib_write_mctrl()
305 ctrl.verb = cpu_to_be16(VSV_SET_MODEM_CTL); hvsilib_write_mctrl()
306 ctrl.mask = cpu_to_be32(HVSI_TSDTR); hvsilib_write_mctrl()
307 ctrl.word = cpu_to_be32(dtr ? HVSI_TSDTR : 0); hvsilib_write_mctrl()
308 return hvsi_send_packet(pv, &ctrl.hdr); hvsilib_write_mctrl()
|
| /linux-4.1.27/sound/soc/omap/ |
| H A D | omap-dmic.c | 75 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG); omap_dmic_start() local
81 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled); omap_dmic_start()
86 u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG); omap_dmic_stop() local
88 ctrl & ~OMAP_DMIC_UP_ENABLE_MASK); omap_dmic_stop()
237 u32 ctrl; omap_dmic_dai_prepare() local
242 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG); omap_dmic_dai_prepare()
245 ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK); omap_dmic_dai_prepare()
246 ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 | omap_dmic_dai_prepare()
250 ctrl &= ~OMAP_DMIC_CLK_DIV_MASK; omap_dmic_dai_prepare()
251 ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div); omap_dmic_dai_prepare()
253 omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl); omap_dmic_dai_prepare()
256 ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 | omap_dmic_dai_prepare()
|
| H A D | omap-mcpdm.c | 128 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); omap_mcpdm_start() local
131 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); omap_mcpdm_start()
132 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); omap_mcpdm_start()
134 ctrl |= link_mask; omap_mcpdm_start()
135 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); omap_mcpdm_start()
137 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); omap_mcpdm_start()
138 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); omap_mcpdm_start()
147 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); omap_mcpdm_stop() local
150 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); omap_mcpdm_stop()
151 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); omap_mcpdm_stop()
153 ctrl &= ~(link_mask); omap_mcpdm_stop()
154 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); omap_mcpdm_stop()
156 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST); omap_mcpdm_stop()
157 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl); omap_mcpdm_stop()
262 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL); omap_mcpdm_dai_startup() local
264 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN); omap_mcpdm_dai_startup()
|
| /linux-4.1.27/sound/pci/ |
| H A D | ens1370.c | 398 unsigned int ctrl; /* control register */ member in struct:ensoniq
857 ensoniq->ctrl |= what;
859 ensoniq->ctrl &= ~what;
860 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL));
898 ensoniq->ctrl &= ~ES_DAC1_EN; snd_ensoniq_playback1_prepare()
902 ensoniq->ctrl |= ES_1373_BYPASS_P1; snd_ensoniq_playback1_prepare()
904 ensoniq->ctrl &= ~ES_1373_BYPASS_P1; snd_ensoniq_playback1_prepare()
906 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_playback1_prepare()
916 ensoniq->ctrl &= ~ES_1370_WTSRSELM; snd_ensoniq_playback1_prepare()
918 case 5512: ensoniq->ctrl |= ES_1370_WTSRSEL(0); break; snd_ensoniq_playback1_prepare()
919 case 11025: ensoniq->ctrl |= ES_1370_WTSRSEL(1); break; snd_ensoniq_playback1_prepare()
920 case 22050: ensoniq->ctrl |= ES_1370_WTSRSEL(2); break; snd_ensoniq_playback1_prepare()
921 case 44100: ensoniq->ctrl |= ES_1370_WTSRSEL(3); break; snd_ensoniq_playback1_prepare()
925 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_playback1_prepare()
946 ensoniq->ctrl &= ~ES_DAC2_EN; snd_ensoniq_playback2_prepare()
947 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_playback2_prepare()
960 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; snd_ensoniq_playback2_prepare()
961 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); snd_ensoniq_playback2_prepare()
965 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_playback2_prepare()
986 ensoniq->ctrl &= ~ES_ADC_EN; snd_ensoniq_capture_prepare()
987 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_capture_prepare()
998 ensoniq->ctrl &= ~ES_1370_PCLKDIVM; snd_ensoniq_capture_prepare()
999 ensoniq->ctrl |= ES_1370_PCLKDIVO(ES_1370_SRTODIV(runtime->rate)); snd_ensoniq_capture_prepare()
1003 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_capture_prepare()
1443 ucontrol->value.integer.value[0] = ensoniq->ctrl & ES_1373_SPDIF_THRU ? 1 : 0; snd_es1371_spdif_get()
1458 change = (ensoniq->ctrl & ES_1373_SPDIF_THRU) != nval1; snd_es1371_spdif_put()
1459 ensoniq->ctrl &= ~ES_1373_SPDIF_THRU; snd_es1371_spdif_put()
1460 ensoniq->ctrl |= nval1; snd_es1371_spdif_put()
1463 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_es1371_spdif_put()
1551 if ((ensoniq->ctrl & ES_1371_GPIO_OUTM) >= 4) snd_es1373_line_get()
1563 unsigned int ctrl; snd_es1373_line_put() local
1566 ctrl = ensoniq->ctrl; snd_es1373_line_put()
1568 ensoniq->ctrl |= ES_1371_GPIO_OUT(4); /* switch line-in -> rear out */ snd_es1373_line_put()
1570 ensoniq->ctrl &= ~ES_1371_GPIO_OUT(4); snd_es1373_line_put()
1571 changed = (ctrl != ensoniq->ctrl); snd_es1373_line_put()
1573 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_es1373_line_put()
1709 ucontrol->value.integer.value[0] = ensoniq->ctrl & mask ? 1 : 0; snd_ensoniq_control_get()
1724 change = (ensoniq->ctrl & mask) != nval; snd_ensoniq_control_put()
1725 ensoniq->ctrl &= ~mask; snd_ensoniq_control_put()
1726 ensoniq->ctrl |= nval; snd_ensoniq_control_put()
1727 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_control_put()
1852 ensoniq->ctrl |= ES_JYSTK_EN; snd_ensoniq_create_gameport()
1854 ensoniq->ctrl &= ~ES_1371_JOY_ASELM; snd_ensoniq_create_gameport()
1855 ensoniq->ctrl |= ES_1371_JOY_ASEL((io_port - 0x200) / 8); snd_ensoniq_create_gameport()
1857 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_create_gameport()
1871 ensoniq->ctrl &= ~ES_JYSTK_EN; snd_ensoniq_free_gameport()
1872 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_free_gameport()
1892 ensoniq->ctrl & ES_JYSTK_EN ? "on" : "off"); snd_ensoniq_proc_read()
1895 ensoniq->ctrl & ES_1370_XCTL1 ? "on" : "off"); snd_ensoniq_proc_read()
1897 ensoniq->ctrl & ES_1370_XCTL0 ? "on" : "off"); snd_ensoniq_proc_read()
1900 (ES_1371_JOY_ASELI(ensoniq->ctrl) * 8) + 0x200); snd_ensoniq_proc_read()
1978 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_chip_init()
1984 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_chip_init()
1994 outl(ensoniq->ctrl | ES_1371_SYNC_RES, ES_REG(ensoniq, CONTROL)); snd_ensoniq_chip_init()
1997 outl(ensoniq->ctrl, ES_REG(ensoniq, CONTROL)); snd_ensoniq_chip_init()
2129 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_SERR_DISABLE | snd_ensoniq_create()
2132 ensoniq->ctrl = ES_1370_CDC_EN | ES_1370_PCLKDIVO(ES_1370_SRTODIV(8000)); snd_ensoniq_create()
2136 ensoniq->ctrl = 0; snd_ensoniq_create()
2140 ensoniq->ctrl |= ES_1371_GPIO_OUT(1); /* turn amplifier on */ snd_ensoniq_create()
2210 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); snd_ensoniq_midi_input_open()
2223 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); snd_ensoniq_midi_input_close()
2243 outl(ensoniq->ctrl |= ES_UART_EN, ES_REG(ensoniq, CONTROL)); snd_ensoniq_midi_output_open()
2256 outl(ensoniq->ctrl &= ~ES_UART_EN, ES_REG(ensoniq, CONTROL)); snd_ensoniq_midi_output_close()
|
| /linux-4.1.27/drivers/media/usb/pvrusb2/ |
| H A D | Makefile | 10 pvrusb2-ctrl.o pvrusb2-std.o pvrusb2-devattr.o \
|
| /linux-4.1.27/arch/m68k/mvme16x/ |
| H A D | rtc.c | 49 rtc->ctrl = RTC_READ; rtc_ioctl()
60 rtc->ctrl = 0; rtc_ioctl()
101 rtc->ctrl = RTC_WRITE; rtc_ioctl()
110 rtc->ctrl = 0; rtc_ioctl()
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| /linux-4.1.27/drivers/video/fbdev/ |
| H A D | jz4740_fb.c | 359 uint32_t ctrl; jzfb_set_par() local
380 ctrl = JZ_LCD_CTRL_OFUP | JZ_LCD_CTRL_BURST_16; jzfb_set_par()
384 ctrl |= JZ_LCD_CTRL_BPP_1; jzfb_set_par()
387 ctrl |= JZ_LCD_CTRL_BPP_2; jzfb_set_par()
390 ctrl |= JZ_LCD_CTRL_BPP_4; jzfb_set_par()
393 ctrl |= JZ_LCD_CTRL_BPP_8; jzfb_set_par()
396 ctrl |= JZ_LCD_CTRL_RGB555; /* Falltrough */ jzfb_set_par()
398 ctrl |= JZ_LCD_CTRL_BPP_15_16; jzfb_set_par()
403 ctrl |= JZ_LCD_CTRL_BPP_18_24; jzfb_set_par()
442 ctrl |= JZ_LCD_CTRL_ENABLE; jzfb_set_par()
471 writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); jzfb_set_par()
486 uint32_t ctrl; jzfb_enable() local
497 ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); jzfb_enable()
498 ctrl |= JZ_LCD_CTRL_ENABLE; jzfb_enable()
499 ctrl &= ~JZ_LCD_CTRL_DISABLE; jzfb_enable()
500 writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); jzfb_enable()
505 uint32_t ctrl; jzfb_disable() local
507 ctrl = readl(jzfb->base + JZ_REG_LCD_CTRL); jzfb_disable()
508 ctrl |= JZ_LCD_CTRL_DISABLE; jzfb_disable()
509 writel(ctrl, jzfb->base + JZ_REG_LCD_CTRL); jzfb_disable()
511 ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); jzfb_disable()
512 } while (!(ctrl & JZ_LCD_STATE_DISABLED)); jzfb_disable()
|
| /linux-4.1.27/drivers/isdn/hardware/mISDN/ |
| H A D | avmfritz.c | 125 u32 ctrl; member in union:hdlc_hw::__anon5265
127 } ctrl; member in struct:hdlc_hw
278 outl(hdlc->ctrl.ctrl, fc->addr + CHIP_WINDOW + HDLC_STATUS); __write_ctrl_pci()
283 outl(hdlc->ctrl.ctrl, fc->addr + (channel == 2 ? AVM_HDLC_STATUS_2 : __write_ctrl_pciv2()
293 pr_debug("%s: hdlc %c wr%x ctrl %x\n", fc->name, '@' + bch->nr, write_ctrl()
294 which, hdlc->ctrl.ctrl); write_ctrl()
358 hdlc->ctrl.ctrl = 0; modehdlc()
367 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; modehdlc()
368 hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS; modehdlc()
376 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; modehdlc()
377 hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS; modehdlc()
379 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS; modehdlc()
381 hdlc->ctrl.sr.cmd = 0; modehdlc()
386 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS | HDLC_CMD_RRS; modehdlc()
387 hdlc->ctrl.sr.mode = mode | HDLC_MODE_ITF_FLG; modehdlc()
389 hdlc->ctrl.sr.cmd = HDLC_CMD_XRS; modehdlc()
391 hdlc->ctrl.sr.cmd = 0; modehdlc()
473 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XME; hdlc_fill_fifo()
478 hdlc->ctrl.sr.cmd |= HDLC_CMD_XME; hdlc_fill_fifo()
488 hdlc->ctrl.sr.xml = ((count == fs) ? 0 : count); hdlc_fill_fifo()
556 hdlc->ctrl.sr.xml = 0; HDLC_irq()
557 hdlc->ctrl.sr.cmd |= HDLC_CMD_RRS; HDLC_irq()
559 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_RRS; HDLC_irq()
598 hdlc->ctrl.sr.xml = 0; HDLC_irq()
599 hdlc->ctrl.sr.cmd |= HDLC_CMD_XRS; HDLC_irq()
601 hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XRS; HDLC_irq()
894 ret = fc->isac.ctrl(&fc->isac, HW_TESTLOOP, cq->channel); channel_ctrl()
897 ret = fc->isac.ctrl(&fc->isac, HW_TIMER3_VALUE, cq->p1); channel_ctrl()
1057 card->isac.dch.dev.D.ctrl = avm_dctrl; setup_instance()
1068 card->bch[i].ch.ctrl = avm_bctrl; setup_instance()
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