183 static void start_int_poll_timer(struct controller *ctrl, int sec);
184 static int hpc_check_cmd_status(struct controller *ctrl);
186 static inline u8 shpc_readb(struct controller *ctrl, int reg)  in shpc_readb()  argument
188 	return readb(ctrl->creg + reg);  in shpc_readb()
191 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)  in shpc_writeb()  argument
193 	writeb(val, ctrl->creg + reg);  in shpc_writeb()
196 static inline u16 shpc_readw(struct controller *ctrl, int reg)  in shpc_readw()  argument
198 	return readw(ctrl->creg + reg);  in shpc_readw()
201 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)  in shpc_writew()  argument
203 	writew(val, ctrl->creg + reg);  in shpc_writew()
206 static inline u32 shpc_readl(struct controller *ctrl, int reg)  in shpc_readl()  argument
208 	return readl(ctrl->creg + reg);  in shpc_readl()
211 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)  in shpc_writel()  argument
213 	writel(val, ctrl->creg + reg);  in shpc_writel()
216 static inline int shpc_indirect_read(struct controller *ctrl, int index,  in shpc_indirect_read()  argument
220 	u32 cap_offset = ctrl->cap_offset;  in shpc_indirect_read()
221 	struct pci_dev *pdev = ctrl->pci_dev;  in shpc_indirect_read()
234 	struct controller *ctrl = (struct controller *)data;  in int_poll_timeout()  local
237 	shpc_isr(0, ctrl);  in int_poll_timeout()
239 	init_timer(&ctrl->poll_timer);  in int_poll_timeout()
243 	start_int_poll_timer(ctrl, shpchp_poll_time);  in int_poll_timeout()
249 static void start_int_poll_timer(struct controller *ctrl, int sec)  in start_int_poll_timer()  argument
255 	ctrl->poll_timer.function = &int_poll_timeout;  in start_int_poll_timer()
256 	ctrl->poll_timer.data = (unsigned long)ctrl;  in start_int_poll_timer()
257 	ctrl->poll_timer.expires = jiffies + sec * HZ;  in start_int_poll_timer()
258 	add_timer(&ctrl->poll_timer);  in start_int_poll_timer()
261 static inline int is_ctrl_busy(struct controller *ctrl)  in is_ctrl_busy()  argument
263 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);  in is_ctrl_busy()
271 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)  in shpc_poll_ctrl_busy()  argument
275 	if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
281 		if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
288 static inline int shpc_wait_cmd(struct controller *ctrl)  in shpc_wait_cmd()  argument
295 		rc = shpc_poll_ctrl_busy(ctrl);  in shpc_wait_cmd()
297 		rc = wait_event_interruptible_timeout(ctrl->queue,  in shpc_wait_cmd()
298 						!is_ctrl_busy(ctrl), timeout);  in shpc_wait_cmd()
299 	if (!rc && is_ctrl_busy(ctrl)) {  in shpc_wait_cmd()
301 		ctrl_err(ctrl, "Command not completed in 1000 msec\n");  in shpc_wait_cmd()
304 		ctrl_info(ctrl, "Command was interrupted by a signal\n");  in shpc_wait_cmd()
312 	struct controller *ctrl = slot->ctrl;  in shpc_write_cmd()  local
317 	mutex_lock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
319 	if (!shpc_poll_ctrl_busy(ctrl)) {  in shpc_write_cmd()
321 		ctrl_err(ctrl, "Controller is still busy after 1 sec\n");  in shpc_write_cmd()
328 	ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);  in shpc_write_cmd()
333 	shpc_writew(ctrl, CMD, temp_word);  in shpc_write_cmd()
338 	retval = shpc_wait_cmd(slot->ctrl);  in shpc_write_cmd()
342 	cmd_status = hpc_check_cmd_status(slot->ctrl);  in shpc_write_cmd()
344 		ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",  in shpc_write_cmd()
349 	mutex_unlock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
353 static int hpc_check_cmd_status(struct controller *ctrl)  in hpc_check_cmd_status()  argument
356 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;  in hpc_check_cmd_status()
364 		ctrl_err(ctrl, "Switch opened!\n");  in hpc_check_cmd_status()
368 		ctrl_err(ctrl, "Invalid HPC command!\n");  in hpc_check_cmd_status()
372 		ctrl_err(ctrl, "Invalid bus speed/mode!\n");  in hpc_check_cmd_status()
384 	struct controller *ctrl = slot->ctrl;  in hpc_get_attention_status()  local
385 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_attention_status()
408 	struct controller *ctrl = slot->ctrl;  in hpc_get_power_status()  local
409 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_power_status()
433 	struct controller *ctrl = slot->ctrl;  in hpc_get_latch_status()  local
434 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_latch_status()
443 	struct controller *ctrl = slot->ctrl;  in hpc_get_adapter_status()  local
444 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_adapter_status()
454 	struct controller *ctrl = slot->ctrl;  in hpc_get_prog_int()  local
456 	*prog_int = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_get_prog_int()
464 	struct controller *ctrl = slot->ctrl;  in hpc_get_adapter_speed()  local
465 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_adapter_speed()
484 	ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",  in hpc_get_adapter_speed()
510 	ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);  in hpc_get_adapter_speed()
517 	struct controller *ctrl = slot->ctrl;  in hpc_get_mode1_ECC_cap()  local
518 	u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);  in hpc_get_mode1_ECC_cap()
519 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_get_mode1_ECC_cap()
527 	ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);  in hpc_get_mode1_ECC_cap()
533 	struct controller *ctrl = slot->ctrl;  in hpc_query_power_fault()  local
534 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_query_power_fault()
577 static void hpc_release_ctlr(struct controller *ctrl)  in hpc_release_ctlr()  argument
585 	for (i = 0; i < ctrl->num_slots; i++) {  in hpc_release_ctlr()
586 		slot_reg = shpc_readl(ctrl, SLOT_REG(i));  in hpc_release_ctlr()
592 		shpc_writel(ctrl, SLOT_REG(i), slot_reg);  in hpc_release_ctlr()
595 	cleanup_slots(ctrl);  in hpc_release_ctlr()
600 	serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in hpc_release_ctlr()
604 	shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in hpc_release_ctlr()
607 		del_timer(&ctrl->poll_timer);  in hpc_release_ctlr()
609 		free_irq(ctrl->pci_dev->irq, ctrl);  in hpc_release_ctlr()
610 		pci_disable_msi(ctrl->pci_dev);  in hpc_release_ctlr()
613 	iounmap(ctrl->creg);  in hpc_release_ctlr()
614 	release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in hpc_release_ctlr()
623 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_power_on_slot()
636 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_slot_enable()
649 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_slot_disable()
654 static int shpc_get_cur_bus_speed(struct controller *ctrl)  in shpc_get_cur_bus_speed()  argument
657 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_cur_bus_speed()
659 	u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);  in shpc_get_cur_bus_speed()
660 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_cur_bus_speed()
726 	struct controller *ctrl = slot->ctrl;  in hpc_set_bus_speed_mode()  local
729 	pi = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_set_bus_speed_mode()
782 		ctrl_err(ctrl, "%s: Write command failed!\n", __func__);  in hpc_set_bus_speed_mode()
784 		shpc_get_cur_bus_speed(ctrl);  in hpc_set_bus_speed_mode()
791 	struct controller *ctrl = (struct controller *)dev_id;  in shpc_isr()  local
796 	intr_loc = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
800 	ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);  in shpc_isr()
807 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
810 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
812 		intr_loc2 = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
813 		ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);  in shpc_isr()
822 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
824 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
826 		wake_up_interruptible(&ctrl->queue);  in shpc_isr()
832 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_isr()
837 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_isr()
838 		ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",  in shpc_isr()
842 			shpchp_handle_switch_change(hp_slot, ctrl);  in shpc_isr()
845 			shpchp_handle_attention_button(hp_slot, ctrl);  in shpc_isr()
848 			shpchp_handle_presence_change(hp_slot, ctrl);  in shpc_isr()
851 			shpchp_handle_power_fault(hp_slot, ctrl);  in shpc_isr()
855 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_isr()
860 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
862 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
868 static int shpc_get_max_bus_speed(struct controller *ctrl)  in shpc_get_max_bus_speed()  argument
871 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_max_bus_speed()
873 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_max_bus_speed()
874 	u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);  in shpc_get_max_bus_speed()
875 	u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);  in shpc_get_max_bus_speed()
908 	ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);  in shpc_get_max_bus_speed()
936 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)  in shpc_init()  argument
944 	ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */  in shpc_init()
945 	ctrl_dbg(ctrl, "Hotplug Controller:\n");  in shpc_init()
950 		ctrl->mmio_base = pci_resource_start(pdev, 0);  in shpc_init()
951 		ctrl->mmio_size = pci_resource_len(pdev, 0);  in shpc_init()
953 		ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);  in shpc_init()
954 		if (!ctrl->cap_offset) {  in shpc_init()
955 			ctrl_err(ctrl, "Cannot find PCI capability\n");  in shpc_init()
958 		ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);  in shpc_init()
960 		rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);  in shpc_init()
962 			ctrl_err(ctrl, "Cannot read base_offset\n");  in shpc_init()
966 		rc = shpc_indirect_read(ctrl, 3, &tempdword);  in shpc_init()
968 			ctrl_err(ctrl, "Cannot read slot config\n");  in shpc_init()
972 		ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);  in shpc_init()
975 			rc = shpc_indirect_read(ctrl, i, &tempdword);  in shpc_init()
977 				ctrl_err(ctrl, "Cannot read creg (index = %d)\n",  in shpc_init()
981 			ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);  in shpc_init()
984 		ctrl->mmio_base =  in shpc_init()
986 		ctrl->mmio_size = 0x24 + 0x4 * num_slots;  in shpc_init()
989 	ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",  in shpc_init()
995 		ctrl_err(ctrl, "pci_enable_device failed\n");  in shpc_init()
999 	if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {  in shpc_init()
1000 		ctrl_err(ctrl, "Cannot reserve MMIO region\n");  in shpc_init()
1005 	ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
1006 	if (!ctrl->creg) {  in shpc_init()
1007 		ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",  in shpc_init()
1008 			 ctrl->mmio_size, ctrl->mmio_base);  in shpc_init()
1009 		release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
1013 	ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);  in shpc_init()
1015 	mutex_init(&ctrl->crit_sect);  in shpc_init()
1016 	mutex_init(&ctrl->cmd_lock);  in shpc_init()
1019 	init_waitqueue_head(&ctrl->queue);  in shpc_init()
1021 	ctrl->hpc_ops = &shpchp_hpc_ops;  in shpc_init()
1024 	slot_config = shpc_readl(ctrl, SLOT_CONFIG);  in shpc_init()
1025 	ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;  in shpc_init()
1026 	ctrl->num_slots = slot_config & SLOT_NUM;  in shpc_init()
1027 	ctrl->first_slot = (slot_config & PSN) >> 16;  in shpc_init()
1028 	ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;  in shpc_init()
1031 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1032 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1036 	shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
1037 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1038 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1043 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
1044 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
1045 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
1052 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
1057 		init_timer(&ctrl->poll_timer);  in shpc_init()
1058 		start_int_poll_timer(ctrl, 10);  in shpc_init()
1063 			ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");  in shpc_init()
1064 			ctrl_info(ctrl, "Use INTx for the hotplug controller\n");  in shpc_init()
1067 		rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,  in shpc_init()
1068 				 MY_NAME, (void *)ctrl);  in shpc_init()
1069 		ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",  in shpc_init()
1070 			 ctrl->pci_dev->irq, rc);  in shpc_init()
1072 			ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",  in shpc_init()
1073 				 ctrl->pci_dev->irq);  in shpc_init()
1077 	ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);  in shpc_init()
1079 	shpc_get_max_bus_speed(ctrl);  in shpc_init()
1080 	shpc_get_cur_bus_speed(ctrl);  in shpc_init()
1085 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
1086 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
1087 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
1092 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
1096 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1099 		shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
1100 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1101 		ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1108 	iounmap(ctrl->creg);  in shpc_init()