29 	u32 ctrl;  member
75 	tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04;  in anx9805_aux()
76 	nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04);  in anx9805_aux()
77 	nv_wri2cr(mast, chan->ctrl, 0x07, tmp);  in anx9805_aux()
78 	nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);  in anx9805_aux()
100 	if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) {  in anx9805_aux()
114 	nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01);  in anx9805_aux()
144 		chan->ctrl = 0x39;  in anx9805_aux_chan_ctor()
148 		chan->ctrl = 0x3b;  in anx9805_aux_chan_ctor()
180 	tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10;  in anx9805_xfer()
181 	nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10);  in anx9805_xfer()
182 	nv_wri2cr(mast, port->ctrl, 0x07, tmp);  in anx9805_xfer()
259 		port->ctrl = 0x39;  in anx9805_ddc_port_ctor()
263 		port->ctrl = 0x3b;  in anx9805_ddc_port_ctor()