1/*
2 * Freescale LBC and UPM routines.
3 *
4 * Copyright © 2007-2008  MontaVista Software, Inc.
5 * Copyright © 2010 Freescale Semiconductor
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 * Author: Jack Lan <Jack.Lan@freescale.com>
9 * Author: Roy Zang <tie-fei.zang@freescale.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#include <linux/init.h>
18#include <linux/export.h>
19#include <linux/kernel.h>
20#include <linux/compiler.h>
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/slab.h>
26#include <linux/sched.h>
27#include <linux/platform_device.h>
28#include <linux/interrupt.h>
29#include <linux/mod_devicetable.h>
30#include <asm/prom.h>
31#include <asm/fsl_lbc.h>
32
33static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
34struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
35EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
36
37/**
38 * fsl_lbc_addr - convert the base address
39 * @addr_base:	base address of the memory bank
40 *
41 * This function converts a base address of lbc into the right format for the
42 * BR register. If the SOC has eLBC then it returns 32bit physical address
43 * else it convers a 34bit local bus physical address to correct format of
44 * 32bit address for BR register (Example: MPC8641).
45 */
46u32 fsl_lbc_addr(phys_addr_t addr_base)
47{
48	struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
49	u32 addr = addr_base & 0xffff8000;
50
51	if (of_device_is_compatible(np, "fsl,elbc"))
52		return addr;
53
54	return addr | ((addr_base & 0x300000000ull) >> 19);
55}
56EXPORT_SYMBOL(fsl_lbc_addr);
57
58/**
59 * fsl_lbc_find - find Localbus bank
60 * @addr_base:	base address of the memory bank
61 *
62 * This function walks LBC banks comparing "Base address" field of the BR
63 * registers with the supplied addr_base argument. When bases match this
64 * function returns bank number (starting with 0), otherwise it returns
65 * appropriate errno value.
66 */
67int fsl_lbc_find(phys_addr_t addr_base)
68{
69	int i;
70	struct fsl_lbc_regs __iomem *lbc;
71
72	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
73		return -ENODEV;
74
75	lbc = fsl_lbc_ctrl_dev->regs;
76	for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
77		u32 br = in_be32(&lbc->bank[i].br);
78		u32 or = in_be32(&lbc->bank[i].or);
79
80		if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
81			return i;
82	}
83
84	return -ENOENT;
85}
86EXPORT_SYMBOL(fsl_lbc_find);
87
88/**
89 * fsl_upm_find - find pre-programmed UPM via base address
90 * @addr_base:	base address of the memory bank controlled by the UPM
91 * @upm:	pointer to the allocated fsl_upm structure
92 *
93 * This function fills fsl_upm structure so you can use it with the rest of
94 * UPM API. On success this function returns 0, otherwise it returns
95 * appropriate errno value.
96 */
97int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
98{
99	int bank;
100	u32 br;
101	struct fsl_lbc_regs __iomem *lbc;
102
103	bank = fsl_lbc_find(addr_base);
104	if (bank < 0)
105		return bank;
106
107	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
108		return -ENODEV;
109
110	lbc = fsl_lbc_ctrl_dev->regs;
111	br = in_be32(&lbc->bank[bank].br);
112
113	switch (br & BR_MSEL) {
114	case BR_MS_UPMA:
115		upm->mxmr = &lbc->mamr;
116		break;
117	case BR_MS_UPMB:
118		upm->mxmr = &lbc->mbmr;
119		break;
120	case BR_MS_UPMC:
121		upm->mxmr = &lbc->mcmr;
122		break;
123	default:
124		return -EINVAL;
125	}
126
127	switch (br & BR_PS) {
128	case BR_PS_8:
129		upm->width = 8;
130		break;
131	case BR_PS_16:
132		upm->width = 16;
133		break;
134	case BR_PS_32:
135		upm->width = 32;
136		break;
137	default:
138		return -EINVAL;
139	}
140
141	return 0;
142}
143EXPORT_SYMBOL(fsl_upm_find);
144
145/**
146 * fsl_upm_run_pattern - actually run an UPM pattern
147 * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
148 * @io_base:	remapped pointer to where memory access should happen
149 * @mar:	MAR register content during pattern execution
150 *
151 * This function triggers dummy write to the memory specified by the io_base,
152 * thus UPM pattern actually executed. Note that mar usage depends on the
153 * pre-programmed AMX bits in the UPM RAM.
154 */
155int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
156{
157	int ret = 0;
158	unsigned long flags;
159
160	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
161		return -ENODEV;
162
163	spin_lock_irqsave(&fsl_lbc_lock, flags);
164
165	out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
166
167	switch (upm->width) {
168	case 8:
169		out_8(io_base, 0x0);
170		break;
171	case 16:
172		out_be16(io_base, 0x0);
173		break;
174	case 32:
175		out_be32(io_base, 0x0);
176		break;
177	default:
178		ret = -EINVAL;
179		break;
180	}
181
182	spin_unlock_irqrestore(&fsl_lbc_lock, flags);
183
184	return ret;
185}
186EXPORT_SYMBOL(fsl_upm_run_pattern);
187
188static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
189			     struct device_node *node)
190{
191	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
192
193	/* clear event registers */
194	setbits32(&lbc->ltesr, LTESR_CLEAR);
195	out_be32(&lbc->lteatr, 0);
196	out_be32(&lbc->ltear, 0);
197	out_be32(&lbc->lteccr, LTECCR_CLEAR);
198	out_be32(&lbc->ltedr, LTEDR_ENABLE);
199
200	/* Set the monitor timeout value to the maximum for erratum A001 */
201	if (of_device_is_compatible(node, "fsl,elbc"))
202		clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
203
204	return 0;
205}
206
207/*
208 * NOTE: This interrupt is used to report localbus events of various kinds,
209 * such as transaction errors on the chipselects.
210 */
211
212static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
213{
214	struct fsl_lbc_ctrl *ctrl = data;
215	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
216	u32 status;
217	unsigned long flags;
218
219	spin_lock_irqsave(&fsl_lbc_lock, flags);
220	status = in_be32(&lbc->ltesr);
221	if (!status) {
222		spin_unlock_irqrestore(&fsl_lbc_lock, flags);
223		return IRQ_NONE;
224	}
225
226	out_be32(&lbc->ltesr, LTESR_CLEAR);
227	out_be32(&lbc->lteatr, 0);
228	out_be32(&lbc->ltear, 0);
229	ctrl->irq_status = status;
230
231	if (status & LTESR_BM)
232		dev_err(ctrl->dev, "Local bus monitor time-out: "
233			"LTESR 0x%08X\n", status);
234	if (status & LTESR_WP)
235		dev_err(ctrl->dev, "Write protect error: "
236			"LTESR 0x%08X\n", status);
237	if (status & LTESR_ATMW)
238		dev_err(ctrl->dev, "Atomic write error: "
239			"LTESR 0x%08X\n", status);
240	if (status & LTESR_ATMR)
241		dev_err(ctrl->dev, "Atomic read error: "
242			"LTESR 0x%08X\n", status);
243	if (status & LTESR_CS)
244		dev_err(ctrl->dev, "Chip select error: "
245			"LTESR 0x%08X\n", status);
246	if (status & LTESR_UPM)
247		;
248	if (status & LTESR_FCT) {
249		dev_err(ctrl->dev, "FCM command time-out: "
250			"LTESR 0x%08X\n", status);
251		smp_wmb();
252		wake_up(&ctrl->irq_wait);
253	}
254	if (status & LTESR_PAR) {
255		dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
256			"LTESR 0x%08X\n", status);
257		smp_wmb();
258		wake_up(&ctrl->irq_wait);
259	}
260	if (status & LTESR_CC) {
261		smp_wmb();
262		wake_up(&ctrl->irq_wait);
263	}
264	if (status & ~LTESR_MASK)
265		dev_err(ctrl->dev, "Unknown error: "
266			"LTESR 0x%08X\n", status);
267	spin_unlock_irqrestore(&fsl_lbc_lock, flags);
268	return IRQ_HANDLED;
269}
270
271/*
272 * fsl_lbc_ctrl_probe
273 *
274 * called by device layer when it finds a device matching
275 * one our driver can handled. This code allocates all of
276 * the resources needed for the controller only.  The
277 * resources for the NAND banks themselves are allocated
278 * in the chip probe function.
279*/
280
281static int fsl_lbc_ctrl_probe(struct platform_device *dev)
282{
283	int ret;
284
285	if (!dev->dev.of_node) {
286		dev_err(&dev->dev, "Device OF-Node is NULL");
287		return -EFAULT;
288	}
289
290	fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
291	if (!fsl_lbc_ctrl_dev)
292		return -ENOMEM;
293
294	dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
295
296	spin_lock_init(&fsl_lbc_ctrl_dev->lock);
297	init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
298
299	fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
300	if (!fsl_lbc_ctrl_dev->regs) {
301		dev_err(&dev->dev, "failed to get memory region\n");
302		ret = -ENODEV;
303		goto err;
304	}
305
306	fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
307	if (!fsl_lbc_ctrl_dev->irq[0]) {
308		dev_err(&dev->dev, "failed to get irq resource\n");
309		ret = -ENODEV;
310		goto err;
311	}
312
313	fsl_lbc_ctrl_dev->dev = &dev->dev;
314
315	ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
316	if (ret < 0)
317		goto err;
318
319	ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
320				"fsl-lbc", fsl_lbc_ctrl_dev);
321	if (ret != 0) {
322		dev_err(&dev->dev, "failed to install irq (%d)\n",
323			fsl_lbc_ctrl_dev->irq[0]);
324		ret = fsl_lbc_ctrl_dev->irq[0];
325		goto err;
326	}
327
328	fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
329	if (fsl_lbc_ctrl_dev->irq[1]) {
330		ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
331				IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
332		if (ret) {
333			dev_err(&dev->dev, "failed to install irq (%d)\n",
334					fsl_lbc_ctrl_dev->irq[1]);
335			ret = fsl_lbc_ctrl_dev->irq[1];
336			goto err1;
337		}
338	}
339
340	/* Enable interrupts for any detected events */
341	out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
342
343	return 0;
344
345err1:
346	free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
347err:
348	iounmap(fsl_lbc_ctrl_dev->regs);
349	kfree(fsl_lbc_ctrl_dev);
350	fsl_lbc_ctrl_dev = NULL;
351	return ret;
352}
353
354#ifdef CONFIG_SUSPEND
355
356/* save lbc registers */
357static int fsl_lbc_suspend(struct platform_device *pdev, pm_message_t state)
358{
359	struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
360	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
361
362	ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
363	if (!ctrl->saved_regs)
364		return -ENOMEM;
365
366	_memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
367	return 0;
368}
369
370/* restore lbc registers */
371static int fsl_lbc_resume(struct platform_device *pdev)
372{
373	struct fsl_lbc_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
374	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
375
376	if (ctrl->saved_regs) {
377		_memcpy_toio(lbc, ctrl->saved_regs,
378				sizeof(struct fsl_lbc_regs));
379		kfree(ctrl->saved_regs);
380		ctrl->saved_regs = NULL;
381	}
382	return 0;
383}
384#endif /* CONFIG_SUSPEND */
385
386static const struct of_device_id fsl_lbc_match[] = {
387	{ .compatible = "fsl,elbc", },
388	{ .compatible = "fsl,pq3-localbus", },
389	{ .compatible = "fsl,pq2-localbus", },
390	{ .compatible = "fsl,pq2pro-localbus", },
391	{},
392};
393
394static struct platform_driver fsl_lbc_ctrl_driver = {
395	.driver = {
396		.name = "fsl-lbc",
397		.of_match_table = fsl_lbc_match,
398	},
399	.probe = fsl_lbc_ctrl_probe,
400#ifdef CONFIG_SUSPEND
401	.suspend     = fsl_lbc_suspend,
402	.resume      = fsl_lbc_resume,
403#endif
404};
405
406static int __init fsl_lbc_init(void)
407{
408	return platform_driver_register(&fsl_lbc_ctrl_driver);
409}
410module_init(fsl_lbc_init);
411