278 	OutReg(scc->ctrl, reg, (scc->wreg[reg] = val));  in wr()
283 	OutReg(scc->ctrl, reg, (scc->wreg[reg] |= val));  in or()
288 	OutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val));  in cl()
358 		OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */  in start_hunt()
384 			Outb(scc->ctrl, RES_Tx_P);  in scc_txint()
393 			Outb(scc->ctrl, RES_Tx_P);  in scc_txint()
399 		OutReg(scc->ctrl, R0, RES_Tx_CRC);  in scc_txint()
406 			Outb(scc->ctrl,RES_EOM_L);  in scc_txint()
414 		Outb(scc->ctrl, RES_Tx_P);	/* reset pending int */  in scc_txint()
436 	status = InReg(scc->ctrl,R0);  in scc_exint()
454 				OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */  in scc_exint()
497 		Outb(scc->ctrl, RES_EXT_INT);	/* reset ext/status interrupts */  in scc_exint()
510 	Outb(scc->ctrl,RES_EXT_INT);  in scc_exint()
570 	status = InReg(scc->ctrl,R1);		/* read receiver status */  in scc_spint()
603 	Outb(scc->ctrl,ERR_RES);  in scc_spint()
634 	struct scc_ctrl *ctrl;  in scc_isr()  local
652 			OutReg(scc->ctrl,R0,RES_H_IUS);              /* Reset Highest IUS */  in scc_isr()
665 	ctrl = SCC_ctrl;  in scc_isr()
666 	while (ctrl->chan_A)  in scc_isr()
668 		if (ctrl->irq != chip_irq)  in scc_isr()
670 			ctrl++;  in scc_isr()
675 		for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++)  in scc_isr()
677 			vector=InReg(ctrl->chan_B,R2);	/* Read the vector */  in scc_isr()
701 			OutReg(scc->ctrl,R0,RES_H_IUS);  in scc_isr()
702 			ctrl = SCC_ctrl;   in scc_isr()
704 			ctrl++;  in scc_isr()
743 	OutReg(scc->ctrl, R14, SSBR|scc->wreg[R14]);	/* DPLL source = BRG */  in init_brg()
744 	OutReg(scc->ctrl, R14, SNRZI|scc->wreg[R14]);	/* DPLL NRZI mode */  in init_brg()
850 			OutReg(scc->ctrl, R14, DISDPLL);  in init_channel()
863 	if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD))  in init_channel()
873 	Outb(scc->ctrl,RES_EXT_INT);	/* reset ext/status interrupts */  in init_channel()
874 	Outb(scc->ctrl,RES_EXT_INT);	/* must be done twice */  in init_channel()
878 	scc->status = InReg(scc->ctrl,R0);	/* read initial status */  in init_channel()
903 		Outb(scc->ctrl + 4, scc->option | (tx? 0x80 : 0));  in scc_key_trx()
1251 	OutReg(scc->ctrl, R0, RES_Tx_P);  in t_maxkeyup()
1410 	Outb(scc->ctrl,RES_EXT_INT);	/* reset ext/status interrupts */  in scc_stop_calibrate()
1411 	Outb(scc->ctrl,RES_EXT_INT);  in scc_stop_calibrate()
1443 	Outb(scc->ctrl,RES_EXT_INT);	/* reset ext/status interrupts */  in scc_start_calibrate()
1444 	Outb(scc->ctrl,RES_EXT_INT);  in scc_start_calibrate()
1482 		if (!scc->ctrl) continue;  in z8530_init()
1497 		Outb(scc->ctrl, 0);  in z8530_init()
1498 		OutReg(scc->ctrl,R9,FHWRES);		/* force hardware reset */  in z8530_init()
1604 	Outb(scc->ctrl,0);		/* Make sure pointer is written */  in scc_net_close()
1779 				SCC_Info[2*Nchips  ].ctrl = hwcfg.ctrl_a;  in scc_net_ioctl()
1782 				SCC_Info[2*Nchips+1].ctrl = hwcfg.ctrl_b;  in scc_net_ioctl()
1806 					SCC_Info[2*Nchips+chan].ctrl);  in scc_net_ioctl()
1818 					request_region(SCC_Info[2*Nchips+chan].ctrl, 1, "scc ctrl");  in scc_net_ioctl()
2036 				scc->data, scc->ctrl, scc->irq, scc->clock, scc->brand,  in scc_net_seq_show()
2065 		seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1));  in scc_net_seq_show()
2067 				seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));  in scc_net_seq_show()
2070 				seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg));  in scc_net_seq_show()
2131 	io_port ctrl;  in scc_cleanup_driver()  local
2146 		if ( (ctrl = SCC_ctrl[k].chan_A) )  in scc_cleanup_driver()
2148 			Outb(ctrl, 0);  in scc_cleanup_driver()
2149 			OutReg(ctrl,R9,FHWRES);	/* force hardware reset */  in scc_cleanup_driver()
2163 		if (scc->ctrl)  in scc_cleanup_driver()
2165 			release_region(scc->ctrl, 1);  in scc_cleanup_driver()