1#define RCS_ID "$Id: scc.c,v 1.75 1998/11/04 15:15:01 jreuter Exp jreuter $" 2 3#define VERSION "3.0" 4 5/* 6 * Please use z8530drv-utils-3.0 with this version. 7 * ------------------ 8 * 9 * You can find a subset of the documentation in 10 * Documentation/networking/z8530drv.txt. 11 */ 12 13/* 14 ******************************************************************** 15 * SCC.C - Linux driver for Z8530 based HDLC cards for AX.25 * 16 ******************************************************************** 17 18 19 ******************************************************************** 20 21 Copyright (c) 1993, 2000 Joerg Reuter DL1BKE 22 23 portions (c) 1993 Guido ten Dolle PE1NNZ 24 25 ******************************************************************** 26 27 The driver and the programs in the archive are UNDER CONSTRUCTION. 28 The code is likely to fail, and so your kernel could --- even 29 a whole network. 30 31 This driver is intended for Amateur Radio use. If you are running it 32 for commercial purposes, please drop me a note. I am nosy... 33 34 ...BUT: 35 36 ! You m u s t recognize the appropriate legislations of your country ! 37 ! before you connect a radio to the SCC board and start to transmit or ! 38 ! receive. The GPL allows you to use the d r i v e r, NOT the RADIO! ! 39 40 For non-Amateur-Radio use please note that you might need a special 41 allowance/licence from the designer of the SCC Board and/or the 42 MODEM. 43 44 This program is free software; you can redistribute it and/or modify 45 it under the terms of the (modified) GNU General Public License 46 delivered with the Linux kernel source. 47 48 This program is distributed in the hope that it will be useful, 49 but WITHOUT ANY WARRANTY; without even the implied warranty of 50 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 51 GNU General Public License for more details. 52 53 You should find a copy of the GNU General Public License in 54 /usr/src/linux/COPYING; 55 56 ******************************************************************** 57 58 59 Incomplete history of z8530drv: 60 ------------------------------- 61 62 1994-09-13 started to write the driver, rescued most of my own 63 code (and Hans Alblas' memory buffer pool concept) from 64 an earlier project "sccdrv" which was initiated by 65 Guido ten Dolle. Not much of the old driver survived, 66 though. The first version I put my hands on was sccdrv1.3 67 from August 1993. The memory buffer pool concept 68 appeared in an unauthorized sccdrv version (1.5) from 69 August 1994. 70 71 1995-01-31 changed copyright notice to GPL without limitations. 72 73 . 74 . <SNIP> 75 . 76 77 1996-10-05 New semester, new driver... 78 79 * KISS TNC emulator removed (TTY driver) 80 * Source moved to drivers/net/ 81 * Includes Z8530 defines from drivers/net/z8530.h 82 * Uses sk_buffer memory management 83 * Reduced overhead of /proc/net/z8530drv output 84 * Streamlined quite a lot things 85 * Invents brand new bugs... ;-) 86 87 The move to version number 3.0 reflects theses changes. 88 You can use 'kissbridge' if you need a KISS TNC emulator. 89 90 1996-12-13 Fixed for Linux networking changes. (G4KLX) 91 1997-01-08 Fixed the remaining problems. 92 1997-04-02 Hopefully fixed the problems with the new *_timer() 93 routines, added calibration code. 94 1997-10-12 Made SCC_DELAY a CONFIG option, added CONFIG_SCC_TRXECHO 95 1998-01-29 Small fix to avoid lock-up on initialization 96 1998-09-29 Fixed the "grouping" bugs, tx_inhibit works again, 97 using dev->tx_queue_len now instead of MAXQUEUE now. 98 1998-10-21 Postponed the spinlock changes, would need a lot of 99 testing I currently don't have the time to. Softdcd doesn't 100 work. 101 1998-11-04 Softdcd does not work correctly in DPLL mode, in fact it 102 never did. The DPLL locks on noise, the SYNC unit sees 103 flags that aren't... Restarting the DPLL does not help 104 either, it resynchronizes too slow and the first received 105 frame gets lost. 106 2000-02-13 Fixed for new network driver interface changes, still 107 does TX timeouts itself since it uses its own queue 108 scheme. 109 110 Thanks to all who contributed to this driver with ideas and bug 111 reports! 112 113 NB -- if you find errors, change something, please let me know 114 first before you distribute it... And please don't touch 115 the version number. Just replace my callsign in 116 "v3.0.dl1bke" with your own. Just to avoid confusion... 117 118 If you want to add your modification to the linux distribution 119 please (!) contact me first. 120 121 New versions of the driver will be announced on the linux-hams 122 mailing list on vger.kernel.org. To subscribe send an e-mail 123 to majordomo@vger.kernel.org with the following line in 124 the body of the mail: 125 126 subscribe linux-hams 127 128 The content of the "Subject" field will be ignored. 129 130 vy 73, 131 Joerg Reuter ampr-net: dl1bke@db0pra.ampr.org 132 AX-25 : DL1BKE @ DB0ABH.#BAY.DEU.EU 133 Internet: jreuter@yaina.de 134 www : http://yaina.de/jreuter 135*/ 136 137/* ----------------------------------------------------------------------- */ 138 139#undef SCC_LDELAY /* slow it even a bit more down */ 140#undef SCC_DONT_CHECK /* don't look if the SCCs you specified are available */ 141 142#define SCC_MAXCHIPS 4 /* number of max. supported chips */ 143#define SCC_BUFSIZE 384 /* must not exceed 4096 */ 144#undef SCC_DEBUG 145 146#define SCC_DEFAULT_CLOCK 4915200 147 /* default pclock if nothing is specified */ 148 149/* ----------------------------------------------------------------------- */ 150 151#include <linux/module.h> 152#include <linux/errno.h> 153#include <linux/signal.h> 154#include <linux/timer.h> 155#include <linux/interrupt.h> 156#include <linux/ioport.h> 157#include <linux/string.h> 158#include <linux/in.h> 159#include <linux/fcntl.h> 160#include <linux/ptrace.h> 161#include <linux/delay.h> 162#include <linux/skbuff.h> 163#include <linux/netdevice.h> 164#include <linux/rtnetlink.h> 165#include <linux/if_ether.h> 166#include <linux/if_arp.h> 167#include <linux/socket.h> 168#include <linux/init.h> 169#include <linux/scc.h> 170#include <linux/ctype.h> 171#include <linux/kernel.h> 172#include <linux/proc_fs.h> 173#include <linux/seq_file.h> 174#include <linux/bitops.h> 175 176#include <net/net_namespace.h> 177#include <net/ax25.h> 178 179#include <asm/irq.h> 180#include <asm/io.h> 181#include <asm/uaccess.h> 182 183#include "z8530.h" 184 185static const char banner[] __initconst = KERN_INFO \ 186 "AX.25: Z8530 SCC driver version "VERSION".dl1bke\n"; 187 188static void t_dwait(unsigned long); 189static void t_txdelay(unsigned long); 190static void t_tail(unsigned long); 191static void t_busy(unsigned long); 192static void t_maxkeyup(unsigned long); 193static void t_idle(unsigned long); 194static void scc_tx_done(struct scc_channel *); 195static void scc_start_tx_timer(struct scc_channel *, void (*)(unsigned long), unsigned long); 196static void scc_start_maxkeyup(struct scc_channel *); 197static void scc_start_defer(struct scc_channel *); 198 199static void z8530_init(void); 200 201static void init_channel(struct scc_channel *scc); 202static void scc_key_trx (struct scc_channel *scc, char tx); 203static void scc_init_timer(struct scc_channel *scc); 204 205static int scc_net_alloc(const char *name, struct scc_channel *scc); 206static void scc_net_setup(struct net_device *dev); 207static int scc_net_open(struct net_device *dev); 208static int scc_net_close(struct net_device *dev); 209static void scc_net_rx(struct scc_channel *scc, struct sk_buff *skb); 210static netdev_tx_t scc_net_tx(struct sk_buff *skb, 211 struct net_device *dev); 212static int scc_net_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); 213static int scc_net_set_mac_address(struct net_device *dev, void *addr); 214static struct net_device_stats * scc_net_get_stats(struct net_device *dev); 215 216static unsigned char SCC_DriverName[] = "scc"; 217 218static struct irqflags { unsigned char used : 1; } Ivec[NR_IRQS]; 219 220static struct scc_channel SCC_Info[2 * SCC_MAXCHIPS]; /* information per channel */ 221 222static struct scc_ctrl { 223 io_port chan_A; 224 io_port chan_B; 225 int irq; 226} SCC_ctrl[SCC_MAXCHIPS+1]; 227 228static unsigned char Driver_Initialized; 229static int Nchips; 230static io_port Vector_Latch; 231 232 233/* ******************************************************************** */ 234/* * Port Access Functions * */ 235/* ******************************************************************** */ 236 237/* These provide interrupt save 2-step access to the Z8530 registers */ 238 239static DEFINE_SPINLOCK(iolock); /* Guards paired accesses */ 240 241static inline unsigned char InReg(io_port port, unsigned char reg) 242{ 243 unsigned long flags; 244 unsigned char r; 245 246 spin_lock_irqsave(&iolock, flags); 247#ifdef SCC_LDELAY 248 Outb(port, reg); 249 udelay(SCC_LDELAY); 250 r=Inb(port); 251 udelay(SCC_LDELAY); 252#else 253 Outb(port, reg); 254 r=Inb(port); 255#endif 256 spin_unlock_irqrestore(&iolock, flags); 257 return r; 258} 259 260static inline void OutReg(io_port port, unsigned char reg, unsigned char val) 261{ 262 unsigned long flags; 263 264 spin_lock_irqsave(&iolock, flags); 265#ifdef SCC_LDELAY 266 Outb(port, reg); udelay(SCC_LDELAY); 267 Outb(port, val); udelay(SCC_LDELAY); 268#else 269 Outb(port, reg); 270 Outb(port, val); 271#endif 272 spin_unlock_irqrestore(&iolock, flags); 273} 274 275static inline void wr(struct scc_channel *scc, unsigned char reg, 276 unsigned char val) 277{ 278 OutReg(scc->ctrl, reg, (scc->wreg[reg] = val)); 279} 280 281static inline void or(struct scc_channel *scc, unsigned char reg, unsigned char val) 282{ 283 OutReg(scc->ctrl, reg, (scc->wreg[reg] |= val)); 284} 285 286static inline void cl(struct scc_channel *scc, unsigned char reg, unsigned char val) 287{ 288 OutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val)); 289} 290 291/* ******************************************************************** */ 292/* * Some useful macros * */ 293/* ******************************************************************** */ 294 295static inline void scc_discard_buffers(struct scc_channel *scc) 296{ 297 unsigned long flags; 298 299 spin_lock_irqsave(&scc->lock, flags); 300 if (scc->tx_buff != NULL) 301 { 302 dev_kfree_skb(scc->tx_buff); 303 scc->tx_buff = NULL; 304 } 305 306 while (!skb_queue_empty(&scc->tx_queue)) 307 dev_kfree_skb(skb_dequeue(&scc->tx_queue)); 308 309 spin_unlock_irqrestore(&scc->lock, flags); 310} 311 312 313 314/* ******************************************************************** */ 315/* * Interrupt Service Routines * */ 316/* ******************************************************************** */ 317 318 319/* ----> subroutines for the interrupt handlers <---- */ 320 321static inline void scc_notify(struct scc_channel *scc, int event) 322{ 323 struct sk_buff *skb; 324 char *bp; 325 326 if (scc->kiss.fulldup != KISS_DUPLEX_OPTIMA) 327 return; 328 329 skb = dev_alloc_skb(2); 330 if (skb != NULL) 331 { 332 bp = skb_put(skb, 2); 333 *bp++ = PARAM_HWEVENT; 334 *bp++ = event; 335 scc_net_rx(scc, skb); 336 } else 337 scc->stat.nospace++; 338} 339 340static inline void flush_rx_FIFO(struct scc_channel *scc) 341{ 342 int k; 343 344 for (k=0; k<3; k++) 345 Inb(scc->data); 346 347 if(scc->rx_buff != NULL) /* did we receive something? */ 348 { 349 scc->stat.rxerrs++; /* then count it as an error */ 350 dev_kfree_skb_irq(scc->rx_buff); 351 scc->rx_buff = NULL; 352 } 353} 354 355static void start_hunt(struct scc_channel *scc) 356{ 357 if ((scc->modem.clocksrc != CLK_EXTERNAL)) 358 OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */ 359 or(scc,R3,ENT_HM|RxENABLE); /* enable the receiver, hunt mode */ 360} 361 362/* ----> four different interrupt handlers for Tx, Rx, changing of */ 363/* DCD/CTS and Rx/Tx errors */ 364 365/* Transmitter interrupt handler */ 366static inline void scc_txint(struct scc_channel *scc) 367{ 368 struct sk_buff *skb; 369 370 scc->stat.txints++; 371 skb = scc->tx_buff; 372 373 /* send first octet */ 374 375 if (skb == NULL) 376 { 377 skb = skb_dequeue(&scc->tx_queue); 378 scc->tx_buff = skb; 379 netif_wake_queue(scc->dev); 380 381 if (skb == NULL) 382 { 383 scc_tx_done(scc); 384 Outb(scc->ctrl, RES_Tx_P); 385 return; 386 } 387 388 if (skb->len == 0) /* Paranoia... */ 389 { 390 dev_kfree_skb_irq(skb); 391 scc->tx_buff = NULL; 392 scc_tx_done(scc); 393 Outb(scc->ctrl, RES_Tx_P); 394 return; 395 } 396 397 scc->stat.tx_state = TXS_ACTIVE; 398 399 OutReg(scc->ctrl, R0, RES_Tx_CRC); 400 /* reset CRC generator */ 401 or(scc,R10,ABUNDER); /* re-install underrun protection */ 402 Outb(scc->data,*skb->data); /* send byte */ 403 skb_pull(skb, 1); 404 405 if (!scc->enhanced) /* reset EOM latch */ 406 Outb(scc->ctrl,RES_EOM_L); 407 return; 408 } 409 410 /* End Of Frame... */ 411 412 if (skb->len == 0) 413 { 414 Outb(scc->ctrl, RES_Tx_P); /* reset pending int */ 415 cl(scc, R10, ABUNDER); /* send CRC */ 416 dev_kfree_skb_irq(skb); 417 scc->tx_buff = NULL; 418 scc->stat.tx_state = TXS_NEWFRAME; /* next frame... */ 419 return; 420 } 421 422 /* send octet */ 423 424 Outb(scc->data,*skb->data); 425 skb_pull(skb, 1); 426} 427 428 429/* External/Status interrupt handler */ 430static inline void scc_exint(struct scc_channel *scc) 431{ 432 unsigned char status,changes,chg_and_stat; 433 434 scc->stat.exints++; 435 436 status = InReg(scc->ctrl,R0); 437 changes = status ^ scc->status; 438 chg_and_stat = changes & status; 439 440 /* ABORT: generated whenever DCD drops while receiving */ 441 442 if (chg_and_stat & BRK_ABRT) /* Received an ABORT */ 443 flush_rx_FIFO(scc); 444 445 /* HUNT: software DCD; on = waiting for SYNC, off = receiving frame */ 446 447 if ((changes & SYNC_HUNT) && scc->kiss.softdcd) 448 { 449 if (status & SYNC_HUNT) 450 { 451 scc->dcd = 0; 452 flush_rx_FIFO(scc); 453 if ((scc->modem.clocksrc != CLK_EXTERNAL)) 454 OutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */ 455 } else { 456 scc->dcd = 1; 457 } 458 459 scc_notify(scc, scc->dcd? HWEV_DCD_OFF:HWEV_DCD_ON); 460 } 461 462 /* DCD: on = start to receive packet, off = ABORT condition */ 463 /* (a successfully received packet generates a special condition int) */ 464 465 if((changes & DCD) && !scc->kiss.softdcd) /* DCD input changed state */ 466 { 467 if(status & DCD) /* DCD is now ON */ 468 { 469 start_hunt(scc); 470 scc->dcd = 1; 471 } else { /* DCD is now OFF */ 472 cl(scc,R3,ENT_HM|RxENABLE); /* disable the receiver */ 473 flush_rx_FIFO(scc); 474 scc->dcd = 0; 475 } 476 477 scc_notify(scc, scc->dcd? HWEV_DCD_ON:HWEV_DCD_OFF); 478 } 479 480#ifdef notdef 481 /* CTS: use external TxDelay (what's that good for?!) 482 * Anyway: If we _could_ use it (BayCom USCC uses CTS for 483 * own purposes) we _should_ use the "autoenable" feature 484 * of the Z8530 and not this interrupt... 485 */ 486 487 if (chg_and_stat & CTS) /* CTS is now ON */ 488 { 489 if (scc->kiss.txdelay == 0) /* zero TXDELAY = wait for CTS */ 490 scc_start_tx_timer(scc, t_txdelay, 0); 491 } 492#endif 493 494 if (scc->stat.tx_state == TXS_ACTIVE && (status & TxEOM)) 495 { 496 scc->stat.tx_under++; /* oops, an underrun! count 'em */ 497 Outb(scc->ctrl, RES_EXT_INT); /* reset ext/status interrupts */ 498 499 if (scc->tx_buff != NULL) 500 { 501 dev_kfree_skb_irq(scc->tx_buff); 502 scc->tx_buff = NULL; 503 } 504 505 or(scc,R10,ABUNDER); 506 scc_start_tx_timer(scc, t_txdelay, 0); /* restart transmission */ 507 } 508 509 scc->status = status; 510 Outb(scc->ctrl,RES_EXT_INT); 511} 512 513 514/* Receiver interrupt handler */ 515static inline void scc_rxint(struct scc_channel *scc) 516{ 517 struct sk_buff *skb; 518 519 scc->stat.rxints++; 520 521 if((scc->wreg[5] & RTS) && scc->kiss.fulldup == KISS_DUPLEX_HALF) 522 { 523 Inb(scc->data); /* discard char */ 524 or(scc,R3,ENT_HM); /* enter hunt mode for next flag */ 525 return; 526 } 527 528 skb = scc->rx_buff; 529 530 if (skb == NULL) 531 { 532 skb = dev_alloc_skb(scc->stat.bufsize); 533 if (skb == NULL) 534 { 535 scc->dev_stat.rx_dropped++; 536 scc->stat.nospace++; 537 Inb(scc->data); 538 or(scc, R3, ENT_HM); 539 return; 540 } 541 542 scc->rx_buff = skb; 543 *(skb_put(skb, 1)) = 0; /* KISS data */ 544 } 545 546 if (skb->len >= scc->stat.bufsize) 547 { 548#ifdef notdef 549 printk(KERN_DEBUG "z8530drv: oops, scc_rxint() received huge frame...\n"); 550#endif 551 dev_kfree_skb_irq(skb); 552 scc->rx_buff = NULL; 553 Inb(scc->data); 554 or(scc, R3, ENT_HM); 555 return; 556 } 557 558 *(skb_put(skb, 1)) = Inb(scc->data); 559} 560 561 562/* Receive Special Condition interrupt handler */ 563static inline void scc_spint(struct scc_channel *scc) 564{ 565 unsigned char status; 566 struct sk_buff *skb; 567 568 scc->stat.spints++; 569 570 status = InReg(scc->ctrl,R1); /* read receiver status */ 571 572 Inb(scc->data); /* throw away Rx byte */ 573 skb = scc->rx_buff; 574 575 if(status & Rx_OVR) /* receiver overrun */ 576 { 577 scc->stat.rx_over++; /* count them */ 578 or(scc,R3,ENT_HM); /* enter hunt mode for next flag */ 579 580 if (skb != NULL) 581 dev_kfree_skb_irq(skb); 582 scc->rx_buff = skb = NULL; 583 } 584 585 if(status & END_FR && skb != NULL) /* end of frame */ 586 { 587 /* CRC okay, frame ends on 8 bit boundary and received something ? */ 588 589 if (!(status & CRC_ERR) && (status & 0xe) == RES8 && skb->len > 0) 590 { 591 /* ignore last received byte (first of the CRC bytes) */ 592 skb_trim(skb, skb->len-1); 593 scc_net_rx(scc, skb); 594 scc->rx_buff = NULL; 595 scc->stat.rxframes++; 596 } else { /* a bad frame */ 597 dev_kfree_skb_irq(skb); 598 scc->rx_buff = NULL; 599 scc->stat.rxerrs++; 600 } 601 } 602 603 Outb(scc->ctrl,ERR_RES); 604} 605 606 607/* ----> interrupt service routine for the Z8530 <---- */ 608 609static void scc_isr_dispatch(struct scc_channel *scc, int vector) 610{ 611 spin_lock(&scc->lock); 612 switch (vector & VECTOR_MASK) 613 { 614 case TXINT: scc_txint(scc); break; 615 case EXINT: scc_exint(scc); break; 616 case RXINT: scc_rxint(scc); break; 617 case SPINT: scc_spint(scc); break; 618 } 619 spin_unlock(&scc->lock); 620} 621 622/* If the card has a latch for the interrupt vector (like the PA0HZP card) 623 use it to get the number of the chip that generated the int. 624 If not: poll all defined chips. 625 */ 626 627#define SCC_IRQTIMEOUT 30000 628 629static irqreturn_t scc_isr(int irq, void *dev_id) 630{ 631 int chip_irq = (long) dev_id; 632 unsigned char vector; 633 struct scc_channel *scc; 634 struct scc_ctrl *ctrl; 635 int k; 636 637 if (Vector_Latch) 638 { 639 for(k=0; k < SCC_IRQTIMEOUT; k++) 640 { 641 Outb(Vector_Latch, 0); /* Generate INTACK */ 642 643 /* Read the vector */ 644 if((vector=Inb(Vector_Latch)) >= 16 * Nchips) break; 645 if (vector & 0x01) break; 646 647 scc=&SCC_Info[vector >> 3 ^ 0x01]; 648 if (!scc->dev) break; 649 650 scc_isr_dispatch(scc, vector); 651 652 OutReg(scc->ctrl,R0,RES_H_IUS); /* Reset Highest IUS */ 653 } 654 655 if (k == SCC_IRQTIMEOUT) 656 printk(KERN_WARNING "z8530drv: endless loop in scc_isr()?\n"); 657 658 return IRQ_HANDLED; 659 } 660 661 /* Find the SCC generating the interrupt by polling all attached SCCs 662 * reading RR3A (the interrupt pending register) 663 */ 664 665 ctrl = SCC_ctrl; 666 while (ctrl->chan_A) 667 { 668 if (ctrl->irq != chip_irq) 669 { 670 ctrl++; 671 continue; 672 } 673 674 scc = NULL; 675 for (k = 0; InReg(ctrl->chan_A,R3) && k < SCC_IRQTIMEOUT; k++) 676 { 677 vector=InReg(ctrl->chan_B,R2); /* Read the vector */ 678 if (vector & 0x01) break; 679 680 scc = &SCC_Info[vector >> 3 ^ 0x01]; 681 if (!scc->dev) break; 682 683 scc_isr_dispatch(scc, vector); 684 } 685 686 if (k == SCC_IRQTIMEOUT) 687 { 688 printk(KERN_WARNING "z8530drv: endless loop in scc_isr()?!\n"); 689 break; 690 } 691 692 /* This looks weird and it is. At least the BayCom USCC doesn't 693 * use the Interrupt Daisy Chain, thus we'll have to start 694 * all over again to be sure not to miss an interrupt from 695 * (any of) the other chip(s)... 696 * Honestly, the situation *is* braindamaged... 697 */ 698 699 if (scc != NULL) 700 { 701 OutReg(scc->ctrl,R0,RES_H_IUS); 702 ctrl = SCC_ctrl; 703 } else 704 ctrl++; 705 } 706 return IRQ_HANDLED; 707} 708 709 710 711/* ******************************************************************** */ 712/* * Init Channel */ 713/* ******************************************************************** */ 714 715 716/* ----> set SCC channel speed <---- */ 717 718static inline void set_brg(struct scc_channel *scc, unsigned int tc) 719{ 720 cl(scc,R14,BRENABL); /* disable baudrate generator */ 721 wr(scc,R12,tc & 255); /* brg rate LOW */ 722 wr(scc,R13,tc >> 8); /* brg rate HIGH */ 723 or(scc,R14,BRENABL); /* enable baudrate generator */ 724} 725 726static inline void set_speed(struct scc_channel *scc) 727{ 728 unsigned long flags; 729 spin_lock_irqsave(&scc->lock, flags); 730 731 if (scc->modem.speed > 0) /* paranoia... */ 732 set_brg(scc, (unsigned) (scc->clock / (scc->modem.speed * 64)) - 2); 733 734 spin_unlock_irqrestore(&scc->lock, flags); 735} 736 737 738/* ----> initialize a SCC channel <---- */ 739 740static inline void init_brg(struct scc_channel *scc) 741{ 742 wr(scc, R14, BRSRC); /* BRG source = PCLK */ 743 OutReg(scc->ctrl, R14, SSBR|scc->wreg[R14]); /* DPLL source = BRG */ 744 OutReg(scc->ctrl, R14, SNRZI|scc->wreg[R14]); /* DPLL NRZI mode */ 745} 746 747/* 748 * Initialization according to the Z8530 manual (SGS-Thomson's version): 749 * 750 * 1. Modes and constants 751 * 752 * WR9 11000000 chip reset 753 * WR4 XXXXXXXX Tx/Rx control, async or sync mode 754 * WR1 0XX00X00 select W/REQ (optional) 755 * WR2 XXXXXXXX program interrupt vector 756 * WR3 XXXXXXX0 select Rx control 757 * WR5 XXXX0XXX select Tx control 758 * WR6 XXXXXXXX sync character 759 * WR7 XXXXXXXX sync character 760 * WR9 000X0XXX select interrupt control 761 * WR10 XXXXXXXX miscellaneous control (optional) 762 * WR11 XXXXXXXX clock control 763 * WR12 XXXXXXXX time constant lower byte (optional) 764 * WR13 XXXXXXXX time constant upper byte (optional) 765 * WR14 XXXXXXX0 miscellaneous control 766 * WR14 XXXSSSSS commands (optional) 767 * 768 * 2. Enables 769 * 770 * WR14 000SSSS1 baud rate enable 771 * WR3 SSSSSSS1 Rx enable 772 * WR5 SSSS1SSS Tx enable 773 * WR0 10000000 reset Tx CRG (optional) 774 * WR1 XSS00S00 DMA enable (optional) 775 * 776 * 3. Interrupt status 777 * 778 * WR15 XXXXXXXX enable external/status 779 * WR0 00010000 reset external status 780 * WR0 00010000 reset external status twice 781 * WR1 SSSXXSXX enable Rx, Tx and Ext/status 782 * WR9 000SXSSS enable master interrupt enable 783 * 784 * 1 = set to one, 0 = reset to zero 785 * X = user defined, S = same as previous init 786 * 787 * 788 * Note that the implementation differs in some points from above scheme. 789 * 790 */ 791 792static void init_channel(struct scc_channel *scc) 793{ 794 del_timer(&scc->tx_t); 795 del_timer(&scc->tx_wdog); 796 797 disable_irq(scc->irq); 798 799 wr(scc,R4,X1CLK|SDLC); /* *1 clock, SDLC mode */ 800 wr(scc,R1,0); /* no W/REQ operation */ 801 wr(scc,R3,Rx8|RxCRC_ENAB); /* RX 8 bits/char, CRC, disabled */ 802 wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */ 803 wr(scc,R6,0); /* SDLC address zero (not used) */ 804 wr(scc,R7,FLAG); /* SDLC flag value */ 805 wr(scc,R9,VIS); /* vector includes status */ 806 wr(scc,R10,(scc->modem.nrz? NRZ : NRZI)|CRCPS|ABUNDER); /* abort on underrun, preset CRC generator, NRZ(I) */ 807 wr(scc,R14, 0); 808 809 810/* set clock sources: 811 812 CLK_DPLL: normal halfduplex operation 813 814 RxClk: use DPLL 815 TxClk: use DPLL 816 TRxC mode DPLL output 817 818 CLK_EXTERNAL: external clocking (G3RUH or DF9IC modem) 819 820 BayCom: others: 821 822 TxClk = pin RTxC TxClk = pin TRxC 823 RxClk = pin TRxC RxClk = pin RTxC 824 825 826 CLK_DIVIDER: 827 RxClk = use DPLL 828 TxClk = pin RTxC 829 830 BayCom: others: 831 pin TRxC = DPLL pin TRxC = BRG 832 (RxClk * 1) (RxClk * 32) 833*/ 834 835 836 switch(scc->modem.clocksrc) 837 { 838 case CLK_DPLL: 839 wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP); 840 init_brg(scc); 841 break; 842 843 case CLK_DIVIDER: 844 wr(scc, R11, ((scc->brand & BAYCOM)? TRxCDP : TRxCBR) | RCDPLL|TCRTxCP|TRxCOI); 845 init_brg(scc); 846 break; 847 848 case CLK_EXTERNAL: 849 wr(scc, R11, (scc->brand & BAYCOM)? RCTRxCP|TCRTxCP : RCRTxCP|TCTRxCP); 850 OutReg(scc->ctrl, R14, DISDPLL); 851 break; 852 853 } 854 855 set_speed(scc); /* set baudrate */ 856 857 if(scc->enhanced) 858 { 859 or(scc,R15,SHDLCE|FIFOE); /* enable FIFO, SDLC/HDLC Enhancements (From now R7 is R7') */ 860 wr(scc,R7,AUTOEOM); 861 } 862 863 if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD)) 864 /* DCD is now ON */ 865 { 866 start_hunt(scc); 867 } 868 869 /* enable ABORT, DCD & SYNC/HUNT interrupts */ 870 871 wr(scc,R15, BRKIE|TxUIE|(scc->kiss.softdcd? SYNCIE:DCDIE)); 872 873 Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */ 874 Outb(scc->ctrl,RES_EXT_INT); /* must be done twice */ 875 876 or(scc,R1,INT_ALL_Rx|TxINT_ENAB|EXT_INT_ENAB); /* enable interrupts */ 877 878 scc->status = InReg(scc->ctrl,R0); /* read initial status */ 879 880 or(scc,R9,MIE); /* master interrupt enable */ 881 882 scc_init_timer(scc); 883 884 enable_irq(scc->irq); 885} 886 887 888 889 890/* ******************************************************************** */ 891/* * SCC timer functions * */ 892/* ******************************************************************** */ 893 894 895/* ----> scc_key_trx sets the time constant for the baudrate 896 generator and keys the transmitter <---- */ 897 898static void scc_key_trx(struct scc_channel *scc, char tx) 899{ 900 unsigned int time_const; 901 902 if (scc->brand & PRIMUS) 903 Outb(scc->ctrl + 4, scc->option | (tx? 0x80 : 0)); 904 905 if (scc->modem.speed < 300) 906 scc->modem.speed = 1200; 907 908 time_const = (unsigned) (scc->clock / (scc->modem.speed * (tx? 2:64))) - 2; 909 910 disable_irq(scc->irq); 911 912 if (tx) 913 { 914 or(scc, R1, TxINT_ENAB); /* t_maxkeyup may have reset these */ 915 or(scc, R15, TxUIE); 916 } 917 918 if (scc->modem.clocksrc == CLK_DPLL) 919 { /* force simplex operation */ 920 if (tx) 921 { 922#ifdef CONFIG_SCC_TRXECHO 923 cl(scc, R3, RxENABLE|ENT_HM); /* switch off receiver */ 924 cl(scc, R15, DCDIE|SYNCIE); /* No DCD changes, please */ 925#endif 926 set_brg(scc, time_const); /* reprogram baudrate generator */ 927 928 /* DPLL -> Rx clk, BRG -> Tx CLK, TRxC mode output, TRxC = BRG */ 929 wr(scc, R11, RCDPLL|TCBR|TRxCOI|TRxCBR); 930 931 /* By popular demand: tx_inhibit */ 932 if (scc->kiss.tx_inhibit) 933 { 934 or(scc,R5, TxENAB); 935 scc->wreg[R5] |= RTS; 936 } else { 937 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */ 938 } 939 } else { 940 cl(scc,R5,RTS|TxENAB); 941 942 set_brg(scc, time_const); /* reprogram baudrate generator */ 943 944 /* DPLL -> Rx clk, DPLL -> Tx CLK, TRxC mode output, TRxC = DPLL */ 945 wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP); 946 947#ifndef CONFIG_SCC_TRXECHO 948 if (scc->kiss.softdcd) 949#endif 950 { 951 or(scc,R15, scc->kiss.softdcd? SYNCIE:DCDIE); 952 start_hunt(scc); 953 } 954 } 955 } else { 956 if (tx) 957 { 958#ifdef CONFIG_SCC_TRXECHO 959 if (scc->kiss.fulldup == KISS_DUPLEX_HALF) 960 { 961 cl(scc, R3, RxENABLE); 962 cl(scc, R15, DCDIE|SYNCIE); 963 } 964#endif 965 966 if (scc->kiss.tx_inhibit) 967 { 968 or(scc,R5, TxENAB); 969 scc->wreg[R5] |= RTS; 970 } else { 971 or(scc,R5,RTS|TxENAB); /* enable tx */ 972 } 973 } else { 974 cl(scc,R5,RTS|TxENAB); /* disable tx */ 975 976 if ((scc->kiss.fulldup == KISS_DUPLEX_HALF) && 977#ifndef CONFIG_SCC_TRXECHO 978 scc->kiss.softdcd) 979#else 980 1) 981#endif 982 { 983 or(scc, R15, scc->kiss.softdcd? SYNCIE:DCDIE); 984 start_hunt(scc); 985 } 986 } 987 } 988 989 enable_irq(scc->irq); 990} 991 992 993/* ----> SCC timer interrupt handler and friends. <---- */ 994 995static void __scc_start_tx_timer(struct scc_channel *scc, void (*handler)(unsigned long), unsigned long when) 996{ 997 del_timer(&scc->tx_t); 998 999 if (when == 0) 1000 { 1001 handler((unsigned long) scc); 1002 } else 1003 if (when != TIMER_OFF) 1004 { 1005 scc->tx_t.data = (unsigned long) scc; 1006 scc->tx_t.function = handler; 1007 scc->tx_t.expires = jiffies + (when*HZ)/100; 1008 add_timer(&scc->tx_t); 1009 } 1010} 1011 1012static void scc_start_tx_timer(struct scc_channel *scc, void (*handler)(unsigned long), unsigned long when) 1013{ 1014 unsigned long flags; 1015 1016 spin_lock_irqsave(&scc->lock, flags); 1017 __scc_start_tx_timer(scc, handler, when); 1018 spin_unlock_irqrestore(&scc->lock, flags); 1019} 1020 1021static void scc_start_defer(struct scc_channel *scc) 1022{ 1023 unsigned long flags; 1024 1025 spin_lock_irqsave(&scc->lock, flags); 1026 del_timer(&scc->tx_wdog); 1027 1028 if (scc->kiss.maxdefer != 0 && scc->kiss.maxdefer != TIMER_OFF) 1029 { 1030 scc->tx_wdog.data = (unsigned long) scc; 1031 scc->tx_wdog.function = t_busy; 1032 scc->tx_wdog.expires = jiffies + HZ*scc->kiss.maxdefer; 1033 add_timer(&scc->tx_wdog); 1034 } 1035 spin_unlock_irqrestore(&scc->lock, flags); 1036} 1037 1038static void scc_start_maxkeyup(struct scc_channel *scc) 1039{ 1040 unsigned long flags; 1041 1042 spin_lock_irqsave(&scc->lock, flags); 1043 del_timer(&scc->tx_wdog); 1044 1045 if (scc->kiss.maxkeyup != 0 && scc->kiss.maxkeyup != TIMER_OFF) 1046 { 1047 scc->tx_wdog.data = (unsigned long) scc; 1048 scc->tx_wdog.function = t_maxkeyup; 1049 scc->tx_wdog.expires = jiffies + HZ*scc->kiss.maxkeyup; 1050 add_timer(&scc->tx_wdog); 1051 } 1052 spin_unlock_irqrestore(&scc->lock, flags); 1053} 1054 1055/* 1056 * This is called from scc_txint() when there are no more frames to send. 1057 * Not exactly a timer function, but it is a close friend of the family... 1058 */ 1059 1060static void scc_tx_done(struct scc_channel *scc) 1061{ 1062 /* 1063 * trx remains keyed in fulldup mode 2 until t_idle expires. 1064 */ 1065 1066 switch (scc->kiss.fulldup) 1067 { 1068 case KISS_DUPLEX_LINK: 1069 scc->stat.tx_state = TXS_IDLE2; 1070 if (scc->kiss.idletime != TIMER_OFF) 1071 scc_start_tx_timer(scc, t_idle, 1072 scc->kiss.idletime*100); 1073 break; 1074 case KISS_DUPLEX_OPTIMA: 1075 scc_notify(scc, HWEV_ALL_SENT); 1076 break; 1077 default: 1078 scc->stat.tx_state = TXS_BUSY; 1079 scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime); 1080 } 1081 1082 netif_wake_queue(scc->dev); 1083} 1084 1085 1086static unsigned char Rand = 17; 1087 1088static inline int is_grouped(struct scc_channel *scc) 1089{ 1090 int k; 1091 struct scc_channel *scc2; 1092 unsigned char grp1, grp2; 1093 1094 grp1 = scc->kiss.group; 1095 1096 for (k = 0; k < (Nchips * 2); k++) 1097 { 1098 scc2 = &SCC_Info[k]; 1099 grp2 = scc2->kiss.group; 1100 1101 if (scc2 == scc || !(scc2->dev && grp2)) 1102 continue; 1103 1104 if ((grp1 & 0x3f) == (grp2 & 0x3f)) 1105 { 1106 if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) ) 1107 return 1; 1108 1109 if ( (grp1 & RXGROUP) && scc2->dcd ) 1110 return 1; 1111 } 1112 } 1113 return 0; 1114} 1115 1116/* DWAIT and SLOTTIME expired 1117 * 1118 * fulldup == 0: DCD is active or Rand > P-persistence: start t_busy timer 1119 * else key trx and start txdelay 1120 * fulldup == 1: key trx and start txdelay 1121 * fulldup == 2: mintime expired, reset status or key trx and start txdelay 1122 */ 1123 1124static void t_dwait(unsigned long channel) 1125{ 1126 struct scc_channel *scc = (struct scc_channel *) channel; 1127 1128 if (scc->stat.tx_state == TXS_WAIT) /* maxkeyup or idle timeout */ 1129 { 1130 if (skb_queue_empty(&scc->tx_queue)) { /* nothing to send */ 1131 scc->stat.tx_state = TXS_IDLE; 1132 netif_wake_queue(scc->dev); /* t_maxkeyup locked it. */ 1133 return; 1134 } 1135 1136 scc->stat.tx_state = TXS_BUSY; 1137 } 1138 1139 if (scc->kiss.fulldup == KISS_DUPLEX_HALF) 1140 { 1141 Rand = Rand * 17 + 31; 1142 1143 if (scc->dcd || (scc->kiss.persist) < Rand || (scc->kiss.group && is_grouped(scc)) ) 1144 { 1145 scc_start_defer(scc); 1146 scc_start_tx_timer(scc, t_dwait, scc->kiss.slottime); 1147 return ; 1148 } 1149 } 1150 1151 if ( !(scc->wreg[R5] & RTS) ) 1152 { 1153 scc_key_trx(scc, TX_ON); 1154 scc_start_tx_timer(scc, t_txdelay, scc->kiss.txdelay); 1155 } else { 1156 scc_start_tx_timer(scc, t_txdelay, 0); 1157 } 1158} 1159 1160 1161/* TXDELAY expired 1162 * 1163 * kick transmission by a fake scc_txint(scc), start 'maxkeyup' watchdog. 1164 */ 1165 1166static void t_txdelay(unsigned long channel) 1167{ 1168 struct scc_channel *scc = (struct scc_channel *) channel; 1169 1170 scc_start_maxkeyup(scc); 1171 1172 if (scc->tx_buff == NULL) 1173 { 1174 disable_irq(scc->irq); 1175 scc_txint(scc); 1176 enable_irq(scc->irq); 1177 } 1178} 1179 1180 1181/* TAILTIME expired 1182 * 1183 * switch off transmitter. If we were stopped by Maxkeyup restart 1184 * transmission after 'mintime' seconds 1185 */ 1186 1187static void t_tail(unsigned long channel) 1188{ 1189 struct scc_channel *scc = (struct scc_channel *) channel; 1190 unsigned long flags; 1191 1192 spin_lock_irqsave(&scc->lock, flags); 1193 del_timer(&scc->tx_wdog); 1194 scc_key_trx(scc, TX_OFF); 1195 spin_unlock_irqrestore(&scc->lock, flags); 1196 1197 if (scc->stat.tx_state == TXS_TIMEOUT) /* we had a timeout? */ 1198 { 1199 scc->stat.tx_state = TXS_WAIT; 1200 scc_start_tx_timer(scc, t_dwait, scc->kiss.mintime*100); 1201 return; 1202 } 1203 1204 scc->stat.tx_state = TXS_IDLE; 1205 netif_wake_queue(scc->dev); 1206} 1207 1208 1209/* BUSY timeout 1210 * 1211 * throw away send buffers if DCD remains active too long. 1212 */ 1213 1214static void t_busy(unsigned long channel) 1215{ 1216 struct scc_channel *scc = (struct scc_channel *) channel; 1217 1218 del_timer(&scc->tx_t); 1219 netif_stop_queue(scc->dev); /* don't pile on the wabbit! */ 1220 1221 scc_discard_buffers(scc); 1222 scc->stat.txerrs++; 1223 scc->stat.tx_state = TXS_IDLE; 1224 1225 netif_wake_queue(scc->dev); 1226} 1227 1228/* MAXKEYUP timeout 1229 * 1230 * this is our watchdog. 1231 */ 1232 1233static void t_maxkeyup(unsigned long channel) 1234{ 1235 struct scc_channel *scc = (struct scc_channel *) channel; 1236 unsigned long flags; 1237 1238 spin_lock_irqsave(&scc->lock, flags); 1239 /* 1240 * let things settle down before we start to 1241 * accept new data. 1242 */ 1243 1244 netif_stop_queue(scc->dev); 1245 scc_discard_buffers(scc); 1246 1247 del_timer(&scc->tx_t); 1248 1249 cl(scc, R1, TxINT_ENAB); /* force an ABORT, but don't */ 1250 cl(scc, R15, TxUIE); /* count it. */ 1251 OutReg(scc->ctrl, R0, RES_Tx_P); 1252 1253 spin_unlock_irqrestore(&scc->lock, flags); 1254 1255 scc->stat.txerrs++; 1256 scc->stat.tx_state = TXS_TIMEOUT; 1257 scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime); 1258} 1259 1260/* IDLE timeout 1261 * 1262 * in fulldup mode 2 it keys down the transmitter after 'idle' seconds 1263 * of inactivity. We will not restart transmission before 'mintime' 1264 * expires. 1265 */ 1266 1267static void t_idle(unsigned long channel) 1268{ 1269 struct scc_channel *scc = (struct scc_channel *) channel; 1270 1271 del_timer(&scc->tx_wdog); 1272 1273 scc_key_trx(scc, TX_OFF); 1274 if(scc->kiss.mintime) 1275 scc_start_tx_timer(scc, t_dwait, scc->kiss.mintime*100); 1276 scc->stat.tx_state = TXS_WAIT; 1277} 1278 1279static void scc_init_timer(struct scc_channel *scc) 1280{ 1281 unsigned long flags; 1282 1283 spin_lock_irqsave(&scc->lock, flags); 1284 scc->stat.tx_state = TXS_IDLE; 1285 spin_unlock_irqrestore(&scc->lock, flags); 1286} 1287 1288 1289/* ******************************************************************** */ 1290/* * Set/get L1 parameters * */ 1291/* ******************************************************************** */ 1292 1293 1294/* 1295 * this will set the "hardware" parameters through KISS commands or ioctl() 1296 */ 1297 1298#define CAST(x) (unsigned long)(x) 1299 1300static unsigned int scc_set_param(struct scc_channel *scc, unsigned int cmd, unsigned int arg) 1301{ 1302 switch (cmd) 1303 { 1304 case PARAM_TXDELAY: scc->kiss.txdelay=arg; break; 1305 case PARAM_PERSIST: scc->kiss.persist=arg; break; 1306 case PARAM_SLOTTIME: scc->kiss.slottime=arg; break; 1307 case PARAM_TXTAIL: scc->kiss.tailtime=arg; break; 1308 case PARAM_FULLDUP: scc->kiss.fulldup=arg; break; 1309 case PARAM_DTR: break; /* does someone need this? */ 1310 case PARAM_GROUP: scc->kiss.group=arg; break; 1311 case PARAM_IDLE: scc->kiss.idletime=arg; break; 1312 case PARAM_MIN: scc->kiss.mintime=arg; break; 1313 case PARAM_MAXKEY: scc->kiss.maxkeyup=arg; break; 1314 case PARAM_WAIT: scc->kiss.waittime=arg; break; 1315 case PARAM_MAXDEFER: scc->kiss.maxdefer=arg; break; 1316 case PARAM_TX: scc->kiss.tx_inhibit=arg; break; 1317 1318 case PARAM_SOFTDCD: 1319 scc->kiss.softdcd=arg; 1320 if (arg) 1321 { 1322 or(scc, R15, SYNCIE); 1323 cl(scc, R15, DCDIE); 1324 start_hunt(scc); 1325 } else { 1326 or(scc, R15, DCDIE); 1327 cl(scc, R15, SYNCIE); 1328 } 1329 break; 1330 1331 case PARAM_SPEED: 1332 if (arg < 256) 1333 scc->modem.speed=arg*100; 1334 else 1335 scc->modem.speed=arg; 1336 1337 if (scc->stat.tx_state == 0) /* only switch baudrate on rx... ;-) */ 1338 set_speed(scc); 1339 break; 1340 1341 case PARAM_RTS: 1342 if ( !(scc->wreg[R5] & RTS) ) 1343 { 1344 if (arg != TX_OFF) { 1345 scc_key_trx(scc, TX_ON); 1346 scc_start_tx_timer(scc, t_txdelay, scc->kiss.txdelay); 1347 } 1348 } else { 1349 if (arg == TX_OFF) 1350 { 1351 scc->stat.tx_state = TXS_BUSY; 1352 scc_start_tx_timer(scc, t_tail, scc->kiss.tailtime); 1353 } 1354 } 1355 break; 1356 1357 case PARAM_HWEVENT: 1358 scc_notify(scc, scc->dcd? HWEV_DCD_ON:HWEV_DCD_OFF); 1359 break; 1360 1361 default: return -EINVAL; 1362 } 1363 1364 return 0; 1365} 1366 1367 1368 1369static unsigned long scc_get_param(struct scc_channel *scc, unsigned int cmd) 1370{ 1371 switch (cmd) 1372 { 1373 case PARAM_TXDELAY: return CAST(scc->kiss.txdelay); 1374 case PARAM_PERSIST: return CAST(scc->kiss.persist); 1375 case PARAM_SLOTTIME: return CAST(scc->kiss.slottime); 1376 case PARAM_TXTAIL: return CAST(scc->kiss.tailtime); 1377 case PARAM_FULLDUP: return CAST(scc->kiss.fulldup); 1378 case PARAM_SOFTDCD: return CAST(scc->kiss.softdcd); 1379 case PARAM_DTR: return CAST((scc->wreg[R5] & DTR)? 1:0); 1380 case PARAM_RTS: return CAST((scc->wreg[R5] & RTS)? 1:0); 1381 case PARAM_SPEED: return CAST(scc->modem.speed); 1382 case PARAM_GROUP: return CAST(scc->kiss.group); 1383 case PARAM_IDLE: return CAST(scc->kiss.idletime); 1384 case PARAM_MIN: return CAST(scc->kiss.mintime); 1385 case PARAM_MAXKEY: return CAST(scc->kiss.maxkeyup); 1386 case PARAM_WAIT: return CAST(scc->kiss.waittime); 1387 case PARAM_MAXDEFER: return CAST(scc->kiss.maxdefer); 1388 case PARAM_TX: return CAST(scc->kiss.tx_inhibit); 1389 default: return NO_SUCH_PARAM; 1390 } 1391 1392} 1393 1394#undef CAST 1395 1396/* ******************************************************************* */ 1397/* * Send calibration pattern * */ 1398/* ******************************************************************* */ 1399 1400static void scc_stop_calibrate(unsigned long channel) 1401{ 1402 struct scc_channel *scc = (struct scc_channel *) channel; 1403 unsigned long flags; 1404 1405 spin_lock_irqsave(&scc->lock, flags); 1406 del_timer(&scc->tx_wdog); 1407 scc_key_trx(scc, TX_OFF); 1408 wr(scc, R6, 0); 1409 wr(scc, R7, FLAG); 1410 Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */ 1411 Outb(scc->ctrl,RES_EXT_INT); 1412 1413 netif_wake_queue(scc->dev); 1414 spin_unlock_irqrestore(&scc->lock, flags); 1415} 1416 1417 1418static void 1419scc_start_calibrate(struct scc_channel *scc, int duration, unsigned char pattern) 1420{ 1421 unsigned long flags; 1422 1423 spin_lock_irqsave(&scc->lock, flags); 1424 netif_stop_queue(scc->dev); 1425 scc_discard_buffers(scc); 1426 1427 del_timer(&scc->tx_wdog); 1428 1429 scc->tx_wdog.data = (unsigned long) scc; 1430 scc->tx_wdog.function = scc_stop_calibrate; 1431 scc->tx_wdog.expires = jiffies + HZ*duration; 1432 add_timer(&scc->tx_wdog); 1433 1434 /* This doesn't seem to work. Why not? */ 1435 wr(scc, R6, 0); 1436 wr(scc, R7, pattern); 1437 1438 /* 1439 * Don't know if this works. 1440 * Damn, where is my Z8530 programming manual...? 1441 */ 1442 1443 Outb(scc->ctrl,RES_EXT_INT); /* reset ext/status interrupts */ 1444 Outb(scc->ctrl,RES_EXT_INT); 1445 1446 scc_key_trx(scc, TX_ON); 1447 spin_unlock_irqrestore(&scc->lock, flags); 1448} 1449 1450/* ******************************************************************* */ 1451/* * Init channel structures, special HW, etc... * */ 1452/* ******************************************************************* */ 1453 1454/* 1455 * Reset the Z8530s and setup special hardware 1456 */ 1457 1458static void z8530_init(void) 1459{ 1460 struct scc_channel *scc; 1461 int chip, k; 1462 unsigned long flags; 1463 char *flag; 1464 1465 1466 printk(KERN_INFO "Init Z8530 driver: %u channels, IRQ", Nchips*2); 1467 1468 flag=" "; 1469 for (k = 0; k < nr_irqs; k++) 1470 if (Ivec[k].used) 1471 { 1472 printk("%s%d", flag, k); 1473 flag=","; 1474 } 1475 printk("\n"); 1476 1477 1478 /* reset and pre-init all chips in the system */ 1479 for (chip = 0; chip < Nchips; chip++) 1480 { 1481 scc=&SCC_Info[2*chip]; 1482 if (!scc->ctrl) continue; 1483 1484 /* Special SCC cards */ 1485 1486 if(scc->brand & EAGLE) /* this is an EAGLE card */ 1487 Outb(scc->special,0x08); /* enable interrupt on the board */ 1488 1489 if(scc->brand & (PC100 | PRIMUS)) /* this is a PC100/PRIMUS card */ 1490 Outb(scc->special,scc->option); /* set the MODEM mode (0x22) */ 1491 1492 1493 /* Reset and pre-init Z8530 */ 1494 1495 spin_lock_irqsave(&scc->lock, flags); 1496 1497 Outb(scc->ctrl, 0); 1498 OutReg(scc->ctrl,R9,FHWRES); /* force hardware reset */ 1499 udelay(100); /* give it 'a bit' more time than required */ 1500 wr(scc, R2, chip*16); /* interrupt vector */ 1501 wr(scc, R9, VIS); /* vector includes status */ 1502 spin_unlock_irqrestore(&scc->lock, flags); 1503 } 1504 1505 1506 Driver_Initialized = 1; 1507} 1508 1509/* 1510 * Allocate device structure, err, instance, and register driver 1511 */ 1512 1513static int scc_net_alloc(const char *name, struct scc_channel *scc) 1514{ 1515 int err; 1516 struct net_device *dev; 1517 1518 dev = alloc_netdev(0, name, NET_NAME_UNKNOWN, scc_net_setup); 1519 if (!dev) 1520 return -ENOMEM; 1521 1522 dev->ml_priv = scc; 1523 scc->dev = dev; 1524 spin_lock_init(&scc->lock); 1525 init_timer(&scc->tx_t); 1526 init_timer(&scc->tx_wdog); 1527 1528 err = register_netdevice(dev); 1529 if (err) { 1530 printk(KERN_ERR "%s: can't register network device (%d)\n", 1531 name, err); 1532 free_netdev(dev); 1533 scc->dev = NULL; 1534 return err; 1535 } 1536 1537 return 0; 1538} 1539 1540 1541 1542/* ******************************************************************** */ 1543/* * Network driver methods * */ 1544/* ******************************************************************** */ 1545 1546static const struct net_device_ops scc_netdev_ops = { 1547 .ndo_open = scc_net_open, 1548 .ndo_stop = scc_net_close, 1549 .ndo_start_xmit = scc_net_tx, 1550 .ndo_set_mac_address = scc_net_set_mac_address, 1551 .ndo_get_stats = scc_net_get_stats, 1552 .ndo_do_ioctl = scc_net_ioctl, 1553}; 1554 1555/* ----> Initialize device <----- */ 1556 1557static void scc_net_setup(struct net_device *dev) 1558{ 1559 dev->tx_queue_len = 16; /* should be enough... */ 1560 1561 dev->netdev_ops = &scc_netdev_ops; 1562 dev->header_ops = &ax25_header_ops; 1563 1564 memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN); 1565 memcpy(dev->dev_addr, &ax25_defaddr, AX25_ADDR_LEN); 1566 1567 dev->flags = 0; 1568 1569 dev->type = ARPHRD_AX25; 1570 dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN; 1571 dev->mtu = AX25_DEF_PACLEN; 1572 dev->addr_len = AX25_ADDR_LEN; 1573 1574} 1575 1576/* ----> open network device <---- */ 1577 1578static int scc_net_open(struct net_device *dev) 1579{ 1580 struct scc_channel *scc = (struct scc_channel *) dev->ml_priv; 1581 1582 if (!scc->init) 1583 return -EINVAL; 1584 1585 scc->tx_buff = NULL; 1586 skb_queue_head_init(&scc->tx_queue); 1587 1588 init_channel(scc); 1589 1590 netif_start_queue(dev); 1591 return 0; 1592} 1593 1594/* ----> close network device <---- */ 1595 1596static int scc_net_close(struct net_device *dev) 1597{ 1598 struct scc_channel *scc = (struct scc_channel *) dev->ml_priv; 1599 unsigned long flags; 1600 1601 netif_stop_queue(dev); 1602 1603 spin_lock_irqsave(&scc->lock, flags); 1604 Outb(scc->ctrl,0); /* Make sure pointer is written */ 1605 wr(scc,R1,0); /* disable interrupts */ 1606 wr(scc,R3,0); 1607 spin_unlock_irqrestore(&scc->lock, flags); 1608 1609 del_timer_sync(&scc->tx_t); 1610 del_timer_sync(&scc->tx_wdog); 1611 1612 scc_discard_buffers(scc); 1613 1614 return 0; 1615} 1616 1617/* ----> receive frame, called from scc_rxint() <---- */ 1618 1619static void scc_net_rx(struct scc_channel *scc, struct sk_buff *skb) 1620{ 1621 if (skb->len == 0) { 1622 dev_kfree_skb_irq(skb); 1623 return; 1624 } 1625 1626 scc->dev_stat.rx_packets++; 1627 scc->dev_stat.rx_bytes += skb->len; 1628 1629 skb->protocol = ax25_type_trans(skb, scc->dev); 1630 1631 netif_rx(skb); 1632} 1633 1634/* ----> transmit frame <---- */ 1635 1636static netdev_tx_t scc_net_tx(struct sk_buff *skb, struct net_device *dev) 1637{ 1638 struct scc_channel *scc = (struct scc_channel *) dev->ml_priv; 1639 unsigned long flags; 1640 char kisscmd; 1641 1642 if (skb->protocol == htons(ETH_P_IP)) 1643 return ax25_ip_xmit(skb); 1644 1645 if (skb->len > scc->stat.bufsize || skb->len < 2) { 1646 scc->dev_stat.tx_dropped++; /* bogus frame */ 1647 dev_kfree_skb(skb); 1648 return NETDEV_TX_OK; 1649 } 1650 1651 scc->dev_stat.tx_packets++; 1652 scc->dev_stat.tx_bytes += skb->len; 1653 scc->stat.txframes++; 1654 1655 kisscmd = *skb->data & 0x1f; 1656 skb_pull(skb, 1); 1657 1658 if (kisscmd) { 1659 scc_set_param(scc, kisscmd, *skb->data); 1660 dev_kfree_skb(skb); 1661 return NETDEV_TX_OK; 1662 } 1663 1664 spin_lock_irqsave(&scc->lock, flags); 1665 1666 if (skb_queue_len(&scc->tx_queue) > scc->dev->tx_queue_len) { 1667 struct sk_buff *skb_del; 1668 skb_del = skb_dequeue(&scc->tx_queue); 1669 dev_kfree_skb(skb_del); 1670 } 1671 skb_queue_tail(&scc->tx_queue, skb); 1672 dev->trans_start = jiffies; 1673 1674 1675 /* 1676 * Start transmission if the trx state is idle or 1677 * t_idle hasn't expired yet. Use dwait/persistence/slottime 1678 * algorithm for normal halfduplex operation. 1679 */ 1680 1681 if(scc->stat.tx_state == TXS_IDLE || scc->stat.tx_state == TXS_IDLE2) { 1682 scc->stat.tx_state = TXS_BUSY; 1683 if (scc->kiss.fulldup == KISS_DUPLEX_HALF) 1684 __scc_start_tx_timer(scc, t_dwait, scc->kiss.waittime); 1685 else 1686 __scc_start_tx_timer(scc, t_dwait, 0); 1687 } 1688 spin_unlock_irqrestore(&scc->lock, flags); 1689 return NETDEV_TX_OK; 1690} 1691 1692/* ----> ioctl functions <---- */ 1693 1694/* 1695 * SIOCSCCCFG - configure driver arg: (struct scc_hw_config *) arg 1696 * SIOCSCCINI - initialize driver arg: --- 1697 * SIOCSCCCHANINI - initialize channel arg: (struct scc_modem *) arg 1698 * SIOCSCCSMEM - set memory arg: (struct scc_mem_config *) arg 1699 * SIOCSCCGKISS - get level 1 parameter arg: (struct scc_kiss_cmd *) arg 1700 * SIOCSCCSKISS - set level 1 parameter arg: (struct scc_kiss_cmd *) arg 1701 * SIOCSCCGSTAT - get driver status arg: (struct scc_stat *) arg 1702 * SIOCSCCCAL - send calib. pattern arg: (struct scc_calibrate *) arg 1703 */ 1704 1705static int scc_net_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1706{ 1707 struct scc_kiss_cmd kiss_cmd; 1708 struct scc_mem_config memcfg; 1709 struct scc_hw_config hwcfg; 1710 struct scc_calibrate cal; 1711 struct scc_channel *scc = (struct scc_channel *) dev->ml_priv; 1712 int chan; 1713 unsigned char device_name[IFNAMSIZ]; 1714 void __user *arg = ifr->ifr_data; 1715 1716 1717 if (!Driver_Initialized) 1718 { 1719 if (cmd == SIOCSCCCFG) 1720 { 1721 int found = 1; 1722 1723 if (!capable(CAP_SYS_RAWIO)) return -EPERM; 1724 if (!arg) return -EFAULT; 1725 1726 if (Nchips >= SCC_MAXCHIPS) 1727 return -EINVAL; 1728 1729 if (copy_from_user(&hwcfg, arg, sizeof(hwcfg))) 1730 return -EFAULT; 1731 1732 if (hwcfg.irq == 2) hwcfg.irq = 9; 1733 1734 if (hwcfg.irq < 0 || hwcfg.irq >= nr_irqs) 1735 return -EINVAL; 1736 1737 if (!Ivec[hwcfg.irq].used && hwcfg.irq) 1738 { 1739 if (request_irq(hwcfg.irq, scc_isr, 1740 0, "AX.25 SCC", 1741 (void *)(long) hwcfg.irq)) 1742 printk(KERN_WARNING "z8530drv: warning, cannot get IRQ %d\n", hwcfg.irq); 1743 else 1744 Ivec[hwcfg.irq].used = 1; 1745 } 1746 1747 if (hwcfg.vector_latch && !Vector_Latch) { 1748 if (!request_region(hwcfg.vector_latch, 1, "scc vector latch")) 1749 printk(KERN_WARNING "z8530drv: warning, cannot reserve vector latch port 0x%lx\n, disabled.", hwcfg.vector_latch); 1750 else 1751 Vector_Latch = hwcfg.vector_latch; 1752 } 1753 1754 if (hwcfg.clock == 0) 1755 hwcfg.clock = SCC_DEFAULT_CLOCK; 1756 1757#ifndef SCC_DONT_CHECK 1758 1759 if(request_region(hwcfg.ctrl_a, 1, "scc-probe")) 1760 { 1761 disable_irq(hwcfg.irq); 1762 Outb(hwcfg.ctrl_a, 0); 1763 OutReg(hwcfg.ctrl_a, R9, FHWRES); 1764 udelay(100); 1765 OutReg(hwcfg.ctrl_a,R13,0x55); /* is this chip really there? */ 1766 udelay(5); 1767 1768 if (InReg(hwcfg.ctrl_a,R13) != 0x55) 1769 found = 0; 1770 enable_irq(hwcfg.irq); 1771 release_region(hwcfg.ctrl_a, 1); 1772 } 1773 else 1774 found = 0; 1775#endif 1776 1777 if (found) 1778 { 1779 SCC_Info[2*Nchips ].ctrl = hwcfg.ctrl_a; 1780 SCC_Info[2*Nchips ].data = hwcfg.data_a; 1781 SCC_Info[2*Nchips ].irq = hwcfg.irq; 1782 SCC_Info[2*Nchips+1].ctrl = hwcfg.ctrl_b; 1783 SCC_Info[2*Nchips+1].data = hwcfg.data_b; 1784 SCC_Info[2*Nchips+1].irq = hwcfg.irq; 1785 1786 SCC_ctrl[Nchips].chan_A = hwcfg.ctrl_a; 1787 SCC_ctrl[Nchips].chan_B = hwcfg.ctrl_b; 1788 SCC_ctrl[Nchips].irq = hwcfg.irq; 1789 } 1790 1791 1792 for (chan = 0; chan < 2; chan++) 1793 { 1794 sprintf(device_name, "%s%i", SCC_DriverName, 2*Nchips+chan); 1795 1796 SCC_Info[2*Nchips+chan].special = hwcfg.special; 1797 SCC_Info[2*Nchips+chan].clock = hwcfg.clock; 1798 SCC_Info[2*Nchips+chan].brand = hwcfg.brand; 1799 SCC_Info[2*Nchips+chan].option = hwcfg.option; 1800 SCC_Info[2*Nchips+chan].enhanced = hwcfg.escc; 1801 1802#ifdef SCC_DONT_CHECK 1803 printk(KERN_INFO "%s: data port = 0x%3.3x control port = 0x%3.3x\n", 1804 device_name, 1805 SCC_Info[2*Nchips+chan].data, 1806 SCC_Info[2*Nchips+chan].ctrl); 1807 1808#else 1809 printk(KERN_INFO "%s: data port = 0x%3.3lx control port = 0x%3.3lx -- %s\n", 1810 device_name, 1811 chan? hwcfg.data_b : hwcfg.data_a, 1812 chan? hwcfg.ctrl_b : hwcfg.ctrl_a, 1813 found? "found" : "missing"); 1814#endif 1815 1816 if (found) 1817 { 1818 request_region(SCC_Info[2*Nchips+chan].ctrl, 1, "scc ctrl"); 1819 request_region(SCC_Info[2*Nchips+chan].data, 1, "scc data"); 1820 if (Nchips+chan != 0 && 1821 scc_net_alloc(device_name, 1822 &SCC_Info[2*Nchips+chan])) 1823 return -EINVAL; 1824 } 1825 } 1826 1827 if (found) Nchips++; 1828 1829 return 0; 1830 } 1831 1832 if (cmd == SIOCSCCINI) 1833 { 1834 if (!capable(CAP_SYS_RAWIO)) 1835 return -EPERM; 1836 1837 if (Nchips == 0) 1838 return -EINVAL; 1839 1840 z8530_init(); 1841 return 0; 1842 } 1843 1844 return -EINVAL; /* confuse the user */ 1845 } 1846 1847 if (!scc->init) 1848 { 1849 if (cmd == SIOCSCCCHANINI) 1850 { 1851 if (!capable(CAP_NET_ADMIN)) return -EPERM; 1852 if (!arg) return -EINVAL; 1853 1854 scc->stat.bufsize = SCC_BUFSIZE; 1855 1856 if (copy_from_user(&scc->modem, arg, sizeof(struct scc_modem))) 1857 return -EINVAL; 1858 1859 /* default KISS Params */ 1860 1861 if (scc->modem.speed < 4800) 1862 { 1863 scc->kiss.txdelay = 36; /* 360 ms */ 1864 scc->kiss.persist = 42; /* 25% persistence */ /* was 25 */ 1865 scc->kiss.slottime = 16; /* 160 ms */ 1866 scc->kiss.tailtime = 4; /* minimal reasonable value */ 1867 scc->kiss.fulldup = 0; /* CSMA */ 1868 scc->kiss.waittime = 50; /* 500 ms */ 1869 scc->kiss.maxkeyup = 10; /* 10 s */ 1870 scc->kiss.mintime = 3; /* 3 s */ 1871 scc->kiss.idletime = 30; /* 30 s */ 1872 scc->kiss.maxdefer = 120; /* 2 min */ 1873 scc->kiss.softdcd = 0; /* hardware dcd */ 1874 } else { 1875 scc->kiss.txdelay = 10; /* 100 ms */ 1876 scc->kiss.persist = 64; /* 25% persistence */ /* was 25 */ 1877 scc->kiss.slottime = 8; /* 160 ms */ 1878 scc->kiss.tailtime = 1; /* minimal reasonable value */ 1879 scc->kiss.fulldup = 0; /* CSMA */ 1880 scc->kiss.waittime = 50; /* 500 ms */ 1881 scc->kiss.maxkeyup = 7; /* 7 s */ 1882 scc->kiss.mintime = 3; /* 3 s */ 1883 scc->kiss.idletime = 30; /* 30 s */ 1884 scc->kiss.maxdefer = 120; /* 2 min */ 1885 scc->kiss.softdcd = 0; /* hardware dcd */ 1886 } 1887 1888 scc->tx_buff = NULL; 1889 skb_queue_head_init(&scc->tx_queue); 1890 scc->init = 1; 1891 1892 return 0; 1893 } 1894 1895 return -EINVAL; 1896 } 1897 1898 switch(cmd) 1899 { 1900 case SIOCSCCRESERVED: 1901 return -ENOIOCTLCMD; 1902 1903 case SIOCSCCSMEM: 1904 if (!capable(CAP_SYS_RAWIO)) return -EPERM; 1905 if (!arg || copy_from_user(&memcfg, arg, sizeof(memcfg))) 1906 return -EINVAL; 1907 scc->stat.bufsize = memcfg.bufsize; 1908 return 0; 1909 1910 case SIOCSCCGSTAT: 1911 if (!arg || copy_to_user(arg, &scc->stat, sizeof(scc->stat))) 1912 return -EINVAL; 1913 return 0; 1914 1915 case SIOCSCCGKISS: 1916 if (!arg || copy_from_user(&kiss_cmd, arg, sizeof(kiss_cmd))) 1917 return -EINVAL; 1918 kiss_cmd.param = scc_get_param(scc, kiss_cmd.command); 1919 if (copy_to_user(arg, &kiss_cmd, sizeof(kiss_cmd))) 1920 return -EINVAL; 1921 return 0; 1922 1923 case SIOCSCCSKISS: 1924 if (!capable(CAP_NET_ADMIN)) return -EPERM; 1925 if (!arg || copy_from_user(&kiss_cmd, arg, sizeof(kiss_cmd))) 1926 return -EINVAL; 1927 return scc_set_param(scc, kiss_cmd.command, kiss_cmd.param); 1928 1929 case SIOCSCCCAL: 1930 if (!capable(CAP_SYS_RAWIO)) return -EPERM; 1931 if (!arg || copy_from_user(&cal, arg, sizeof(cal)) || cal.time == 0) 1932 return -EINVAL; 1933 1934 scc_start_calibrate(scc, cal.time, cal.pattern); 1935 return 0; 1936 1937 default: 1938 return -ENOIOCTLCMD; 1939 1940 } 1941 1942 return -EINVAL; 1943} 1944 1945/* ----> set interface callsign <---- */ 1946 1947static int scc_net_set_mac_address(struct net_device *dev, void *addr) 1948{ 1949 struct sockaddr *sa = (struct sockaddr *) addr; 1950 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len); 1951 return 0; 1952} 1953 1954/* ----> get statistics <---- */ 1955 1956static struct net_device_stats *scc_net_get_stats(struct net_device *dev) 1957{ 1958 struct scc_channel *scc = (struct scc_channel *) dev->ml_priv; 1959 1960 scc->dev_stat.rx_errors = scc->stat.rxerrs + scc->stat.rx_over; 1961 scc->dev_stat.tx_errors = scc->stat.txerrs + scc->stat.tx_under; 1962 scc->dev_stat.rx_fifo_errors = scc->stat.rx_over; 1963 scc->dev_stat.tx_fifo_errors = scc->stat.tx_under; 1964 1965 return &scc->dev_stat; 1966} 1967 1968/* ******************************************************************** */ 1969/* * dump statistics to /proc/net/z8530drv * */ 1970/* ******************************************************************** */ 1971 1972#ifdef CONFIG_PROC_FS 1973 1974static inline struct scc_channel *scc_net_seq_idx(loff_t pos) 1975{ 1976 int k; 1977 1978 for (k = 0; k < Nchips*2; ++k) { 1979 if (!SCC_Info[k].init) 1980 continue; 1981 if (pos-- == 0) 1982 return &SCC_Info[k]; 1983 } 1984 return NULL; 1985} 1986 1987static void *scc_net_seq_start(struct seq_file *seq, loff_t *pos) 1988{ 1989 return *pos ? scc_net_seq_idx(*pos - 1) : SEQ_START_TOKEN; 1990 1991} 1992 1993static void *scc_net_seq_next(struct seq_file *seq, void *v, loff_t *pos) 1994{ 1995 unsigned k; 1996 struct scc_channel *scc = v; 1997 ++*pos; 1998 1999 for (k = (v == SEQ_START_TOKEN) ? 0 : (scc - SCC_Info)+1; 2000 k < Nchips*2; ++k) { 2001 if (SCC_Info[k].init) 2002 return &SCC_Info[k]; 2003 } 2004 return NULL; 2005} 2006 2007static void scc_net_seq_stop(struct seq_file *seq, void *v) 2008{ 2009} 2010 2011static int scc_net_seq_show(struct seq_file *seq, void *v) 2012{ 2013 if (v == SEQ_START_TOKEN) { 2014 seq_puts(seq, "z8530drv-"VERSION"\n"); 2015 } else if (!Driver_Initialized) { 2016 seq_puts(seq, "not initialized\n"); 2017 } else if (!Nchips) { 2018 seq_puts(seq, "chips missing\n"); 2019 } else { 2020 const struct scc_channel *scc = v; 2021 const struct scc_stat *stat = &scc->stat; 2022 const struct scc_kiss *kiss = &scc->kiss; 2023 2024 2025 /* dev data ctrl irq clock brand enh vector special option 2026 * baud nrz clocksrc softdcd bufsize 2027 * rxints txints exints spints 2028 * rcvd rxerrs over / xmit txerrs under / nospace bufsize 2029 * txd pers slot tail ful wait min maxk idl defr txof grp 2030 * W ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## ## 2031 * R ## ## XX ## ## ## ## ## XX ## ## ## ## ## ## ## 2032 */ 2033 2034 seq_printf(seq, "%s\t%3.3lx %3.3lx %d %lu %2.2x %d %3.3lx %3.3lx %d\n", 2035 scc->dev->name, 2036 scc->data, scc->ctrl, scc->irq, scc->clock, scc->brand, 2037 scc->enhanced, Vector_Latch, scc->special, 2038 scc->option); 2039 seq_printf(seq, "\t%lu %d %d %d %d\n", 2040 scc->modem.speed, scc->modem.nrz, 2041 scc->modem.clocksrc, kiss->softdcd, 2042 stat->bufsize); 2043 seq_printf(seq, "\t%lu %lu %lu %lu\n", 2044 stat->rxints, stat->txints, stat->exints, stat->spints); 2045 seq_printf(seq, "\t%lu %lu %d / %lu %lu %d / %d %d\n", 2046 stat->rxframes, stat->rxerrs, stat->rx_over, 2047 stat->txframes, stat->txerrs, stat->tx_under, 2048 stat->nospace, stat->tx_state); 2049 2050#define K(x) kiss->x 2051 seq_printf(seq, "\t%d %d %d %d %d %d %d %d %d %d %d %d\n", 2052 K(txdelay), K(persist), K(slottime), K(tailtime), 2053 K(fulldup), K(waittime), K(mintime), K(maxkeyup), 2054 K(idletime), K(maxdefer), K(tx_inhibit), K(group)); 2055#undef K 2056#ifdef SCC_DEBUG 2057 { 2058 int reg; 2059 2060 seq_printf(seq, "\tW "); 2061 for (reg = 0; reg < 16; reg++) 2062 seq_printf(seq, "%2.2x ", scc->wreg[reg]); 2063 seq_printf(seq, "\n"); 2064 2065 seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1)); 2066 for (reg = 3; reg < 8; reg++) 2067 seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg)); 2068 seq_printf(seq, "XX "); 2069 for (reg = 9; reg < 16; reg++) 2070 seq_printf(seq, "%2.2x ", InReg(scc->ctrl, reg)); 2071 seq_printf(seq, "\n"); 2072 } 2073#endif 2074 seq_putc(seq, '\n'); 2075 } 2076 2077 return 0; 2078} 2079 2080static const struct seq_operations scc_net_seq_ops = { 2081 .start = scc_net_seq_start, 2082 .next = scc_net_seq_next, 2083 .stop = scc_net_seq_stop, 2084 .show = scc_net_seq_show, 2085}; 2086 2087 2088static int scc_net_seq_open(struct inode *inode, struct file *file) 2089{ 2090 return seq_open(file, &scc_net_seq_ops); 2091} 2092 2093static const struct file_operations scc_net_seq_fops = { 2094 .owner = THIS_MODULE, 2095 .open = scc_net_seq_open, 2096 .read = seq_read, 2097 .llseek = seq_lseek, 2098 .release = seq_release_private, 2099}; 2100 2101#endif /* CONFIG_PROC_FS */ 2102 2103 2104/* ******************************************************************** */ 2105/* * Init SCC driver * */ 2106/* ******************************************************************** */ 2107 2108static int __init scc_init_driver (void) 2109{ 2110 char devname[IFNAMSIZ]; 2111 2112 printk(banner); 2113 2114 sprintf(devname,"%s0", SCC_DriverName); 2115 2116 rtnl_lock(); 2117 if (scc_net_alloc(devname, SCC_Info)) { 2118 rtnl_unlock(); 2119 printk(KERN_ERR "z8530drv: cannot initialize module\n"); 2120 return -EIO; 2121 } 2122 rtnl_unlock(); 2123 2124 proc_create("z8530drv", 0, init_net.proc_net, &scc_net_seq_fops); 2125 2126 return 0; 2127} 2128 2129static void __exit scc_cleanup_driver(void) 2130{ 2131 io_port ctrl; 2132 int k; 2133 struct scc_channel *scc; 2134 struct net_device *dev; 2135 2136 if (Nchips == 0 && (dev = SCC_Info[0].dev)) 2137 { 2138 unregister_netdev(dev); 2139 free_netdev(dev); 2140 } 2141 2142 /* Guard against chip prattle */ 2143 local_irq_disable(); 2144 2145 for (k = 0; k < Nchips; k++) 2146 if ( (ctrl = SCC_ctrl[k].chan_A) ) 2147 { 2148 Outb(ctrl, 0); 2149 OutReg(ctrl,R9,FHWRES); /* force hardware reset */ 2150 udelay(50); 2151 } 2152 2153 /* To unload the port must be closed so no real IRQ pending */ 2154 for (k = 0; k < nr_irqs ; k++) 2155 if (Ivec[k].used) free_irq(k, NULL); 2156 2157 local_irq_enable(); 2158 2159 /* Now clean up */ 2160 for (k = 0; k < Nchips*2; k++) 2161 { 2162 scc = &SCC_Info[k]; 2163 if (scc->ctrl) 2164 { 2165 release_region(scc->ctrl, 1); 2166 release_region(scc->data, 1); 2167 } 2168 if (scc->dev) 2169 { 2170 unregister_netdev(scc->dev); 2171 free_netdev(scc->dev); 2172 } 2173 } 2174 2175 2176 if (Vector_Latch) 2177 release_region(Vector_Latch, 1); 2178 2179 remove_proc_entry("z8530drv", init_net.proc_net); 2180} 2181 2182MODULE_AUTHOR("Joerg Reuter <jreuter@yaina.de>"); 2183MODULE_DESCRIPTION("AX.25 Device Driver for Z8530 based HDLC cards"); 2184MODULE_SUPPORTED_DEVICE("Z8530 based SCC cards for Amateur Radio"); 2185MODULE_LICENSE("GPL"); 2186module_init(scc_init_driver); 2187module_exit(scc_cleanup_driver); 2188