1/** 2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com 5 * 6 * Authors: Felipe Balbi <balbi@ti.com>, 7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de> 8 * 9 * This program is free software: you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 of 11 * the License as published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19#include <linux/kernel.h> 20#include <linux/slab.h> 21#include <linux/spinlock.h> 22#include <linux/platform_device.h> 23#include <linux/pm_runtime.h> 24#include <linux/interrupt.h> 25#include <linux/io.h> 26#include <linux/list.h> 27#include <linux/dma-mapping.h> 28 29#include <linux/usb/ch9.h> 30#include <linux/usb/gadget.h> 31#include <linux/usb/composite.h> 32 33#include "core.h" 34#include "debug.h" 35#include "gadget.h" 36#include "io.h" 37 38static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep); 39static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 40 struct dwc3_ep *dep, struct dwc3_request *req); 41 42static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state) 43{ 44 switch (state) { 45 case EP0_UNCONNECTED: 46 return "Unconnected"; 47 case EP0_SETUP_PHASE: 48 return "Setup Phase"; 49 case EP0_DATA_PHASE: 50 return "Data Phase"; 51 case EP0_STATUS_PHASE: 52 return "Status Phase"; 53 default: 54 return "UNKNOWN"; 55 } 56} 57 58static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, 59 u32 len, u32 type) 60{ 61 struct dwc3_gadget_ep_cmd_params params; 62 struct dwc3_trb *trb; 63 struct dwc3_ep *dep; 64 65 int ret; 66 67 dep = dwc->eps[epnum]; 68 if (dep->flags & DWC3_EP_BUSY) { 69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name); 70 return 0; 71 } 72 73 trb = dwc->ep0_trb; 74 75 trb->bpl = lower_32_bits(buf_dma); 76 trb->bph = upper_32_bits(buf_dma); 77 trb->size = len; 78 trb->ctrl = type; 79 80 trb->ctrl |= (DWC3_TRB_CTRL_HWO 81 | DWC3_TRB_CTRL_LST 82 | DWC3_TRB_CTRL_IOC 83 | DWC3_TRB_CTRL_ISP_IMI); 84 85 memset(¶ms, 0, sizeof(params)); 86 params.param0 = upper_32_bits(dwc->ep0_trb_addr); 87 params.param1 = lower_32_bits(dwc->ep0_trb_addr); 88 89 trace_dwc3_prepare_trb(dep, trb); 90 91 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, 92 DWC3_DEPCMD_STARTTRANSFER, ¶ms); 93 if (ret < 0) { 94 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed", 95 dep->name); 96 return ret; 97 } 98 99 dep->flags |= DWC3_EP_BUSY; 100 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc, 101 dep->number); 102 103 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 104 105 return 0; 106} 107 108static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep, 109 struct dwc3_request *req) 110{ 111 struct dwc3 *dwc = dep->dwc; 112 113 req->request.actual = 0; 114 req->request.status = -EINPROGRESS; 115 req->epnum = dep->number; 116 117 list_add_tail(&req->list, &dep->request_list); 118 119 /* 120 * Gadget driver might not be quick enough to queue a request 121 * before we get a Transfer Not Ready event on this endpoint. 122 * 123 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that 124 * flag is set, it's telling us that as soon as Gadget queues the 125 * required request, we should kick the transfer here because the 126 * IRQ we were waiting for is long gone. 127 */ 128 if (dep->flags & DWC3_EP_PENDING_REQUEST) { 129 unsigned direction; 130 131 direction = !!(dep->flags & DWC3_EP0_DIR_IN); 132 133 if (dwc->ep0state != EP0_DATA_PHASE) { 134 dev_WARN(dwc->dev, "Unexpected pending request\n"); 135 return 0; 136 } 137 138 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 139 140 dep->flags &= ~(DWC3_EP_PENDING_REQUEST | 141 DWC3_EP0_DIR_IN); 142 143 return 0; 144 } 145 146 /* 147 * In case gadget driver asked us to delay the STATUS phase, 148 * handle it here. 149 */ 150 if (dwc->delayed_status) { 151 unsigned direction; 152 153 direction = !dwc->ep0_expect_in; 154 dwc->delayed_status = false; 155 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); 156 157 if (dwc->ep0state == EP0_STATUS_PHASE) 158 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]); 159 else 160 dwc3_trace(trace_dwc3_ep0, 161 "too early for delayed status"); 162 163 return 0; 164 } 165 166 /* 167 * Unfortunately we have uncovered a limitation wrt the Data Phase. 168 * 169 * Section 9.4 says we can wait for the XferNotReady(DATA) event to 170 * come before issueing Start Transfer command, but if we do, we will 171 * miss situations where the host starts another SETUP phase instead of 172 * the DATA phase. Such cases happen at least on TD.7.6 of the Link 173 * Layer Compliance Suite. 174 * 175 * The problem surfaces due to the fact that in case of back-to-back 176 * SETUP packets there will be no XferNotReady(DATA) generated and we 177 * will be stuck waiting for XferNotReady(DATA) forever. 178 * 179 * By looking at tables 9-13 and 9-14 of the Databook, we can see that 180 * it tells us to start Data Phase right away. It also mentions that if 181 * we receive a SETUP phase instead of the DATA phase, core will issue 182 * XferComplete for the DATA phase, before actually initiating it in 183 * the wire, with the TRB's status set to "SETUP_PENDING". Such status 184 * can only be used to print some debugging logs, as the core expects 185 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB, 186 * just so it completes right away, without transferring anything and, 187 * only then, we can go back to the SETUP phase. 188 * 189 * Because of this scenario, SNPS decided to change the programming 190 * model of control transfers and support on-demand transfers only for 191 * the STATUS phase. To fix the issue we have now, we will always wait 192 * for gadget driver to queue the DATA phase's struct usb_request, then 193 * start it right away. 194 * 195 * If we're actually in a 2-stage transfer, we will wait for 196 * XferNotReady(STATUS). 197 */ 198 if (dwc->three_stage_setup) { 199 unsigned direction; 200 201 direction = dwc->ep0_expect_in; 202 dwc->ep0state = EP0_DATA_PHASE; 203 204 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req); 205 206 dep->flags &= ~DWC3_EP0_DIR_IN; 207 } 208 209 return 0; 210} 211 212int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request, 213 gfp_t gfp_flags) 214{ 215 struct dwc3_request *req = to_dwc3_request(request); 216 struct dwc3_ep *dep = to_dwc3_ep(ep); 217 struct dwc3 *dwc = dep->dwc; 218 219 unsigned long flags; 220 221 int ret; 222 223 spin_lock_irqsave(&dwc->lock, flags); 224 if (!dep->endpoint.desc) { 225 dwc3_trace(trace_dwc3_ep0, 226 "trying to queue request %p to disabled %s", 227 request, dep->name); 228 ret = -ESHUTDOWN; 229 goto out; 230 } 231 232 /* we share one TRB for ep0/1 */ 233 if (!list_empty(&dep->request_list)) { 234 ret = -EBUSY; 235 goto out; 236 } 237 238 dwc3_trace(trace_dwc3_ep0, 239 "queueing request %p to %s length %d state '%s'", 240 request, dep->name, request->length, 241 dwc3_ep0_state_string(dwc->ep0state)); 242 243 ret = __dwc3_gadget_ep0_queue(dep, req); 244 245out: 246 spin_unlock_irqrestore(&dwc->lock, flags); 247 248 return ret; 249} 250 251static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) 252{ 253 struct dwc3_ep *dep; 254 255 /* reinitialize physical ep1 */ 256 dep = dwc->eps[1]; 257 dep->flags = DWC3_EP_ENABLED; 258 259 /* stall is always issued on EP0 */ 260 dep = dwc->eps[0]; 261 __dwc3_gadget_ep_set_halt(dep, 1, false); 262 dep->flags = DWC3_EP_ENABLED; 263 dwc->delayed_status = false; 264 265 if (!list_empty(&dep->request_list)) { 266 struct dwc3_request *req; 267 268 req = next_request(&dep->request_list); 269 dwc3_gadget_giveback(dep, req, -ECONNRESET); 270 } 271 272 dwc->ep0state = EP0_SETUP_PHASE; 273 dwc3_ep0_out_start(dwc); 274} 275 276int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 277{ 278 struct dwc3_ep *dep = to_dwc3_ep(ep); 279 struct dwc3 *dwc = dep->dwc; 280 281 dwc3_ep0_stall_and_restart(dwc); 282 283 return 0; 284} 285 286int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value) 287{ 288 struct dwc3_ep *dep = to_dwc3_ep(ep); 289 struct dwc3 *dwc = dep->dwc; 290 unsigned long flags; 291 int ret; 292 293 spin_lock_irqsave(&dwc->lock, flags); 294 ret = __dwc3_gadget_ep0_set_halt(ep, value); 295 spin_unlock_irqrestore(&dwc->lock, flags); 296 297 return ret; 298} 299 300void dwc3_ep0_out_start(struct dwc3 *dwc) 301{ 302 int ret; 303 304 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, 305 DWC3_TRBCTL_CONTROL_SETUP); 306 WARN_ON(ret < 0); 307} 308 309static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le) 310{ 311 struct dwc3_ep *dep; 312 u32 windex = le16_to_cpu(wIndex_le); 313 u32 epnum; 314 315 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1; 316 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) 317 epnum |= 1; 318 319 dep = dwc->eps[epnum]; 320 if (dep->flags & DWC3_EP_ENABLED) 321 return dep; 322 323 return NULL; 324} 325 326static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req) 327{ 328} 329/* 330 * ch 9.4.5 331 */ 332static int dwc3_ep0_handle_status(struct dwc3 *dwc, 333 struct usb_ctrlrequest *ctrl) 334{ 335 struct dwc3_ep *dep; 336 u32 recip; 337 u32 reg; 338 u16 usb_status = 0; 339 __le16 *response_pkt; 340 341 recip = ctrl->bRequestType & USB_RECIP_MASK; 342 switch (recip) { 343 case USB_RECIP_DEVICE: 344 /* 345 * LTM will be set once we know how to set this in HW. 346 */ 347 usb_status |= dwc->gadget.is_selfpowered; 348 349 if (dwc->speed == DWC3_DSTS_SUPERSPEED) { 350 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 351 if (reg & DWC3_DCTL_INITU1ENA) 352 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED; 353 if (reg & DWC3_DCTL_INITU2ENA) 354 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED; 355 } 356 357 break; 358 359 case USB_RECIP_INTERFACE: 360 /* 361 * Function Remote Wake Capable D0 362 * Function Remote Wakeup D1 363 */ 364 break; 365 366 case USB_RECIP_ENDPOINT: 367 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex); 368 if (!dep) 369 return -EINVAL; 370 371 if (dep->flags & DWC3_EP_STALL) 372 usb_status = 1 << USB_ENDPOINT_HALT; 373 break; 374 default: 375 return -EINVAL; 376 } 377 378 response_pkt = (__le16 *) dwc->setup_buf; 379 *response_pkt = cpu_to_le16(usb_status); 380 381 dep = dwc->eps[0]; 382 dwc->ep0_usb_req.dep = dep; 383 dwc->ep0_usb_req.request.length = sizeof(*response_pkt); 384 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 385 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl; 386 387 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 388} 389 390static int dwc3_ep0_handle_feature(struct dwc3 *dwc, 391 struct usb_ctrlrequest *ctrl, int set) 392{ 393 struct dwc3_ep *dep; 394 u32 recip; 395 u32 wValue; 396 u32 wIndex; 397 u32 reg; 398 int ret; 399 enum usb_device_state state; 400 401 wValue = le16_to_cpu(ctrl->wValue); 402 wIndex = le16_to_cpu(ctrl->wIndex); 403 recip = ctrl->bRequestType & USB_RECIP_MASK; 404 state = dwc->gadget.state; 405 406 switch (recip) { 407 case USB_RECIP_DEVICE: 408 409 switch (wValue) { 410 case USB_DEVICE_REMOTE_WAKEUP: 411 break; 412 /* 413 * 9.4.1 says only only for SS, in AddressState only for 414 * default control pipe 415 */ 416 case USB_DEVICE_U1_ENABLE: 417 if (state != USB_STATE_CONFIGURED) 418 return -EINVAL; 419 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 420 return -EINVAL; 421 422 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 423 if (set) 424 reg |= DWC3_DCTL_INITU1ENA; 425 else 426 reg &= ~DWC3_DCTL_INITU1ENA; 427 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 428 break; 429 430 case USB_DEVICE_U2_ENABLE: 431 if (state != USB_STATE_CONFIGURED) 432 return -EINVAL; 433 if (dwc->speed != DWC3_DSTS_SUPERSPEED) 434 return -EINVAL; 435 436 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 437 if (set) 438 reg |= DWC3_DCTL_INITU2ENA; 439 else 440 reg &= ~DWC3_DCTL_INITU2ENA; 441 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 442 break; 443 444 case USB_DEVICE_LTM_ENABLE: 445 return -EINVAL; 446 447 case USB_DEVICE_TEST_MODE: 448 if ((wIndex & 0xff) != 0) 449 return -EINVAL; 450 if (!set) 451 return -EINVAL; 452 453 dwc->test_mode_nr = wIndex >> 8; 454 dwc->test_mode = true; 455 break; 456 default: 457 return -EINVAL; 458 } 459 break; 460 461 case USB_RECIP_INTERFACE: 462 switch (wValue) { 463 case USB_INTRF_FUNC_SUSPEND: 464 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP) 465 /* XXX enable Low power suspend */ 466 ; 467 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW) 468 /* XXX enable remote wakeup */ 469 ; 470 break; 471 default: 472 return -EINVAL; 473 } 474 break; 475 476 case USB_RECIP_ENDPOINT: 477 switch (wValue) { 478 case USB_ENDPOINT_HALT: 479 dep = dwc3_wIndex_to_dep(dwc, wIndex); 480 if (!dep) 481 return -EINVAL; 482 if (set == 0 && (dep->flags & DWC3_EP_WEDGE)) 483 break; 484 ret = __dwc3_gadget_ep_set_halt(dep, set, true); 485 if (ret) 486 return -EINVAL; 487 break; 488 default: 489 return -EINVAL; 490 } 491 break; 492 493 default: 494 return -EINVAL; 495 } 496 497 return 0; 498} 499 500static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 501{ 502 enum usb_device_state state = dwc->gadget.state; 503 u32 addr; 504 u32 reg; 505 506 addr = le16_to_cpu(ctrl->wValue); 507 if (addr > 127) { 508 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr); 509 return -EINVAL; 510 } 511 512 if (state == USB_STATE_CONFIGURED) { 513 dwc3_trace(trace_dwc3_ep0, 514 "trying to set address when configured"); 515 return -EINVAL; 516 } 517 518 reg = dwc3_readl(dwc->regs, DWC3_DCFG); 519 reg &= ~(DWC3_DCFG_DEVADDR_MASK); 520 reg |= DWC3_DCFG_DEVADDR(addr); 521 dwc3_writel(dwc->regs, DWC3_DCFG, reg); 522 523 if (addr) 524 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS); 525 else 526 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT); 527 528 return 0; 529} 530 531static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 532{ 533 int ret; 534 535 spin_unlock(&dwc->lock); 536 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl); 537 spin_lock(&dwc->lock); 538 return ret; 539} 540 541static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 542{ 543 enum usb_device_state state = dwc->gadget.state; 544 u32 cfg; 545 int ret; 546 u32 reg; 547 548 cfg = le16_to_cpu(ctrl->wValue); 549 550 switch (state) { 551 case USB_STATE_DEFAULT: 552 return -EINVAL; 553 554 case USB_STATE_ADDRESS: 555 ret = dwc3_ep0_delegate_req(dwc, ctrl); 556 /* if the cfg matches and the cfg is non zero */ 557 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) { 558 559 /* 560 * only change state if set_config has already 561 * been processed. If gadget driver returns 562 * USB_GADGET_DELAYED_STATUS, we will wait 563 * to change the state on the next usb_ep_queue() 564 */ 565 if (ret == 0) 566 usb_gadget_set_state(&dwc->gadget, 567 USB_STATE_CONFIGURED); 568 569 /* 570 * Enable transition to U1/U2 state when 571 * nothing is pending from application. 572 */ 573 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 574 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); 575 dwc3_writel(dwc->regs, DWC3_DCTL, reg); 576 577 dwc->resize_fifos = true; 578 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET"); 579 } 580 break; 581 582 case USB_STATE_CONFIGURED: 583 ret = dwc3_ep0_delegate_req(dwc, ctrl); 584 if (!cfg && !ret) 585 usb_gadget_set_state(&dwc->gadget, 586 USB_STATE_ADDRESS); 587 break; 588 default: 589 ret = -EINVAL; 590 } 591 return ret; 592} 593 594static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req) 595{ 596 struct dwc3_ep *dep = to_dwc3_ep(ep); 597 struct dwc3 *dwc = dep->dwc; 598 599 u32 param = 0; 600 u32 reg; 601 602 struct timing { 603 u8 u1sel; 604 u8 u1pel; 605 u16 u2sel; 606 u16 u2pel; 607 } __packed timing; 608 609 int ret; 610 611 memcpy(&timing, req->buf, sizeof(timing)); 612 613 dwc->u1sel = timing.u1sel; 614 dwc->u1pel = timing.u1pel; 615 dwc->u2sel = le16_to_cpu(timing.u2sel); 616 dwc->u2pel = le16_to_cpu(timing.u2pel); 617 618 reg = dwc3_readl(dwc->regs, DWC3_DCTL); 619 if (reg & DWC3_DCTL_INITU2ENA) 620 param = dwc->u2pel; 621 if (reg & DWC3_DCTL_INITU1ENA) 622 param = dwc->u1pel; 623 624 /* 625 * According to Synopsys Databook, if parameter is 626 * greater than 125, a value of zero should be 627 * programmed in the register. 628 */ 629 if (param > 125) 630 param = 0; 631 632 /* now that we have the time, issue DGCMD Set Sel */ 633 ret = dwc3_send_gadget_generic_command(dwc, 634 DWC3_DGCMD_SET_PERIODIC_PAR, param); 635 WARN_ON(ret < 0); 636} 637 638static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 639{ 640 struct dwc3_ep *dep; 641 enum usb_device_state state = dwc->gadget.state; 642 u16 wLength; 643 u16 wValue; 644 645 if (state == USB_STATE_DEFAULT) 646 return -EINVAL; 647 648 wValue = le16_to_cpu(ctrl->wValue); 649 wLength = le16_to_cpu(ctrl->wLength); 650 651 if (wLength != 6) { 652 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n", 653 wLength); 654 return -EINVAL; 655 } 656 657 /* 658 * To handle Set SEL we need to receive 6 bytes from Host. So let's 659 * queue a usb_request for 6 bytes. 660 * 661 * Remember, though, this controller can't handle non-wMaxPacketSize 662 * aligned transfers on the OUT direction, so we queue a request for 663 * wMaxPacketSize instead. 664 */ 665 dep = dwc->eps[0]; 666 dwc->ep0_usb_req.dep = dep; 667 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket; 668 dwc->ep0_usb_req.request.buf = dwc->setup_buf; 669 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl; 670 671 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req); 672} 673 674static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 675{ 676 u16 wLength; 677 u16 wValue; 678 u16 wIndex; 679 680 wValue = le16_to_cpu(ctrl->wValue); 681 wLength = le16_to_cpu(ctrl->wLength); 682 wIndex = le16_to_cpu(ctrl->wIndex); 683 684 if (wIndex || wLength) 685 return -EINVAL; 686 687 /* 688 * REVISIT It's unclear from Databook what to do with this 689 * value. For now, just cache it. 690 */ 691 dwc->isoch_delay = wValue; 692 693 return 0; 694} 695 696static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) 697{ 698 int ret; 699 700 switch (ctrl->bRequest) { 701 case USB_REQ_GET_STATUS: 702 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS"); 703 ret = dwc3_ep0_handle_status(dwc, ctrl); 704 break; 705 case USB_REQ_CLEAR_FEATURE: 706 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE"); 707 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0); 708 break; 709 case USB_REQ_SET_FEATURE: 710 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE"); 711 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1); 712 break; 713 case USB_REQ_SET_ADDRESS: 714 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS"); 715 ret = dwc3_ep0_set_address(dwc, ctrl); 716 break; 717 case USB_REQ_SET_CONFIGURATION: 718 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION"); 719 ret = dwc3_ep0_set_config(dwc, ctrl); 720 break; 721 case USB_REQ_SET_SEL: 722 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL"); 723 ret = dwc3_ep0_set_sel(dwc, ctrl); 724 break; 725 case USB_REQ_SET_ISOCH_DELAY: 726 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY"); 727 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl); 728 break; 729 default: 730 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver"); 731 ret = dwc3_ep0_delegate_req(dwc, ctrl); 732 break; 733 } 734 735 return ret; 736} 737 738static void dwc3_ep0_inspect_setup(struct dwc3 *dwc, 739 const struct dwc3_event_depevt *event) 740{ 741 struct usb_ctrlrequest *ctrl = dwc->ctrl_req; 742 int ret = -EINVAL; 743 u32 len; 744 745 if (!dwc->gadget_driver) 746 goto out; 747 748 trace_dwc3_ctrl_req(ctrl); 749 750 len = le16_to_cpu(ctrl->wLength); 751 if (!len) { 752 dwc->three_stage_setup = false; 753 dwc->ep0_expect_in = false; 754 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 755 } else { 756 dwc->three_stage_setup = true; 757 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN); 758 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA; 759 } 760 761 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) 762 ret = dwc3_ep0_std_request(dwc, ctrl); 763 else 764 ret = dwc3_ep0_delegate_req(dwc, ctrl); 765 766 if (ret == USB_GADGET_DELAYED_STATUS) 767 dwc->delayed_status = true; 768 769out: 770 if (ret < 0) 771 dwc3_ep0_stall_and_restart(dwc); 772} 773 774static void dwc3_ep0_complete_data(struct dwc3 *dwc, 775 const struct dwc3_event_depevt *event) 776{ 777 struct dwc3_request *r = NULL; 778 struct usb_request *ur; 779 struct dwc3_trb *trb; 780 struct dwc3_ep *ep0; 781 u32 transferred; 782 u32 status; 783 u32 length; 784 u8 epnum; 785 786 epnum = event->endpoint_number; 787 ep0 = dwc->eps[0]; 788 789 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS; 790 791 trb = dwc->ep0_trb; 792 793 trace_dwc3_complete_trb(ep0, trb); 794 795 r = next_request(&ep0->request_list); 796 if (!r) 797 return; 798 799 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 800 if (status == DWC3_TRBSTS_SETUP_PENDING) { 801 dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); 802 803 if (r) 804 dwc3_gadget_giveback(ep0, r, -ECONNRESET); 805 806 return; 807 } 808 809 ur = &r->request; 810 811 length = trb->size & DWC3_TRB_SIZE_MASK; 812 813 if (dwc->ep0_bounced) { 814 unsigned transfer_size = ur->length; 815 unsigned maxp = ep0->endpoint.maxpacket; 816 817 transfer_size += (maxp - (transfer_size % maxp)); 818 819 /* Maximum of DWC3_EP0_BOUNCE_SIZE can only be received */ 820 if (transfer_size > DWC3_EP0_BOUNCE_SIZE) 821 transfer_size = DWC3_EP0_BOUNCE_SIZE; 822 823 transferred = min_t(u32, ur->length, 824 transfer_size - length); 825 memcpy(ur->buf, dwc->ep0_bounce, transferred); 826 } else { 827 transferred = ur->length - length; 828 } 829 830 ur->actual += transferred; 831 832 if ((epnum & 1) && ur->actual < ur->length) { 833 /* for some reason we did not get everything out */ 834 835 dwc3_ep0_stall_and_restart(dwc); 836 } else { 837 dwc3_gadget_giveback(ep0, r, 0); 838 839 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) && 840 ur->length && ur->zero) { 841 int ret; 842 843 dwc->ep0_next_event = DWC3_EP0_COMPLETE; 844 845 ret = dwc3_ep0_start_trans(dwc, epnum, 846 dwc->ctrl_req_addr, 0, 847 DWC3_TRBCTL_CONTROL_DATA); 848 WARN_ON(ret < 0); 849 } 850 } 851} 852 853static void dwc3_ep0_complete_status(struct dwc3 *dwc, 854 const struct dwc3_event_depevt *event) 855{ 856 struct dwc3_request *r; 857 struct dwc3_ep *dep; 858 struct dwc3_trb *trb; 859 u32 status; 860 861 dep = dwc->eps[0]; 862 trb = dwc->ep0_trb; 863 864 trace_dwc3_complete_trb(dep, trb); 865 866 if (!list_empty(&dep->request_list)) { 867 r = next_request(&dep->request_list); 868 869 dwc3_gadget_giveback(dep, r, 0); 870 } 871 872 if (dwc->test_mode) { 873 int ret; 874 875 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr); 876 if (ret < 0) { 877 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d", 878 dwc->test_mode_nr); 879 dwc3_ep0_stall_and_restart(dwc); 880 return; 881 } 882 } 883 884 status = DWC3_TRB_SIZE_TRBSTS(trb->size); 885 if (status == DWC3_TRBSTS_SETUP_PENDING) 886 dwc3_trace(trace_dwc3_ep0, "Setup Pending received"); 887 888 dwc->ep0state = EP0_SETUP_PHASE; 889 dwc3_ep0_out_start(dwc); 890} 891 892static void dwc3_ep0_xfer_complete(struct dwc3 *dwc, 893 const struct dwc3_event_depevt *event) 894{ 895 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 896 897 dep->flags &= ~DWC3_EP_BUSY; 898 dep->resource_index = 0; 899 dwc->setup_packet_pending = false; 900 901 switch (dwc->ep0state) { 902 case EP0_SETUP_PHASE: 903 dwc3_trace(trace_dwc3_ep0, "Setup Phase"); 904 dwc3_ep0_inspect_setup(dwc, event); 905 break; 906 907 case EP0_DATA_PHASE: 908 dwc3_trace(trace_dwc3_ep0, "Data Phase"); 909 dwc3_ep0_complete_data(dwc, event); 910 break; 911 912 case EP0_STATUS_PHASE: 913 dwc3_trace(trace_dwc3_ep0, "Status Phase"); 914 dwc3_ep0_complete_status(dwc, event); 915 break; 916 default: 917 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state); 918 } 919} 920 921static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, 922 struct dwc3_ep *dep, struct dwc3_request *req) 923{ 924 int ret; 925 926 req->direction = !!dep->number; 927 928 if (req->request.length == 0) { 929 ret = dwc3_ep0_start_trans(dwc, dep->number, 930 dwc->ctrl_req_addr, 0, 931 DWC3_TRBCTL_CONTROL_DATA); 932 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) 933 && (dep->number == 0)) { 934 u32 transfer_size; 935 u32 maxpacket; 936 937 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 938 dep->number); 939 if (ret) { 940 dev_dbg(dwc->dev, "failed to map request\n"); 941 return; 942 } 943 944 maxpacket = dep->endpoint.maxpacket; 945 transfer_size = roundup(req->request.length, maxpacket); 946 947 if (transfer_size > DWC3_EP0_BOUNCE_SIZE) { 948 dev_WARN(dwc->dev, "bounce buf can't handle req len\n"); 949 transfer_size = DWC3_EP0_BOUNCE_SIZE; 950 } 951 952 dwc->ep0_bounced = true; 953 954 /* 955 * REVISIT in case request length is bigger than 956 * DWC3_EP0_BOUNCE_SIZE we will need two chained 957 * TRBs to handle the transfer. 958 */ 959 ret = dwc3_ep0_start_trans(dwc, dep->number, 960 dwc->ep0_bounce_addr, transfer_size, 961 DWC3_TRBCTL_CONTROL_DATA); 962 } else { 963 ret = usb_gadget_map_request(&dwc->gadget, &req->request, 964 dep->number); 965 if (ret) { 966 dev_dbg(dwc->dev, "failed to map request\n"); 967 return; 968 } 969 970 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, 971 req->request.length, DWC3_TRBCTL_CONTROL_DATA); 972 } 973 974 WARN_ON(ret < 0); 975} 976 977static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) 978{ 979 struct dwc3 *dwc = dep->dwc; 980 u32 type; 981 982 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 983 : DWC3_TRBCTL_CONTROL_STATUS2; 984 985 return dwc3_ep0_start_trans(dwc, dep->number, 986 dwc->ctrl_req_addr, 0, type); 987} 988 989static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) 990{ 991 if (dwc->resize_fifos) { 992 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs"); 993 dwc3_gadget_resize_tx_fifos(dwc); 994 dwc->resize_fifos = 0; 995 } 996 997 WARN_ON(dwc3_ep0_start_control_status(dep)); 998} 999 1000static void dwc3_ep0_do_control_status(struct dwc3 *dwc, 1001 const struct dwc3_event_depevt *event) 1002{ 1003 struct dwc3_ep *dep = dwc->eps[event->endpoint_number]; 1004 1005 __dwc3_ep0_do_control_status(dwc, dep); 1006} 1007 1008static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep) 1009{ 1010 struct dwc3_gadget_ep_cmd_params params; 1011 u32 cmd; 1012 int ret; 1013 1014 if (!dep->resource_index) 1015 return; 1016 1017 cmd = DWC3_DEPCMD_ENDTRANSFER; 1018 cmd |= DWC3_DEPCMD_CMDIOC; 1019 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index); 1020 memset(¶ms, 0, sizeof(params)); 1021 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms); 1022 WARN_ON_ONCE(ret); 1023 dep->resource_index = 0; 1024} 1025 1026static void dwc3_ep0_xfernotready(struct dwc3 *dwc, 1027 const struct dwc3_event_depevt *event) 1028{ 1029 dwc->setup_packet_pending = true; 1030 1031 switch (event->status) { 1032 case DEPEVT_STATUS_CONTROL_DATA: 1033 dwc3_trace(trace_dwc3_ep0, "Control Data"); 1034 1035 /* 1036 * We already have a DATA transfer in the controller's cache, 1037 * if we receive a XferNotReady(DATA) we will ignore it, unless 1038 * it's for the wrong direction. 1039 * 1040 * In that case, we must issue END_TRANSFER command to the Data 1041 * Phase we already have started and issue SetStall on the 1042 * control endpoint. 1043 */ 1044 if (dwc->ep0_expect_in != event->endpoint_number) { 1045 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in]; 1046 1047 dwc3_trace(trace_dwc3_ep0, 1048 "Wrong direction for Data phase"); 1049 dwc3_ep0_end_control_data(dwc, dep); 1050 dwc3_ep0_stall_and_restart(dwc); 1051 return; 1052 } 1053 1054 break; 1055 1056 case DEPEVT_STATUS_CONTROL_STATUS: 1057 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS) 1058 return; 1059 1060 dwc3_trace(trace_dwc3_ep0, "Control Status"); 1061 1062 dwc->ep0state = EP0_STATUS_PHASE; 1063 1064 if (dwc->delayed_status) { 1065 WARN_ON_ONCE(event->endpoint_number != 1); 1066 dwc3_trace(trace_dwc3_ep0, "Delayed Status"); 1067 return; 1068 } 1069 1070 dwc3_ep0_do_control_status(dwc, event); 1071 } 1072} 1073 1074void dwc3_ep0_interrupt(struct dwc3 *dwc, 1075 const struct dwc3_event_depevt *event) 1076{ 1077 u8 epnum = event->endpoint_number; 1078 1079 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'", 1080 dwc3_ep_event_string(event->endpoint_event), 1081 epnum >> 1, (epnum & 1) ? "in" : "out", 1082 dwc3_ep0_state_string(dwc->ep0state)); 1083 1084 switch (event->endpoint_event) { 1085 case DWC3_DEPEVT_XFERCOMPLETE: 1086 dwc3_ep0_xfer_complete(dwc, event); 1087 break; 1088 1089 case DWC3_DEPEVT_XFERNOTREADY: 1090 dwc3_ep0_xfernotready(dwc, event); 1091 break; 1092 1093 case DWC3_DEPEVT_XFERINPROGRESS: 1094 case DWC3_DEPEVT_RXTXFIFOEVT: 1095 case DWC3_DEPEVT_STREAMEVT: 1096 case DWC3_DEPEVT_EPCMDCMPLT: 1097 break; 1098 } 1099} 1100