Lines Matching refs:ctrl
145 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uqrx_full() local
152 pos = &ctrl->upos; in spdif_irq_uqrx_full()
157 pos = &ctrl->qpos; in spdif_irq_uqrx_full()
176 ctrl->subcode[*pos++] = val >> 16; in spdif_irq_uqrx_full()
177 ctrl->subcode[*pos++] = val >> 8; in spdif_irq_uqrx_full()
178 ctrl->subcode[*pos++] = val; in spdif_irq_uqrx_full()
184 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_sync() local
190 if (ctrl->qpos == 0) in spdif_irq_uq_sync()
194 ctrl->ready_buf = (ctrl->qpos - 1) / SPDIF_QSUB_SIZE + 1; in spdif_irq_uq_sync()
200 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_irq_uq_err() local
212 ctrl->ready_buf = 0; in spdif_irq_uq_err()
213 ctrl->upos = 0; in spdif_irq_uq_err()
214 ctrl->qpos = 0; in spdif_irq_uq_err()
319 static void spdif_set_cstatus(struct spdif_mixer_control *ctrl, in spdif_set_cstatus() argument
322 ctrl->ch_status[3] &= ~mask; in spdif_set_cstatus()
323 ctrl->ch_status[3] |= cstatus & mask; in spdif_set_cstatus()
328 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_write_channel_status() local
333 ch_status = (bitrev8(ctrl->ch_status[0]) << 16) | in spdif_write_channel_status()
334 (bitrev8(ctrl->ch_status[1]) << 8) | in spdif_write_channel_status()
335 bitrev8(ctrl->ch_status[2]); in spdif_write_channel_status()
340 ch_status = bitrev8(ctrl->ch_status[3]) << 16; in spdif_write_channel_status()
368 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in spdif_set_sample_rate() local
437 spdif_set_cstatus(ctrl, IEC958_AES3_CON_FS, csfs); in spdif_set_sample_rate()
546 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_hw_params() local
558 spdif_set_cstatus(ctrl, IEC958_AES3_CON_CLOCK, in fsl_spdif_hw_params()
631 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_get() local
633 uvalue->value.iec958.status[0] = ctrl->ch_status[0]; in fsl_spdif_pb_get()
634 uvalue->value.iec958.status[1] = ctrl->ch_status[1]; in fsl_spdif_pb_get()
635 uvalue->value.iec958.status[2] = ctrl->ch_status[2]; in fsl_spdif_pb_get()
636 uvalue->value.iec958.status[3] = ctrl->ch_status[3]; in fsl_spdif_pb_get()
646 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_pb_put() local
648 ctrl->ch_status[0] = uvalue->value.iec958.status[0]; in fsl_spdif_pb_put()
649 ctrl->ch_status[1] = uvalue->value.iec958.status[1]; in fsl_spdif_pb_put()
650 ctrl->ch_status[2] = uvalue->value.iec958.status[2]; in fsl_spdif_pb_put()
651 ctrl->ch_status[3] = uvalue->value.iec958.status[3]; in fsl_spdif_pb_put()
696 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_subcode_get() local
700 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
701 if (ctrl->ready_buf) { in fsl_spdif_subcode_get()
702 int idx = (ctrl->ready_buf - 1) * SPDIF_UBITS_SIZE; in fsl_spdif_subcode_get()
704 &ctrl->subcode[idx], SPDIF_UBITS_SIZE); in fsl_spdif_subcode_get()
707 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_subcode_get()
728 struct spdif_mixer_control *ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_qget() local
732 spin_lock_irqsave(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
733 if (ctrl->ready_buf) { in fsl_spdif_qget()
734 int idx = (ctrl->ready_buf - 1) * SPDIF_QSUB_SIZE; in fsl_spdif_qget()
736 &ctrl->qsub[idx], SPDIF_QSUB_SIZE); in fsl_spdif_qget()
739 spin_unlock_irqrestore(&ctrl->ctl_lock, flags); in fsl_spdif_qget()
1159 struct spdif_mixer_control *ctrl; in fsl_spdif_probe() local
1232 ctrl = &spdif_priv->fsl_spdif_control; in fsl_spdif_probe()
1233 spin_lock_init(&ctrl->ctl_lock); in fsl_spdif_probe()
1236 ctrl->ch_status[0] = IEC958_AES0_CON_NOT_COPYRIGHT | in fsl_spdif_probe()
1238 ctrl->ch_status[1] = IEC958_AES1_CON_DIGDIGCONV_ID; in fsl_spdif_probe()
1239 ctrl->ch_status[2] = 0x00; in fsl_spdif_probe()
1240 ctrl->ch_status[3] = IEC958_AES3_CON_FS_44100 | in fsl_spdif_probe()