125 		u32 ctrl;  member
127 	} ctrl;  member
278 	outl(hdlc->ctrl.ctrl, fc->addr + CHIP_WINDOW + HDLC_STATUS);  in __write_ctrl_pci()
283 	outl(hdlc->ctrl.ctrl, fc->addr + (channel == 2 ? AVM_HDLC_STATUS_2 :  in __write_ctrl_pciv2()
294 		 which, hdlc->ctrl.ctrl);  in write_ctrl()
358 	hdlc->ctrl.ctrl = 0;  in modehdlc()
367 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;  in modehdlc()
368 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS;  in modehdlc()
376 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;  in modehdlc()
377 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_TRANS;  in modehdlc()
379 		hdlc->ctrl.sr.cmd = HDLC_CMD_XRS;  in modehdlc()
381 		hdlc->ctrl.sr.cmd = 0;  in modehdlc()
386 		hdlc->ctrl.sr.cmd  = HDLC_CMD_XRS | HDLC_CMD_RRS;  in modehdlc()
387 		hdlc->ctrl.sr.mode = mode | HDLC_MODE_ITF_FLG;  in modehdlc()
389 		hdlc->ctrl.sr.cmd = HDLC_CMD_XRS;  in modehdlc()
391 		hdlc->ctrl.sr.cmd = 0;  in modehdlc()
473 	hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XME;  in hdlc_fill_fifo()
478 			hdlc->ctrl.sr.cmd |= HDLC_CMD_XME;  in hdlc_fill_fifo()
488 	hdlc->ctrl.sr.xml = ((count == fs) ? 0 : count);  in hdlc_fill_fifo()
556 			hdlc->ctrl.sr.xml = 0;  in HDLC_irq()
557 			hdlc->ctrl.sr.cmd |= HDLC_CMD_RRS;  in HDLC_irq()
559 			hdlc->ctrl.sr.cmd &= ~HDLC_CMD_RRS;  in HDLC_irq()
598 		hdlc->ctrl.sr.xml = 0;  in HDLC_irq()
599 		hdlc->ctrl.sr.cmd |= HDLC_CMD_XRS;  in HDLC_irq()
601 		hdlc->ctrl.sr.cmd &= ~HDLC_CMD_XRS;  in HDLC_irq()
894 		ret = fc->isac.ctrl(&fc->isac, HW_TESTLOOP, cq->channel);  in channel_ctrl()
897 		ret = fc->isac.ctrl(&fc->isac, HW_TIMER3_VALUE, cq->p1);  in channel_ctrl()
1057 	card->isac.dch.dev.D.ctrl = avm_dctrl;  in setup_instance()
1068 		card->bch[i].ch.ctrl = avm_bctrl;  in setup_instance()