62 #define ctrl_dbg(ctrl, format, arg...)					\  argument
65 			dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev,	\
68 #define ctrl_err(ctrl, format, arg...)					\  argument
69 	dev_err(&ctrl->pci_dev->dev, format, ## arg)
70 #define ctrl_info(ctrl, format, arg...)					\  argument
71 	dev_info(&ctrl->pci_dev->dev, format, ## arg)
72 #define ctrl_warn(ctrl, format, arg...)					\  argument
73 	dev_warn(&ctrl->pci_dev->dev, format, ## arg)
86 	struct controller *ctrl;  member
171 int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
172 void shpchp_remove_ctrl_files(struct controller *ctrl);
175 u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
176 u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
177 u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
178 u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
181 void cleanup_slots(struct controller *ctrl);
183 int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
239 static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)  in shpchp_find_slot()  argument
243 	list_for_each_entry(slot, &ctrl->slot_list, slot_list) {  in shpchp_find_slot()
248 	ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);  in shpchp_find_slot()
257 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);  in amd_pogo_errata_save_misc_reg()
259 	p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;  in amd_pogo_errata_save_misc_reg()
267 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);  in amd_pogo_errata_save_misc_reg()
279 …pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_r…  in amd_pogo_errata_restore_misc_reg()
282 		ctrl_dbg(p_slot->ctrl,  in amd_pogo_errata_restore_misc_reg()
286 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);  in amd_pogo_errata_restore_misc_reg()
290 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);  in amd_pogo_errata_restore_misc_reg()
293 		ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");  in amd_pogo_errata_restore_misc_reg()
295 		pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);  in amd_pogo_errata_restore_misc_reg()
298 	pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );  in amd_pogo_errata_restore_misc_reg()
300 	if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
305 	if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
310 	if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
315 	if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
320 	if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)  in amd_pogo_errata_restore_misc_reg()
324 	pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);  in amd_pogo_errata_restore_misc_reg()
344 	void (*release_ctlr)(struct controller *ctrl);
345 	int (*check_cmd_status)(struct controller *ctrl);