1/* 2 * 3 * Copyright (C) 2007 Google, Inc. 4 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved. 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17#include <linux/clocksource.h> 18#include <linux/clockchips.h> 19#include <linux/cpu.h> 20#include <linux/init.h> 21#include <linux/interrupt.h> 22#include <linux/irq.h> 23#include <linux/io.h> 24#include <linux/of.h> 25#include <linux/of_address.h> 26#include <linux/of_irq.h> 27#include <linux/sched_clock.h> 28 29#include <asm/delay.h> 30 31#define TIMER_MATCH_VAL 0x0000 32#define TIMER_COUNT_VAL 0x0004 33#define TIMER_ENABLE 0x0008 34#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1) 35#define TIMER_ENABLE_EN BIT(0) 36#define TIMER_CLEAR 0x000C 37#define DGT_CLK_CTL 0x10 38#define DGT_CLK_CTL_DIV_4 0x3 39#define TIMER_STS_GPT0_CLR_PEND BIT(10) 40 41#define GPT_HZ 32768 42 43#define MSM_DGT_SHIFT 5 44 45static void __iomem *event_base; 46static void __iomem *sts_base; 47 48static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) 49{ 50 struct clock_event_device *evt = dev_id; 51 /* Stop the timer tick */ 52 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) { 53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 54 ctrl &= ~TIMER_ENABLE_EN; 55 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 56 } 57 evt->event_handler(evt); 58 return IRQ_HANDLED; 59} 60 61static int msm_timer_set_next_event(unsigned long cycles, 62 struct clock_event_device *evt) 63{ 64 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 65 66 ctrl &= ~TIMER_ENABLE_EN; 67 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 68 69 writel_relaxed(ctrl, event_base + TIMER_CLEAR); 70 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL); 71 72 if (sts_base) 73 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND) 74 cpu_relax(); 75 76 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE); 77 return 0; 78} 79 80static void msm_timer_set_mode(enum clock_event_mode mode, 81 struct clock_event_device *evt) 82{ 83 u32 ctrl; 84 85 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 86 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN); 87 88 switch (mode) { 89 case CLOCK_EVT_MODE_RESUME: 90 case CLOCK_EVT_MODE_PERIODIC: 91 break; 92 case CLOCK_EVT_MODE_ONESHOT: 93 /* Timer is enabled in set_next_event */ 94 break; 95 case CLOCK_EVT_MODE_UNUSED: 96 case CLOCK_EVT_MODE_SHUTDOWN: 97 break; 98 } 99 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 100} 101 102static struct clock_event_device __percpu *msm_evt; 103 104static void __iomem *source_base; 105 106static notrace cycle_t msm_read_timer_count(struct clocksource *cs) 107{ 108 return readl_relaxed(source_base + TIMER_COUNT_VAL); 109} 110 111static struct clocksource msm_clocksource = { 112 .name = "dg_timer", 113 .rating = 300, 114 .read = msm_read_timer_count, 115 .mask = CLOCKSOURCE_MASK(32), 116 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 117}; 118 119static int msm_timer_irq; 120static int msm_timer_has_ppi; 121 122static int msm_local_timer_setup(struct clock_event_device *evt) 123{ 124 int cpu = smp_processor_id(); 125 int err; 126 127 evt->irq = msm_timer_irq; 128 evt->name = "msm_timer"; 129 evt->features = CLOCK_EVT_FEAT_ONESHOT; 130 evt->rating = 200; 131 evt->set_mode = msm_timer_set_mode; 132 evt->set_next_event = msm_timer_set_next_event; 133 evt->cpumask = cpumask_of(cpu); 134 135 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff); 136 137 if (msm_timer_has_ppi) { 138 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); 139 } else { 140 err = request_irq(evt->irq, msm_timer_interrupt, 141 IRQF_TIMER | IRQF_NOBALANCING | 142 IRQF_TRIGGER_RISING, "gp_timer", evt); 143 if (err) 144 pr_err("request_irq failed\n"); 145 } 146 147 return 0; 148} 149 150static void msm_local_timer_stop(struct clock_event_device *evt) 151{ 152 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 153 disable_percpu_irq(evt->irq); 154} 155 156static int msm_timer_cpu_notify(struct notifier_block *self, 157 unsigned long action, void *hcpu) 158{ 159 /* 160 * Grab cpu pointer in each case to avoid spurious 161 * preemptible warnings 162 */ 163 switch (action & ~CPU_TASKS_FROZEN) { 164 case CPU_STARTING: 165 msm_local_timer_setup(this_cpu_ptr(msm_evt)); 166 break; 167 case CPU_DYING: 168 msm_local_timer_stop(this_cpu_ptr(msm_evt)); 169 break; 170 } 171 172 return NOTIFY_OK; 173} 174 175static struct notifier_block msm_timer_cpu_nb = { 176 .notifier_call = msm_timer_cpu_notify, 177}; 178 179static u64 notrace msm_sched_clock_read(void) 180{ 181 return msm_clocksource.read(&msm_clocksource); 182} 183 184static unsigned long msm_read_current_timer(void) 185{ 186 return msm_clocksource.read(&msm_clocksource); 187} 188 189static struct delay_timer msm_delay_timer = { 190 .read_current_timer = msm_read_current_timer, 191}; 192 193static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, 194 bool percpu) 195{ 196 struct clocksource *cs = &msm_clocksource; 197 int res = 0; 198 199 msm_timer_irq = irq; 200 msm_timer_has_ppi = percpu; 201 202 msm_evt = alloc_percpu(struct clock_event_device); 203 if (!msm_evt) { 204 pr_err("memory allocation failed for clockevents\n"); 205 goto err; 206 } 207 208 if (percpu) 209 res = request_percpu_irq(irq, msm_timer_interrupt, 210 "gp_timer", msm_evt); 211 212 if (res) { 213 pr_err("request_percpu_irq failed\n"); 214 } else { 215 res = register_cpu_notifier(&msm_timer_cpu_nb); 216 if (res) { 217 free_percpu_irq(irq, msm_evt); 218 goto err; 219 } 220 221 /* Immediately configure the timer on the boot CPU */ 222 msm_local_timer_setup(raw_cpu_ptr(msm_evt)); 223 } 224 225err: 226 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); 227 res = clocksource_register_hz(cs, dgt_hz); 228 if (res) 229 pr_err("clocksource_register failed\n"); 230 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); 231 msm_delay_timer.freq = dgt_hz; 232 register_current_timer_delay(&msm_delay_timer); 233} 234 235#ifdef CONFIG_ARCH_QCOM 236static void __init msm_dt_timer_init(struct device_node *np) 237{ 238 u32 freq; 239 int irq; 240 struct resource res; 241 u32 percpu_offset; 242 void __iomem *base; 243 void __iomem *cpu0_base; 244 245 base = of_iomap(np, 0); 246 if (!base) { 247 pr_err("Failed to map event base\n"); 248 return; 249 } 250 251 /* We use GPT0 for the clockevent */ 252 irq = irq_of_parse_and_map(np, 1); 253 if (irq <= 0) { 254 pr_err("Can't get irq\n"); 255 return; 256 } 257 258 /* We use CPU0's DGT for the clocksource */ 259 if (of_property_read_u32(np, "cpu-offset", &percpu_offset)) 260 percpu_offset = 0; 261 262 if (of_address_to_resource(np, 0, &res)) { 263 pr_err("Failed to parse DGT resource\n"); 264 return; 265 } 266 267 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res)); 268 if (!cpu0_base) { 269 pr_err("Failed to map source base\n"); 270 return; 271 } 272 273 if (of_property_read_u32(np, "clock-frequency", &freq)) { 274 pr_err("Unknown frequency\n"); 275 return; 276 } 277 278 event_base = base + 0x4; 279 sts_base = base + 0x88; 280 source_base = cpu0_base + 0x24; 281 freq /= 4; 282 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL); 283 284 msm_timer_init(freq, 32, irq, !!percpu_offset); 285} 286CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); 287CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); 288#else 289 290static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, 291 u32 sts) 292{ 293 void __iomem *base; 294 295 base = ioremap(addr, SZ_256); 296 if (!base) { 297 pr_err("Failed to map timer base\n"); 298 return -ENOMEM; 299 } 300 event_base = base + event; 301 source_base = base + source; 302 if (sts) 303 sts_base = base + sts; 304 305 return 0; 306} 307 308static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs) 309{ 310 /* 311 * Shift timer count down by a constant due to unreliable lower bits 312 * on some targets. 313 */ 314 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT; 315} 316 317void __init msm7x01_timer_init(void) 318{ 319 struct clocksource *cs = &msm_clocksource; 320 321 if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0)) 322 return; 323 cs->read = msm_read_timer_count_shift; 324 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)); 325 /* 600 KHz */ 326 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7, 327 false); 328} 329 330void __init msm7x30_timer_init(void) 331{ 332 if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80)) 333 return; 334 msm_timer_init(24576000 / 4, 32, 1, false); 335} 336 337void __init qsd8x50_timer_init(void) 338{ 339 if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34)) 340 return; 341 msm_timer_init(19200000 / 4, 32, 7, false); 342} 343#endif 344