Searched refs:mask (Results 1 - 200 of 6530) sorted by relevance

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/linux-4.4.14/include/uapi/linux/
H A Dkernel.h10 #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask))
/linux-4.4.14/arch/tile/include/asm/
H A Dword-at-a-time.h14 unsigned long mask = __insn_v1cmpeqi(val, 0); has_zero() local
16 unsigned long mask = __insn_seqib(val, 0); has_zero()
18 *data = mask; has_zero()
19 return mask; has_zero()
27 static inline long find_zero(unsigned long mask) find_zero() argument
30 return __builtin_clzl(mask) >> 3; find_zero()
32 return __builtin_ctzl(mask) >> 3; find_zero()
37 #define zero_bytemask(mask) (~1ul << (63 - __builtin_clzl(mask)))
39 #define zero_bytemask(mask) ((2ul << __builtin_ctzl(mask)) - 1)
H A Dbitops_64.h25 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); set_bit() local
26 __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask); set_bit()
31 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); clear_bit() local
32 __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask); clear_bit()
37 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); change_bit() local
43 oldval = cmpxchg(addr, guess, guess ^ mask); change_bit()
58 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); test_and_set_bit() local
60 val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask) test_and_set_bit()
61 & mask) != 0; test_and_set_bit()
70 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); test_and_clear_bit() local
72 val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask) test_and_clear_bit()
73 & mask) != 0; test_and_clear_bit()
82 unsigned long mask = (1UL << (nr % BITS_PER_LONG)); test_and_change_bit() local
88 oldval = cmpxchg(addr, guess, guess ^ mask); test_and_change_bit()
90 return (oldval & mask) != 0; test_and_change_bit()
/linux-4.4.14/include/uapi/linux/iio/
H A Devents.h28 #define IIO_EVENT_CODE_EXTRACT_TYPE(mask) ((mask >> 56) & 0xFF)
30 #define IIO_EVENT_CODE_EXTRACT_DIR(mask) ((mask >> 48) & 0x7F)
32 #define IIO_EVENT_CODE_EXTRACT_CHAN_TYPE(mask) ((mask >> 32) & 0xFF)
36 #define IIO_EVENT_CODE_EXTRACT_CHAN(mask) ((__s16)(mask & 0xFFFF))
37 #define IIO_EVENT_CODE_EXTRACT_CHAN2(mask) ((__s16)(((mask) >> 16) & 0xFFFF))
39 #define IIO_EVENT_CODE_EXTRACT_MODIFIER(mask) ((mask >> 40) & 0xFF)
40 #define IIO_EVENT_CODE_EXTRACT_DIFF(mask) (((mask) >> 55) & 0x1)
/linux-4.4.14/include/asm-generic/
H A Dword-at-a-time.h18 unsigned long mask = (val & c->low_bits) + c->low_bits; prep_zero_mask() local
19 return ~(mask | rhs); prep_zero_mask()
22 #define create_zero_mask(mask) (mask)
24 static inline long find_zero(unsigned long mask) find_zero() argument
28 if (mask >> 32) find_zero()
29 mask >>= 32; find_zero()
33 if (mask >> 16) find_zero()
34 mask >>= 16; find_zero()
37 return (mask >> 8) ? byte : byte + 1; find_zero()
48 #define zero_bytemask(mask) (~1ul << __fls(mask))
54 * The optimal byte mask counting is probably going to be something
69 * the simpler "(mask & ONEBYTES) * ONEBYTES >> 56"
71 * mask them first.
73 static inline long count_masked_bytes(unsigned long mask) count_masked_bytes() argument
75 return mask*0x0001020304050608ul >> 56; count_masked_bytes()
81 static inline long count_masked_bytes(long mask) count_masked_bytes() argument
84 long a = (0x0ff0001+mask) >> 23; count_masked_bytes()
86 return a & mask; count_masked_bytes()
94 unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; has_zero() local
95 *bits = mask; has_zero()
96 return mask; has_zero()
110 /* The mask we created is directly usable as a bytemask */
111 #define zero_bytemask(mask) (mask)
113 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
115 return count_masked_bytes(mask); find_zero()
/linux-4.4.14/arch/arm/mach-rpc/
H A Dirq.c12 unsigned int val, mask; iomd_ack_irq_a() local
14 mask = 1 << d->irq; iomd_ack_irq_a()
16 iomd_writeb(val & ~mask, IOMD_IRQMASKA); iomd_ack_irq_a()
17 iomd_writeb(mask, IOMD_IRQCLRA); iomd_ack_irq_a()
22 unsigned int val, mask; iomd_mask_irq_a() local
24 mask = 1 << d->irq; iomd_mask_irq_a()
26 iomd_writeb(val & ~mask, IOMD_IRQMASKA); iomd_mask_irq_a()
31 unsigned int val, mask; iomd_unmask_irq_a() local
33 mask = 1 << d->irq; iomd_unmask_irq_a()
35 iomd_writeb(val | mask, IOMD_IRQMASKA); iomd_unmask_irq_a()
46 unsigned int val, mask; iomd_mask_irq_b() local
48 mask = 1 << (d->irq & 7); iomd_mask_irq_b()
50 iomd_writeb(val & ~mask, IOMD_IRQMASKB); iomd_mask_irq_b()
55 unsigned int val, mask; iomd_unmask_irq_b() local
57 mask = 1 << (d->irq & 7); iomd_unmask_irq_b()
59 iomd_writeb(val | mask, IOMD_IRQMASKB); iomd_unmask_irq_b()
70 unsigned int val, mask; iomd_mask_irq_dma() local
72 mask = 1 << (d->irq & 7); iomd_mask_irq_dma()
74 iomd_writeb(val & ~mask, IOMD_DMAMASK); iomd_mask_irq_dma()
79 unsigned int val, mask; iomd_unmask_irq_dma() local
81 mask = 1 << (d->irq & 7); iomd_unmask_irq_dma()
83 iomd_writeb(val | mask, IOMD_DMAMASK); iomd_unmask_irq_dma()
94 unsigned int val, mask; iomd_mask_irq_fiq() local
96 mask = 1 << (d->irq & 7); iomd_mask_irq_fiq()
98 iomd_writeb(val & ~mask, IOMD_FIQMASK); iomd_mask_irq_fiq()
103 unsigned int val, mask; iomd_unmask_irq_fiq() local
105 mask = 1 << (d->irq & 7); iomd_unmask_irq_fiq()
107 iomd_writeb(val | mask, IOMD_FIQMASK); iomd_unmask_irq_fiq()
/linux-4.4.14/drivers/mfd/
H A Dsec-irq.c30 .mask = S2MPS11_IRQ_PWRONF_MASK,
34 .mask = S2MPS11_IRQ_PWRONR_MASK,
38 .mask = S2MPS11_IRQ_JIGONBF_MASK,
42 .mask = S2MPS11_IRQ_JIGONBR_MASK,
46 .mask = S2MPS11_IRQ_ACOKBF_MASK,
50 .mask = S2MPS11_IRQ_ACOKBR_MASK,
54 .mask = S2MPS11_IRQ_PWRON1S_MASK,
58 .mask = S2MPS11_IRQ_MRB_MASK,
62 .mask = S2MPS11_IRQ_RTC60S_MASK,
66 .mask = S2MPS11_IRQ_RTCA1_MASK,
70 .mask = S2MPS11_IRQ_RTCA0_MASK,
74 .mask = S2MPS11_IRQ_SMPL_MASK,
78 .mask = S2MPS11_IRQ_RTC1S_MASK,
82 .mask = S2MPS11_IRQ_WTSR_MASK,
86 .mask = S2MPS11_IRQ_INT120C_MASK,
90 .mask = S2MPS11_IRQ_INT140C_MASK,
97 .mask = S2MPS11_IRQ_PWRONF_MASK,
101 .mask = S2MPS11_IRQ_PWRONR_MASK,
105 .mask = S2MPS11_IRQ_JIGONBF_MASK,
109 .mask = S2MPS11_IRQ_JIGONBR_MASK,
113 .mask = S2MPS11_IRQ_ACOKBF_MASK,
117 .mask = S2MPS11_IRQ_ACOKBR_MASK,
121 .mask = S2MPS11_IRQ_PWRON1S_MASK,
125 .mask = S2MPS11_IRQ_MRB_MASK,
129 .mask = S2MPS11_IRQ_RTC60S_MASK,
133 .mask = S2MPS11_IRQ_RTCA1_MASK,
137 .mask = S2MPS11_IRQ_RTCA0_MASK,
141 .mask = S2MPS11_IRQ_SMPL_MASK,
145 .mask = S2MPS11_IRQ_RTC1S_MASK,
149 .mask = S2MPS11_IRQ_WTSR_MASK,
153 .mask = S2MPS11_IRQ_INT120C_MASK,
157 .mask = S2MPS11_IRQ_INT140C_MASK,
161 .mask = S2MPS14_IRQ_TSD_MASK,
168 .mask = S2MPS11_IRQ_PWRONF_MASK,
172 .mask = S2MPS11_IRQ_PWRONR_MASK,
176 .mask = S2MPS11_IRQ_JIGONBF_MASK,
180 .mask = S2MPS11_IRQ_JIGONBR_MASK,
184 .mask = S2MPS11_IRQ_ACOKBF_MASK,
188 .mask = S2MPS11_IRQ_ACOKBR_MASK,
192 .mask = S2MPS11_IRQ_PWRON1S_MASK,
196 .mask = S2MPS11_IRQ_MRB_MASK,
200 .mask = S2MPS11_IRQ_RTC60S_MASK,
204 .mask = S2MPS11_IRQ_RTCA1_MASK,
208 .mask = S2MPS11_IRQ_RTCA0_MASK,
212 .mask = S2MPS11_IRQ_SMPL_MASK,
216 .mask = S2MPS11_IRQ_RTC1S_MASK,
220 .mask = S2MPS11_IRQ_WTSR_MASK,
224 .mask = S2MPS11_IRQ_INT120C_MASK,
228 .mask = S2MPS11_IRQ_INT140C_MASK,
232 .mask = S2MPS14_IRQ_TSD_MASK,
239 .mask = S5M8767_IRQ_PWRR_MASK,
243 .mask = S5M8767_IRQ_PWRF_MASK,
247 .mask = S5M8767_IRQ_PWR1S_MASK,
251 .mask = S5M8767_IRQ_JIGR_MASK,
255 .mask = S5M8767_IRQ_JIGF_MASK,
259 .mask = S5M8767_IRQ_LOWBAT2_MASK,
263 .mask = S5M8767_IRQ_LOWBAT1_MASK,
267 .mask = S5M8767_IRQ_MRB_MASK,
271 .mask = S5M8767_IRQ_DVSOK2_MASK,
275 .mask = S5M8767_IRQ_DVSOK3_MASK,
279 .mask = S5M8767_IRQ_DVSOK4_MASK,
283 .mask = S5M8767_IRQ_RTC60S_MASK,
287 .mask = S5M8767_IRQ_RTCA1_MASK,
291 .mask = S5M8767_IRQ_RTCA2_MASK,
295 .mask = S5M8767_IRQ_SMPL_MASK,
299 .mask = S5M8767_IRQ_RTC1S_MASK,
303 .mask = S5M8767_IRQ_WTSR_MASK,
310 .mask = S5M8763_IRQ_DCINF_MASK,
314 .mask = S5M8763_IRQ_DCINR_MASK,
318 .mask = S5M8763_IRQ_JIGF_MASK,
322 .mask = S5M8763_IRQ_JIGR_MASK,
326 .mask = S5M8763_IRQ_PWRONF_MASK,
330 .mask = S5M8763_IRQ_PWRONR_MASK,
334 .mask = S5M8763_IRQ_WTSREVNT_MASK,
338 .mask = S5M8763_IRQ_SMPLEVNT_MASK,
342 .mask = S5M8763_IRQ_ALARM1_MASK,
346 .mask = S5M8763_IRQ_ALARM0_MASK,
350 .mask = S5M8763_IRQ_ONKEY1S_MASK,
354 .mask = S5M8763_IRQ_TOPOFFR_MASK,
358 .mask = S5M8763_IRQ_DCINOVPR_MASK,
362 .mask = S5M8763_IRQ_CHGRSTF_MASK,
366 .mask = S5M8763_IRQ_DONER_MASK,
370 .mask = S5M8763_IRQ_CHGFAULT_MASK,
374 .mask = S5M8763_IRQ_LOBAT1_MASK,
378 .mask = S5M8763_IRQ_LOBAT2_MASK,
H A Dda9063-irq.c34 u8 mask; member in struct:da9063_irq_data
41 .mask = DA9063_M_ONKEY,
45 .mask = DA9063_M_ALARM,
49 .mask = DA9063_M_TICK,
53 .mask = DA9063_M_ADC_RDY,
57 .mask = DA9063_M_SEQ_RDY,
62 .mask = DA9063_M_WAKE,
66 .mask = DA9063_M_TEMP,
70 .mask = DA9063_M_COMP_1V2,
74 .mask = DA9063_M_LDO_LIM,
78 .mask = DA9063_M_UVOV,
82 .mask = DA9063_M_DVC_RDY,
86 .mask = DA9063_M_VDD_MON,
90 .mask = DA9063_M_VDD_WARN,
95 .mask = DA9063_M_GPI0,
99 .mask = DA9063_M_GPI1,
103 .mask = DA9063_M_GPI2,
107 .mask = DA9063_M_GPI3,
111 .mask = DA9063_M_GPI4,
115 .mask = DA9063_M_GPI5,
119 .mask = DA9063_M_GPI6,
123 .mask = DA9063_M_GPI7,
128 .mask = DA9063_M_GPI8,
132 .mask = DA9063_M_GPI9,
136 .mask = DA9063_M_GPI10,
140 .mask = DA9063_M_GPI11,
144 .mask = DA9063_M_GPI12,
148 .mask = DA9063_M_GPI13,
152 .mask = DA9063_M_GPI14,
156 .mask = DA9063_M_GPI15,
H A Dwm8350-irq.c42 int mask; member in struct:wm8350_irq_data
50 .mask = WM8350_OC_LS_EINT,
56 .mask = WM8350_UV_DC1_EINT,
61 .mask = WM8350_UV_DC2_EINT,
66 .mask = WM8350_UV_DC3_EINT,
71 .mask = WM8350_UV_DC4_EINT,
76 .mask = WM8350_UV_DC5_EINT,
81 .mask = WM8350_UV_DC6_EINT,
86 .mask = WM8350_UV_LDO1_EINT,
91 .mask = WM8350_UV_LDO2_EINT,
96 .mask = WM8350_UV_LDO3_EINT,
101 .mask = WM8350_UV_LDO4_EINT,
106 .mask = WM8350_CHG_BAT_HOT_EINT,
111 .mask = WM8350_CHG_BAT_COLD_EINT,
116 .mask = WM8350_CHG_BAT_FAIL_EINT,
121 .mask = WM8350_CHG_TO_EINT,
126 .mask = WM8350_CHG_END_EINT,
131 .mask = WM8350_CHG_START_EINT,
136 .mask = WM8350_CHG_FAST_RDY_EINT,
141 .mask = WM8350_CHG_VBATT_LT_3P9_EINT,
146 .mask = WM8350_CHG_VBATT_LT_3P1_EINT,
151 .mask = WM8350_CHG_VBATT_LT_2P85_EINT,
156 .mask = WM8350_RTC_ALM_EINT,
161 .mask = WM8350_RTC_SEC_EINT,
166 .mask = WM8350_RTC_PER_EINT,
171 .mask = WM8350_CS1_EINT,
176 .mask = WM8350_CS2_EINT,
181 .mask = WM8350_SYS_HYST_COMP_FAIL_EINT,
186 .mask = WM8350_SYS_CHIP_GT115_EINT,
191 .mask = WM8350_SYS_CHIP_GT140_EINT,
196 .mask = WM8350_SYS_WDOG_TO_EINT,
201 .mask = WM8350_AUXADC_DATARDY_EINT,
206 .mask = WM8350_AUXADC_DCOMP4_EINT,
211 .mask = WM8350_AUXADC_DCOMP3_EINT,
216 .mask = WM8350_AUXADC_DCOMP2_EINT,
221 .mask = WM8350_AUXADC_DCOMP1_EINT,
226 .mask = WM8350_USB_LIMIT_EINT,
232 .mask = WM8350_WKUP_OFF_STATE_EINT,
237 .mask = WM8350_WKUP_HIB_STATE_EINT,
242 .mask = WM8350_WKUP_CONV_FAULT_EINT,
247 .mask = WM8350_WKUP_WDOG_RST_EINT,
252 .mask = WM8350_WKUP_GP_PWR_ON_EINT,
257 .mask = WM8350_WKUP_ONKEY_EINT,
262 .mask = WM8350_WKUP_GP_WAKEUP_EINT,
267 .mask = WM8350_CODEC_JCK_DET_L_EINT,
272 .mask = WM8350_CODEC_JCK_DET_R_EINT,
277 .mask = WM8350_CODEC_MICSCD_EINT,
282 .mask = WM8350_CODEC_MICD_EINT,
287 .mask = WM8350_EXT_USB_FB_EINT,
292 .mask = WM8350_EXT_WALL_FB_EINT,
297 .mask = WM8350_EXT_BAT_FB_EINT,
302 .mask = WM8350_GP0_EINT,
307 .mask = WM8350_GP1_EINT,
312 .mask = WM8350_GP2_EINT,
317 .mask = WM8350_GP3_EINT,
322 .mask = WM8350_GP4_EINT,
327 .mask = WM8350_GP5_EINT,
332 .mask = WM8350_GP6_EINT,
337 .mask = WM8350_GP7_EINT,
342 .mask = WM8350_GP8_EINT,
347 .mask = WM8350_GP9_EINT,
352 .mask = WM8350_GP10_EINT,
357 .mask = WM8350_GP11_EINT,
362 .mask = WM8350_GP12_EINT,
412 if (sub_reg[data->reg] & data->mask) wm8350_irq()
432 /* If there's been a change in the mask write it back wm8350_irq_sync_unlock()
448 wm8350->irq_masks[irq_data->reg] &= ~irq_data->mask; wm8350_irq_enable()
457 wm8350->irq_masks[irq_data->reg] |= irq_data->mask; wm8350_irq_disable()
485 * bits in the mask registers. */ wm8350_irq_init()
H A Dda9052-irq.c41 .mask = DA9052_IRQ_MASK_POS_1,
45 .mask = DA9052_IRQ_MASK_POS_2,
49 .mask = DA9052_IRQ_MASK_POS_3,
53 .mask = DA9052_IRQ_MASK_POS_4,
57 .mask = DA9052_IRQ_MASK_POS_5,
61 .mask = DA9052_IRQ_MASK_POS_6,
65 .mask = DA9052_IRQ_MASK_POS_7,
69 .mask = DA9052_IRQ_MASK_POS_8,
73 .mask = DA9052_IRQ_MASK_POS_1,
77 .mask = DA9052_IRQ_MASK_POS_2,
81 .mask = DA9052_IRQ_MASK_POS_3,
85 .mask = DA9052_IRQ_MASK_POS_4,
89 .mask = DA9052_IRQ_MASK_POS_5,
93 .mask = DA9052_IRQ_MASK_POS_6,
97 .mask = DA9052_IRQ_MASK_POS_7,
101 .mask = DA9052_IRQ_MASK_POS_8,
105 .mask = DA9052_IRQ_MASK_POS_1,
109 .mask = DA9052_IRQ_MASK_POS_2,
113 .mask = DA9052_IRQ_MASK_POS_3,
117 .mask = DA9052_IRQ_MASK_POS_4,
121 .mask = DA9052_IRQ_MASK_POS_5,
125 .mask = DA9052_IRQ_MASK_POS_6,
129 .mask = DA9052_IRQ_MASK_POS_7,
133 .mask = DA9052_IRQ_MASK_POS_8,
137 .mask = DA9052_IRQ_MASK_POS_1,
141 .mask = DA9052_IRQ_MASK_POS_2,
145 .mask = DA9052_IRQ_MASK_POS_3,
149 .mask = DA9052_IRQ_MASK_POS_4,
153 .mask = DA9052_IRQ_MASK_POS_5,
157 .mask = DA9052_IRQ_MASK_POS_6,
161 .mask = DA9052_IRQ_MASK_POS_7,
165 .mask = DA9052_IRQ_MASK_POS_8,
H A Dwm831x-irq.c33 int mask; member in struct:wm831x_irq_data
40 .mask = WM831X_TEMP_THW_EINT,
45 .mask = WM831X_GP1_EINT,
50 .mask = WM831X_GP2_EINT,
55 .mask = WM831X_GP3_EINT,
60 .mask = WM831X_GP4_EINT,
65 .mask = WM831X_GP5_EINT,
70 .mask = WM831X_GP6_EINT,
75 .mask = WM831X_GP7_EINT,
80 .mask = WM831X_GP8_EINT,
85 .mask = WM831X_GP9_EINT,
90 .mask = WM831X_GP10_EINT,
95 .mask = WM831X_GP11_EINT,
100 .mask = WM831X_GP12_EINT,
105 .mask = WM831X_GP13_EINT,
110 .mask = WM831X_GP14_EINT,
115 .mask = WM831X_GP15_EINT,
120 .mask = WM831X_GP16_EINT,
125 .mask = WM831X_ON_PIN_EINT,
130 .mask = WM831X_PPM_SYSLO_EINT,
135 .mask = WM831X_PPM_PWR_SRC_EINT,
140 .mask = WM831X_PPM_USB_CURR_EINT,
145 .mask = WM831X_WDOG_TO_EINT,
150 .mask = WM831X_RTC_PER_EINT,
155 .mask = WM831X_RTC_ALM_EINT,
160 .mask = WM831X_CHG_BATT_HOT_EINT,
165 .mask = WM831X_CHG_BATT_COLD_EINT,
170 .mask = WM831X_CHG_BATT_FAIL_EINT,
175 .mask = WM831X_CHG_OV_EINT,
180 .mask = WM831X_CHG_END_EINT,
185 .mask = WM831X_CHG_TO_EINT,
190 .mask = WM831X_CHG_MODE_EINT,
195 .mask = WM831X_CHG_START_EINT,
200 .mask = WM831X_TCHDATA_EINT,
205 .mask = WM831X_TCHPD_EINT,
210 .mask = WM831X_AUXADC_DATA_EINT,
215 .mask = WM831X_AUXADC_DCOMP1_EINT,
220 .mask = WM831X_AUXADC_DCOMP2_EINT,
225 .mask = WM831X_AUXADC_DCOMP3_EINT,
230 .mask = WM831X_AUXADC_DCOMP4_EINT,
235 .mask = WM831X_CS1_EINT,
240 .mask = WM831X_CS2_EINT,
245 .mask = WM831X_HC_DC1_EINT,
250 .mask = WM831X_HC_DC2_EINT,
255 .mask = WM831X_UV_LDO1_EINT,
260 .mask = WM831X_UV_LDO2_EINT,
265 .mask = WM831X_UV_LDO3_EINT,
270 .mask = WM831X_UV_LDO4_EINT,
275 .mask = WM831X_UV_LDO5_EINT,
280 .mask = WM831X_UV_LDO6_EINT,
285 .mask = WM831X_UV_LDO7_EINT,
290 .mask = WM831X_UV_LDO8_EINT,
295 .mask = WM831X_UV_LDO9_EINT,
300 .mask = WM831X_UV_LDO10_EINT,
305 .mask = WM831X_UV_DC1_EINT,
310 .mask = WM831X_UV_DC2_EINT,
315 .mask = WM831X_UV_DC3_EINT,
320 .mask = WM831X_UV_DC4_EINT,
357 /* If there's been a change in the mask write it back wm831x_irq_sync_unlock()
360 dev_dbg(wm831x->dev, "IRQ mask sync: %x = %x\n", wm831x_irq_sync_unlock()
380 wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; wm831x_irq_enable()
389 wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; wm831x_irq_disable()
515 if (*status & wm831x_irqs[i].mask) wm831x_irq_thread()
648 /* Enable top level interrupts, we mask at secondary level */ wm831x_irq_init()
H A Dwm8994-irq.c34 .mask = WM8994_TEMP_SHUT_EINT,
38 .mask = WM8994_MIC1_DET_EINT,
42 .mask = WM8994_MIC1_SHRT_EINT,
46 .mask = WM8994_MIC2_DET_EINT,
50 .mask = WM8994_MIC2_SHRT_EINT,
54 .mask = WM8994_FLL1_LOCK_EINT,
58 .mask = WM8994_FLL2_LOCK_EINT,
62 .mask = WM8994_SRC1_LOCK_EINT,
66 .mask = WM8994_SRC2_LOCK_EINT,
70 .mask = WM8994_AIF1DRC1_SIG_DET,
74 .mask = WM8994_AIF1DRC2_SIG_DET_EINT,
78 .mask = WM8994_AIF2DRC_SIG_DET_EINT,
82 .mask = WM8994_FIFOS_ERR_EINT,
86 .mask = WM8994_WSEQ_DONE_EINT,
90 .mask = WM8994_DCS_DONE_EINT,
94 .mask = WM8994_TEMP_WARN_EINT,
97 .mask = WM8994_GP1_EINT,
100 .mask = WM8994_GP2_EINT,
103 .mask = WM8994_GP3_EINT,
106 .mask = WM8994_GP4_EINT,
109 .mask = WM8994_GP5_EINT,
112 .mask = WM8994_GP6_EINT,
115 .mask = WM8994_GP7_EINT,
118 .mask = WM8994_GP8_EINT,
121 .mask = WM8994_GP8_EINT,
124 .mask = WM8994_GP10_EINT,
127 .mask = WM8994_GP11_EINT,
H A Dpalmas.c52 .mask = TPS65917_RESERVED,
55 .mask = TPS65917_INT1_STATUS_PWRON,
58 .mask = TPS65917_INT1_STATUS_LONG_PRESS_KEY,
61 .mask = TPS65917_RESERVED,
64 .mask = TPS65917_INT1_STATUS_PWRDOWN,
67 .mask = TPS65917_INT1_STATUS_HOTDIE,
70 .mask = TPS65917_INT1_STATUS_VSYS_MON,
73 .mask = TPS65917_RESERVED,
77 .mask = TPS65917_RESERVED,
81 .mask = TPS65917_INT2_STATUS_OTP_ERROR,
85 .mask = TPS65917_INT2_STATUS_WDT,
89 .mask = TPS65917_RESERVED,
93 .mask = TPS65917_INT2_STATUS_RESET_IN,
97 .mask = TPS65917_INT2_STATUS_FSD,
101 .mask = TPS65917_INT2_STATUS_SHORT,
105 .mask = TPS65917_RESERVED,
110 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_0,
114 .mask = TPS65917_INT3_STATUS_GPADC_AUTO_1,
118 .mask = TPS65917_INT3_STATUS_GPADC_EOC_SW,
122 .mask = TPS65917_RESERVED6,
126 .mask = TPS65917_RESERVED,
130 .mask = TPS65917_RESERVED,
134 .mask = TPS65917_RESERVED,
138 .mask = TPS65917_INT3_STATUS_VBUS,
143 .mask = TPS65917_INT4_STATUS_GPIO_0,
147 .mask = TPS65917_INT4_STATUS_GPIO_1,
151 .mask = TPS65917_INT4_STATUS_GPIO_2,
155 .mask = TPS65917_INT4_STATUS_GPIO_3,
159 .mask = TPS65917_INT4_STATUS_GPIO_4,
163 .mask = TPS65917_INT4_STATUS_GPIO_5,
167 .mask = TPS65917_INT4_STATUS_GPIO_6,
171 .mask = TPS65917_RESERVED10,
179 .mask = PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV,
182 .mask = PALMAS_INT1_STATUS_PWRON,
185 .mask = PALMAS_INT1_STATUS_LONG_PRESS_KEY,
188 .mask = PALMAS_INT1_STATUS_RPWRON,
191 .mask = PALMAS_INT1_STATUS_PWRDOWN,
194 .mask = PALMAS_INT1_STATUS_HOTDIE,
197 .mask = PALMAS_INT1_STATUS_VSYS_MON,
200 .mask = PALMAS_INT1_STATUS_VBAT_MON,
204 .mask = PALMAS_INT2_STATUS_RTC_ALARM,
208 .mask = PALMAS_INT2_STATUS_RTC_TIMER,
212 .mask = PALMAS_INT2_STATUS_WDT,
216 .mask = PALMAS_INT2_STATUS_BATREMOVAL,
220 .mask = PALMAS_INT2_STATUS_RESET_IN,
224 .mask = PALMAS_INT2_STATUS_FBI_BB,
228 .mask = PALMAS_INT2_STATUS_SHORT,
232 .mask = PALMAS_INT2_STATUS_VAC_ACOK,
237 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_0,
241 .mask = PALMAS_INT3_STATUS_GPADC_AUTO_1,
245 .mask = PALMAS_INT3_STATUS_GPADC_EOC_SW,
249 .mask = PALMAS_INT3_STATUS_GPADC_EOC_RT,
253 .mask = PALMAS_INT3_STATUS_ID_OTG,
257 .mask = PALMAS_INT3_STATUS_ID,
261 .mask = PALMAS_INT3_STATUS_VBUS_OTG,
265 .mask = PALMAS_INT3_STATUS_VBUS,
270 .mask = PALMAS_INT4_STATUS_GPIO_0,
274 .mask = PALMAS_INT4_STATUS_GPIO_1,
278 .mask = PALMAS_INT4_STATUS_GPIO_2,
282 .mask = PALMAS_INT4_STATUS_GPIO_3,
286 .mask = PALMAS_INT4_STATUS_GPIO_4,
290 .mask = PALMAS_INT4_STATUS_GPIO_5,
294 .mask = PALMAS_INT4_STATUS_GPIO_6,
298 .mask = PALMAS_INT4_STATUS_GPIO_7,
H A Dmax8998-irq.c22 int mask; member in struct:max8998_irq_data
28 .mask = MAX8998_IRQ_DCINF_MASK,
32 .mask = MAX8998_IRQ_DCINR_MASK,
36 .mask = MAX8998_IRQ_JIGF_MASK,
40 .mask = MAX8998_IRQ_JIGR_MASK,
44 .mask = MAX8998_IRQ_PWRONF_MASK,
48 .mask = MAX8998_IRQ_PWRONR_MASK,
52 .mask = MAX8998_IRQ_WTSREVNT_MASK,
56 .mask = MAX8998_IRQ_SMPLEVNT_MASK,
60 .mask = MAX8998_IRQ_ALARM1_MASK,
64 .mask = MAX8998_IRQ_ALARM0_MASK,
68 .mask = MAX8998_IRQ_ONKEY1S_MASK,
72 .mask = MAX8998_IRQ_TOPOFFR_MASK,
76 .mask = MAX8998_IRQ_DCINOVPR_MASK,
80 .mask = MAX8998_IRQ_CHGRSTF_MASK,
84 .mask = MAX8998_IRQ_DONER_MASK,
88 .mask = MAX8998_IRQ_CHGFAULT_MASK,
92 .mask = MAX8998_IRQ_LOBAT1_MASK,
96 .mask = MAX8998_IRQ_LOBAT2_MASK,
120 * If there's been a change in the mask write it back max8998_irq_sync_unlock()
138 max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask; max8998_irq_unmask()
146 max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask; max8998_irq_mask()
178 if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) { max8998_irq_thread()
H A Das3722.c85 .mask = AS3722_INTERRUPT_MASK1_LID,
88 .mask = AS3722_INTERRUPT_MASK1_ACOK,
91 .mask = AS3722_INTERRUPT_MASK1_ENABLE1,
94 .mask = AS3722_INTERRUPT_MASK1_OCURR_ALARM_SD0,
97 .mask = AS3722_INTERRUPT_MASK1_ONKEY_LONG,
100 .mask = AS3722_INTERRUPT_MASK1_ONKEY,
103 .mask = AS3722_INTERRUPT_MASK1_OVTMP,
106 .mask = AS3722_INTERRUPT_MASK1_LOWBAT,
111 .mask = AS3722_INTERRUPT_MASK2_SD0_LV,
115 .mask = AS3722_INTERRUPT_MASK2_SD1_LV,
119 .mask = AS3722_INTERRUPT_MASK2_SD2345_LV,
123 .mask = AS3722_INTERRUPT_MASK2_PWM1_OV_PROT,
127 .mask = AS3722_INTERRUPT_MASK2_PWM2_OV_PROT,
131 .mask = AS3722_INTERRUPT_MASK2_ENABLE2,
135 .mask = AS3722_INTERRUPT_MASK2_SD6_LV,
139 .mask = AS3722_INTERRUPT_MASK2_RTC_REP,
145 .mask = AS3722_INTERRUPT_MASK3_RTC_ALARM,
149 .mask = AS3722_INTERRUPT_MASK3_GPIO1,
153 .mask = AS3722_INTERRUPT_MASK3_GPIO2,
157 .mask = AS3722_INTERRUPT_MASK3_GPIO3,
161 .mask = AS3722_INTERRUPT_MASK3_GPIO4,
165 .mask = AS3722_INTERRUPT_MASK3_GPIO5,
169 .mask = AS3722_INTERRUPT_MASK3_WATCHDOG,
173 .mask = AS3722_INTERRUPT_MASK3_ENABLE3,
179 .mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_SHUTDOWN,
183 .mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_SHUTDOWN,
187 .mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_SHUTDOWN,
191 .mask = AS3722_INTERRUPT_MASK4_TEMP_SD0_ALARM,
195 .mask = AS3722_INTERRUPT_MASK4_TEMP_SD1_ALARM,
199 .mask = AS3722_INTERRUPT_MASK4_TEMP_SD6_ALARM,
203 .mask = AS3722_INTERRUPT_MASK4_OCCUR_ALARM_SD6,
207 .mask = AS3722_INTERRUPT_MASK4_ADC,
H A Dtps65910.c60 .mask = INT_MSK_PWRHOLD_F_IT_MSK_MASK,
64 .mask = INT_MSK_VMBHI_IT_MSK_MASK,
68 .mask = INT_MSK_PWRON_IT_MSK_MASK,
72 .mask = INT_MSK_PWRON_LP_IT_MSK_MASK,
76 .mask = INT_MSK_PWRHOLD_R_IT_MSK_MASK,
80 .mask = INT_MSK_HOTDIE_IT_MSK_MASK,
84 .mask = INT_MSK_RTC_ALARM_IT_MSK_MASK,
88 .mask = INT_MSK_RTC_PERIOD_IT_MSK_MASK,
94 .mask = INT_MSK2_GPIO0_R_IT_MSK_MASK,
98 .mask = INT_MSK2_GPIO0_F_IT_MSK_MASK,
102 .mask = INT_MSK2_GPIO1_R_IT_MSK_MASK,
106 .mask = INT_MSK2_GPIO1_F_IT_MSK_MASK,
110 .mask = INT_MSK2_GPIO2_R_IT_MSK_MASK,
114 .mask = INT_MSK2_GPIO2_F_IT_MSK_MASK,
118 .mask = INT_MSK2_GPIO3_R_IT_MSK_MASK,
122 .mask = INT_MSK2_GPIO3_F_IT_MSK_MASK,
128 .mask = INT_MSK3_GPIO4_R_IT_MSK_MASK,
132 .mask = INT_MSK3_GPIO4_F_IT_MSK_MASK,
136 .mask = INT_MSK3_GPIO5_R_IT_MSK_MASK,
140 .mask = INT_MSK3_GPIO5_F_IT_MSK_MASK,
144 .mask = INT_MSK3_WTCHDG_IT_MSK_MASK,
148 .mask = INT_MSK3_VMBCH2_H_IT_MSK_MASK,
152 .mask = INT_MSK3_VMBCH2_L_IT_MSK_MASK,
156 .mask = INT_MSK3_PWRDN_IT_MSK_MASK,
164 .mask = TPS65910_INT_MSK_VMBDCH_IT_MSK_MASK,
168 .mask = TPS65910_INT_MSK_VMBHI_IT_MSK_MASK,
172 .mask = TPS65910_INT_MSK_PWRON_IT_MSK_MASK,
176 .mask = TPS65910_INT_MSK_PWRON_LP_IT_MSK_MASK,
180 .mask = TPS65910_INT_MSK_PWRHOLD_IT_MSK_MASK,
184 .mask = TPS65910_INT_MSK_HOTDIE_IT_MSK_MASK,
188 .mask = TPS65910_INT_MSK_RTC_ALARM_IT_MSK_MASK,
192 .mask = TPS65910_INT_MSK_RTC_PERIOD_IT_MSK_MASK,
198 .mask = TPS65910_INT_MSK2_GPIO0_F_IT_MSK_MASK,
202 .mask = TPS65910_INT_MSK2_GPIO0_R_IT_MSK_MASK,
H A D88pm805.c92 .mask = PM805_INT1_HP1_SHRT,
95 .mask = PM805_INT1_HP2_SHRT,
98 .mask = PM805_INT1_MIC_CONFLICT,
101 .mask = PM805_INT1_CLIP_FAULT,
104 .mask = PM805_INT1_LDO_OFF,
107 .mask = PM805_INT1_SRC_DPLL_LOCK,
112 .mask = PM805_INT2_MIC_DET,
116 .mask = PM805_INT2_SHRT_BTN_DET,
120 .mask = PM805_INT2_VOLM_BTN_DET,
124 .mask = PM805_INT2_VOLP_BTN_DET,
128 .mask = PM805_INT2_RAW_PLL_FAULT,
132 .mask = PM805_INT2_FINE_PLL_FAULT,
140 int data, mask, ret = -EINVAL; device_irq_init_805() local
151 mask = device_irq_init_805()
156 ret = regmap_update_bits(map, PM805_INT_STATUS0, mask, data); device_irq_init_805()
H A Dtps65090.c79 .mask = TPS65090_INT1_MASK_VAC_STATUS_CHANGE,
82 .mask = TPS65090_INT1_MASK_VSYS_STATUS_CHANGE,
85 .mask = TPS65090_INT1_MASK_BAT_STATUS_CHANGE,
88 .mask = TPS65090_INT1_MASK_CHARGING_STATUS_CHANGE,
91 .mask = TPS65090_INT1_MASK_CHARGING_COMPLETE,
94 .mask = TPS65090_INT1_MASK_OVERLOAD_DCDC1,
97 .mask = TPS65090_INT1_MASK_OVERLOAD_DCDC2,
102 .mask = TPS65090_INT2_MASK_OVERLOAD_DCDC3,
106 .mask = TPS65090_INT2_MASK_OVERLOAD_FET1,
110 .mask = TPS65090_INT2_MASK_OVERLOAD_FET2,
114 .mask = TPS65090_INT2_MASK_OVERLOAD_FET3,
118 .mask = TPS65090_INT2_MASK_OVERLOAD_FET4,
122 .mask = TPS65090_INT2_MASK_OVERLOAD_FET5,
126 .mask = TPS65090_INT2_MASK_OVERLOAD_FET6,
130 .mask = TPS65090_INT2_MASK_OVERLOAD_FET7,
H A Dmax8907.c119 { .reg_offset = 0, .mask = 1 << 0, },
120 { .reg_offset = 0, .mask = 1 << 1, },
121 { .reg_offset = 0, .mask = 1 << 2, },
122 { .reg_offset = 1, .mask = 1 << 0, },
123 { .reg_offset = 1, .mask = 1 << 1, },
124 { .reg_offset = 1, .mask = 1 << 2, },
125 { .reg_offset = 1, .mask = 1 << 3, },
126 { .reg_offset = 1, .mask = 1 << 4, },
127 { .reg_offset = 1, .mask = 1 << 5, },
128 { .reg_offset = 1, .mask = 1 << 6, },
129 { .reg_offset = 1, .mask = 1 << 7, },
144 { .reg_offset = 0, .mask = 1 << 0, },
145 { .reg_offset = 0, .mask = 1 << 1, },
146 { .reg_offset = 0, .mask = 1 << 2, },
147 { .reg_offset = 0, .mask = 1 << 3, },
148 { .reg_offset = 0, .mask = 1 << 4, },
149 { .reg_offset = 0, .mask = 1 << 5, },
150 { .reg_offset = 0, .mask = 1 << 6, },
151 { .reg_offset = 0, .mask = 1 << 7, },
152 { .reg_offset = 1, .mask = 1 << 0, },
153 { .reg_offset = 1, .mask = 1 << 1, },
167 { .reg_offset = 0, .mask = 1 << 2, },
168 { .reg_offset = 0, .mask = 1 << 3, },
H A Dmax77693.c69 { .mask = LED_IRQ_FLED2_OPEN, },
70 { .mask = LED_IRQ_FLED2_SHORT, },
71 { .mask = LED_IRQ_FLED1_OPEN, },
72 { .mask = LED_IRQ_FLED1_SHORT, },
73 { .mask = LED_IRQ_MAX_FLASH, },
87 { .mask = TOPSYS_IRQ_T120C_INT, },
88 { .mask = TOPSYS_IRQ_T140C_INT, },
89 { .mask = TOPSYS_IRQ_LOWSYS_INT, },
103 { .mask = CHG_IRQ_BYP_I, },
104 { .mask = CHG_IRQ_THM_I, },
105 { .mask = CHG_IRQ_BAT_I, },
106 { .mask = CHG_IRQ_CHG_I, },
107 { .mask = CHG_IRQ_CHGIN_I, },
127 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC, },
128 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_LOW, },
129 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC_ERR, },
130 { .reg_offset = 0, .mask = MUIC_IRQ_INT1_ADC1K, },
132 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGTYP, },
133 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_CHGDETREUN, },
134 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DCDTMR, },
135 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_DXOVP, },
136 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VBVOLT, },
137 { .reg_offset = 1, .mask = MUIC_IRQ_INT2_VIDRM, },
139 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_EOC, },
140 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CGMBC, },
141 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_OVP, },
142 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_MBCCHG_ERR, },
143 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_CHG_ENABLED, },
144 { .reg_offset = 2, .mask = MUIC_IRQ_INT3_BAT_DET, },
H A Dintel_soc_pmic_crc.c127 .mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC),
130 .mask = BIT(CRYSTAL_COVE_IRQ_THRM),
133 .mask = BIT(CRYSTAL_COVE_IRQ_BCU),
136 .mask = BIT(CRYSTAL_COVE_IRQ_ADC),
139 .mask = BIT(CRYSTAL_COVE_IRQ_CHGR),
142 .mask = BIT(CRYSTAL_COVE_IRQ_GPIO),
145 .mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP),
H A Dtps65218.c82 * tps65218_update_bits: Modify bits w.r.t mask, val and level.
86 * @mask: Mask.
91 unsigned int mask, unsigned int val, unsigned int level) tps65218_update_bits()
102 data &= ~mask; tps65218_update_bits()
103 data |= val & mask; tps65218_update_bits()
115 unsigned int mask, unsigned int val, unsigned int level) tps65218_set_bits()
117 return tps65218_update_bits(tps, reg, mask, val, level); tps65218_set_bits()
122 unsigned int mask, unsigned int level) tps65218_clear_bits()
124 return tps65218_update_bits(tps, reg, mask, 0, level); tps65218_clear_bits()
148 .mask = TPS65218_INT1_PRGC,
151 .mask = TPS65218_INT1_CC_AQC,
154 .mask = TPS65218_INT1_HOT,
157 .mask = TPS65218_INT1_PB,
160 .mask = TPS65218_INT1_AC,
163 .mask = TPS65218_INT1_VPRG,
171 .mask = TPS65218_INT2_LS1_I,
175 .mask = TPS65218_INT2_LS2_I,
179 .mask = TPS65218_INT2_LS3_I,
183 .mask = TPS65218_INT2_LS1_F,
187 .mask = TPS65218_INT2_LS2_F,
191 .mask = TPS65218_INT2_LS3_F,
90 tps65218_update_bits(struct tps65218 *tps, unsigned int reg, unsigned int mask, unsigned int val, unsigned int level) tps65218_update_bits() argument
114 tps65218_set_bits(struct tps65218 *tps, unsigned int reg, unsigned int mask, unsigned int val, unsigned int level) tps65218_set_bits() argument
121 tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, unsigned int mask, unsigned int level) tps65218_clear_bits() argument
/linux-4.4.14/drivers/video/fbdev/riva/
H A Dnvreg.h31 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
33 /* Macro to set specific bitfields (mask has to be a macro x:y) ! */
34 #define SetBF(mask,value) ((value) << (0?mask))
35 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
38 | SetBF(mask,value)))
51 #define DEVICE_DEF(device,mask,value) \
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
54 #define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)
61 #define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)
66 #define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
67 #define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
68 #define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
73 #define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)
74 #define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)
75 #define PRM_Mask(mask) DEVICE_MASK(PRM,mask)
80 #define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)
81 #define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)
82 #define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)
87 #define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
88 #define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
89 #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
94 #define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value)
95 #define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value)
96 #define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask)
101 #define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)
102 #define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)
103 #define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
108 #define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
109 #define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
110 #define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
115 #define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)
116 #define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)
117 #define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)
122 #define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)
123 #define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)
124 #define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)
129 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
130 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
136 #define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
137 #define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
138 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
144 #define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)
145 #define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)
146 #define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)
152 #define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)
153 #define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)
154 #define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)
173 #define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
174 #define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
175 #define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
/linux-4.4.14/drivers/video/fbdev/
H A Dc2p_core.h21 unsigned int shift, u32 mask) _transp()
23 u32 t = (d[i1] ^ (d[i2] >> shift)) & mask; _transp()
62 u32 mask = get_mask(n); transp8() local
67 _transp(d, 0, 1, n, mask); transp8()
69 _transp(d, 2, 3, n, mask); transp8()
71 _transp(d, 4, 5, n, mask); transp8()
73 _transp(d, 6, 7, n, mask); transp8()
78 _transp(d, 0, 2, n, mask); transp8()
79 _transp(d, 1, 3, n, mask); transp8()
81 _transp(d, 4, 6, n, mask); transp8()
82 _transp(d, 5, 7, n, mask); transp8()
87 _transp(d, 0, 4, n, mask); transp8()
88 _transp(d, 1, 5, n, mask); transp8()
89 _transp(d, 2, 6, n, mask); transp8()
90 _transp(d, 3, 7, n, mask); transp8()
104 u32 mask = get_mask(n); transp4() local
109 _transp(d, 0, 1, n, mask); transp4()
111 _transp(d, 2, 3, n, mask); transp4()
116 _transp(d, 0, 2, n, mask); transp4()
117 _transp(d, 1, 3, n, mask); transp4()
131 u32 mask = get_mask(n); transp4x() local
136 _transp(d, 2, 0, n, mask); transp4x()
137 _transp(d, 3, 1, n, mask); transp4x()
147 * This is equivalent to (a & mask) | (b & ~mask)
150 static inline u32 comp(u32 a, u32 b, u32 mask) comp() argument
152 return ((a ^ b) & mask) ^ b; comp()
20 _transp(u32 d[], unsigned int i1, unsigned int i2, unsigned int shift, u32 mask) _transp() argument
H A Datafb_iplan2p8.c114 u32 pval[4], v, v1, mask; atafb_iplan2p8_copyarea() local
120 mask = 0xff00ff00; atafb_iplan2p8_copyarea()
135 pval[0] = (*src32++ << 8) & mask; atafb_iplan2p8_copyarea()
136 pval[1] = (*src32++ << 8) & mask; atafb_iplan2p8_copyarea()
137 pval[2] = (*src32++ << 8) & mask; atafb_iplan2p8_copyarea()
138 pval[3] = (*src32++ << 8) & mask; atafb_iplan2p8_copyarea()
140 pval[0] = dst32[0] & mask; atafb_iplan2p8_copyarea()
141 pval[1] = dst32[1] & mask; atafb_iplan2p8_copyarea()
142 pval[2] = dst32[2] & mask; atafb_iplan2p8_copyarea()
143 pval[3] = dst32[3] & mask; atafb_iplan2p8_copyarea()
148 v1 = v & mask; atafb_iplan2p8_copyarea()
152 v1 = v & mask; atafb_iplan2p8_copyarea()
156 v1 = v & mask; atafb_iplan2p8_copyarea()
160 v1 = v & mask; atafb_iplan2p8_copyarea()
166 dst32[0] = (dst32[0] & mask) | pval[0]; atafb_iplan2p8_copyarea()
167 dst32[1] = (dst32[1] & mask) | pval[1]; atafb_iplan2p8_copyarea()
168 dst32[2] = (dst32[2] & mask) | pval[2]; atafb_iplan2p8_copyarea()
169 dst32[3] = (dst32[3] & mask) | pval[3]; atafb_iplan2p8_copyarea()
177 u32 pval[4], v, v1, mask; atafb_iplan2p8_copyarea() local
183 mask = 0xff00ff; atafb_iplan2p8_copyarea()
198 pval[0] = dst32[-1] & mask; atafb_iplan2p8_copyarea()
199 pval[1] = dst32[-2] & mask; atafb_iplan2p8_copyarea()
200 pval[2] = dst32[-3] & mask; atafb_iplan2p8_copyarea()
201 pval[3] = dst32[-4] & mask; atafb_iplan2p8_copyarea()
203 pval[0] = (*--src32 >> 8) & mask; atafb_iplan2p8_copyarea()
204 pval[1] = (*--src32 >> 8) & mask; atafb_iplan2p8_copyarea()
205 pval[2] = (*--src32 >> 8) & mask; atafb_iplan2p8_copyarea()
206 pval[3] = (*--src32 >> 8) & mask; atafb_iplan2p8_copyarea()
211 v1 = v & mask; atafb_iplan2p8_copyarea()
215 v1 = v & mask; atafb_iplan2p8_copyarea()
219 v1 = v & mask; atafb_iplan2p8_copyarea()
223 v1 = v & mask; atafb_iplan2p8_copyarea()
229 dst32[-1] = (dst32[-1] & mask) | pval[0]; atafb_iplan2p8_copyarea()
230 dst32[-2] = (dst32[-2] & mask) | pval[1]; atafb_iplan2p8_copyarea()
231 dst32[-3] = (dst32[-3] & mask) | pval[2]; atafb_iplan2p8_copyarea()
232 dst32[-4] = (dst32[-4] & mask) | pval[3]; atafb_iplan2p8_copyarea()
/linux-4.4.14/include/linux/netfilter/ipset/
H A Dip_set_bitmap.h19 u32 mask = 0xFFFFFFFE; range_to_mask() local
22 while (--(*bits) > 0 && mask && (to & mask) != from) range_to_mask()
23 mask <<= 1; range_to_mask()
25 return mask; range_to_mask()
/linux-4.4.14/arch/m32r/include/asm/
H A Dsmp.h16 unsigned long mask[PHYSID_ARRAY_SIZE]; member in struct:physid_mask
21 #define physid_set(physid, map) set_bit(physid, (map).mask)
22 #define physid_clear(physid, map) clear_bit(physid, (map).mask)
23 #define physid_isset(physid, map) test_bit(physid, (map).mask)
24 #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask)
26 #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
27 #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS)
28 #define physids_clear(map) bitmap_zero((map).mask, MAX_APICS)
29 #define physids_complement(dst, src) bitmap_complement((dst).mask,(src).mask, MAX_APICS)
30 #define physids_empty(map) bitmap_empty((map).mask, MAX_APICS)
31 #define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS)
32 #define physids_weight(map) bitmap_weight((map).mask, MAX_APICS)
33 #define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS)
34 #define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS)
35 #define physids_coerce(map) ((map).mask[0])
40 __physid_mask.mask[0] = physids; \
86 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
H A Ducontext.h9 sigset_t uc_sigmask; /* mask last for extensibility */
/linux-4.4.14/arch/sh/include/asm/
H A Dbitops-llsc.h6 int mask; set_bit() local
11 mask = 1 << (nr & 0x1f); set_bit()
20 : "r" (a), "r" (mask) set_bit()
27 int mask; clear_bit() local
32 mask = 1 << (nr & 0x1f); clear_bit()
41 : "r" (a), "r" (~mask) clear_bit()
48 int mask; change_bit() local
53 mask = 1 << (nr & 0x1f); change_bit()
62 : "r" (a), "r" (mask) change_bit()
69 int mask, retval; test_and_set_bit() local
74 mask = 1 << (nr & 0x1f); test_and_set_bit()
85 : "r" (a), "r" (mask) test_and_set_bit()
94 int mask, retval; test_and_clear_bit() local
99 mask = 1 << (nr & 0x1f); test_and_clear_bit()
111 : "r" (a), "r" (mask), "r" (~mask) test_and_clear_bit()
120 int mask, retval; test_and_change_bit() local
125 mask = 1 << (nr & 0x1f); test_and_change_bit()
137 : "r" (a), "r" (mask) test_and_change_bit()
H A Dword-at-a-time.h17 static inline long count_masked_bytes(long mask) count_masked_bytes() argument
20 long a = (0x0ff0001+mask) >> 23; count_masked_bytes()
22 return a & mask; count_masked_bytes()
28 unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; has_zero() local
29 *bits = mask; has_zero()
30 return mask; has_zero()
44 /* The mask we created is directly usable as a bytemask */
45 #define zero_bytemask(mask) (mask)
47 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
49 return count_masked_bytes(mask); find_zero()
H A Dbitops-grb.h6 int mask; set_bit() local
11 mask = 1 << (nr & 0x1f); set_bit()
24 : "r" (mask) set_bit()
30 int mask; clear_bit() local
35 mask = ~(1 << (nr & 0x1f)); clear_bit()
47 : "r" (mask) clear_bit()
53 int mask; change_bit() local
58 mask = 1 << (nr & 0x1f); change_bit()
70 : "r" (mask) change_bit()
76 int mask, retval; test_and_set_bit() local
81 mask = 1 << (nr & 0x1f); test_and_set_bit()
90 " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ test_and_set_bit()
92 " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ test_and_set_bit()
99 : "r" (mask) test_and_set_bit()
107 int mask, retval,not_mask; test_and_clear_bit() local
112 mask = 1 << (nr & 0x1f); test_and_clear_bit()
114 not_mask = ~mask; test_and_clear_bit()
123 " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ test_and_clear_bit()
125 " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ test_and_clear_bit()
132 : "r" (mask), test_and_clear_bit()
141 int mask, retval; test_and_change_bit() local
146 mask = 1 << (nr & 0x1f); test_and_change_bit()
155 " tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */ test_and_change_bit()
157 " negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */ test_and_change_bit()
164 : "r" (mask) test_and_change_bit()
H A Dheartbeat.h14 unsigned int mask; member in struct:heartbeat_data
H A Dbitops-op32.h30 unsigned long mask = BIT_MASK(nr); __set_bit() local
33 *p |= mask; __set_bit()
48 unsigned long mask = BIT_MASK(nr); __clear_bit() local
51 *p &= ~mask; __clear_bit()
75 unsigned long mask = BIT_MASK(nr); __change_bit() local
78 *p ^= mask; __change_bit()
93 unsigned long mask = BIT_MASK(nr); __test_and_set_bit() local
97 *p = old | mask; __test_and_set_bit()
98 return (old & mask) != 0; __test_and_set_bit()
112 unsigned long mask = BIT_MASK(nr); __test_and_clear_bit() local
116 *p = old & ~mask; __test_and_clear_bit()
117 return (old & mask) != 0; __test_and_clear_bit()
124 unsigned long mask = BIT_MASK(nr); __test_and_change_bit() local
128 *p = old ^ mask; __test_and_change_bit()
129 return (old & mask) != 0; __test_and_change_bit()
/linux-4.4.14/include/linux/ssb/
H A Dssb_embedded.h11 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask);
12 u32 ssb_gpio_out(struct ssb_bus *bus, u32 mask, u32 value);
13 u32 ssb_gpio_outen(struct ssb_bus *bus, u32 mask, u32 value);
14 u32 ssb_gpio_control(struct ssb_bus *bus, u32 mask, u32 value);
15 u32 ssb_gpio_intmask(struct ssb_bus *bus, u32 mask, u32 value);
16 u32 ssb_gpio_polarity(struct ssb_bus *bus, u32 mask, u32 value);
/linux-4.4.14/include/uapi/linux/netfilter/
H A Dxt_mark.h7 __u32 mark, mask; member in struct:xt_mark_tginfo2
11 __u32 mark, mask; member in struct:xt_mark_mtinfo1
H A Dxt_addrtype.h31 __u16 source; /* source-type mask */
32 __u16 dest; /* dest-type mask */
38 __u16 source; /* source-type mask */
39 __u16 dest; /* dest-type mask */
H A Dxt_realm.h8 __u32 mask; member in struct:xt_realm_info
/linux-4.4.14/kernel/time/
H A Dtimekeeping_internal.h16 static inline cycle_t clocksource_delta(cycle_t now, cycle_t last, cycle_t mask) clocksource_delta() argument
18 cycle_t ret = (now - last) & mask; clocksource_delta()
23 static inline cycle_t clocksource_delta(cycle_t now, cycle_t last, cycle_t mask) clocksource_delta() argument
25 return (now - last) & mask; clocksource_delta()
H A Dtimecounter.c28 tc->mask = (1ULL << cc->shift) - 1; timecounter_init()
53 cycle_delta = (cycle_now - tc->cycle_last) & tc->cc->mask; timecounter_read_delta()
57 tc->mask, &tc->frac); timecounter_read_delta()
83 cycle_t cycles, u64 mask, u64 frac) cc_cyc2ns_backwards()
95 u64 delta = (cycle_tstamp - tc->cycle_last) & tc->cc->mask; timecounter_cyc2time()
103 if (delta > tc->cc->mask / 2) { timecounter_cyc2time()
104 delta = (tc->cycle_last - cycle_tstamp) & tc->cc->mask; timecounter_cyc2time()
105 nsec -= cc_cyc2ns_backwards(tc->cc, delta, tc->mask, frac); timecounter_cyc2time()
107 nsec += cyclecounter_cyc2ns(tc->cc, delta, tc->mask, &frac); timecounter_cyc2time()
82 cc_cyc2ns_backwards(const struct cyclecounter *cc, cycle_t cycles, u64 mask, u64 frac) cc_cyc2ns_backwards() argument
/linux-4.4.14/include/sound/
H A Dpcm_params.h46 static inline void snd_mask_none(struct snd_mask *mask) snd_mask_none() argument
48 memset(mask, 0, sizeof(*mask)); snd_mask_none()
51 static inline void snd_mask_any(struct snd_mask *mask) snd_mask_any() argument
53 memset(mask, 0xff, SNDRV_MASK_SIZE * sizeof(u_int32_t)); snd_mask_any()
56 static inline int snd_mask_empty(const struct snd_mask *mask) snd_mask_empty() argument
60 if (mask->bits[i]) snd_mask_empty()
65 static inline unsigned int snd_mask_min(const struct snd_mask *mask) snd_mask_min() argument
69 if (mask->bits[i]) snd_mask_min()
70 return __ffs(mask->bits[i]) + (i << 5); snd_mask_min()
75 static inline unsigned int snd_mask_max(const struct snd_mask *mask) snd_mask_max() argument
79 if (mask->bits[i]) snd_mask_max()
80 return __fls(mask->bits[i]) + (i << 5); snd_mask_max()
85 static inline void snd_mask_set(struct snd_mask *mask, unsigned int val) snd_mask_set() argument
87 mask->bits[MASK_OFS(val)] |= MASK_BIT(val); snd_mask_set()
90 static inline void snd_mask_reset(struct snd_mask *mask, unsigned int val) snd_mask_reset() argument
92 mask->bits[MASK_OFS(val)] &= ~MASK_BIT(val); snd_mask_reset()
95 static inline void snd_mask_set_range(struct snd_mask *mask, snd_mask_set_range() argument
100 mask->bits[MASK_OFS(i)] |= MASK_BIT(i); snd_mask_set_range()
103 static inline void snd_mask_reset_range(struct snd_mask *mask, snd_mask_reset_range() argument
108 mask->bits[MASK_OFS(i)] &= ~MASK_BIT(i); snd_mask_reset_range()
111 static inline void snd_mask_leave(struct snd_mask *mask, unsigned int val) snd_mask_leave() argument
114 v = mask->bits[MASK_OFS(val)] & MASK_BIT(val); snd_mask_leave()
115 snd_mask_none(mask); snd_mask_leave()
116 mask->bits[MASK_OFS(val)] = v; snd_mask_leave()
119 static inline void snd_mask_intersect(struct snd_mask *mask, snd_mask_intersect() argument
124 mask->bits[i] &= v->bits[i]; snd_mask_intersect()
127 static inline int snd_mask_eq(const struct snd_mask *mask, snd_mask_eq() argument
130 return ! memcmp(mask, v, SNDRV_MASK_SIZE * sizeof(u_int32_t)); snd_mask_eq()
133 static inline void snd_mask_copy(struct snd_mask *mask, snd_mask_copy() argument
136 *mask = *v; snd_mask_copy()
139 static inline int snd_mask_test(const struct snd_mask *mask, unsigned int val) snd_mask_test() argument
141 return mask->bits[MASK_OFS(val)] & MASK_BIT(val); snd_mask_test()
144 static inline int snd_mask_single(const struct snd_mask *mask) snd_mask_single() argument
148 if (! mask->bits[i]) snd_mask_single()
150 if (mask->bits[i] & (mask->bits[i] - 1)) snd_mask_single()
159 static inline int snd_mask_refine(struct snd_mask *mask, snd_mask_refine() argument
163 snd_mask_copy(&old, mask); snd_mask_refine()
164 snd_mask_intersect(mask, v); snd_mask_refine()
165 if (snd_mask_empty(mask)) snd_mask_refine()
167 return !snd_mask_eq(mask, &old); snd_mask_refine()
170 static inline int snd_mask_refine_first(struct snd_mask *mask) snd_mask_refine_first() argument
172 if (snd_mask_single(mask)) snd_mask_refine_first()
174 snd_mask_leave(mask, snd_mask_min(mask)); snd_mask_refine_first()
178 static inline int snd_mask_refine_last(struct snd_mask *mask) snd_mask_refine_last() argument
180 if (snd_mask_single(mask)) snd_mask_refine_last()
182 snd_mask_leave(mask, snd_mask_max(mask)); snd_mask_refine_last()
186 static inline int snd_mask_refine_min(struct snd_mask *mask, unsigned int val) snd_mask_refine_min() argument
188 if (snd_mask_min(mask) >= val) snd_mask_refine_min()
190 snd_mask_reset_range(mask, 0, val - 1); snd_mask_refine_min()
191 if (snd_mask_empty(mask)) snd_mask_refine_min()
196 static inline int snd_mask_refine_max(struct snd_mask *mask, unsigned int val) snd_mask_refine_max() argument
198 if (snd_mask_max(mask) <= val) snd_mask_refine_max()
200 snd_mask_reset_range(mask, val + 1, SNDRV_MASK_BITS); snd_mask_refine_max()
201 if (snd_mask_empty(mask)) snd_mask_refine_max()
206 static inline int snd_mask_refine_set(struct snd_mask *mask, unsigned int val) snd_mask_refine_set() argument
209 changed = !snd_mask_single(mask); snd_mask_refine_set()
210 snd_mask_leave(mask, val); snd_mask_refine_set()
211 if (snd_mask_empty(mask)) snd_mask_refine_set()
216 static inline int snd_mask_value(const struct snd_mask *mask) snd_mask_value() argument
218 return snd_mask_min(mask); snd_mask_value()
/linux-4.4.14/tools/perf/util/
H A Dperf_regs.c13 u64 mask = regs->mask; perf_reg_value() local
18 if (!(mask & (1 << id))) perf_reg_value()
22 if (mask & (1 << i)) perf_reg_value()
H A Dperf_regs.h11 uint64_t mask; member in struct:sample_reg
13 #define SMPL_REG(n, b) { .name = #n, .mask = 1ULL << (b) }
/linux-4.4.14/arch/arm/plat-samsung/
H A Dwakeup-mask.c1 /* arch/arm/plat-samsung/wakeup-mask.c
5 * Support for wakeup mask interrupts on newer SoCs
19 #include <plat/wakeup-mask.h>
23 struct samsung_wakeup_mask *mask, int nr_mask) samsung_sync_wakemask()
30 for (; nr_mask > 0; nr_mask--, mask++) { samsung_sync_wakemask()
31 if (mask->irq == NO_WAKEUP_IRQ) { samsung_sync_wakemask()
32 val |= mask->bit; samsung_sync_wakemask()
36 data = irq_get_irq_data(mask->irq); samsung_sync_wakemask()
40 val &= ~mask->bit; samsung_sync_wakemask()
42 val |= mask->bit; samsung_sync_wakemask()
22 samsung_sync_wakemask(void __iomem *reg, struct samsung_wakeup_mask *mask, int nr_mask) samsung_sync_wakemask() argument
/linux-4.4.14/drivers/video/fbdev/core/
H A Dfb_draw.h10 * This is equivalent to (a & mask) | (b & ~mask)
14 comp(unsigned long a, unsigned long b, unsigned long mask) comp() argument
16 return ((a ^ b) & mask) ^ b; comp()
103 u32 mask; fb_shifted_pixels_mask_u32() local
106 mask = FB_SHIFT_HIGH(p, ~(u32)0, index); fb_shifted_pixels_mask_u32()
108 mask = 0xff << FB_LEFT_POS(p, 8); fb_shifted_pixels_mask_u32()
109 mask = FB_SHIFT_LOW(p, mask, index & (bswapmask)) & mask; fb_shifted_pixels_mask_u32()
110 mask = FB_SHIFT_HIGH(p, mask, index & ~(bswapmask)); fb_shifted_pixels_mask_u32()
115 mask |= FB_SHIFT_HIGH(p, ~(u32)0, fb_shifted_pixels_mask_u32()
118 return mask; fb_shifted_pixels_mask_u32()
125 unsigned long mask; fb_shifted_pixels_mask_long() local
128 mask = FB_SHIFT_HIGH(p, ~0UL, index); fb_shifted_pixels_mask_long()
130 mask = 0xff << FB_LEFT_POS(p, 8); fb_shifted_pixels_mask_long()
131 mask = FB_SHIFT_LOW(p, mask, index & (bswapmask)) & mask; fb_shifted_pixels_mask_long()
132 mask = FB_SHIFT_HIGH(p, mask, index & ~(bswapmask)); fb_shifted_pixels_mask_long()
137 mask |= FB_SHIFT_HIGH(p, ~0UL, fb_shifted_pixels_mask_long()
140 return mask; fb_shifted_pixels_mask_long()
/linux-4.4.14/arch/x86/include/asm/
H A Dmpspec.h93 unsigned long mask[PHYSID_ARRAY_SIZE]; early_reserve_e820_mpc_new() member in struct:physid_mask
98 #define physid_set(physid, map) set_bit(physid, (map).mask)
99 #define physid_clear(physid, map) clear_bit(physid, (map).mask)
100 #define physid_isset(physid, map) test_bit(physid, (map).mask)
102 test_and_set_bit(physid, (map).mask)
105 bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
108 bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_LOCAL_APIC)
111 bitmap_zero((map).mask, MAX_LOCAL_APIC)
114 bitmap_complement((dst).mask, (src).mask, MAX_LOCAL_APIC)
117 bitmap_empty((map).mask, MAX_LOCAL_APIC)
120 bitmap_equal((map1).mask, (map2).mask, MAX_LOCAL_APIC)
123 bitmap_weight((map).mask, MAX_LOCAL_APIC)
126 bitmap_shift_right((d).mask, (s).mask, n, MAX_LOCAL_APIC)
129 bitmap_shift_left((d).mask, (s).mask, n, MAX_LOCAL_APIC)
133 return map->mask[0]; physids_coerce()
139 map->mask[0] = physids; physids_promote()
H A Dword-at-a-time.h8 * optimal byte mask counting is probably going to be something
23 * the simpler "(mask & ONEBYTES) * ONEBYTES >> 56"
25 * mask them first.
27 static inline long count_masked_bytes(unsigned long mask) count_masked_bytes() argument
29 return mask*0x0001020304050608ul >> 56; count_masked_bytes()
35 static inline long count_masked_bytes(long mask) count_masked_bytes() argument
38 long a = (0x0ff0001+mask) >> 23; count_masked_bytes()
40 return a & mask; count_masked_bytes()
48 unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; has_zero() local
49 *bits = mask; has_zero()
50 return mask; has_zero()
64 /* The mask we created is directly usable as a bytemask */
65 #define zero_bytemask(mask) (mask)
67 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
69 return count_masked_bytes(mask); find_zero()
H A Dipi.h49 static inline int __prepare_ICR2(unsigned int mask) __prepare_ICR2() argument
51 return SET_APIC_DEST_FIELD(mask); __prepare_ICR2()
93 __default_send_IPI_dest_field(unsigned int mask, int vector, unsigned int dest) __default_send_IPI_dest_field() argument
108 cfg = __prepare_ICR2(mask); __default_send_IPI_dest_field()
122 extern void default_send_IPI_mask_sequence_phys(const struct cpumask *mask,
124 extern void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask,
149 extern void default_send_IPI_mask_sequence_logical(const struct cpumask *mask,
151 extern void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask,
153 extern void default_send_IPI_mask_logical(const struct cpumask *mask,
/linux-4.4.14/arch/arm/mach-lpc32xx/
H A Dirq.c78 u32 mask; member in struct:lpc32xx_event_info
82 * Maps an IRQ number to and event mask and register
87 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
91 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
95 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
99 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
103 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
107 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
111 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
115 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
119 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
123 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
127 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
131 .mask = LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT,
135 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
139 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
143 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
147 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
151 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
155 .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
159 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
163 .mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
167 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
171 .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
175 .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
179 .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
183 .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
187 .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
191 .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
212 unsigned int reg, ctrl, mask; lpc32xx_mask_irq() local
214 get_controller(d->hwirq, &ctrl, &mask); lpc32xx_mask_irq()
216 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask; lpc32xx_mask_irq()
222 unsigned int reg, ctrl, mask; lpc32xx_unmask_irq() local
224 get_controller(d->hwirq, &ctrl, &mask); lpc32xx_unmask_irq()
226 reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask; lpc32xx_unmask_irq()
232 unsigned int ctrl, mask; lpc32xx_ack_irq() local
234 get_controller(d->hwirq, &ctrl, &mask); lpc32xx_ack_irq()
236 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); lpc32xx_ack_irq()
239 if (lpc32xx_events[d->hwirq].mask != 0) lpc32xx_ack_irq()
240 __raw_writel(lpc32xx_events[d->hwirq].mask, lpc32xx_ack_irq()
247 unsigned int reg, ctrl, mask; __lpc32xx_set_irq_type() local
249 get_controller(irq, &ctrl, &mask); __lpc32xx_set_irq_type()
254 reg |= mask; __lpc32xx_set_irq_type()
256 reg &= ~mask; __lpc32xx_set_irq_type()
262 reg |= mask; __lpc32xx_set_irq_type()
264 reg &= ~mask; __lpc32xx_set_irq_type()
268 if (lpc32xx_events[irq].mask != 0) { __lpc32xx_set_irq_type()
272 reg |= lpc32xx_events[irq].mask; __lpc32xx_set_irq_type()
274 reg &= ~lpc32xx_events[irq].mask; __lpc32xx_set_irq_type()
319 if (lpc32xx_events[d->hwirq].mask != 0) { lpc32xx_irq_wake()
324 eventreg |= lpc32xx_events[d->hwirq].mask; lpc32xx_irq_wake()
326 eventreg &= ~lpc32xx_events[d->hwirq].mask; lpc32xx_irq_wake()
332 __raw_writel(lpc32xx_events[d->hwirq].mask, lpc32xx_irq_wake()
344 __raw_writel(lpc32xx_events[d->hwirq].mask, lpc32xx_irq_wake()
/linux-4.4.14/arch/metag/include/asm/
H A Dbitops.h15 unsigned long mask = 1UL << (bit & 31); set_bit() local
21 *p |= mask; set_bit()
28 unsigned long mask = 1UL << (bit & 31); clear_bit() local
34 *p &= ~mask; clear_bit()
41 unsigned long mask = 1UL << (bit & 31); change_bit() local
47 *p ^= mask; change_bit()
55 unsigned long mask = 1UL << (bit & 31); test_and_set_bit() local
61 if (!(old & mask)) { test_and_set_bit()
63 *p = old | mask; test_and_set_bit()
67 return (old & mask) != 0; test_and_set_bit()
75 unsigned long mask = 1UL << (bit & 31); test_and_clear_bit() local
81 if (old & mask) { test_and_clear_bit()
83 *p = old & ~mask; test_and_clear_bit()
87 return (old & mask) != 0; test_and_clear_bit()
95 unsigned long mask = 1UL << (bit & 31); test_and_change_bit() local
102 *p = old ^ mask; test_and_change_bit()
105 return (old & mask) != 0; test_and_change_bit()
/linux-4.4.14/drivers/gpio/
H A Dgpio-loongson.c40 u32 mask; loongson_gpio_direction_input() local
43 mask = 1 << gpio; loongson_gpio_direction_input()
45 temp |= mask; loongson_gpio_direction_input()
56 u32 mask; loongson_gpio_direction_output() local
60 mask = 1 << gpio; loongson_gpio_direction_output()
62 temp &= (~mask); loongson_gpio_direction_output()
72 u32 mask; loongson_gpio_get_value() local
74 mask = 1 << (gpio + LOONGSON_GPIO_IN_OFFSET); loongson_gpio_get_value()
79 return (val & mask) != 0; loongson_gpio_get_value()
86 u32 mask; loongson_gpio_set_value() local
88 mask = 1 << gpio; loongson_gpio_set_value()
93 val |= mask; loongson_gpio_set_value()
95 val &= (~mask); loongson_gpio_set_value()
H A Dgpio-vr41xx.c235 u16 mask; vr41xx_set_irq_trigger() local
238 mask = 1 << pin; vr41xx_set_irq_trigger()
240 giu_set(GIUINTTYPL, mask); vr41xx_set_irq_trigger()
242 giu_set(GIUINTHTSELL, mask); vr41xx_set_irq_trigger()
244 giu_clear(GIUINTHTSELL, mask); vr41xx_set_irq_trigger()
248 giu_set(GIUFEDGEINHL, mask); vr41xx_set_irq_trigger()
249 giu_clear(GIUREDGEINHL, mask); vr41xx_set_irq_trigger()
252 giu_clear(GIUFEDGEINHL, mask); vr41xx_set_irq_trigger()
253 giu_set(GIUREDGEINHL, mask); vr41xx_set_irq_trigger()
256 giu_set(GIUFEDGEINHL, mask); vr41xx_set_irq_trigger()
257 giu_set(GIUREDGEINHL, mask); vr41xx_set_irq_trigger()
265 giu_clear(GIUINTTYPL, mask); vr41xx_set_irq_trigger()
266 giu_clear(GIUINTHTSELL, mask); vr41xx_set_irq_trigger()
271 giu_write(GIUINTSTATL, mask); vr41xx_set_irq_trigger()
273 mask = 1 << (pin - GIUINT_HIGH_OFFSET); vr41xx_set_irq_trigger()
275 giu_set(GIUINTTYPH, mask); vr41xx_set_irq_trigger()
277 giu_set(GIUINTHTSELH, mask); vr41xx_set_irq_trigger()
279 giu_clear(GIUINTHTSELH, mask); vr41xx_set_irq_trigger()
283 giu_set(GIUFEDGEINHH, mask); vr41xx_set_irq_trigger()
284 giu_clear(GIUREDGEINHH, mask); vr41xx_set_irq_trigger()
287 giu_clear(GIUFEDGEINHH, mask); vr41xx_set_irq_trigger()
288 giu_set(GIUREDGEINHH, mask); vr41xx_set_irq_trigger()
291 giu_set(GIUFEDGEINHH, mask); vr41xx_set_irq_trigger()
292 giu_set(GIUREDGEINHH, mask); vr41xx_set_irq_trigger()
300 giu_clear(GIUINTTYPH, mask); vr41xx_set_irq_trigger()
301 giu_clear(GIUINTHTSELH, mask); vr41xx_set_irq_trigger()
306 giu_write(GIUINTSTATH, mask); vr41xx_set_irq_trigger()
313 u16 mask; vr41xx_set_irq_level() local
316 mask = 1 << pin; vr41xx_set_irq_level()
318 giu_set(GIUINTALSELL, mask); vr41xx_set_irq_level()
320 giu_clear(GIUINTALSELL, mask); vr41xx_set_irq_level()
321 giu_write(GIUINTSTATL, mask); vr41xx_set_irq_level()
323 mask = 1 << (pin - GIUINT_HIGH_OFFSET); vr41xx_set_irq_level()
325 giu_set(GIUINTALSELH, mask); vr41xx_set_irq_level()
327 giu_clear(GIUINTALSELH, mask); vr41xx_set_irq_level()
328 giu_write(GIUINTSTATH, mask); vr41xx_set_irq_level()
335 u16 offset, mask, reg; giu_set_direction() local
343 mask = 1 << pin; giu_set_direction()
346 mask = 1 << (pin - 16); giu_set_direction()
350 mask = 1 << (pin - 32); giu_set_direction()
355 mask = PIOEN0; giu_set_direction()
359 mask = PIOEN1; giu_set_direction()
371 reg |= mask; giu_set_direction()
373 reg &= ~mask; giu_set_direction()
383 u16 reg, mask; vr41xx_gpio_pullupdown() local
392 mask = 1 << pin; vr41xx_gpio_pullupdown()
399 reg |= mask; vr41xx_gpio_pullupdown()
401 reg &= ~mask; vr41xx_gpio_pullupdown()
405 reg |= mask; vr41xx_gpio_pullupdown()
409 reg &= ~mask; vr41xx_gpio_pullupdown()
421 u16 reg, mask; vr41xx_gpio_get() local
428 mask = 1 << pin; vr41xx_gpio_get()
431 mask = 1 << (pin - 16); vr41xx_gpio_get()
434 mask = 1 << (pin - 32); vr41xx_gpio_get()
437 mask = 1 << (pin - 48); vr41xx_gpio_get()
440 if (reg & mask) vr41xx_gpio_get()
449 u16 offset, mask, reg; vr41xx_gpio_set() local
457 mask = 1 << pin; vr41xx_gpio_set()
460 mask = 1 << (pin - 16); vr41xx_gpio_set()
463 mask = 1 << (pin - 32); vr41xx_gpio_set()
466 mask = 1 << (pin - 48); vr41xx_gpio_set()
473 reg |= mask; vr41xx_gpio_set()
475 reg &= ~mask; vr41xx_gpio_set()
H A Dgpio-sa1100.c79 unsigned int mask; sa1100_gpio_type() local
81 mask = BIT(d->hwirq); sa1100_gpio_type()
84 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) sa1100_gpio_type()
90 GPIO_IRQ_rising_edge |= mask; sa1100_gpio_type()
92 GPIO_IRQ_rising_edge &= ~mask; sa1100_gpio_type()
94 GPIO_IRQ_falling_edge |= mask; sa1100_gpio_type()
96 GPIO_IRQ_falling_edge &= ~mask; sa1100_gpio_type()
114 unsigned int mask = BIT(d->hwirq); sa1100_gpio_mask() local
116 GPIO_IRQ_mask &= ~mask; sa1100_gpio_mask()
118 GRER &= ~mask; sa1100_gpio_mask()
119 GFER &= ~mask; sa1100_gpio_mask()
124 unsigned int mask = BIT(d->hwirq); sa1100_gpio_unmask() local
126 GPIO_IRQ_mask |= mask; sa1100_gpio_unmask()
177 unsigned int irq, mask; sa1100_gpio_handler() local
179 mask = GEDR; sa1100_gpio_handler()
185 GEDR = mask; sa1100_gpio_handler()
189 if (mask & 1) sa1100_gpio_handler()
191 mask >>= 1; sa1100_gpio_handler()
193 } while (mask); sa1100_gpio_handler()
195 mask = GEDR; sa1100_gpio_handler()
196 } while (mask); sa1100_gpio_handler()
H A Dgpio-stmpe.c49 u8 mask = 1 << (offset % 8); stmpe_gpio_get() local
56 return !!(ret & mask); stmpe_gpio_get()
65 u8 mask = 1 << (offset % 8); stmpe_gpio_set() local
72 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0); stmpe_gpio_set()
74 stmpe_reg_write(stmpe, reg, mask); stmpe_gpio_set()
83 u8 mask = 1 << (offset % 8); stmpe_gpio_direction_output() local
87 return stmpe_set_bits(stmpe, reg, mask, mask); stmpe_gpio_direction_output()
96 u8 mask = 1 << (offset % 8); stmpe_gpio_direction_input() local
98 return stmpe_set_bits(stmpe, reg, mask, 0); stmpe_gpio_direction_input()
129 int mask = 1 << (offset % 8); stmpe_gpio_irq_set_type() local
139 stmpe_gpio->regs[REG_RE][regoffset] |= mask; stmpe_gpio_irq_set_type()
141 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask; stmpe_gpio_irq_set_type()
144 stmpe_gpio->regs[REG_FE][regoffset] |= mask; stmpe_gpio_irq_set_type()
146 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask; stmpe_gpio_irq_set_type()
199 int mask = 1 << (offset % 8); stmpe_gpio_irq_mask() local
201 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask; stmpe_gpio_irq_mask()
210 int mask = 1 << (offset % 8); stmpe_gpio_irq_unmask() local
212 stmpe_gpio->regs[REG_IE][regoffset] |= mask; stmpe_gpio_irq_unmask()
225 u8 mask = 1 << (offset % 8); stmpe_dbg_show_one() local
232 dir = !!(ret & mask); stmpe_dbg_show_one()
251 edge_det = !!(ret & mask); stmpe_dbg_show_one()
255 rise = !!(ret & mask); stmpe_dbg_show_one()
259 fall = !!(ret & mask); stmpe_dbg_show_one()
263 irqen = !!(ret & mask); stmpe_dbg_show_one()
366 of_property_read_u32(np, "st,norequest-mask", stmpe_gpio_probe()
/linux-4.4.14/arch/powerpc/lib/
H A Dalloc.c9 void * __init_refok zalloc_maybe_bootmem(size_t size, gfp_t mask) zalloc_maybe_bootmem() argument
14 p = kzalloc(size, mask); zalloc_maybe_bootmem()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dhwsq.h16 u32 mask; member in struct:hwsq_reg
21 hwsq_stride(u32 addr, u32 stride, u32 mask) hwsq_stride() argument
28 .mask = mask, hwsq_stride()
41 .mask = 0x3, hwsq_reg2()
54 .mask = 0x1, hwsq_reg()
96 u32 mask, off = 0; hwsq_wr32() local
101 for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { hwsq_wr32()
102 if (mask & 1) hwsq_wr32()
116 hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data) hwsq_mask() argument
119 if (temp != ((temp & ~mask) | data) || reg->force) hwsq_mask()
120 hwsq_wr32(ram, reg, (temp & ~mask) | data); hwsq_mask()
/linux-4.4.14/drivers/memory/tegra/
H A Dtegra114.c32 .mask = 0xff,
46 .mask = 0xff,
60 .mask = 0xff,
74 .mask = 0xff,
88 .mask = 0xff,
102 .mask = 0xff,
116 .mask = 0xff,
130 .mask = 0xff,
144 .mask = 0xff,
158 .mask = 0xff,
172 .mask = 0xff,
186 .mask = 0xff,
200 .mask = 0xff,
214 .mask = 0xff,
228 .mask = 0xff,
242 .mask = 0xff,
256 .mask = 0xff,
270 .mask = 0xff,
284 .mask = 0xff,
298 .mask = 0xff,
312 .mask = 0xff,
326 .mask = 0xff,
340 .mask = 0xff,
354 .mask = 0xff,
368 .mask = 0xff,
382 .mask = 0xff,
396 .mask = 0xff,
406 .mask = 0xff,
416 .mask = 0xff,
430 .mask = 0xff,
444 .mask = 0xff,
458 .mask = 0xff,
472 .mask = 0xff,
486 .mask = 0xff,
500 .mask = 0xff,
514 .mask = 0xff,
528 .mask = 0xff,
542 .mask = 0xff,
556 .mask = 0xff,
570 .mask = 0xff,
584 .mask = 0xff,
598 .mask = 0xff,
612 .mask = 0xff,
626 .mask = 0xff,
636 .mask = 0xff,
646 .mask = 0xff,
660 .mask = 0xff,
674 .mask = 0xff,
688 .mask = 0xff,
702 .mask = 0xff,
716 .mask = 0xff,
730 .mask = 0xff,
744 .mask = 0xff,
758 .mask = 0xff,
772 .mask = 0xff,
786 .mask = 0xff,
800 .mask = 0xff,
814 .mask = 0xff,
828 .mask = 0xff,
842 .mask = 0xff,
852 .mask = 0xff,
862 .mask = 0xff,
876 .mask = 0xff,
890 .mask = 0xff,
H A Dtegra210.c34 .mask = 0xff,
48 .mask = 0xff,
62 .mask = 0xff,
76 .mask = 0xff,
90 .mask = 0xff,
104 .mask = 0xff,
118 .mask = 0xff,
132 .mask = 0xff,
146 .mask = 0xff,
160 .mask = 0xff,
174 .mask = 0xff,
188 .mask = 0xff,
202 .mask = 0xff,
216 .mask = 0xff,
230 .mask = 0xff,
244 .mask = 0xff,
258 .mask = 0xff,
268 .mask = 0xff,
282 .mask = 0xff,
296 .mask = 0xff,
310 .mask = 0xff,
324 .mask = 0xff,
338 .mask = 0xff,
348 .mask = 0xff,
362 .mask = 0xff,
376 .mask = 0xff,
390 .mask = 0xff,
404 .mask = 0xff,
418 .mask = 0xff,
432 .mask = 0xff,
446 .mask = 0xff,
460 .mask = 0xff,
474 .mask = 0xff,
488 .mask = 0xff,
502 .mask = 0xff,
516 .mask = 0xff,
530 .mask = 0xff,
544 .mask = 0xff,
558 .mask = 0xff,
572 .mask = 0xff,
586 .mask = 0xff,
601 .mask = 0xff,
616 .mask = 0xff,
630 .mask = 0xff,
644 .mask = 0xff,
658 .mask = 0xff,
672 .mask = 0xff,
686 .mask = 0xff,
700 .mask = 0xff,
714 .mask = 0xff,
728 .mask = 0xff,
742 .mask = 0xff,
756 .mask = 0xff,
770 .mask = 0xff,
784 .mask = 0xff,
798 .mask = 0xff,
812 .mask = 0xff,
826 .mask = 0xff,
840 .mask = 0xff,
854 .mask = 0xff,
868 .mask = 0xff,
882 .mask = 0xff,
896 .mask = 0xff,
910 .mask = 0xff,
924 .mask = 0xff,
938 .mask = 0xff,
952 .mask = 0xff,
966 .mask = 0xff,
980 .mask = 0xff,
994 .mask = 0xff,
1009 .mask = 0xff,
1024 .mask = 0xff,
H A Dtegra124.c74 .mask = 0xff,
88 .mask = 0xff,
102 .mask = 0xff,
116 .mask = 0xff,
130 .mask = 0xff,
144 .mask = 0xff,
158 .mask = 0xff,
172 .mask = 0xff,
186 .mask = 0xff,
200 .mask = 0xff,
214 .mask = 0xff,
228 .mask = 0xff,
242 .mask = 0xff,
256 .mask = 0xff,
270 .mask = 0xff,
284 .mask = 0xff,
298 .mask = 0xff,
312 .mask = 0xff,
326 .mask = 0xff,
340 .mask = 0xff,
354 .mask = 0xff,
364 .mask = 0xff,
374 .mask = 0xff,
388 .mask = 0xff,
402 .mask = 0xff,
416 .mask = 0xff,
430 .mask = 0xff,
444 .mask = 0xff,
454 .mask = 0xff,
464 .mask = 0xff,
478 .mask = 0xff,
492 .mask = 0xff,
506 .mask = 0xff,
520 .mask = 0xff,
534 .mask = 0xff,
548 .mask = 0xff,
562 .mask = 0xff,
576 .mask = 0xff,
590 .mask = 0xff,
604 .mask = 0xff,
618 .mask = 0xff,
632 .mask = 0xff,
646 .mask = 0xff,
660 .mask = 0xff,
674 .mask = 0xff,
688 .mask = 0xff,
702 .mask = 0xff,
716 .mask = 0xff,
730 .mask = 0xff,
744 .mask = 0xff,
758 .mask = 0xff,
773 .mask = 0xff,
788 .mask = 0xff,
802 .mask = 0xff,
816 .mask = 0xff,
830 .mask = 0xff,
844 .mask = 0xff,
858 .mask = 0xff,
872 .mask = 0xff,
886 .mask = 0xff,
900 .mask = 0xff,
914 .mask = 0xff,
928 .mask = 0xff,
942 .mask = 0xff,
956 .mask = 0xff,
970 .mask = 0xff,
H A Dtegra30.c32 .mask = 0xff,
46 .mask = 0xff,
60 .mask = 0xff,
74 .mask = 0xff,
88 .mask = 0xff,
102 .mask = 0xff,
116 .mask = 0xff,
130 .mask = 0xff,
144 .mask = 0xff,
158 .mask = 0xff,
172 .mask = 0xff,
186 .mask = 0xff,
200 .mask = 0xff,
214 .mask = 0xff,
228 .mask = 0xff,
242 .mask = 0xff,
256 .mask = 0xff,
270 .mask = 0xff,
284 .mask = 0xff,
298 .mask = 0xff,
312 .mask = 0xff,
326 .mask = 0xff,
340 .mask = 0xff,
354 .mask = 0xff,
368 .mask = 0xff,
382 .mask = 0xff,
396 .mask = 0xff,
410 .mask = 0xff,
424 .mask = 0xff,
438 .mask = 0xff,
452 .mask = 0xff,
466 .mask = 0xff,
480 .mask = 0xff,
494 .mask = 0xff,
508 .mask = 0xff,
522 .mask = 0xff,
536 .mask = 0xff,
546 .mask = 0xff,
556 .mask = 0xff,
570 .mask = 0xff,
584 .mask = 0xff,
598 .mask = 0xff,
612 .mask = 0xff,
626 .mask = 0xff,
640 .mask = 0xff,
654 .mask = 0xff,
668 .mask = 0xff,
682 .mask = 0xff,
696 .mask = 0xff,
710 .mask = 0xff,
724 .mask = 0xff,
738 .mask = 0xff,
752 .mask = 0xff,
766 .mask = 0xff,
780 .mask = 0xff,
790 .mask = 0xff,
800 .mask = 0xff,
814 .mask = 0xff,
828 .mask = 0xff,
842 .mask = 0xff,
856 .mask = 0xff,
870 .mask = 0xff,
884 .mask = 0xff,
898 .mask = 0xff,
912 .mask = 0xff,
/linux-4.4.14/include/linux/
H A Ddevice_cgroup.h4 extern int __devcgroup_inode_permission(struct inode *inode, int mask);
6 static inline int devcgroup_inode_permission(struct inode *inode, int mask) devcgroup_inode_permission() argument
12 return __devcgroup_inode_permission(inode, mask); devcgroup_inode_permission()
15 static inline int devcgroup_inode_permission(struct inode *inode, int mask) devcgroup_inode_permission() argument
H A Dfsnotify.h29 static inline int fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask) fsnotify_parent() argument
34 return __fsnotify_parent(path, dentry, mask); fsnotify_parent()
38 static inline int fsnotify_perm(struct file *file, int mask) fsnotify_perm() argument
47 if (!(mask & (MAY_READ | MAY_OPEN))) fsnotify_perm()
49 if (mask & MAY_OPEN) fsnotify_perm()
51 else if (mask & MAY_READ) fsnotify_perm()
138 __u32 mask = FS_DELETE; fsnotify_nameremove() local
141 mask |= FS_ISDIR; fsnotify_nameremove()
143 fsnotify_parent(NULL, dentry, mask); fsnotify_nameremove()
183 __u32 mask = (FS_CREATE | FS_ISDIR); fsnotify_mkdir() local
188 fsnotify(inode, mask, d_inode, FSNOTIFY_EVENT_INODE, dentry->d_name.name, 0); fsnotify_mkdir()
198 __u32 mask = FS_ACCESS; fsnotify_access() local
201 mask |= FS_ISDIR; fsnotify_access()
204 fsnotify_parent(path, NULL, mask); fsnotify_access()
205 fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0); fsnotify_access()
216 __u32 mask = FS_MODIFY; fsnotify_modify() local
219 mask |= FS_ISDIR; fsnotify_modify()
222 fsnotify_parent(path, NULL, mask); fsnotify_modify()
223 fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0); fsnotify_modify()
234 __u32 mask = FS_OPEN; fsnotify_open() local
237 mask |= FS_ISDIR; fsnotify_open()
239 fsnotify_parent(path, NULL, mask); fsnotify_open()
240 fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0); fsnotify_open()
251 __u32 mask = (mode & FMODE_WRITE) ? FS_CLOSE_WRITE : FS_CLOSE_NOWRITE; fsnotify_close() local
254 mask |= FS_ISDIR; fsnotify_close()
257 fsnotify_parent(path, NULL, mask); fsnotify_close()
258 fsnotify(inode, mask, path, FSNOTIFY_EVENT_PATH, NULL, 0); fsnotify_close()
268 __u32 mask = FS_ATTRIB; fsnotify_xattr() local
271 mask |= FS_ISDIR; fsnotify_xattr()
273 fsnotify_parent(NULL, dentry, mask); fsnotify_xattr()
274 fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0); fsnotify_xattr()
284 __u32 mask = 0; fsnotify_change() local
287 mask |= FS_ATTRIB; fsnotify_change()
289 mask |= FS_ATTRIB; fsnotify_change()
291 mask |= FS_MODIFY; fsnotify_change()
295 mask |= FS_ATTRIB; fsnotify_change()
297 mask |= FS_ACCESS; fsnotify_change()
299 mask |= FS_MODIFY; fsnotify_change()
302 mask |= FS_ATTRIB; fsnotify_change()
304 if (mask) { fsnotify_change()
306 mask |= FS_ISDIR; fsnotify_change()
308 fsnotify_parent(NULL, dentry, mask); fsnotify_change()
309 fsnotify(inode, mask, inode, FSNOTIFY_EVENT_INODE, NULL, 0); fsnotify_change()
H A Dperf_regs.h12 int perf_reg_validate(u64 mask);
23 static inline int perf_reg_validate(u64 mask) perf_reg_validate() argument
25 return mask ? -ENOSYS : 0; perf_reg_validate()
H A Dioprio.h14 #define IOPRIO_PRIO_CLASS(mask) ((mask) >> IOPRIO_CLASS_SHIFT)
15 #define IOPRIO_PRIO_DATA(mask) ((mask) & IOPRIO_PRIO_MASK)
18 #define ioprio_valid(mask) (IOPRIO_PRIO_CLASS((mask)) != IOPRIO_CLASS_NONE)
/linux-4.4.14/arch/powerpc/math-emu/
H A Dmtfsfi.c11 u32 mask = 0xf; mtfsfi() local
14 mask = 9; mtfsfi()
16 __FPU_FPSCR &= ~(mask << ((7 - crfD) << 2)); mtfsfi()
H A Dmtfsf.c11 u32 mask; mtfsf() local
15 mask = 0x0f; mtfsf()
17 mask = ~0; mtfsf()
19 mask = ((FM & 1) | mtfsf()
29 fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) & mtfsf()
38 * is the same. Simply shift and mask to check for enabled mtfsf()
/linux-4.4.14/arch/powerpc/sysdev/
H A Dmpc8xx_pic.h11 * Some internal interrupt registers use an 8-bit mask for the interrupt
14 static inline uint mk_int_int_mask(uint mask) mk_int_int_mask() argument
16 return (1 << (7 - (mask/2))); mk_int_int_mask()
H A Dipic.c38 .mask = IPIC_SIMSR_H,
45 .mask = IPIC_SIMSR_H,
52 .mask = IPIC_SIMSR_H,
59 .mask = IPIC_SIMSR_H,
66 .mask = IPIC_SIMSR_H,
73 .mask = IPIC_SIMSR_H,
80 .mask = IPIC_SIMSR_H,
87 .mask = IPIC_SIMSR_H,
94 .mask = IPIC_SIMSR_H,
101 .mask = IPIC_SIMSR_H,
108 .mask = IPIC_SIMSR_H,
115 .mask = IPIC_SIMSR_H,
122 .mask = IPIC_SIMSR_H,
129 .mask = IPIC_SIMSR_H,
136 .mask = IPIC_SIMSR_H,
143 .mask = IPIC_SIMSR_H,
151 .mask = IPIC_SEMSR,
159 .mask = IPIC_SEMSR,
167 .mask = IPIC_SEMSR,
175 .mask = IPIC_SEMSR,
183 .mask = IPIC_SEMSR,
191 .mask = IPIC_SEMSR,
199 .mask = IPIC_SEMSR,
206 .mask = IPIC_SIMSR_H,
213 .mask = IPIC_SIMSR_H,
220 .mask = IPIC_SIMSR_H,
227 .mask = IPIC_SIMSR_H,
234 .mask = IPIC_SIMSR_H,
241 .mask = IPIC_SIMSR_H,
248 .mask = IPIC_SIMSR_H,
255 .mask = IPIC_SIMSR_H,
262 .mask = IPIC_SIMSR_H,
269 .mask = IPIC_SIMSR_H,
276 .mask = IPIC_SIMSR_H,
283 .mask = IPIC_SIMSR_H,
290 .mask = IPIC_SIMSR_H,
297 .mask = IPIC_SIMSR_H,
304 .mask = IPIC_SIMSR_H,
311 .mask = IPIC_SIMSR_H,
318 .mask = IPIC_SEMSR,
325 .mask = IPIC_SIMSR_L,
332 .mask = IPIC_SIMSR_L,
339 .mask = IPIC_SIMSR_L,
346 .mask = IPIC_SIMSR_L,
353 .mask = IPIC_SIMSR_L,
360 .mask = IPIC_SIMSR_L,
367 .mask = IPIC_SIMSR_L,
374 .mask = IPIC_SIMSR_L,
381 .mask = IPIC_SIMSR_L,
387 .mask = IPIC_SIMSR_L,
393 .mask = IPIC_SIMSR_L,
399 .mask = IPIC_SIMSR_L,
405 .mask = IPIC_SIMSR_L,
411 .mask = IPIC_SIMSR_L,
417 .mask = IPIC_SIMSR_L,
423 .mask = IPIC_SIMSR_L,
429 .mask = IPIC_SIMSR_L,
435 .mask = IPIC_SIMSR_L,
441 .mask = IPIC_SIMSR_L,
447 .mask = IPIC_SIMSR_L,
453 .mask = IPIC_SIMSR_L,
459 .mask = IPIC_SIMSR_L,
465 .mask = IPIC_SIMSR_L,
471 .mask = IPIC_SIMSR_L,
477 .mask = IPIC_SIMSR_L,
483 .mask = IPIC_SIMSR_L,
489 .mask = IPIC_SIMSR_L,
495 .mask = IPIC_SIMSR_L,
501 .mask = IPIC_SIMSR_L,
532 temp = ipic_read(ipic->regs, ipic_info[src].mask); ipic_unmask_irq()
534 ipic_write(ipic->regs, ipic_info[src].mask, temp); ipic_unmask_irq()
548 temp = ipic_read(ipic->regs, ipic_info[src].mask); ipic_mask_irq()
550 ipic_write(ipic->regs, ipic_info[src].mask, temp); ipic_mask_irq()
587 temp = ipic_read(ipic->regs, ipic_info[src].mask); ipic_mask_irq_and_ack()
589 ipic_write(ipic->regs, ipic_info[src].mask, temp); ipic_mask_irq_and_ack()
851 void ipic_clear_mcp_status(u32 mask) ipic_clear_mcp_status() argument
853 ipic_write(primary_ipic->regs, IPIC_SERMR, mask); ipic_clear_mcp_status()
/linux-4.4.14/arch/sh/include/mach-common/mach/
H A Dmagicpanelr2.h22 #define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg)
23 #define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg)
24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
25 #define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg)
26 #define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg)
27 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
/linux-4.4.14/arch/sparc/include/asm/
H A Dbitops_32.h21 unsigned long ___set_bit(unsigned long *addr, unsigned long mask);
22 unsigned long ___clear_bit(unsigned long *addr, unsigned long mask);
23 unsigned long ___change_bit(unsigned long *addr, unsigned long mask);
33 unsigned long *ADDR, mask; test_and_set_bit() local
36 mask = 1 << (nr & 31); test_and_set_bit()
38 return ___set_bit(ADDR, mask) != 0; test_and_set_bit()
43 unsigned long *ADDR, mask; set_bit() local
46 mask = 1 << (nr & 31); set_bit()
48 (void) ___set_bit(ADDR, mask); set_bit()
53 unsigned long *ADDR, mask; test_and_clear_bit() local
56 mask = 1 << (nr & 31); test_and_clear_bit()
58 return ___clear_bit(ADDR, mask) != 0; test_and_clear_bit()
63 unsigned long *ADDR, mask; clear_bit() local
66 mask = 1 << (nr & 31); clear_bit()
68 (void) ___clear_bit(ADDR, mask); clear_bit()
73 unsigned long *ADDR, mask; test_and_change_bit() local
76 mask = 1 << (nr & 31); test_and_change_bit()
78 return ___change_bit(ADDR, mask) != 0; test_and_change_bit()
83 unsigned long *ADDR, mask; change_bit() local
86 mask = 1 << (nr & 31); change_bit()
88 (void) ___change_bit(ADDR, mask); change_bit()
H A Dlsu.h7 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
8 #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
13 #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables. */
H A Ddma-mapping.h11 int dma_supported(struct device *dev, u64 mask);
42 static inline int dma_set_mask(struct device *dev, u64 mask) dma_set_mask() argument
46 if (!dev->dma_mask || !dma_supported(dev, mask)) dma_set_mask()
48 *dev->dma_mask = mask; dma_set_mask()
H A Dobio.h103 int mask; bw_get_intr_mask() local
106 "=r" (mask) : bw_get_intr_mask()
109 return mask; bw_get_intr_mask()
112 static inline void bw_clear_intr_mask(int sbus_level, int mask) bw_clear_intr_mask() argument
115 "r" (mask), bw_clear_intr_mask()
179 unsigned mask; cc_get_imsk() local
182 "=r" (mask) : cc_get_imsk()
185 return mask; cc_get_imsk()
188 static inline void cc_set_imsk(unsigned mask) cc_set_imsk() argument
191 "r" (mask), cc_set_imsk()
198 unsigned mask; cc_get_imsk_other() local
201 "=r" (mask) : cc_get_imsk_other()
204 return mask; cc_get_imsk_other()
207 static inline void cc_set_imsk_other(int cpuid, unsigned mask) cc_set_imsk_other() argument
210 "r" (mask), cc_set_imsk_other()
/linux-4.4.14/arch/arm/mach-ixp4xx/
H A Dixp4xx_qmgr.c119 u32 mask = 1 << (queue & (HALF_QUEUES - 1)); qmgr_enable_irq() local
122 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, qmgr_enable_irq()
131 u32 mask = 1 << (queue & (HALF_QUEUES - 1)); qmgr_disable_irq() local
134 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, qmgr_disable_irq()
136 __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ qmgr_disable_irq()
140 static inline void shift_mask(u32 *mask) shift_mask() argument
142 mask[3] = mask[3] << 1 | mask[2] >> 31; shift_mask()
143 mask[2] = mask[2] << 1 | mask[1] >> 31; shift_mask()
144 mask[1] = mask[1] << 1 | mask[0] >> 31; shift_mask()
145 mask[0] <<= 1; shift_mask()
159 u32 cfg, addr = 0, mask[4]; /* in 16-dwords */ qmgr_request_queue() local
170 mask[0] = 0x1; qmgr_request_queue()
174 mask[0] = 0x3; qmgr_request_queue()
178 mask[0] = 0xF; qmgr_request_queue()
182 mask[0] = 0xFF; qmgr_request_queue()
191 mask[1] = mask[2] = mask[3] = 0; qmgr_request_queue()
203 if (!(used_sram_bitmap[0] & mask[0]) && qmgr_request_queue()
204 !(used_sram_bitmap[1] & mask[1]) && qmgr_request_queue()
205 !(used_sram_bitmap[2] & mask[2]) && qmgr_request_queue()
206 !(used_sram_bitmap[3] & mask[3])) qmgr_request_queue()
210 shift_mask(mask); qmgr_request_queue()
219 used_sram_bitmap[0] |= mask[0]; qmgr_request_queue()
220 used_sram_bitmap[1] |= mask[1]; qmgr_request_queue()
221 used_sram_bitmap[2] |= mask[2]; qmgr_request_queue()
222 used_sram_bitmap[3] |= mask[3]; qmgr_request_queue()
241 u32 cfg, addr, mask[4]; qmgr_release_queue() local
252 case 0: mask[0] = 0x1; break; qmgr_release_queue()
253 case 1: mask[0] = 0x3; break; qmgr_release_queue()
254 case 2: mask[0] = 0xF; break; qmgr_release_queue()
255 case 3: mask[0] = 0xFF; break; qmgr_release_queue()
258 mask[1] = mask[2] = mask[3] = 0; qmgr_release_queue()
261 shift_mask(mask); qmgr_release_queue()
275 used_sram_bitmap[0] &= ~mask[0]; qmgr_release_queue()
276 used_sram_bitmap[1] &= ~mask[1]; qmgr_release_queue()
277 used_sram_bitmap[2] &= ~mask[2]; qmgr_release_queue()
278 used_sram_bitmap[3] &= ~mask[3]; qmgr_release_queue()
/linux-4.4.14/lib/
H A Dcpumask.c28 * @mask: the cpumask to search
31 * Often used to find any cpu but smp_processor_id() in a mask.
34 int cpumask_any_but(const struct cpumask *mask, unsigned int cpu) cpumask_any_but() argument
39 for_each_cpu(i, mask) cpumask_any_but()
49 * @mask: pointer to cpumask_var_t where the cpumask is returned
56 * In addition, mask will be NULL if this fails. Note that gcc is
57 * usually smart enough to know that mask can never be NULL if
61 bool alloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node) alloc_cpumask_var_node() argument
63 *mask = kmalloc_node(cpumask_size(), flags, node); alloc_cpumask_var_node()
66 if (!*mask) { alloc_cpumask_var_node()
72 return *mask != NULL; alloc_cpumask_var_node()
76 bool zalloc_cpumask_var_node(cpumask_var_t *mask, gfp_t flags, int node) zalloc_cpumask_var_node() argument
78 return alloc_cpumask_var_node(mask, flags | __GFP_ZERO, node); zalloc_cpumask_var_node()
84 * @mask: pointer to cpumask_var_t where the cpumask is returned
92 bool alloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) alloc_cpumask_var() argument
94 return alloc_cpumask_var_node(mask, flags, NUMA_NO_NODE); alloc_cpumask_var()
98 bool zalloc_cpumask_var(cpumask_var_t *mask, gfp_t flags) zalloc_cpumask_var() argument
100 return alloc_cpumask_var(mask, flags | __GFP_ZERO); zalloc_cpumask_var()
106 * @mask: pointer to cpumask_var_t where the cpumask is returned
113 void __init alloc_bootmem_cpumask_var(cpumask_var_t *mask) alloc_bootmem_cpumask_var() argument
115 *mask = memblock_virt_alloc(cpumask_size(), 0); alloc_bootmem_cpumask_var()
120 * @mask: cpumask to free
122 * This is safe on a NULL mask.
124 void free_cpumask_var(cpumask_var_t mask) free_cpumask_var() argument
126 kfree(mask); free_cpumask_var()
132 * @mask: cpumask to free
134 void __init free_bootmem_cpumask_var(cpumask_var_t mask) free_bootmem_cpumask_var() argument
136 memblock_free_early(__pa(mask), cpumask_size()); free_bootmem_cpumask_var()
/linux-4.4.14/arch/mips/bcm63xx/
H A Dgpio.c42 u32 mask; bcm63xx_gpio_set() local
51 mask = 1 << gpio; bcm63xx_gpio_set()
55 mask = 1 << (gpio - 32); bcm63xx_gpio_set()
61 *v |= mask; bcm63xx_gpio_set()
63 *v &= ~mask; bcm63xx_gpio_set()
71 u32 mask; bcm63xx_gpio_get() local
78 mask = 1 << gpio; bcm63xx_gpio_get()
81 mask = 1 << (gpio - 32); bcm63xx_gpio_get()
84 return !!(bcm_gpio_readl(reg) & mask); bcm63xx_gpio_get()
91 u32 mask; bcm63xx_gpio_set_direction() local
100 mask = 1 << gpio; bcm63xx_gpio_set_direction()
103 mask = 1 << (gpio - 32); bcm63xx_gpio_set_direction()
109 tmp &= ~mask; bcm63xx_gpio_set_direction()
111 tmp |= mask; bcm63xx_gpio_set_direction()
H A Dprom.c23 u32 reg, mask; prom_init() local
33 mask = CKCTL_3368_ALL_SAFE_EN; prom_init()
35 mask = CKCTL_6328_ALL_SAFE_EN; prom_init()
37 mask = CKCTL_6338_ALL_SAFE_EN; prom_init()
39 mask = CKCTL_6345_ALL_SAFE_EN; prom_init()
41 mask = CKCTL_6348_ALL_SAFE_EN; prom_init()
43 mask = CKCTL_6358_ALL_SAFE_EN; prom_init()
45 mask = CKCTL_6362_ALL_SAFE_EN; prom_init()
47 mask = CKCTL_6368_ALL_SAFE_EN; prom_init()
49 mask = 0; prom_init()
52 reg &= ~mask; prom_init()
H A Dclk.c41 static void bcm_hwclock_set(u32 mask, int enable) bcm_hwclock_set() argument
47 reg |= mask; bcm_hwclock_set()
49 reg &= ~mask; bcm_hwclock_set()
58 u32 mask; enet_misc_set() local
61 mask = CKCTL_6338_ENET_EN; enet_misc_set()
63 mask = CKCTL_6345_ENET_EN; enet_misc_set()
65 mask = CKCTL_6348_ENET_EN; enet_misc_set()
68 mask = CKCTL_6358_EMUSB_EN; enet_misc_set()
69 bcm_hwclock_set(mask, enable); enet_misc_set()
88 u32 mask; enetx_set() local
91 mask = CKCTL_6358_ENET0_EN; enetx_set()
93 mask = CKCTL_6358_ENET1_EN; enetx_set()
94 bcm_hwclock_set(mask, enable); enetx_set()
208 u32 mask; spi_set() local
211 mask = CKCTL_6338_SPI_EN; spi_set()
213 mask = CKCTL_6348_SPI_EN; spi_set()
215 mask = CKCTL_6358_SPI_EN; spi_set()
217 mask = CKCTL_6362_SPI_EN; spi_set()
220 mask = CKCTL_6368_SPI_EN; spi_set()
221 bcm_hwclock_set(mask, enable); spi_set()
233 u32 mask; hsspi_set() local
236 mask = CKCTL_6328_HSSPI_EN; hsspi_set()
238 mask = CKCTL_6362_HSSPI_EN; hsspi_set()
242 bcm_hwclock_set(mask, enable); hsspi_set()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramfuc.h17 u32 mask; member in struct:ramfuc_reg
22 ramfuc_stride(u32 addr, u32 stride, u32 mask) ramfuc_stride() argument
28 .mask = mask, ramfuc_stride()
40 .mask = 0x3, ramfuc_reg2()
52 .mask = 0x1, ramfuc_reg()
92 unsigned int mask, off = 0; ramfuc_wr32() local
97 for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { ramfuc_wr32()
98 if (mask & 1) ramfuc_wr32()
111 ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) ramfuc_mask() argument
114 if (temp != ((temp & ~mask) | data) || reg->force) { ramfuc_mask()
115 ramfuc_wr32(ram, reg, (temp & ~mask) | data); ramfuc_mask()
122 ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) ramfuc_wait() argument
124 nvkm_memx_wait(ram->memx, addr, mask, data, nsec); ramfuc_wait()
/linux-4.4.14/arch/xtensa/kernel/
H A Dirq.c96 u32 mask = 1 << hw; xtensa_irq_map() local
98 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) { xtensa_irq_map()
102 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) { xtensa_irq_map()
106 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) { xtensa_irq_map()
110 } else if (mask & XCHAL_INTTYPE_MASK_TIMER) { xtensa_irq_map()
115 } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) { xtensa_irq_map()
131 unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE | xtensa_map_ext_irq() local
135 for (i = 0; mask; ++i, mask >>= 1) { xtensa_map_ext_irq()
136 if ((mask & 1) && ext_irq-- == 0) xtensa_map_ext_irq()
144 unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE | xtensa_get_ext_irq_no() local
147 return hweight32(mask); xtensa_get_ext_irq_no()
180 struct cpumask *mask; for_each_active_irq() local
186 mask = irq_data_get_affinity_mask(data); for_each_active_irq()
187 if (!cpumask_test_cpu(cpu, mask)) for_each_active_irq()
190 newcpu = cpumask_any_and(mask, cpu_online_mask); for_each_active_irq()
196 cpumask_setall(mask); for_each_active_irq()
198 irq_set_affinity(i, mask); for_each_active_irq()
/linux-4.4.14/drivers/leds/
H A Dleds-ot200.c22 u8 mask; member in struct:ot200_led
34 .mask = BIT(0),
39 .mask = BIT(1),
44 .mask = BIT(2),
49 .mask = BIT(6),
54 .mask = BIT(5),
59 .mask = BIT(4),
64 .mask = BIT(3),
69 .mask = BIT(2),
74 .mask = BIT(1),
79 .mask = BIT(0),
109 *val &= ~led->mask; ot200_led_brightness_set()
111 *val |= led->mask; ot200_led_brightness_set()
/linux-4.4.14/arch/mips/lib/
H A Dbitops.c24 unsigned long mask; __mips_set_bit() local
28 mask = 1UL << bit; __mips_set_bit()
30 *a |= mask; __mips_set_bit()
46 unsigned long mask; __mips_clear_bit() local
50 mask = 1UL << bit; __mips_clear_bit()
52 *a &= ~mask; __mips_clear_bit()
68 unsigned long mask; __mips_change_bit() local
72 mask = 1UL << bit; __mips_change_bit()
74 *a ^= mask; __mips_change_bit()
91 unsigned long mask; __mips_test_and_set_bit() local
96 mask = 1UL << bit; __mips_test_and_set_bit()
98 res = (mask & *a) != 0; __mips_test_and_set_bit()
99 *a |= mask; __mips_test_and_set_bit()
117 unsigned long mask; __mips_test_and_set_bit_lock() local
122 mask = 1UL << bit; __mips_test_and_set_bit_lock()
124 res = (mask & *a) != 0; __mips_test_and_set_bit_lock()
125 *a |= mask; __mips_test_and_set_bit_lock()
142 unsigned long mask; __mips_test_and_clear_bit() local
147 mask = 1UL << bit; __mips_test_and_clear_bit()
149 res = (mask & *a) != 0; __mips_test_and_clear_bit()
150 *a &= ~mask; __mips_test_and_clear_bit()
167 unsigned long mask; __mips_test_and_change_bit() local
172 mask = 1UL << bit; __mips_test_and_change_bit()
174 res = (mask & *a) != 0; __mips_test_and_change_bit()
175 *a ^= mask; __mips_test_and_change_bit()
/linux-4.4.14/arch/x86/math-emu/
H A Dcontrol_w.h22 #define CW_Precision Const_(0x0020) /* loss of precision mask */
23 #define CW_Underflow Const_(0x0010) /* underflow mask */
24 #define CW_Overflow Const_(0x0008) /* overflow mask */
25 #define CW_ZeroDiv Const_(0x0004) /* divide by zero mask */
26 #define CW_Denormal Const_(0x0002) /* denormalized operand mask */
27 #define CW_Invalid Const_(0x0001) /* invalid operation mask */
/linux-4.4.14/arch/powerpc/include/asm/
H A Dword-at-a-time.h22 unsigned long mask = (val & c->low_bits) + c->low_bits; prep_zero_mask() local
23 return ~(mask | rhs); prep_zero_mask()
26 #define create_zero_mask(mask) (mask)
28 static inline long find_zero(unsigned long mask) find_zero() argument
32 asm (PPC_CNTLZL "%0,%1" : "=r" (leading_zero_bits) : "r" (mask)); find_zero()
43 static inline unsigned long zero_bytemask(unsigned long mask) zero_bytemask() argument
45 return ~1ul << __fls(mask); zero_bytemask()
90 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
92 return mask >> 3; find_zero()
96 static inline unsigned long zero_bytemask(unsigned long mask) zero_bytemask() argument
98 return (1UL << mask) - 1; zero_bytemask()
111 * optimal byte mask counting is probably going to be something
118 static inline long count_masked_bytes(long mask) count_masked_bytes() argument
121 long a = (0x0ff0001+mask) >> 23; count_masked_bytes()
123 return a & mask; count_masked_bytes()
132 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
134 return count_masked_bytes(mask); find_zero()
140 unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; has_zero() local
141 *bits = mask; has_zero()
142 return mask; has_zero()
150 /* The mask we created is directly usable as a bytemask */
151 #define zero_bytemask(mask) (mask)
/linux-4.4.14/tools/testing/selftests/powerpc/primitives/
H A Dword-at-a-time.h22 unsigned long mask = (val & c->low_bits) + c->low_bits; prep_zero_mask() local
23 return ~(mask | rhs); prep_zero_mask()
26 #define create_zero_mask(mask) (mask)
28 static inline long find_zero(unsigned long mask) find_zero() argument
32 asm (PPC_CNTLZL "%0,%1" : "=r" (leading_zero_bits) : "r" (mask)); find_zero()
43 static inline unsigned long zero_bytemask(unsigned long mask) zero_bytemask() argument
45 return ~1ul << __fls(mask); zero_bytemask()
90 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
92 return mask >> 3; find_zero()
96 static inline unsigned long zero_bytemask(unsigned long mask) zero_bytemask() argument
98 return (1UL << mask) - 1; zero_bytemask()
111 * optimal byte mask counting is probably going to be something
118 static inline long count_masked_bytes(long mask) count_masked_bytes() argument
121 long a = (0x0ff0001+mask) >> 23; count_masked_bytes()
123 return a & mask; count_masked_bytes()
132 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
134 return count_masked_bytes(mask); find_zero()
140 unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; has_zero() local
141 *bits = mask; has_zero()
142 return mask; has_zero()
150 /* The mask we created is directly usable as a bytemask */
151 #define zero_bytemask(mask) (mask)
/linux-4.4.14/drivers/soc/mediatek/
H A Dmtk-infracfg.c26 * @mask: The mask containing the protection bits to be enabled.
32 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask) mtk_infracfg_set_bus_protection() argument
38 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, mask); mtk_infracfg_set_bus_protection()
47 if ((val & mask) == mask) mtk_infracfg_set_bus_protection()
61 * @mask: The mask containing the protection bits to be disabled.
66 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask) mtk_infracfg_clear_bus_protection() argument
71 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); mtk_infracfg_clear_bus_protection()
82 if (!(val & mask)) mtk_infracfg_clear_bus_protection()
/linux-4.4.14/arch/arm/kernel/
H A Dperf_regs.c19 int perf_reg_validate(u64 mask) perf_reg_validate() argument
21 if (!mask || mask & REG_RESERVED) perf_reg_validate()
H A Dio.c14 void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set) atomic_io_modify_relaxed() argument
20 value = readl_relaxed(reg) & ~mask; atomic_io_modify_relaxed()
21 value |= (set & mask); atomic_io_modify_relaxed()
27 void atomic_io_modify(void __iomem *reg, u32 mask, u32 set) atomic_io_modify() argument
33 value = readl_relaxed(reg) & ~mask; atomic_io_modify()
34 value |= (set & mask); atomic_io_modify()
H A Dsleep.S18 * @mask: register containing MPIDR mask
24 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 mpidr, u32 mask) {
26 * u32 mpidr_masked = mpidr & mask;
32 * Input registers: rs0, rs1, rs2, mpidr, mask
37 .macro compute_mpidr_hash dst, rs0, rs1, rs2, mpidr, mask
38 and \mpidr, \mpidr, \mask @ mask out MPIDR bits
39 and \dst, \mpidr, #0xff @ mask=aff0
42 and \mask, \mpidr, #0xff00 @ mask = aff1
43 ARM( orr \dst, \dst, \mask, lsr \rs1 ) @ dst|=(aff1>>rs1)
44 THUMB( lsr \mask, \mask, \rs1 )
45 THUMB( orr \dst, \dst, \mask )
46 and \mask, \mpidr, #0xff0000 @ mask = aff2
47 ARM( orr \dst, \dst, \mask, lsr \rs2 ) @ dst|=(aff2>>rs2)
48 THUMB( lsr \mask, \mask, \rs2 )
49 THUMB( orr \dst, \dst, \mask )
77 ldmia r0, {r1, r6-r8} @ r1 = mpidr mask (r6,r7,r8) = l[0,1,2] shifts
147 ldmia r2, { r3-r6 } @ r3 = mpidr mask (r4,r5,r6) = l[0,1,2] shifts
/linux-4.4.14/arch/alpha/include/asm/
H A Ducontext.h10 sigset_t uc_sigmask; /* mask last for extensibility */
H A Dspecial_insns.h36 #define amask(mask) \
37 ({ unsigned long __amask, __input = (mask); \
/linux-4.4.14/include/uapi/asm-generic/
H A Ducontext.h9 sigset_t uc_sigmask; /* mask last for extensibility */
/linux-4.4.14/arch/parisc/include/asm/
H A Ducontext.h9 sigset_t uc_sigmask; /* mask last for extensibility */
/linux-4.4.14/arch/cris/include/asm/
H A Ducontext.h9 sigset_t uc_sigmask; /* mask last for extensibility */
/linux-4.4.14/arch/frv/include/asm/
H A Ducontext.h9 sigset_t uc_sigmask; /* mask last for extensibility */
H A Dbitops.h33 unsigned int mask = 1UL << (nr & 31); test_and_clear_bit() local
35 return (__atomic32_fetch_and(~mask, ptr) & mask) != 0; test_and_clear_bit()
41 unsigned int mask = 1UL << (nr & 31); test_and_set_bit() local
43 return (__atomic32_fetch_or(mask, ptr) & mask) != 0; test_and_set_bit()
49 unsigned int mask = 1UL << (nr & 31); test_and_change_bit() local
51 return (__atomic32_fetch_xor(mask, ptr) & mask) != 0; test_and_change_bit()
72 int mask; __clear_bit() local
75 mask = 1 << (nr & 31); __clear_bit()
76 *a &= ~mask; __clear_bit()
82 int mask; __set_bit() local
85 mask = 1 << (nr & 31); __set_bit()
86 *a |= mask; __set_bit()
92 int mask; __change_bit() local
95 mask = 1 << (nr & 31); __change_bit()
96 *a ^= mask; __change_bit()
102 int mask, retval; __test_and_clear_bit() local
105 mask = 1 << (nr & 31); __test_and_clear_bit()
106 retval = (mask & *a) != 0; __test_and_clear_bit()
107 *a &= ~mask; __test_and_clear_bit()
114 int mask, retval; __test_and_set_bit() local
117 mask = 1 << (nr & 31); __test_and_set_bit()
118 retval = (mask & *a) != 0; __test_and_set_bit()
119 *a |= mask; __test_and_set_bit()
126 int mask, retval; __test_and_change_bit() local
129 mask = 1 << (nr & 31); __test_and_change_bit()
130 retval = (mask & *a) != 0; __test_and_change_bit()
131 *a ^= mask; __test_and_change_bit()
147 int mask; __test_bit() local
150 mask = 1 << (nr & 0x1f); __test_bit()
151 return ((mask & *a) != 0); __test_bit()
237 /* Note: (x & -x) gives us a mask that is the least significant ffs()
/linux-4.4.14/arch/arm/mach-mv78xx0/include/mach/
H A Duncompress.h31 unsigned char mask; flush() local
34 mask = UART_LSR_TEMT | UART_LSR_THRE; flush()
37 if ((base[UART_LSR << 2] & mask) == mask) flush()
/linux-4.4.14/arch/arm/mach-orion5x/include/mach/
H A Duncompress.h33 unsigned char mask; flush() local
36 mask = UART_LSR_TEMT | UART_LSR_THRE; flush()
39 if ((base[UART_LSR << 2] & mask) == mask) flush()
/linux-4.4.14/arch/arm/include/asm/
H A Dword-at-a-time.h21 unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; has_zero() local
22 *bits = mask; has_zero()
23 return mask; has_zero()
34 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
40 ret = fls(mask) >> 3; find_zero()
43 ret = (0x0ff0001 + mask) >> 23; find_zero()
45 ret &= mask; find_zero()
51 #define zero_bytemask(mask) (mask)
/linux-4.4.14/arch/alpha/kernel/
H A Dsys_rawhide.c38 /* Note mask bit is true for ENABLED irqs. */
47 rawhide_update_irq_hw(int hose, int mask) rawhide_update_irq_hw() argument
49 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(hose)) = mask; rawhide_update_irq_hw()
60 unsigned int mask, hose; rawhide_enable_irq() local
69 mask = 1 << irq; rawhide_enable_irq()
72 mask |= cached_irq_masks[hose]; rawhide_enable_irq()
73 cached_irq_masks[hose] = mask; rawhide_enable_irq()
74 rawhide_update_irq_hw(hose, mask); rawhide_enable_irq()
81 unsigned int mask, hose; rawhide_disable_irq() local
90 mask = ~(1 << irq) | hose_irq_masks[hose]; rawhide_disable_irq()
93 mask &= cached_irq_masks[hose]; rawhide_disable_irq()
94 cached_irq_masks[hose] = mask; rawhide_disable_irq()
95 rawhide_update_irq_hw(hose, mask); rawhide_disable_irq()
102 unsigned int mask, mask1, hose; rawhide_mask_and_ack_irq() local
112 mask = ~mask1 | hose_irq_masks[hose]; rawhide_mask_and_ack_irq()
116 mask &= cached_irq_masks[hose]; rawhide_mask_and_ack_irq()
117 cached_irq_masks[hose] = mask; rawhide_mask_and_ack_irq()
118 rawhide_update_irq_hw(hose, mask); rawhide_mask_and_ack_irq()
145 * which is how we manage the interrupts/mask. Sigh... rawhide_srm_device_interrupt()
174 unsigned int mask = hose_irq_masks[h]; rawhide_init_irq() local
176 cached_irq_masks[h] = mask; rawhide_init_irq()
177 *(vuip)MCPCIA_INT_MASK0(MCPCIA_HOSE2MID(h)) = mask; rawhide_init_irq()
H A Dsys_sable.c39 /* Note mask bit is true for DISABLED irqs. */
42 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
93 sable_update_irq_hw(unsigned long bit, unsigned long mask) sable_update_irq_hw() argument
99 mask >>= 16; sable_update_irq_hw()
102 mask >>= 8; sable_update_irq_hw()
105 outb(mask, port); sable_update_irq_hw()
143 34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */
144 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
145 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
292 lynx_update_irq_hw(unsigned long bit, unsigned long mask) lynx_update_irq_hw() argument
296 * address of the IC mask register (offset 0x40) lynx_update_irq_hw()
302 *(vulp)T2_DIR = mask; lynx_update_irq_hw()
321 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
322 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
323 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
324 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
327 -1, -1, -1, 12, -1, -1, 1, 6, /* mask 0-7 */
328 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
329 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
330 -1, -1, -1, -1, 28, -1, -1, -1, /* mask 24-31 */
331 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
332 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
333 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
334 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
447 unsigned long bit, mask; sable_lynx_enable_irq() local
451 mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit); sable_lynx_enable_irq()
452 sable_lynx_irq_swizzle->update_irq_hw(bit, mask); sable_lynx_enable_irq()
455 printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n", sable_lynx_enable_irq()
456 __func__, mask, bit, irq); sable_lynx_enable_irq()
463 unsigned long bit, mask; sable_lynx_disable_irq() local
467 mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit; sable_lynx_disable_irq()
468 sable_lynx_irq_swizzle->update_irq_hw(bit, mask); sable_lynx_disable_irq()
471 printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n", sable_lynx_disable_irq()
472 __func__, mask, bit, irq); sable_lynx_disable_irq()
479 unsigned long bit, mask; sable_lynx_mask_and_ack_irq() local
483 mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit; sable_lynx_mask_and_ack_irq()
484 sable_lynx_irq_swizzle->update_irq_hw(bit, mask); sable_lynx_mask_and_ack_irq()
500 to the interrupt mask bits, but we have to manage via the sable_lynx_srm_device_interrupt()
/linux-4.4.14/net/sched/
H A Dcls_flower.c52 struct fl_flow_mask mask; member in struct:cls_fl_head
72 static unsigned short int fl_mask_range(const struct fl_flow_mask *mask) fl_mask_range() argument
74 return mask->range.end - mask->range.start; fl_mask_range()
77 static void fl_mask_update_range(struct fl_flow_mask *mask) fl_mask_update_range() argument
79 const u8 *bytes = (const u8 *) &mask->key; fl_mask_update_range()
80 size_t size = sizeof(mask->key); fl_mask_update_range()
83 for (i = 0; i < sizeof(mask->key); i++) { fl_mask_update_range()
90 mask->range.start = rounddown(first, sizeof(long)); fl_mask_update_range()
91 mask->range.end = roundup(last + 1, sizeof(long)); fl_mask_update_range()
95 const struct fl_flow_mask *mask) fl_key_get_start()
97 return (u8 *) key + mask->range.start; fl_key_get_start()
101 struct fl_flow_mask *mask) fl_set_masked_key()
103 const long *lkey = fl_key_get_start(key, mask); fl_set_masked_key()
104 const long *lmask = fl_key_get_start(&mask->key, mask); fl_set_masked_key()
105 long *lmkey = fl_key_get_start(mkey, mask); fl_set_masked_key()
108 for (i = 0; i < fl_mask_range(mask); i += sizeof(long)) fl_set_masked_key()
113 struct fl_flow_mask *mask) fl_clear_masked_range()
115 memset(fl_key_get_start(key, mask), 0, fl_mask_range(mask)); fl_clear_masked_range()
126 fl_clear_masked_range(&skb_key, &head->mask); fl_classify()
134 fl_set_masked_key(&skb_mkey, &skb_key, &head->mask); fl_classify()
137 fl_key_get_start(&skb_mkey, &head->mask), fl_classify()
225 void *mask, int mask_type, int len) fl_set_key_val()
231 memset(mask, 0xff, len); fl_set_key_val()
233 memcpy(mask, nla_data(tb[mask_type]), len); fl_set_key_val()
237 struct fl_flow_key *key, struct fl_flow_key *mask) fl_set_key()
245 mask->indev_ifindex = 0xffffffff; fl_set_key()
250 mask->eth.dst, TCA_FLOWER_KEY_ETH_DST_MASK, fl_set_key()
253 mask->eth.src, TCA_FLOWER_KEY_ETH_SRC_MASK, fl_set_key()
257 &mask->basic.n_proto, TCA_FLOWER_UNSPEC, fl_set_key()
263 &mask->basic.ip_proto, TCA_FLOWER_UNSPEC, fl_set_key()
270 &mask->ipv4.src, TCA_FLOWER_KEY_IPV4_SRC_MASK, fl_set_key()
273 &mask->ipv4.dst, TCA_FLOWER_KEY_IPV4_DST_MASK, fl_set_key()
278 &mask->ipv6.src, TCA_FLOWER_KEY_IPV6_SRC_MASK, fl_set_key()
281 &mask->ipv6.dst, TCA_FLOWER_KEY_IPV6_DST_MASK, fl_set_key()
287 &mask->tp.src, TCA_FLOWER_UNSPEC, fl_set_key()
290 &mask->tp.dst, TCA_FLOWER_UNSPEC, fl_set_key()
294 &mask->tp.src, TCA_FLOWER_UNSPEC, fl_set_key()
297 &mask->tp.dst, TCA_FLOWER_UNSPEC, fl_set_key()
321 struct fl_flow_mask *mask) fl_init_hashtable()
324 head->ht_params.key_len = fl_mask_range(mask); fl_init_hashtable()
325 head->ht_params.key_offset += mask->range.start; fl_init_hashtable()
335 #define FL_KEY_IN_RANGE(mask, member) \
336 (FL_KEY_MEMBER_OFFSET(member) <= (mask)->range.end && \
337 FL_KEY_MEMBER_END_OFFSET(member) >= (mask)->range.start)
346 #define FL_KEY_SET_IF_IN_RANGE(mask, keys, cnt, id, member) \
348 if (FL_KEY_IN_RANGE(mask, member)) \
353 struct fl_flow_mask *mask) fl_init_dissector()
360 FL_KEY_SET_IF_IN_RANGE(mask, keys, cnt, fl_init_dissector()
362 FL_KEY_SET_IF_IN_RANGE(mask, keys, cnt, fl_init_dissector()
364 FL_KEY_SET_IF_IN_RANGE(mask, keys, cnt, fl_init_dissector()
366 FL_KEY_SET_IF_IN_RANGE(mask, keys, cnt, fl_init_dissector()
373 struct fl_flow_mask *mask) fl_check_assign_mask()
378 if (!fl_mask_eq(&head->mask, mask)) fl_check_assign_mask()
387 err = fl_init_hashtable(head, mask); fl_check_assign_mask()
390 memcpy(&head->mask, mask, sizeof(head->mask)); fl_check_assign_mask()
393 fl_init_dissector(head, mask); fl_check_assign_mask()
399 struct cls_fl_filter *f, struct fl_flow_mask *mask, fl_set_parms()
416 err = fl_set_key(net, tb, &f->key, &mask->key); fl_set_parms()
420 fl_mask_update_range(mask); fl_set_parms()
421 fl_set_masked_key(&f->mkey, &f->key, mask); fl_set_parms()
461 struct fl_flow_mask mask = {}; fl_change() local
489 err = fl_set_parms(net, tp, fnew, &mask, base, tb, tca[TCA_RATE], ovr); fl_change()
493 err = fl_check_assign_mask(head, &mask); fl_change()
554 void *mask, int mask_type, int len) fl_dump_key_val()
558 if (!memchr_inv(mask, 0, len)) fl_dump_key_val()
564 err = nla_put(skb, mask_type, len, mask); fl_dump_key_val()
577 struct fl_flow_key *key, *mask; fl_dump() local
593 mask = &head->mask.key; fl_dump()
595 if (mask->indev_ifindex) { fl_dump()
604 mask->eth.dst, TCA_FLOWER_KEY_ETH_DST_MASK, fl_dump()
607 mask->eth.src, TCA_FLOWER_KEY_ETH_SRC_MASK, fl_dump()
610 &mask->basic.n_proto, TCA_FLOWER_UNSPEC, fl_dump()
616 &mask->basic.ip_proto, TCA_FLOWER_UNSPEC, fl_dump()
622 &mask->ipv4.src, TCA_FLOWER_KEY_IPV4_SRC_MASK, fl_dump()
625 &mask->ipv4.dst, TCA_FLOWER_KEY_IPV4_DST_MASK, fl_dump()
630 &mask->ipv6.src, TCA_FLOWER_KEY_IPV6_SRC_MASK, fl_dump()
633 &mask->ipv6.dst, TCA_FLOWER_KEY_IPV6_DST_MASK, fl_dump()
639 &mask->tp.src, TCA_FLOWER_UNSPEC, fl_dump()
642 &mask->tp.dst, TCA_FLOWER_UNSPEC, fl_dump()
647 &mask->tp.src, TCA_FLOWER_UNSPEC, fl_dump()
650 &mask->tp.dst, TCA_FLOWER_UNSPEC, fl_dump()
94 fl_key_get_start(struct fl_flow_key *key, const struct fl_flow_mask *mask) fl_key_get_start() argument
100 fl_set_masked_key(struct fl_flow_key *mkey, struct fl_flow_key *key, struct fl_flow_mask *mask) fl_set_masked_key() argument
112 fl_clear_masked_range(struct fl_flow_key *key, struct fl_flow_mask *mask) fl_clear_masked_range() argument
223 fl_set_key_val(struct nlattr **tb, void *val, int val_type, void *mask, int mask_type, int len) fl_set_key_val() argument
236 fl_set_key(struct net *net, struct nlattr **tb, struct fl_flow_key *key, struct fl_flow_key *mask) fl_set_key() argument
320 fl_init_hashtable(struct cls_fl_head *head, struct fl_flow_mask *mask) fl_init_hashtable() argument
352 fl_init_dissector(struct cls_fl_head *head, struct fl_flow_mask *mask) fl_init_dissector() argument
372 fl_check_assign_mask(struct cls_fl_head *head, struct fl_flow_mask *mask) fl_check_assign_mask() argument
398 fl_set_parms(struct net *net, struct tcf_proto *tp, struct cls_fl_filter *f, struct fl_flow_mask *mask, unsigned long base, struct nlattr **tb, struct nlattr *est, bool ovr) fl_set_parms() argument
552 fl_dump_key_val(struct sk_buff *skb, void *val, int val_type, void *mask, int mask_type, int len) fl_dump_key_val() argument
/linux-4.4.14/include/asm-generic/bitops/
H A Dnon-atomic.h17 unsigned long mask = BIT_MASK(nr); __set_bit() local
20 *p |= mask; __set_bit()
25 unsigned long mask = BIT_MASK(nr); __clear_bit() local
28 *p &= ~mask; __clear_bit()
42 unsigned long mask = BIT_MASK(nr); __change_bit() local
45 *p ^= mask; __change_bit()
59 unsigned long mask = BIT_MASK(nr); __test_and_set_bit() local
63 *p = old | mask; __test_and_set_bit()
64 return (old & mask) != 0; __test_and_set_bit()
78 unsigned long mask = BIT_MASK(nr); __test_and_clear_bit() local
82 *p = old & ~mask; __test_and_clear_bit()
83 return (old & mask) != 0; __test_and_clear_bit()
90 unsigned long mask = BIT_MASK(nr); __test_and_change_bit() local
94 *p = old ^ mask; __test_and_change_bit()
95 return (old & mask) != 0; __test_and_change_bit()
/linux-4.4.14/arch/mips/kernel/
H A Dirq-gt641xx.c47 u32 mask; mask_gt641xx_irq() local
50 mask = GT_READ(GT_INTRMASK_OFS); mask_gt641xx_irq()
51 mask &= ~GT641XX_IRQ_TO_BIT(d->irq); mask_gt641xx_irq()
52 GT_WRITE(GT_INTRMASK_OFS, mask); mask_gt641xx_irq()
59 u32 cause, mask; mask_ack_gt641xx_irq() local
62 mask = GT_READ(GT_INTRMASK_OFS); mask_ack_gt641xx_irq()
63 mask &= ~GT641XX_IRQ_TO_BIT(d->irq); mask_ack_gt641xx_irq()
64 GT_WRITE(GT_INTRMASK_OFS, mask); mask_ack_gt641xx_irq()
75 u32 mask; unmask_gt641xx_irq() local
78 mask = GT_READ(GT_INTRMASK_OFS); unmask_gt641xx_irq()
79 mask |= GT641XX_IRQ_TO_BIT(d->irq); unmask_gt641xx_irq()
80 GT_WRITE(GT_INTRMASK_OFS, mask); unmask_gt641xx_irq()
94 u32 cause, mask; gt641xx_irq_dispatch() local
98 mask = GT_READ(GT_INTRMASK_OFS); gt641xx_irq_dispatch()
99 cause &= mask; gt641xx_irq_dispatch()
/linux-4.4.14/Documentation/arm/Samsung/
H A Dclksrc-change-registers.awk66 # read the header file and find the mask values that we will need
89 mask=""
105 } else if (line ~ /\.mask/) {
106 mask = extract_value(line)
122 printf "mask '" mask "'\n" > "/dev/stderr"
128 generated = mask
135 printf "/* mask " mask " */\n"
149 printf ".shift = " dmask[mask,1] ", "
150 printf ".size = " dmask[mask,0] ", "
/linux-4.4.14/net/netlabel/
H A Dnetlabel_addrlist.c66 if (iter->valid && (addr & iter->mask) == iter->addr) netlbl_af4list_search()
75 * @mask: IPv4 address mask
85 __be32 mask, netlbl_af4list_search_exact()
91 if (iter->valid && iter->addr == addr && iter->mask == mask) netlbl_af4list_search_exact()
117 ipv6_masked_addr_cmp(&iter->addr, &iter->mask, addr) == 0) netlbl_af6list_search()
126 * @mask: IPv6 address mask
136 const struct in6_addr *mask, netlbl_af6list_search_exact()
144 ipv6_addr_equal(&iter->mask, mask)) netlbl_af6list_search_exact()
168 iter->addr == entry->addr && iter->mask == entry->mask) netlbl_af4list_add()
173 * address mask such that the entry with the widest mask (smallest netlbl_af4list_add()
177 ntohl(entry->mask) > ntohl(iter->mask)) { list_for_each_entry_rcu()
206 ipv6_addr_equal(&iter->mask, &entry->mask)) netlbl_af6list_add()
211 * address mask such that the entry with the widest mask (smallest netlbl_af6list_add()
215 ipv6_addr_cmp(&entry->mask, &iter->mask) > 0) { list_for_each_entry_rcu()
244 * @mask: IP address mask
253 struct netlbl_af4list *netlbl_af4list_remove(__be32 addr, __be32 mask, netlbl_af4list_remove() argument
258 entry = netlbl_af4list_search_exact(addr, mask, head); netlbl_af4list_remove()
284 * @mask: IP address mask
294 const struct in6_addr *mask, netlbl_af6list_remove()
299 entry = netlbl_af6list_search_exact(addr, mask, head); netlbl_af6list_remove()
318 * @mask: IP address mask
321 * Write the IPv4 address and address mask, if necessary, to @audit_buf.
326 __be32 addr, __be32 mask) netlbl_af4list_audit_addr()
328 u32 mask_val = ntohl(mask); netlbl_af4list_audit_addr()
351 * @mask: IP address mask
354 * Write the IPv6 address and address mask, if necessary, to @audit_buf.
361 const struct in6_addr *mask) netlbl_af6list_audit_addr()
368 if (ntohl(mask->s6_addr32[3]) != 0xffffffff) { netlbl_af6list_audit_addr()
372 while (ntohl(mask->s6_addr32[++iter]) == 0xffffffff) netlbl_af6list_audit_addr()
374 mask_val = ntohl(mask->s6_addr32[iter]); netlbl_af6list_audit_addr()
84 netlbl_af4list_search_exact(__be32 addr, __be32 mask, struct list_head *head) netlbl_af4list_search_exact() argument
135 netlbl_af6list_search_exact(const struct in6_addr *addr, const struct in6_addr *mask, struct list_head *head) netlbl_af6list_search_exact() argument
293 netlbl_af6list_remove(const struct in6_addr *addr, const struct in6_addr *mask, struct list_head *head) netlbl_af6list_remove() argument
324 netlbl_af4list_audit_addr(struct audit_buffer *audit_buf, int src, const char *dev, __be32 addr, __be32 mask) netlbl_af4list_audit_addr() argument
357 netlbl_af6list_audit_addr(struct audit_buffer *audit_buf, int src, const char *dev, const struct in6_addr *addr, const struct in6_addr *mask) netlbl_af6list_audit_addr() argument
H A Dnetlabel_addrlist.h43 * @mask: IPv4 address mask
49 __be32 mask; member in struct:netlbl_af4list
58 * @mask: IPv6 address mask
64 struct in6_addr mask; member in struct:netlbl_af6list
114 struct netlbl_af4list *netlbl_af4list_remove(__be32 addr, __be32 mask,
120 __be32 mask,
126 __be32 addr, __be32 mask);
130 __be32 addr, __be32 mask) netlbl_af4list_audit_addr()
182 const struct in6_addr *mask,
188 const struct in6_addr *mask,
196 const struct in6_addr *mask);
202 const struct in6_addr *mask) netlbl_af6list_audit_addr()
128 netlbl_af4list_audit_addr(struct audit_buffer *audit_buf, int src, const char *dev, __be32 addr, __be32 mask) netlbl_af4list_audit_addr() argument
198 netlbl_af6list_audit_addr(struct audit_buffer *audit_buf, int src, const char *dev, const struct in6_addr *addr, const struct in6_addr *mask) netlbl_af6list_audit_addr() argument
/linux-4.4.14/fs/hfsplus/
H A Dbitmap.c25 u32 mask, start, len, n; hfsplus_block_allocate() local
54 mask = (1U << 31) >> i; hfsplus_block_allocate()
55 for (; i < 32; mask >>= 1, i++) { hfsplus_block_allocate()
56 if (!(n & mask)) hfsplus_block_allocate()
68 mask = 1 << 31; hfsplus_block_allocate()
69 for (i = 0; i < 32; mask >>= 1, i++) { hfsplus_block_allocate()
70 if (!(n & mask)) hfsplus_block_allocate()
105 n |= mask; hfsplus_block_allocate()
108 mask >>= 1; hfsplus_block_allocate()
109 if (!--len || n & mask) hfsplus_block_allocate()
143 mask = 1U << 31; hfsplus_block_allocate()
145 if (n & mask) hfsplus_block_allocate()
147 n |= mask; hfsplus_block_allocate()
148 mask >>= 1; hfsplus_block_allocate()
169 u32 mask, len, pnr; hfsplus_block_free() local
196 mask = 0xffffffffU << j; hfsplus_block_free()
198 mask |= 0xffffffffU >> (i + count); hfsplus_block_free()
199 *curr++ &= cpu_to_be32(mask); hfsplus_block_free()
202 *curr++ &= cpu_to_be32(mask); hfsplus_block_free()
228 mask = 0xffffffffU >> count; hfsplus_block_free()
229 *curr &= cpu_to_be32(mask); hfsplus_block_free()
/linux-4.4.14/arch/um/include/shared/
H A Dframe_kern.h10 struct pt_regs *regs, sigset_t *mask);
12 struct pt_regs *regs, sigset_t *mask);
/linux-4.4.14/arch/x86/xen/
H A Dsmp.h3 extern void xen_send_IPI_mask(const struct cpumask *mask,
5 extern void xen_send_IPI_mask_allbutself(const struct cpumask *mask,
/linux-4.4.14/arch/arm/mm/
H A Ddump.c48 u64 mask; member in struct:prot_bits
56 .mask = L_PTE_USER,
61 .mask = L_PTE_RDONLY,
66 .mask = L_PTE_XN,
71 .mask = L_PTE_SHARED,
76 .mask = L_PTE_MT_MASK,
80 .mask = L_PTE_MT_MASK,
84 .mask = L_PTE_MT_MASK,
88 .mask = L_PTE_MT_MASK,
93 .mask = L_PTE_MT_MASK,
98 .mask = L_PTE_MT_MASK,
102 .mask = L_PTE_MT_MASK,
107 .mask = L_PTE_MT_MASK,
112 .mask = L_PTE_MT_MASK,
116 .mask = L_PTE_MT_MASK,
125 .mask = PMD_SECT_USER,
129 .mask = L_PMD_SECT_RDONLY,
135 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
139 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
143 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
147 .mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
153 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
157 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
161 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
165 .mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
170 .mask = PMD_SECT_XN,
175 .mask = PMD_SECT_S,
185 u64 mask; member in struct:pg_level
208 if ((st->current_prot & bits->mask) == bits->val) dump_prot()
221 u64 prot = val & pg_level[level].mask; note_page()
352 pg_level[i].mask |= pg_level[i].bits[j].mask; ptdump_init()
/linux-4.4.14/arch/avr32/mach-at32ap/
H A Dhmatrix.c59 * @mask: mask of bits to be set in the SFR
61 void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask) hmatrix_sfr_set_bits() argument
67 value |= mask; hmatrix_sfr_set_bits()
76 * @mask: mask of bits to be cleared in the SFR
78 void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask) hmatrix_sfr_clear_bits() argument
84 value &= ~mask; hmatrix_sfr_clear_bits()
H A Dpio.c107 u32 mask = 1 << pin_index; at32_select_gpio() local
122 pio_writel(pio, SODR, mask); at32_select_gpio()
124 pio_writel(pio, CODR, mask); at32_select_gpio()
126 pio_writel(pio, MDER, mask); at32_select_gpio()
128 pio_writel(pio, MDDR, mask); at32_select_gpio()
129 pio_writel(pio, PUDR, mask); at32_select_gpio()
130 pio_writel(pio, OER, mask); at32_select_gpio()
133 pio_writel(pio, PUER, mask); at32_select_gpio()
135 pio_writel(pio, PUDR, mask); at32_select_gpio()
137 pio_writel(pio, IFER, mask); at32_select_gpio()
139 pio_writel(pio, IFDR, mask); at32_select_gpio()
140 pio_writel(pio, ODR, mask); at32_select_gpio()
143 pio_writel(pio, PER, mask); at32_select_gpio()
207 u32 mask = 1 << offset; direction_input() local
209 if (!(pio_readl(pio, PSR) & mask)) direction_input()
212 pio_writel(pio, ODR, mask); direction_input()
228 u32 mask = 1 << offset; direction_output() local
230 if (!(pio_readl(pio, PSR) & mask)) direction_output()
234 pio_writel(pio, OER, mask); direction_output()
241 u32 mask = 1 << offset; gpio_set() local
244 pio_writel(pio, SODR, mask); gpio_set()
246 pio_writel(pio, CODR, mask); gpio_set()
341 u32 mask; pio_bank_show() local
354 for (i = 0, mask = 1; i < 32; i++, mask <<= 1) { pio_bank_show()
358 if (!label && (imr & mask)) pio_bank_show()
366 (osr & mask) ? "out" : "in ", pio_bank_show()
367 (mask & pdsr) ? "hi" : "lo", pio_bank_show()
368 (mask & pusr) ? " " : "up"); pio_bank_show()
369 if (ifsr & mask) pio_bank_show()
371 if ((osr & mdsr) & mask) pio_bank_show()
373 if (imr & mask) pio_bank_show()
/linux-4.4.14/arch/arm/mach-sa1100/include/mach/
H A Dreset.h13 static inline void clear_reset_status(unsigned int mask) clear_reset_status() argument
15 RCSR = mask; clear_reset_status()
/linux-4.4.14/arch/x86/kernel/apic/
H A Dipi.c21 void default_send_IPI_mask_sequence_phys(const struct cpumask *mask, int vector) default_send_IPI_mask_sequence_phys() argument
28 * to an arbitrary mask, so I do a unicast to each CPU instead. default_send_IPI_mask_sequence_phys()
32 for_each_cpu(query_cpu, mask) { for_each_cpu()
39 void default_send_IPI_mask_allbutself_phys(const struct cpumask *mask, default_send_IPI_mask_allbutself_phys() argument
49 for_each_cpu(query_cpu, mask) { for_each_cpu()
60 void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, default_send_IPI_mask_sequence_logical() argument
68 * to an arbitrary mask, so I do a unicasts to each CPU instead. This default_send_IPI_mask_sequence_logical()
73 for_each_cpu(query_cpu, mask) default_send_IPI_mask_sequence_logical()
80 void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, default_send_IPI_mask_allbutself_logical() argument
90 for_each_cpu(query_cpu, mask) { for_each_cpu()
105 unsigned long mask = cpumask_bits(cpumask)[0]; default_send_IPI_mask_logical() local
108 if (!mask) default_send_IPI_mask_logical()
112 WARN_ON(mask & ~cpumask_bits(cpu_online_mask)[0]); default_send_IPI_mask_logical()
113 __default_send_IPI_dest_field(mask, vector, apic->dest_logical); default_send_IPI_mask_logical()
H A Dx2apic_phys.c40 __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) __x2apic_send_IPI_mask() argument
51 for_each_cpu(query_cpu, mask) { for_each_cpu()
60 static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) x2apic_send_IPI_mask() argument
62 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); x2apic_send_IPI_mask()
66 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) x2apic_send_IPI_mask_allbutself() argument
68 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); x2apic_send_IPI_mask_allbutself()
/linux-4.4.14/drivers/media/pci/ivtv/
H A Divtv-gpio.c161 u16 mask, data; subdev_s_clock_freq() local
163 mask = itv->card->gpio_audio_freq.mask; subdev_s_clock_freq()
176 if (mask) subdev_s_clock_freq()
177 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_clock_freq()
184 u16 mask; subdev_g_tuner() local
186 mask = itv->card->gpio_audio_detect.mask; subdev_g_tuner()
187 if (mask == 0 || (read_reg(IVTV_REG_GPIO_IN) & mask)) subdev_g_tuner()
198 u16 mask, data; subdev_s_tuner() local
200 mask = itv->card->gpio_audio_mode.mask; subdev_s_tuner()
217 if (mask) subdev_s_tuner()
218 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_tuner()
225 u16 mask, data; subdev_s_radio() local
227 mask = itv->card->gpio_audio_input.mask; subdev_s_radio()
229 if (mask) subdev_s_radio()
230 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_radio()
238 u16 mask, data; subdev_s_audio_routing() local
242 mask = itv->card->gpio_audio_input.mask; subdev_s_audio_routing()
255 if (mask) subdev_s_audio_routing()
256 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_audio_routing()
264 u16 mask, data; subdev_s_ctrl() local
268 mask = itv->card->gpio_audio_mute.mask; subdev_s_ctrl()
270 if (mask) subdev_s_ctrl()
271 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | subdev_s_ctrl()
272 (data & mask), IVTV_REG_GPIO_OUT); subdev_s_ctrl()
294 u16 mask, data; subdev_s_video_routing() local
298 mask = itv->card->gpio_video_input.mask; subdev_s_video_routing()
305 if (mask) subdev_s_video_routing()
306 write_reg((read_reg(IVTV_REG_GPIO_OUT) & ~mask) | (data & mask), IVTV_REG_GPIO_OUT); subdev_s_video_routing()
/linux-4.4.14/arch/arm/mach-imx/
H A Diomux-v1.c50 unsigned long mask, unsigned long value) imx_iomuxv1_rmwl()
54 reg &= ~mask; imx_iomuxv1_rmwl()
63 unsigned long mask = 1 << pin; imx_iomuxv1_set_puen() local
65 imx_iomuxv1_rmwl(MXC_PUEN(port), mask, on ? mask : 0); imx_iomuxv1_set_puen() local
71 unsigned long mask = 1 << pin; imx_iomuxv1_set_ddir() local
73 imx_iomuxv1_rmwl(MXC_DDIR(port), mask, out ? mask : 0); imx_iomuxv1_set_ddir() local
79 unsigned long mask = 1 << pin; imx_iomuxv1_set_gpr() local
81 imx_iomuxv1_rmwl(MXC_GPR(port), mask, af ? mask : 0); imx_iomuxv1_set_gpr() local
87 unsigned long mask = 1 << pin; imx_iomuxv1_set_gius() local
89 imx_iomuxv1_rmwl(MXC_GIUS(port), mask, inuse ? mask : 0); imx_iomuxv1_set_gius() local
96 unsigned long mask = 3 << shift; imx_iomuxv1_set_ocr() local
100 imx_iomuxv1_rmwl(offset, mask, value); imx_iomuxv1_set_ocr()
107 unsigned long mask = 3 << shift; imx_iomuxv1_set_iconfa() local
111 imx_iomuxv1_rmwl(offset, mask, value); imx_iomuxv1_set_iconfa()
118 unsigned long mask = 3 << shift; imx_iomuxv1_set_iconfb() local
122 imx_iomuxv1_rmwl(offset, mask, value); imx_iomuxv1_set_iconfb()
49 imx_iomuxv1_rmwl(unsigned offset, unsigned long mask, unsigned long value) imx_iomuxv1_rmwl() argument
/linux-4.4.14/arch/mips/pci/
H A Dpci-malta.c93 resource_size_t start, end, map, start1, end1, map1, map2, map3, mask; mips_pcibios_init() local
129 mask = ~(start ^ end); mips_pcibios_init()
130 /* We don't support remapping with a discontiguous mask. */ mips_pcibios_init()
132 mask != ~((mask & -mask) - 1)); mips_pcibios_init()
135 gt64120_controller.mem_offset = (start & mask) - (map & mask); mips_pcibios_init()
146 mask = ~(start ^ end); mips_pcibios_init()
147 /* We don't support remapping with a discontiguous mask. */ mips_pcibios_init()
149 mask != ~((mask & -mask) - 1)); mips_pcibios_init()
150 gt64120_io_resource.start = map & mask; mips_pcibios_init()
151 gt64120_io_resource.end = (map & mask) | ~mask; mips_pcibios_init()
199 MSC_READ(MSC01_PCI_SC2PMMSKL, mask); mips_pcibios_init()
201 msc_mem_resource.start = start & mask; mips_pcibios_init()
202 msc_mem_resource.end = (start & mask) | ~mask; mips_pcibios_init()
203 msc_controller.mem_offset = (start & mask) - (map & mask); mips_pcibios_init()
206 write_gcr_reg0_mask(mask | mips_pcibios_init()
210 MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); mips_pcibios_init()
212 msc_io_resource.start = map & mask; mips_pcibios_init()
213 msc_io_resource.end = (map & mask) | ~mask; mips_pcibios_init()
215 ioport_resource.end = ~mask; mips_pcibios_init()
218 write_gcr_reg1_mask(mask | mips_pcibios_init()
222 start = start & mask; mips_pcibios_init()
223 end = start | ~mask; mips_pcibios_init()
/linux-4.4.14/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.c46 unsigned int mask; /* bit mask in PWER or PKWR */ member in struct:gpio_desc
47 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
57 unsigned long gafr, mask = GPIO_bit(gpio); __mfp_config_gpio() local
77 GPDR(gpio) |= mask; __mfp_config_gpio()
79 GPDR(gpio) &= ~mask; __mfp_config_gpio()
84 PGSR(bank) |= mask; __mfp_config_gpio()
88 PGSR(bank) &= ~mask; __mfp_config_gpio()
102 gpdr_lpm[bank] |= mask; __mfp_config_gpio()
104 gpdr_lpm[bank] &= ~mask; __mfp_config_gpio()
193 PKWR |= d->mask; gpio_set_wake()
195 PKWR &= ~d->mask; gpio_set_wake()
199 mux_taken = (PWER & d->mux_mask) & (~d->mask); gpio_set_wake()
205 PWER = (PWER & ~d->mux_mask) | d->mask; gpio_set_wake()
208 PRER |= d->mask; gpio_set_wake()
210 PRER &= ~d->mask; gpio_set_wake()
213 PFER |= d->mask; gpio_set_wake()
215 PFER &= ~d->mask; gpio_set_wake()
217 PWER &= ~d->mask; gpio_set_wake()
218 PRER &= ~d->mask; gpio_set_wake()
219 PFER &= ~d->mask; gpio_set_wake()
241 gpio_desc[i].mask = GPIO_bit(i); pxa25x_mfp_init()
262 unsigned int i, gpio, mask = 0; keypad_set_wake() local
275 mask |= gpio_desc[gpio].mask; keypad_set_wake()
279 PKWR |= mask; keypad_set_wake()
281 PKWR &= ~mask; keypad_set_wake()
297 gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \
321 gpio_desc[gpio].mask = 1 << i; pxa27x_mfp_init()
331 gpio_desc[i].mask = GPIO_bit(i); pxa27x_mfp_init()
335 gpio_desc[35].mask = PWER_WE35; pxa27x_mfp_init()
H A Dpxa3xx.c201 unsigned long flags, mask = 0; pxa3xx_set_wake() local
205 mask = ADXER_MFP_WSSP3; pxa3xx_set_wake()
208 mask = ADXER_WMSL0; pxa3xx_set_wake()
212 mask = ADXER_WUSBH; pxa3xx_set_wake()
215 mask = ADXER_WKP; pxa3xx_set_wake()
218 mask = ADXER_MFP_WAC97; pxa3xx_set_wake()
221 mask = ADXER_WUSIM0; pxa3xx_set_wake()
224 mask = ADXER_MFP_WSSP2; pxa3xx_set_wake()
227 mask = ADXER_MFP_WI2C; pxa3xx_set_wake()
230 mask = ADXER_MFP_WUART3; pxa3xx_set_wake()
233 mask = ADXER_MFP_WUART2; pxa3xx_set_wake()
236 mask = ADXER_MFP_WUART1; pxa3xx_set_wake()
239 mask = ADXER_MFP_WMMC1; pxa3xx_set_wake()
242 mask = ADXER_MFP_WSSP1; pxa3xx_set_wake()
245 mask = ADXER_WRTC; pxa3xx_set_wake()
248 mask = ADXER_MFP_WSSP4; pxa3xx_set_wake()
251 mask = ADXER_WTSI; pxa3xx_set_wake()
254 mask = ADXER_WUSIM1; pxa3xx_set_wake()
257 mask = ADXER_MFP_WMMC2; pxa3xx_set_wake()
260 mask = ADXER_MFP_WFLASH; pxa3xx_set_wake()
263 mask = ADXER_WUSB2; pxa3xx_set_wake()
266 mask = ADXER_WEXTWAKE0; pxa3xx_set_wake()
269 mask = ADXER_WEXTWAKE1; pxa3xx_set_wake()
272 mask = ADXER_MFP_GEN12; pxa3xx_set_wake()
280 wakeup_src |= mask; pxa3xx_set_wake()
282 wakeup_src &= ~mask; pxa3xx_set_wake()
/linux-4.4.14/drivers/iommu/
H A Domap-iopgtable.h19 * "L2 table" address mask and size definitions.
26 * "section" address mask and size definitions.
33 * "supersection" address mask and size definitions.
43 * "small page" address mask and size definitions.
50 * "large page" address mask and size definitions.
65 * @mask: omap iommu descriptor mask
69 static inline phys_addr_t omap_iommu_translate(u32 d, u32 va, u32 mask) omap_iommu_translate() argument
71 return (d & mask) | (va & (~mask)); omap_iommu_translate()
/linux-4.4.14/drivers/input/joystick/
H A Danalog.c115 int mask; member in struct:analog
124 unsigned char mask; member in struct:analog_port
207 if (analog->mask & ANALOG_HAT_FCS) analog_decode()
215 if (analog->mask & (0x10 << i)) analog_decode()
218 if (analog->mask & ANALOG_HBTN_CHF) analog_decode()
222 if (analog->mask & ANALOG_BTN_TL) analog_decode()
224 if (analog->mask & ANALOG_BTN_TR) analog_decode()
226 if (analog->mask & ANALOG_BTN_TL2) analog_decode()
228 if (analog->mask & ANALOG_BTN_TR2) analog_decode()
232 if (analog->mask & (1 << i)) analog_decode()
236 if (analog->mask & analog_exts[i]) { analog_decode()
268 this = port->mask; analog_cooked_read()
276 this = gameport_read(gameport) & port->mask; analog_cooked_read()
297 return -(this != port->mask); analog_cooked_read()
321 while (((u = gameport_read(port->gameport)) & port->mask) && t) t--; analog_button_read()
337 char saitek = !!(port->analog[0].mask & ANALOG_SAITEK); analog_poll()
338 char chf = !!(port->analog[0].mask & ANALOG_ANY_CHF); analog_poll()
358 if (port->analog[i].mask) analog_poll()
439 hweight8(analog->mask & ANALOG_AXES_STD), analog_name()
440 hweight8(analog->mask & ANALOG_BTNS_STD) + !!(analog->mask & ANALOG_BTNS_CHF) * 2 + analog_name()
441 hweight16(analog->mask & ANALOG_BTNS_GAMEPAD) + !!(analog->mask & ANALOG_HBTN_CHF) * 4); analog_name()
443 if (analog->mask & ANALOG_HATS_ALL) analog_name()
445 analog->name, hweight16(analog->mask & ANALOG_HATS_ALL)); analog_name()
447 if (analog->mask & ANALOG_HAT_FCS) analog_name()
449 if (analog->mask & ANALOG_ANY_CHF) analog_name()
450 strlcat(analog->name, (analog->mask & ANALOG_SAITEK) ? " Saitek" : " CHF", analog_name()
453 strlcat(analog->name, (analog->mask & ANALOG_GAMEPAD) ? " gamepad": " joystick", analog_name()
470 analog->buttons = (analog->mask & ANALOG_GAMEPAD) ? analog_pad_btn : analog_joy_btn; analog_init_device()
480 input_dev->id.product = analog->mask >> 4; analog_init_device()
492 if (analog->mask & (1 << i)) { analog_init_device()
505 if (analog->mask & ANALOG_SAITEK) { analog_init_device()
516 if (analog->mask & analog_exts[i]) analog_init_device()
523 if (analog->mask & (0x10 << i)) analog_init_device()
526 if (analog->mask & ANALOG_BTNS_CHF) analog_init_device()
530 if (analog->mask & ANALOG_HBTN_CHF) analog_init_device()
535 if (analog->mask & (ANALOG_BTN_TL << i)) analog_init_device()
559 if (!port->mask) analog_init_masks()
562 if ((port->mask & 3) != 3 && port->mask != 0xc) { analog_init_masks()
565 port->mask, port->gameport->phys); analog_init_masks()
572 analog[0].mask = i & 0xfffff; analog_init_masks()
574 analog[0].mask &= ~(ANALOG_AXES_STD | ANALOG_HAT_FCS | ANALOG_BTNS_GAMEPAD) analog_init_masks()
575 | port->mask | ((port->mask << 8) & ANALOG_HAT_FCS) analog_init_masks()
576 | ((port->mask << 10) & ANALOG_BTNS_TLR) | ((port->mask << 12) & ANALOG_BTNS_TLR2); analog_init_masks()
578 analog[0].mask &= ~(ANALOG_HAT2_CHF) analog_init_masks()
579 | ((analog[0].mask & ANALOG_HBTN_CHF) ? 0 : ANALOG_HAT2_CHF); analog_init_masks()
581 analog[0].mask &= ~(ANALOG_THROTTLE | ANALOG_BTN_TR | ANALOG_BTN_TR2) analog_init_masks()
582 | ((~analog[0].mask & ANALOG_HAT_FCS) >> 8) analog_init_masks()
583 | ((~analog[0].mask & ANALOG_HAT_FCS) << 2) analog_init_masks()
584 | ((~analog[0].mask & ANALOG_HAT_FCS) << 4); analog_init_masks()
586 analog[0].mask &= ~(ANALOG_THROTTLE | ANALOG_RUDDER) analog_init_masks()
587 | (((~analog[0].mask & ANALOG_BTNS_TLR ) >> 10) analog_init_masks()
588 & ((~analog[0].mask & ANALOG_BTNS_TLR2) >> 12)); analog_init_masks()
590 analog[1].mask = ((i >> 20) & 0xff) | ((i >> 12) & 0xf0000); analog_init_masks()
592 analog[1].mask &= (analog[0].mask & ANALOG_EXTENSIONS) ? ANALOG_GAMEPAD analog_init_masks()
593 : (((ANALOG_BTNS_STD | port->mask) & ~analog[0].mask) | ANALOG_GAMEPAD); analog_init_masks()
599 if ((analog[0].mask & 0x7) == 0x7) max[2] = (max[0] + max[1]) >> 1; analog_init_masks()
600 if ((analog[0].mask & 0xb) == 0xb) max[3] = (max[0] + max[1]) >> 1; analog_init_masks()
601 if ((analog[0].mask & ANALOG_BTN_TL) && !(analog[0].mask & ANALOG_BTN_TL2)) max[2] >>= 1; analog_init_masks()
602 if ((analog[0].mask & ANALOG_BTN_TR) && !(analog[0].mask & ANALOG_BTN_TR2)) max[3] >>= 1; analog_init_masks()
603 if ((analog[0].mask & ANALOG_HAT_FCS)) max[3] >>= 1; analog_init_masks()
611 return -!(analog[0].mask || analog[1].mask); analog_init_masks()
629 port->mask = (gameport_read(gameport) ^ t) & t & 0xf; analog_init_port()
643 while ((gameport_read(port->gameport) & port->mask) && (u < t)) analog_init_port()
648 while ((gameport_read(port->gameport) & port->mask) && (v < t)) analog_init_port()
667 port->mask |= 1 << i; analog_init_port()
698 if (port->analog[i].mask) { analog_connect()
707 if (port->analog[i].mask) analog_connect()
721 if (port->analog[i].mask) analog_disconnect()
/linux-4.4.14/fs/ocfs2/cluster/
H A Dmasklog.c36 static ssize_t mlog_mask_show(u64 mask, char *buf) mlog_mask_show() argument
40 if (__mlog_test_u64(mask, mlog_and_bits)) mlog_mask_show()
42 else if (__mlog_test_u64(mask, mlog_not_bits)) mlog_mask_show()
50 static ssize_t mlog_mask_store(u64 mask, const char *buf, size_t count) mlog_mask_store() argument
53 __mlog_set_u64(mask, mlog_and_bits); mlog_mask_store()
54 __mlog_clear_u64(mask, mlog_not_bits); mlog_mask_store()
56 __mlog_set_u64(mask, mlog_not_bits); mlog_mask_store()
57 __mlog_clear_u64(mask, mlog_and_bits); mlog_mask_store()
59 __mlog_clear_u64(mask, mlog_not_bits); mlog_mask_store()
60 __mlog_clear_u64(mask, mlog_and_bits); mlog_mask_store()
67 void __mlog_printk(const u64 *mask, const char *func, int line, __mlog_printk() argument
75 if (!__mlog_test_u64(*mask, mlog_and_bits) || __mlog_printk()
76 __mlog_test_u64(*mask, mlog_not_bits)) __mlog_printk()
79 if (*mask & ML_ERROR) { __mlog_printk()
82 } else if (*mask & ML_NOTICE) { __mlog_printk()
103 u64 mask; member in struct:mlog_attribute
113 .mask = ML_##_name, \
146 return mlog_mask_show(mlog_attr->mask, buf); mlog_show()
154 return mlog_mask_store(mlog_attr->mask, buf, count); mlog_store()
H A Dmasklog.h49 * mask, as is almost always the case.
134 #define __mlog_test_u64(mask, bits) \
135 ( (u32)(mask & 0xffffffff) & bits.words[0] || \
136 ((u64)(mask) >> 32) & bits.words[1] )
137 #define __mlog_set_u64(mask, bits) do { \
138 bits.words[0] |= (u32)(mask & 0xffffffff); \
139 bits.words[1] |= (u64)(mask) >> 32; \
141 #define __mlog_clear_u64(mask, bits) do { \
142 bits.words[0] &= ~((u32)(mask & 0xffffffff)); \
143 bits.words[1] &= ~((u64)(mask) >> 32); \
145 #define MLOG_BITS_RHS(mask) { \
147 [0] = (u32)(mask & 0xffffffff), \
148 [1] = (u64)(mask) >> 32, \
154 #define __mlog_test_u64(mask, bits) ((mask) & bits.words[0])
155 #define __mlog_set_u64(mask, bits) do { \
156 bits.words[0] |= (mask); \
158 #define __mlog_clear_u64(mask, bits) do { \
159 bits.words[0] &= ~(mask); \
161 #define MLOG_BITS_RHS(mask) { { (mask) } }
173 #define mlog(mask, fmt, ...) \
175 u64 _m = MLOG_MASK_PREFIX | (mask); \
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Ddt2817.c49 unsigned int mask; dt2817_dio_insn_config() local
53 mask = 0x000000ff; dt2817_dio_insn_config()
55 mask = 0x0000ff00; dt2817_dio_insn_config()
57 mask = 0x00ff0000; dt2817_dio_insn_config()
59 mask = 0xff000000; dt2817_dio_insn_config()
61 ret = comedi_dio_insn_config(dev, s, insn, data, mask); dt2817_dio_insn_config()
85 unsigned int mask; dt2817_dio_insn_bits() local
88 mask = comedi_dio_update_state(s, data); dt2817_dio_insn_bits()
89 if (mask) { dt2817_dio_insn_bits()
90 if (mask & 0x000000ff) dt2817_dio_insn_bits()
92 if (mask & 0x0000ff00) dt2817_dio_insn_bits()
94 if (mask & 0x00ff0000) dt2817_dio_insn_bits()
96 if (mask & 0xff000000) dt2817_dio_insn_bits()
/linux-4.4.14/drivers/irqchip/
H A Dirq-xtensa-mx.c70 unsigned int mask = 1u << d->hwirq; xtensa_mx_irq_mask() local
72 if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | xtensa_mx_irq_mask()
77 mask = __this_cpu_read(cached_irq_mask) & ~mask; xtensa_mx_irq_mask()
78 __this_cpu_write(cached_irq_mask, mask); xtensa_mx_irq_mask()
79 set_sr(mask, intenable); xtensa_mx_irq_mask()
85 unsigned int mask = 1u << d->hwirq; xtensa_mx_irq_unmask() local
87 if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | xtensa_mx_irq_unmask()
92 mask |= __this_cpu_read(cached_irq_mask); xtensa_mx_irq_unmask()
93 __this_cpu_write(cached_irq_mask, mask); xtensa_mx_irq_unmask()
94 set_sr(mask, intenable); xtensa_mx_irq_unmask()
124 unsigned mask = 1u << cpumask_any_and(dest, cpu_online_mask); xtensa_mx_irq_set_affinity() local
126 set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE)); xtensa_mx_irq_set_affinity()
/linux-4.4.14/drivers/pinctrl/spear/
H A Dpinctrl-spear320.c37 .mask = 0x00000007,
45 .mask = 0x00000007,
53 .mask = 0x00000007,
61 .mask = 0x00000007,
69 .mask = 0x00000001,
466 .mask = PMX_PL_69_MASK,
470 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
478 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
484 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
523 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
531 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
535 .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK |
542 .mask = PMX_PL_69_MASK,
546 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
554 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
560 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
566 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
604 .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK |
610 .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK |
616 .mask = EMI_FSMC_DYNAMIC_MUX_MASK,
642 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
650 .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK,
654 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK,
697 .mask = PMX_PL_69_MASK,
701 .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK |
709 .mask = PMX_PL_80_TO_85_MASK,
742 .mask = PMX_SSP_CS_MASK,
750 .mask = PMX_PL_34_MASK,
782 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
790 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK |
796 .mask = PMX_PL_50_MASK,
800 .mask = PMX_PL_99_MASK,
804 .mask = PMX_PL_100_101_MASK,
812 .mask = PMX_MII_MASK,
816 .mask = PMX_PL_12_MASK,
820 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
828 .mask = PMX_PL_51_MASK,
832 .mask = PMX_SDHCI_CD_PORT_SEL_MASK,
899 .mask = PMX_SSP_CS_MASK,
903 .mask = PMX_UART0_MODEM_MASK,
911 .mask = PMX_PL_35_MASK | PMX_PL_39_MASK,
915 .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK,
952 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
960 .mask = PMX_PL_28_29_MASK,
1002 .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK,
1006 .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK,
1011 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1019 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
1028 .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK |
1035 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1043 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK |
1052 .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK,
1057 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1061 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1069 .mask = PMX_PL_80_TO_85_MASK,
1073 .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK,
1077 .mask = PMX_UART1_ENH_PORT_SEL_MASK,
1164 .mask = PMX_FIRDA_MASK,
1172 .mask = PMX_PL_0_1_MASK,
1212 .mask = PMX_SSP_MASK,
1216 .mask = PMX_PL_8_9_MASK,
1220 .mask = PMX_UART3_PORT_SEL_MASK,
1228 .mask = PMX_MII_MASK,
1232 .mask = PMX_PL_15_16_MASK,
1236 .mask = PMX_UART3_PORT_SEL_MASK,
1244 .mask = PMX_UART0_MODEM_MASK,
1248 .mask = PMX_PL_41_42_MASK,
1252 .mask = PMX_UART3_PORT_SEL_MASK,
1260 .mask = PMX_PL_52_53_MASK,
1264 .mask = PMX_UART3_PORT_SEL_MASK,
1272 .mask = PMX_PL_73_MASK | PMX_PL_74_MASK,
1276 .mask = PMX_UART3_PORT_SEL_MASK,
1284 .mask = PMX_PL_94_95_MASK,
1288 .mask = PMX_UART3_PORT_SEL_MASK,
1296 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
1300 .mask = PMX_UART3_PORT_SEL_MASK,
1421 .mask = PMX_SSP_MASK,
1425 .mask = PMX_PL_6_7_MASK,
1429 .mask = PMX_UART4_PORT_SEL_MASK,
1437 .mask = PMX_MII_MASK,
1441 .mask = PMX_PL_13_14_MASK,
1445 .mask = PMX_UART4_PORT_SEL_MASK,
1453 .mask = PMX_UART0_MODEM_MASK,
1457 .mask = PMX_PL_39_MASK,
1461 .mask = PMX_PL_40_MASK,
1465 .mask = PMX_UART4_PORT_SEL_MASK,
1473 .mask = PMX_PL_71_72_MASK,
1477 .mask = PMX_UART4_PORT_SEL_MASK,
1485 .mask = PMX_PL_92_93_MASK,
1489 .mask = PMX_UART4_PORT_SEL_MASK,
1497 .mask = PMX_PL_100_101_MASK |
1607 .mask = PMX_I2C_MASK,
1611 .mask = PMX_PL_4_5_MASK,
1615 .mask = PMX_UART5_PORT_SEL_MASK,
1623 .mask = PMX_UART0_MODEM_MASK,
1627 .mask = PMX_PL_37_38_MASK,
1631 .mask = PMX_UART5_PORT_SEL_MASK,
1639 .mask = PMX_PL_69_MASK,
1643 .mask = PMX_PL_70_MASK,
1647 .mask = PMX_UART5_PORT_SEL_MASK,
1655 .mask = PMX_PL_90_91_MASK,
1659 .mask = PMX_UART5_PORT_SEL_MASK,
1737 .mask = PMX_UART0_MASK,
1741 .mask = PMX_PL_2_3_MASK,
1745 .mask = PMX_UART6_PORT_SEL_MASK,
1753 .mask = PMX_PL_88_89_MASK,
1757 .mask = PMX_UART6_PORT_SEL_MASK,
1808 .mask = PMX_PL_77_78_79_MASK,
1841 .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK,
1849 .mask = PMX_PL_5_MASK,
1853 .mask = PMX_PL_36_MASK,
1890 .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
1898 .mask = PMX_PL_32_33_MASK,
1935 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
1943 .mask = PMX_PL_30_31_MASK,
1983 .mask = PMX_SSP_MASK,
1987 .mask = PMX_PL_8_9_MASK,
1995 .mask = PMX_MII_MASK,
2003 .mask = PMX_PL_14_MASK | PMX_PL_15_MASK,
2011 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK,
2015 .mask = PMX_PL_30_MASK | PMX_PL_31_MASK,
2023 .mask = PMX_UART0_MODEM_MASK,
2031 .mask = PMX_PL_37_38_MASK,
2039 .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK ,
2043 .mask = PMX_PL_42_MASK | PMX_PL_43_MASK,
2052 .mask = PMX_PL_59_MASK,
2056 .mask = PMX_PL_60_MASK,
2064 .mask = PMX_PL_88_89_MASK,
2196 .mask = PMX_SSP_CS_MASK,
2204 .mask = PMX_PL_7_MASK,
2212 .mask = PMX_MII_MASK,
2220 .mask = PMX_PL_13_MASK,
2228 .mask = PMX_GPIO_PIN1_MASK,
2232 .mask = PMX_PL_29_MASK,
2240 .mask = PMX_SSP_CS_MASK,
2244 .mask = PMX_PWM_MASK,
2248 .mask = PMX_PL_34_MASK,
2256 .mask = PMX_UART0_MODEM_MASK,
2260 .mask = PMX_PL_41_MASK,
2268 .mask = PMX_PL_58_MASK,
2276 .mask = PMX_PL_87_MASK,
2403 .mask = PMX_SSP_MASK,
2407 .mask = PMX_PL_6_MASK,
2415 .mask = PMX_MII_MASK,
2423 .mask = PMX_PL_12_MASK,
2431 .mask = PMX_GPIO_PIN0_MASK,
2435 .mask = PMX_PL_28_MASK,
2443 .mask = PMX_UART0_MODEM_MASK,
2447 .mask = PMX_PL_40_MASK,
2455 .mask = PMX_PL_57_MASK,
2463 .mask = PMX_PL_86_MASK,
2576 .mask = PMX_MII_MASK,
2584 .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK,
2588 .mask = PMX_PL_20_MASK,
2592 .mask = PMX_SSP1_PORT_SEL_MASK,
2600 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
2604 .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK,
2609 .mask = PMX_SSP1_PORT_SEL_MASK,
2617 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2621 .mask = PMX_PL_48_49_MASK,
2625 .mask = PMX_PL_50_51_MASK,
2629 .mask = PMX_SSP1_PORT_SEL_MASK,
2637 .mask = PMX_PL_65_TO_68_MASK,
2641 .mask = PMX_SSP1_PORT_SEL_MASK,
2649 .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK,
2653 .mask = PMX_SSP1_PORT_SEL_MASK,
2751 .mask = PMX_MII_MASK,
2759 .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK,
2763 .mask = PMX_SSP2_PORT_SEL_MASK,
2771 .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK |
2776 .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK,
2781 .mask = PMX_SSP2_PORT_SEL_MASK,
2789 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
2793 .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK,
2797 .mask = PMX_SSP2_PORT_SEL_MASK,
2805 .mask = PMX_PL_61_TO_64_MASK,
2809 .mask = PMX_SSP2_PORT_SEL_MASK,
2817 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK,
2821 .mask = PMX_SSP2_PORT_SEL_MASK,
2918 .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK |
2924 .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK |
2930 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2969 .mask = PMX_MII_MASK,
2977 .mask = PMX_PL_10_11_MASK,
2981 .mask = PMX_PL_21_TO_27_MASK,
2985 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
2997 .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK |
3004 .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK,
3008 .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) |
3073 .mask = PMX_SSP_CS_MASK,
3077 .mask = PMX_PL_8_9_MASK,
3081 .mask = PMX_I2C1_PORT_SEL_MASK,
3089 .mask = PMX_PL_98_MASK | PMX_PL_99_MASK,
3093 .mask = PMX_I2C1_PORT_SEL_MASK,
3145 .mask = PMX_FIRDA_MASK,
3149 .mask = PMX_PL_0_1_MASK,
3153 .mask = PMX_I2C2_PORT_SEL_MASK,
3161 .mask = PMX_UART0_MASK,
3165 .mask = PMX_PL_2_3_MASK,
3169 .mask = PMX_I2C2_PORT_SEL_MASK,
3177 .mask = PMX_MII_MASK,
3181 .mask = PMX_PL_19_MASK,
3185 .mask = PMX_PL_20_MASK,
3189 .mask = PMX_I2C2_PORT_SEL_MASK,
3197 .mask = PMX_PL_75_76_MASK,
3201 .mask = PMX_I2C2_PORT_SEL_MASK,
3209 .mask = PMX_PL_96_97_MASK,
3213 .mask = PMX_I2C2_PORT_SEL_MASK,
H A Dpinctrl-spear1310.c242 .mask = PMX_I2C0_MASK,
246 .mask = PMX_I2C0_MASK,
278 .mask = PMX_SSP0_MASK,
282 .mask = PMX_SSP0_MASK,
307 .mask = PMX_SSP0_CS0_MASK,
311 .mask = PMX_SSP0_CS0_MASK,
336 .mask = PMX_SSP0_CS1_2_MASK,
340 .mask = PMX_SSP0_CS1_2_MASK,
373 .mask = PMX_I2S0_MASK,
377 .mask = PMX_I2S0_MASK,
409 .mask = PMX_I2S1_MASK,
413 .mask = PMX_I2S1_MASK,
447 .mask = PMX_CLCD1_MASK,
451 .mask = PMX_CLCD1_MASK,
476 .mask = PMX_CLCD2_MASK,
480 .mask = PMX_CLCD2_MASK,
512 .mask = PMX_EGPIO_0_GRP_MASK,
516 .mask = PMX_EGPIO_1_GRP_MASK,
520 .mask = PMX_EGPIO_0_GRP_MASK,
524 .mask = PMX_EGPIO_1_GRP_MASK,
556 .mask = PMX_SMI_MASK,
560 .mask = PMX_SMI_MASK,
584 .mask = PMX_SMI_MASK,
588 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
592 .mask = PMX_SMI_MASK,
596 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
630 .mask = PMX_GMII_MASK,
634 .mask = PMX_GMII_MASK,
668 .mask = PMX_RGMII_REG0_MASK,
672 .mask = PMX_RGMII_REG1_MASK,
676 .mask = PMX_RGMII_REG2_MASK,
680 .mask = PMX_RGMII_REG0_MASK,
684 .mask = PMX_RGMII_REG1_MASK,
688 .mask = PMX_RGMII_REG2_MASK,
722 .mask = PMX_SMII_0_1_2_MASK,
726 .mask = PMX_SMII_0_1_2_MASK,
758 .mask = PMX_NFCE2_MASK,
762 .mask = PMX_NFCE2_MASK,
798 .mask = PMX_NAND8BIT_0_MASK,
802 .mask = PMX_NAND8BIT_1_MASK,
806 .mask = PMX_NAND8BIT_0_MASK,
810 .mask = PMX_NAND8BIT_1_MASK,
836 .mask = PMX_NAND16BIT_1_MASK,
840 .mask = PMX_NAND16BIT_1_MASK,
865 .mask = PMX_NAND_4CHIPS_MASK,
869 .mask = PMX_NAND_4CHIPS_MASK,
903 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
930 .mask = PMX_KBD_ROWCOL68_MASK,
934 .mask = PMX_KBD_ROWCOL68_MASK,
967 .mask = PMX_UART0_MASK,
971 .mask = PMX_UART0_MASK,
996 .mask = PMX_UART0_MODEM_MASK,
1000 .mask = PMX_UART0_MODEM_MASK,
1032 .mask = PMX_GPT0_TMR0_MASK,
1036 .mask = PMX_GPT0_TMR0_MASK,
1061 .mask = PMX_GPT0_TMR1_MASK,
1065 .mask = PMX_GPT0_TMR1_MASK,
1097 .mask = PMX_GPT1_TMR0_MASK,
1101 .mask = PMX_GPT1_TMR0_MASK,
1126 .mask = PMX_GPT1_TMR1_MASK,
1130 .mask = PMX_GPT1_TMR1_MASK,
1165 .mask = PMX_MCI_DATA8_15_MASK, \
1169 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1174 .mask = PMX_MCIFALL_2_MASK, \
1178 .mask = PMX_MCI_DATA8_15_MASK, \
1182 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1188 .mask = PMX_MCIFALL_2_MASK, \
1197 .mask = MCIF_SEL_MASK,
1229 .mask = MCIF_SEL_MASK,
1261 .mask = MCIF_SEL_MASK,
1293 .mask = PMX_TOUCH_XY_MASK,
1297 .mask = PMX_TOUCH_XY_MASK,
1330 .mask = PMX_I2C0_MASK,
1334 .mask = PMX_I2C0_MASK,
1359 .mask = PMX_MCIDATA1_MASK |
1364 .mask = PMX_MCIDATA1_MASK |
1399 .mask = PMX_I2S0_MASK,
1403 .mask = PMX_I2S0_MASK,
1435 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1439 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1471 .mask = PMX_CLCD1_MASK,
1475 .mask = PMX_CLCD1_MASK,
1509 .mask = PMX_CLCD1_MASK,
1513 .mask = PMX_CLCD1_MASK,
1545 .mask = PMX_CLCD1_MASK,
1549 .mask = PMX_CLCD1_MASK,
1582 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1586 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1612 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1616 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1650 .mask = PMX_SMI_MASK,
1654 .mask = PMX_SMI_MASK,
1680 .mask = PMX_MCIDATA4_MASK,
1684 .mask = PMX_MCIDATA5_MASK,
1688 .mask = PMX_MCIDATA4_MASK,
1692 .mask = PMX_MCIDATA5_MASK,
1718 .mask = PMX_MCIDATA6_MASK |
1723 .mask = PMX_MCIDATA6_MASK |
1759 .mask = PMX_KBD_ROWCOL25_MASK,
1763 .mask = PMX_KBD_ROWCOL25_MASK,
1789 .mask = PMX_MCIIORDRE_MASK |
1794 .mask = PMX_MCIIORDRE_MASK |
1821 .mask = PMX_MCIRESETCF_MASK |
1826 .mask = PMX_MCIRESETCF_MASK |
1862 .mask = PMX_NFRSTPWDWN2_MASK,
1866 .mask = PMX_NFRSTPWDWN3_MASK,
1870 .mask = PMX_NFRSTPWDWN2_MASK,
1874 .mask = PMX_NFRSTPWDWN3_MASK,
1900 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1904 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1938 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1942 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1968 .mask = PMX_KBD_ROWCOL25_MASK,
1972 .mask = PMX_KBD_ROWCOL25_MASK,
2009 .mask = PMX_MCI_DATA8_15_MASK,
2013 .mask = PMX_PCI_REG1_MASK,
2017 .mask = PMX_PCI_REG2_MASK,
2021 .mask = PMX_MCI_DATA8_15_MASK,
2025 .mask = PMX_PCI_REG1_MASK,
2029 .mask = PMX_PCI_REG2_MASK,
2060 .mask = PCIE_CFG_VAL(0),
2082 .mask = PCIE_CFG_VAL(1),
2104 .mask = PCIE_CFG_VAL(2),
2134 .mask = SATA_CFG_VAL(0),
2156 .mask = SATA_CFG_VAL(1),
2178 .mask = SATA_CFG_VAL(2),
2209 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2215 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2244 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2249 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2284 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2289 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
H A Dpinctrl-spear1340.c220 .mask = PADS_AS_GPIO_REG0_MASK,
224 .mask = PADS_AS_GPIO_REGS_MASK,
228 .mask = PADS_AS_GPIO_REGS_MASK,
232 .mask = PADS_AS_GPIO_REGS_MASK,
236 .mask = PADS_AS_GPIO_REGS_MASK,
240 .mask = PADS_AS_GPIO_REGS_MASK,
244 .mask = PADS_AS_GPIO_REGS_MASK,
248 .mask = PADS_AS_GPIO_REG7_MASK,
281 .mask = FSMC_8BIT_REG7_MASK,
306 .mask = KBD_ROW_COL_MASK,
310 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
337 .mask = MCIF_MASK,
341 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK,
375 .mask = KBD_ROW_COL_MASK,
379 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK,
404 .mask = KBD_COL5_MASK,
408 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
441 .mask = SPDIF_IN_REG0_MASK,
473 .mask = SPDIF_OUT_REG4_MASK,
477 .mask = SPDIF_OUT_ENB_MASK,
509 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK,
513 .mask = UART0_ENH_AND_GPT_REG0_MASK |
549 .mask = SSP0_CS1_MASK,
553 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
578 .mask = KBD_COL5_MASK,
582 .mask = PWM1_AND_KBD_COL5_REG0_MASK,
607 .mask = GPT0_TMR0_CPT_MASK,
611 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK,
636 .mask = GPT0_TMR1_CLK_MASK,
640 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK,
673 .mask = VIP_REG1_MASK,
699 .mask = CAM0_MASK,
703 .mask = VIP_AND_CAM0_REG2_MASK,
729 .mask = CAM1_MASK,
733 .mask = VIP_AND_CAM1_REG1_MASK,
737 .mask = VIP_AND_CAM1_REG2_MASK,
763 .mask = CAM2_MASK,
767 .mask = VIP_AND_CAM2_REG1_MASK,
793 .mask = CAM3_MASK,
797 .mask = VIP_AND_CAM3_REG0_MASK,
801 .mask = VIP_AND_CAM3_REG1_MASK,
835 .mask = CAM0_MASK,
839 .mask = VIP_AND_CAM0_REG2_MASK,
872 .mask = CAM1_MASK,
876 .mask = VIP_AND_CAM1_REG1_MASK,
880 .mask = VIP_AND_CAM1_REG2_MASK,
913 .mask = CAM2_MASK,
917 .mask = VIP_AND_CAM2_REG1_MASK,
950 .mask = CAM3_MASK,
954 .mask = VIP_AND_CAM3_REG0_MASK,
958 .mask = VIP_AND_CAM3_REG1_MASK,
990 .mask = SMI_REG2_MASK,
1022 .mask = SSP0_REG2_MASK,
1047 .mask = SSP0_CS1_MASK,
1051 .mask = PWM0_AND_SSP0_CS1_REG0_MASK,
1076 .mask = SSP0_CS2_MASK,
1080 .mask = TS_AND_SSP0_CS2_REG2_MASK,
1105 .mask = SSP0_CS3_REG4_MASK,
1138 .mask = UART0_REG2_MASK,
1163 .mask = GPT_MASK,
1167 .mask = UART0_ENH_AND_GPT_REG0_MASK,
1199 .mask = UART1_REG2_MASK,
1231 .mask = I2S_IN_REG2_MASK,
1235 .mask = I2S_IN_REG3_MASK,
1260 .mask = I2S_OUT_REG3_MASK,
1294 .mask = GMAC_REG3_MASK, \
1298 .mask = GMAC_REG4_MASK, \
1307 .mask = GMAC_PHY_IF_SEL_MASK,
1332 .mask = GMAC_PHY_IF_SEL_MASK,
1357 .mask = GMAC_PHY_IF_SEL_MASK,
1382 .mask = GMAC_PHY_IF_SEL_MASK,
1415 .mask = I2C0_REG4_MASK,
1447 .mask = I2C1_REG0_MASK,
1479 .mask = CEC0_REG4_MASK,
1511 .mask = CEC1_REG4_MASK,
1546 .mask = MCIF_MASK, \
1550 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \
1554 .mask = MCIF_REG7_MASK, \
1563 .mask = MCIF_SEL_MASK,
1595 .mask = MCIF_SEL_MASK,
1627 .mask = MCIF_SEL_MASK,
1663 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1667 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1671 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1675 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1699 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK,
1703 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK,
1707 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1711 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1746 .mask = ARM_TRACE_MASK,
1750 .mask = CLCD_AND_ARM_TRACE_REG4_MASK,
1754 .mask = CLCD_AND_ARM_TRACE_REG5_MASK,
1758 .mask = CLCD_AND_ARM_TRACE_REG6_MASK,
1792 .mask = MIPHY_DBG_MASK,
1796 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK,
1828 .mask = SATA_PCIE_CFG_MASK,
1860 .mask = SATA_PCIE_CFG_MASK,
H A Dpinctrl-spear300.c44 .mask = 0x0000000F,
52 .mask = 0x0000000F,
60 .mask = 0x0000000F,
68 .mask = 0x0000000F,
76 .mask = 0x0000000F,
84 .mask = 0x0000000F,
92 .mask = 0x0000000F,
100 .mask = 0x0000000F,
108 .mask = 0x0000000F,
116 .mask = 0x0000000F,
124 .mask = 0x0000000F,
132 .mask = 0x0000000F,
140 .mask = 0x0000000F,
165 .mask = PMX_FIRDA_MASK,
192 .mask = PMX_FIRDA_MASK | PMX_UART0_MASK,
227 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
254 .mask = PMX_TIMER_2_3_MASK,
288 .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK,
325 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
361 .mask = PMX_MII_MASK,
387 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK,
420 .mask = PMX_TIMER_0_1_MASK,
454 .mask = PMX_UART0_MODEM_MASK,
490 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
522 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK |
560 .mask = PMX_UART0_MODEM_MASK,
587 .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK,
/linux-4.4.14/drivers/gpu/drm/exynos/
H A Dregs-rotator.h66 #define ROT_ALIGN(x, align, mask) (((x) + (1 << ((align) - 1))) & (mask))
68 #define ROT_MIN(min, mask) (((min) + ~(mask)) & (mask))
70 #define ROT_MAX(max, mask) ((max) & (mask))
/linux-4.4.14/drivers/clk/qcom/
H A Dreset.c35 u32 mask; qcom_reset_assert() local
39 mask = BIT(map->bit); qcom_reset_assert()
41 return regmap_update_bits(rst->regmap, map->reg, mask, mask); qcom_reset_assert()
49 u32 mask; qcom_reset_deassert() local
53 mask = BIT(map->bit); qcom_reset_deassert()
55 return regmap_update_bits(rst->regmap, map->reg, mask, 0); qcom_reset_deassert()
/linux-4.4.14/net/bridge/netfilter/
H A Debt_mark_m.c21 return !!(skb->mark & info->mask) ^ info->invert; ebt_mark_mt()
22 return ((skb->mark & info->mask) == info->mark) ^ info->invert; ebt_mark_mt()
41 compat_ulong_t mark, mask; member in struct:compat_ebt_mark_m_info
51 kern->mask = user->mask; mark_mt_compat_from_user()
62 put_user(kern->mask, &user->mask) || mark_mt_compat_to_user()
/linux-4.4.14/drivers/crypto/ux500/cryp/
H A Dcryp_p.h23 #define CRYP_SET_BITS(reg_name, mask) \
24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
26 #define CRYP_WRITE_BIT(reg_name, val, mask) \
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
28 ((val) & (mask))), reg_name)
33 #define CRYP_PUT_BITS(reg, val, shift, mask) \
34 writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
35 (((u32)val << shift) & (mask))), reg)
66 * CRYP Control register specific mask
/linux-4.4.14/fs/nfsd/
H A Dnfs4acl.c68 int mask = NFS4_ANYONE_MODE; mask_from_posix() local
71 mask |= NFS4_OWNER_MODE; mask_from_posix()
73 mask |= NFS4_READ_MODE; mask_from_posix()
75 mask |= NFS4_WRITE_MODE; mask_from_posix()
77 mask |= NFS4_ACE_DELETE_CHILD; mask_from_posix()
79 mask |= NFS4_EXECUTE_MODE; mask_from_posix()
80 return mask; mask_from_posix()
86 u32 mask = 0; deny_mask_from_posix() local
89 mask |= NFS4_READ_MODE; deny_mask_from_posix()
91 mask |= NFS4_WRITE_MODE; deny_mask_from_posix()
93 mask |= NFS4_ACE_DELETE_CHILD; deny_mask_from_posix()
95 mask |= NFS4_EXECUTE_MODE; deny_mask_from_posix()
96 return mask; deny_mask_from_posix()
185 unsigned short mask; member in struct:posix_acl_summary
199 pas->mask = 07; summarize_posix_acl()
221 pas->mask = pa->e_perm; FOREACH_ACL_ENTRY()
226 pas->users &= pas->mask;
227 pas->group &= pas->mask;
228 pas->groups &= pas->mask;
274 deny = ~(pa->e_perm & pas.mask); _posix_to_nfsv4_one()
287 ace->access_mask = mask_from_posix(pa->e_perm & pas.mask, _posix_to_nfsv4_one()
314 ace->access_mask = mask_from_posix(pa->e_perm & pas.mask, _posix_to_nfsv4_one()
339 deny = ~(pa->e_perm & pas.mask); _posix_to_nfsv4_one()
449 struct posix_ace_state mask; /* Deny unused in this case */ member in struct:posix_acl_state
487 state->mask.allow |= astate->allow; add_to_mask()
549 low_mode_from_nfs4(state->mask.allow, &pace->e_perm, flags); posix_state_to_acl()
559 static inline void allow_bits(struct posix_ace_state *astate, u32 mask) allow_bits() argument
561 /* Allow all bits in the mask not already denied: */ allow_bits()
562 astate->allow |= mask & ~astate->deny; allow_bits()
565 static inline void deny_bits(struct posix_ace_state *astate, u32 mask) deny_bits() argument
567 /* Deny all bits in the mask not already allowed: */ deny_bits()
568 astate->deny |= mask & ~astate->allow; deny_bits()
605 static void deny_bits_array(struct posix_ace_state_array *a, u32 mask) deny_bits_array() argument
610 deny_bits(&a->aces[i].perms, mask); deny_bits_array()
613 static void allow_bits_array(struct posix_ace_state_array *a, u32 mask) allow_bits_array() argument
618 allow_bits(&a->aces[i].perms, mask); allow_bits_array()
624 u32 mask = ace->access_mask; process_one_v4_ace() local
632 allow_bits(&state->owner, mask); process_one_v4_ace()
634 deny_bits(&state->owner, mask); process_one_v4_ace()
640 allow_bits(&state->users->aces[i].perms, mask); process_one_v4_ace()
642 deny_bits(&state->users->aces[i].perms, mask); process_one_v4_ace()
643 mask = state->users->aces[i].perms.deny; process_one_v4_ace()
644 deny_bits(&state->owner, mask); process_one_v4_ace()
649 allow_bits(&state->group, mask); process_one_v4_ace()
651 deny_bits(&state->group, mask); process_one_v4_ace()
652 mask = state->group.deny; process_one_v4_ace()
653 deny_bits(&state->owner, mask); process_one_v4_ace()
654 deny_bits(&state->everyone, mask); process_one_v4_ace()
655 deny_bits_array(state->users, mask); process_one_v4_ace()
656 deny_bits_array(state->groups, mask); process_one_v4_ace()
662 allow_bits(&state->groups->aces[i].perms, mask); process_one_v4_ace()
664 deny_bits(&state->groups->aces[i].perms, mask); process_one_v4_ace()
665 mask = state->groups->aces[i].perms.deny; process_one_v4_ace()
666 deny_bits(&state->owner, mask); process_one_v4_ace()
667 deny_bits(&state->group, mask); process_one_v4_ace()
668 deny_bits(&state->everyone, mask); process_one_v4_ace()
669 deny_bits_array(state->users, mask); process_one_v4_ace()
670 deny_bits_array(state->groups, mask); process_one_v4_ace()
675 allow_bits(&state->owner, mask); process_one_v4_ace()
676 allow_bits(&state->group, mask); process_one_v4_ace()
677 allow_bits(&state->other, mask); process_one_v4_ace()
678 allow_bits(&state->everyone, mask); process_one_v4_ace()
679 allow_bits_array(state->users, mask); process_one_v4_ace()
680 allow_bits_array(state->groups, mask); process_one_v4_ace()
682 deny_bits(&state->owner, mask); process_one_v4_ace()
683 deny_bits(&state->group, mask); process_one_v4_ace()
684 deny_bits(&state->other, mask); process_one_v4_ace()
685 deny_bits(&state->everyone, mask); process_one_v4_ace()
686 deny_bits_array(state->users, mask); process_one_v4_ace()
687 deny_bits_array(state->groups, mask); process_one_v4_ace()
/linux-4.4.14/drivers/media/usb/pvrusb2/
H A Dpvrusb2-ctrl.h37 int pvr2_ctrl_set_mask_value(struct pvr2_ctrl *,int mask,int val);
57 /* Retrieve control's valid mask bits (bit mask only) */
66 /* Retrieve a control enumeration or bit mask value */
83 /* Convert a given mask/val to a custom symbolic value */
85 int mask,int val,
89 /* Convert a symbolic value to a mask/value pair */
94 /* Convert a given mask/val to a symbolic value */
96 int mask,int val,
100 /* Convert a symbolic value to a mask/value pair */
105 /* Convert a given mask/val to a symbolic value - must already be
108 int mask,int val,
/linux-4.4.14/arch/powerpc/kernel/
H A Ddma-iommu.c76 int dma_iommu_dma_supported(struct device *dev, u64 mask) dma_iommu_dma_supported() argument
81 dev_info(dev, "Warning: IOMMU dma not supported: mask 0x%08llx" dma_iommu_dma_supported()
82 ", table unavailable\n", mask); dma_iommu_dma_supported()
86 if (tbl->it_offset > (mask >> tbl->it_page_shift)) { dma_iommu_dma_supported()
87 dev_info(dev, "Warning: IOMMU offset too big for device mask\n"); dma_iommu_dma_supported()
88 dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n", dma_iommu_dma_supported()
89 mask, tbl->it_offset << tbl->it_page_shift); dma_iommu_dma_supported()
98 u64 mask; dma_iommu_get_required_mask() local
102 mask = 1ULL < (fls_long(tbl->it_offset + tbl->it_size) - 1); dma_iommu_get_required_mask()
103 mask += mask - 1; dma_iommu_get_required_mask()
105 return mask; dma_iommu_get_required_mask()
/linux-4.4.14/arch/mips/include/asm/vr41xx/
H A Dvr41xx.h87 extern void vr41xx_enable_piuint(uint16_t mask);
88 extern void vr41xx_disable_piuint(uint16_t mask);
98 extern void vr41xx_enable_aiuint(uint16_t mask);
99 extern void vr41xx_disable_aiuint(uint16_t mask);
105 extern void vr41xx_enable_kiuint(uint16_t mask);
106 extern void vr41xx_disable_kiuint(uint16_t mask);
114 extern void vr41xx_enable_dsiuint(uint16_t mask);
115 extern void vr41xx_disable_dsiuint(uint16_t mask);
123 extern void vr41xx_enable_firint(uint16_t mask);
124 extern void vr41xx_disable_firint(uint16_t mask);
140 extern void vr41xx_enable_csiint(uint16_t mask);
141 extern void vr41xx_disable_csiint(uint16_t mask);
/linux-4.4.14/arch/ia64/include/asm/sn/
H A Dleds.h26 set_led_bits(u8 value, u8 mask) set_led_bits() argument
28 pda->led_state = (pda->led_state & ~mask) | (value & mask); set_led_bits()
/linux-4.4.14/sound/pci/ac97/
H A Dac97_patch.h25 #define AC97_SINGLE_VALUE(reg,shift,mask,invert) \
26 ((reg) | ((shift) << 8) | ((shift) << 12) | ((mask) << 16) | \
28 #define AC97_PAGE_SINGLE_VALUE(reg,shift,mask,invert,page) \
29 (AC97_SINGLE_VALUE(reg,shift,mask,invert) | (1<<25) | ((page) << 26))
30 #define AC97_SINGLE(xname, reg, shift, mask, invert) \
34 .private_value = AC97_SINGLE_VALUE(reg, shift, mask, invert) }
35 #define AC97_PAGE_SINGLE(xname, reg, shift, mask, invert, page) \
39 .private_value = AC97_PAGE_SINGLE_VALUE(reg, shift, mask, invert, page) }
40 #define AC97_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
44 .private_value = (reg) | ((shift_left) << 8) | ((shift_right) << 12) | ((mask) << 16) | ((invert) << 24) }
51 unsigned short mask; member in struct:ac97_enum
57 .mask = xmask, .texts = xtexts }
/linux-4.4.14/arch/m68k/amiga/
H A Dcia.c51 unsigned char cia_set_irq(struct ciabase *base, unsigned char mask) cia_set_irq() argument
56 if (mask & CIA_ICR_SETCLR) cia_set_irq()
57 base->icr_data |= mask; cia_set_irq()
59 base->icr_data &= ~mask; cia_set_irq()
66 * Enable or disable CIA interrupts, return old interrupt mask,
69 unsigned char cia_able_irq(struct ciabase *base, unsigned char mask) cia_able_irq() argument
75 base->cia->icr = mask; cia_able_irq()
76 if (mask & CIA_ICR_SETCLR) cia_able_irq()
77 base->icr_mask |= mask; cia_able_irq()
79 base->icr_mask &= ~mask; cia_able_irq()
105 unsigned char mask; cia_irq_enable() local
108 mask = 1 << (irq - IRQ_AMIGA_CIAB); cia_irq_enable()
109 cia_set_irq(&ciab_base, mask); cia_irq_enable()
110 cia_able_irq(&ciab_base, CIA_ICR_SETCLR | mask); cia_irq_enable()
112 mask = 1 << (irq - IRQ_AMIGA_CIAA); cia_irq_enable()
113 cia_set_irq(&ciaa_base, mask); cia_irq_enable()
114 cia_able_irq(&ciaa_base, CIA_ICR_SETCLR | mask); cia_irq_enable()
/linux-4.4.14/crypto/
H A Dapi.c60 u32 mask) __crypto_alg_lookup()
71 if ((q->cra_flags ^ type) & mask) __crypto_alg_lookup()
76 ((struct crypto_larval *)q)->mask != mask) __crypto_alg_lookup()
109 struct crypto_larval *crypto_larval_alloc(const char *name, u32 type, u32 mask) crypto_larval_alloc() argument
117 larval->mask = mask; crypto_larval_alloc()
130 u32 mask) crypto_larval_add()
135 larval = crypto_larval_alloc(name, type, mask); crypto_larval_add()
142 alg = __crypto_alg_lookup(name, type, mask); crypto_larval_add()
195 struct crypto_alg *crypto_alg_lookup(const char *name, u32 type, u32 mask) crypto_alg_lookup() argument
200 alg = __crypto_alg_lookup(name, type, mask); crypto_alg_lookup()
207 struct crypto_alg *crypto_larval_lookup(const char *name, u32 type, u32 mask) crypto_larval_lookup() argument
214 mask &= ~(CRYPTO_ALG_LARVAL | CRYPTO_ALG_DEAD); crypto_larval_lookup()
215 type &= mask; crypto_larval_lookup()
217 alg = crypto_alg_lookup(name, type, mask); crypto_larval_lookup()
221 if (!((type ^ CRYPTO_ALG_NEED_FALLBACK) & mask & crypto_larval_lookup()
225 alg = crypto_alg_lookup(name, type, mask); crypto_larval_lookup()
231 return crypto_larval_add(name, type, mask); crypto_larval_lookup()
249 struct crypto_alg *crypto_alg_mod_lookup(const char *name, u32 type, u32 mask) crypto_alg_mod_lookup() argument
255 if (!((type | mask) & CRYPTO_ALG_TESTED)) { crypto_alg_mod_lookup()
257 mask |= CRYPTO_ALG_TESTED; crypto_alg_mod_lookup()
265 * !(mask & CRYPTO_ALG_INTERNAL). crypto_alg_mod_lookup()
267 if (!((type | mask) & CRYPTO_ALG_INTERNAL)) crypto_alg_mod_lookup()
268 mask |= CRYPTO_ALG_INTERNAL; crypto_alg_mod_lookup()
270 larval = crypto_larval_lookup(name, type, mask); crypto_alg_mod_lookup()
287 static int crypto_init_ops(struct crypto_tfm *tfm, u32 type, u32 mask) crypto_init_ops() argument
292 return type_obj->init(tfm, type, mask); crypto_init_ops()
333 static unsigned int crypto_ctxsize(struct crypto_alg *alg, u32 type, u32 mask) crypto_ctxsize() argument
340 return len + type_obj->ctxsize(alg, type, mask); crypto_ctxsize()
367 u32 mask) __crypto_alloc_tfm()
373 tfm_size = sizeof(*tfm) + crypto_ctxsize(alg, type, mask); __crypto_alloc_tfm()
380 err = crypto_init_ops(tfm, type, mask); __crypto_alloc_tfm()
406 * @mask: Mask for type comparison
424 struct crypto_tfm *crypto_alloc_base(const char *alg_name, u32 type, u32 mask) crypto_alloc_base() argument
432 alg = crypto_alg_mod_lookup(alg_name, type, mask); crypto_alloc_base()
438 tfm = __crypto_alloc_tfm(alg, type, mask); crypto_alloc_base()
501 u32 type, u32 mask) crypto_find_alg()
503 struct crypto_alg *(*lookup)(const char *name, u32 type, u32 mask) = crypto_find_alg()
508 mask &= frontend->maskclear; crypto_find_alg()
510 mask |= frontend->maskset; crypto_find_alg()
516 return lookup(alg_name, type, mask); crypto_find_alg()
525 * @mask: Mask for type comparison
541 const struct crypto_type *frontend, u32 type, u32 mask) crypto_alloc_tfm()
549 alg = crypto_find_alg(alg_name, frontend, type, mask); crypto_alloc_tfm()
600 int crypto_has_alg(const char *name, u32 type, u32 mask) crypto_has_alg() argument
603 struct crypto_alg *alg = crypto_alg_mod_lookup(name, type, mask); crypto_has_alg()
59 __crypto_alg_lookup(const char *name, u32 type, u32 mask) __crypto_alg_lookup() argument
129 crypto_larval_add(const char *name, u32 type, u32 mask) crypto_larval_add() argument
366 __crypto_alloc_tfm(struct crypto_alg *alg, u32 type, u32 mask) __crypto_alloc_tfm() argument
499 crypto_find_alg(const char *alg_name, const struct crypto_type *frontend, u32 type, u32 mask) crypto_find_alg() argument
540 crypto_alloc_tfm(const char *alg_name, const struct crypto_type *frontend, u32 type, u32 mask) crypto_alloc_tfm() argument
/linux-4.4.14/arch/powerpc/platforms/85xx/
H A Dsocrates_fpga_pic.c115 uint32_t mask; socrates_fpga_pic_ack() local
119 mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) socrates_fpga_pic_ack()
121 mask |= (1 << (hwirq + 16)); socrates_fpga_pic_ack()
122 socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); socrates_fpga_pic_ack() local
131 u32 mask; socrates_fpga_pic_mask() local
135 mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) socrates_fpga_pic_mask()
137 mask &= ~(1 << hwirq); socrates_fpga_pic_mask()
138 socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); socrates_fpga_pic_mask() local
147 u32 mask; socrates_fpga_pic_mask_ack() local
151 mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) socrates_fpga_pic_mask_ack()
153 mask &= ~(1 << hwirq); socrates_fpga_pic_mask_ack()
154 mask |= (1 << (hwirq + 16)); socrates_fpga_pic_mask_ack()
155 socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); socrates_fpga_pic_mask_ack() local
164 u32 mask; socrates_fpga_pic_unmask() local
168 mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) socrates_fpga_pic_unmask()
170 mask |= (1 << hwirq); socrates_fpga_pic_unmask()
171 socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); socrates_fpga_pic_unmask() local
180 u32 mask; socrates_fpga_pic_eoi() local
184 mask = socrates_fpga_pic_read(FPGA_PIC_IRQMASK(irq_line)) socrates_fpga_pic_eoi()
186 mask |= (1 << (hwirq + 16)); socrates_fpga_pic_eoi()
187 socrates_fpga_pic_write(FPGA_PIC_IRQMASK(irq_line), mask); socrates_fpga_pic_eoi() local
197 u32 mask; socrates_fpga_pic_set_type() local
213 mask = socrates_fpga_pic_read(FPGA_PIC_IRQCFG); socrates_fpga_pic_set_type()
215 mask |= (1 << hwirq); socrates_fpga_pic_set_type()
217 mask &= ~(1 << hwirq); socrates_fpga_pic_set_type()
218 socrates_fpga_pic_write(FPGA_PIC_IRQCFG, mask); socrates_fpga_pic_set_type()
/linux-4.4.14/kernel/irq/
H A Dgeneric-chip.c32 * Chip has separate enable/disable registers instead of a single mask
39 u32 mask = d->mask; irq_gc_mask_disable_reg() local
42 irq_reg_writel(gc, mask, ct->regs.disable); irq_gc_mask_disable_reg()
43 *ct->mask_cache &= ~mask; irq_gc_mask_disable_reg()
48 * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
51 * Chip has a single mask register. Values of this register are cached
58 u32 mask = d->mask; irq_gc_mask_set_bit() local
61 *ct->mask_cache |= mask; irq_gc_mask_set_bit()
62 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); irq_gc_mask_set_bit()
68 * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
71 * Chip has a single mask register. Values of this register are cached
78 u32 mask = d->mask; irq_gc_mask_clr_bit() local
81 *ct->mask_cache &= ~mask; irq_gc_mask_clr_bit()
82 irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); irq_gc_mask_clr_bit()
91 * Chip has separate enable/disable registers instead of a single mask
98 u32 mask = d->mask; irq_gc_unmask_enable_reg() local
101 irq_reg_writel(gc, mask, ct->regs.enable); irq_gc_unmask_enable_reg()
102 *ct->mask_cache |= mask; irq_gc_unmask_enable_reg()
114 u32 mask = d->mask; irq_gc_ack_set_bit() local
117 irq_reg_writel(gc, mask, ct->regs.ack); irq_gc_ack_set_bit()
130 u32 mask = ~d->mask; irq_gc_ack_clr_bit() local
133 irq_reg_writel(gc, mask, ct->regs.ack); irq_gc_ack_clr_bit()
145 u32 mask = d->mask; irq_gc_mask_disable_reg_and_ack() local
148 irq_reg_writel(gc, mask, ct->regs.mask); irq_gc_mask_disable_reg_and_ack()
149 irq_reg_writel(gc, mask, ct->regs.ack); irq_gc_mask_disable_reg_and_ack()
161 u32 mask = d->mask; irq_gc_eoi() local
164 irq_reg_writel(gc, mask, ct->regs.eoi); irq_gc_eoi()
180 u32 mask = d->mask; irq_gc_set_wake() local
182 if (!(mask & gc->wake_enabled)) irq_gc_set_wake()
187 gc->wake_active |= mask; irq_gc_set_wake()
189 gc->wake_active &= ~mask; irq_gc_set_wake()
248 u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; irq_gc_init_mask_cache()
254 mskreg = ct[i].regs.mask; irq_gc_init_mask_cache()
406 data->mask = 1 << idx; irq_map_generic_chip()
459 d->mask = 1 << (i - gc->irq_base); irq_setup_generic_chip()
515 /* Remove handler first. That will mask the irq line */ irq_remove_generic_chip()
/linux-4.4.14/arch/nios2/include/asm/
H A Dasm-macros.h4 * depending on the mask value.
25 * ANDs reg2 with mask and places the result in reg1.
30 .macro ANDI32 reg1, reg2, mask
31 .if \mask & 0xffff
32 .if \mask & 0xffff0000
33 movhi \reg1, %hi(\mask)
34 movui \reg1, %lo(\mask)
37 andi \reg1, \reg2, %lo(\mask)
40 andhi \reg1, \reg2, %hi(\mask)
45 * ORs reg2 with mask and places the result in reg1.
50 .macro ORI32 reg1, reg2, mask
51 .if \mask & 0xffff
52 .if \mask & 0xffff0000
53 orhi \reg1, \reg2, %hi(\mask)
54 ori \reg1, \reg2, %lo(\mask)
56 ori \reg1, \reg2, %lo(\mask)
59 orhi \reg1, \reg2, %hi(\mask)
64 * XORs reg2 with mask and places the result in reg1.
69 .macro XORI32 reg1, reg2, mask
70 .if \mask & 0xffff
71 .if \mask & 0xffff0000
72 xorhi \reg1, \reg2, %hi(\mask)
73 xori \reg1, \reg1, %lo(\mask)
75 xori \reg1, \reg2, %lo(\mask)
78 xorhi \reg1, \reg2, %hi(\mask)
267 * Tests the bits in mask against reg2 stores the result in reg1.
268 * If the all the bits in the mask are zero it branches to label.
273 .macro TSTBZ reg1, reg2, mask, label
274 ANDI32 \reg1, \reg2, \mask
279 * Tests the bits in mask against reg2 stores the result in reg1.
280 * If the any of the bits in the mask are 1 it branches to label.
285 .macro TSTBNZ reg1, reg2, mask, label
286 ANDI32 \reg1, \reg2, \mask
/linux-4.4.14/drivers/video/fbdev/matrox/
H A Dmatroxfb_maven.h17 } mask; member in struct:i2c_bit_adapter
/linux-4.4.14/drivers/clk/ti/
H A Dmux.c45 val &= mux->mask; ti_clk_mux_get_parent()
84 val = mux->mask << (mux->shift + 16); ti_clk_mux_set_parent()
87 val &= ~(mux->mask << mux->shift); ti_clk_mux_set_parent()
104 u8 shift, u32 mask, u8 clk_mux_flags, _register_mux()
127 mux->mask = mask; _register_mux()
147 u32 mask; ti_clk_register_mux() local
154 mask = mux->num_parents; ti_clk_register_mux()
156 mask--; ti_clk_register_mux()
158 mask = (1 << fls(mask)) - 1; ti_clk_register_mux()
169 flags, (void __iomem *)reg, mux->bit_shift, mask, ti_clk_register_mux()
186 u32 mask = 0; of_mux_clk_setup() local
214 /* Generate bit-mask based on parent info */ of_mux_clk_setup()
215 mask = num_parents; of_mux_clk_setup()
217 mask--; of_mux_clk_setup()
219 mask = (1 << fls(mask)) - 1; of_mux_clk_setup()
222 flags, reg, shift, mask, clk_mux_flags, NULL); of_mux_clk_setup()
257 mux->mask = num_parents - 1; ti_clk_build_component_mux()
258 mux->mask = (1 << fls(mux->mask)) - 1; ti_clk_build_component_mux()
291 mux->mask = num_parents - 1; of_ti_composite_mux_clk_setup()
292 mux->mask = (1 << fls(mux->mask)) - 1; of_ti_composite_mux_clk_setup()
101 _register_mux(struct device *dev, const char *name, const char **parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 shift, u32 mask, u8 clk_mux_flags, u32 *table) _register_mux() argument
/linux-4.4.14/arch/x86/boot/
H A Dcpuflags.h16 int has_eflag(unsigned long mask);
/linux-4.4.14/drivers/clk/st/
H A Dclkgen.h16 unsigned int mask; member in struct:clkgen_field
23 return (readl(base + field->offset) >> field->shift) & field->mask; clkgen_read()
31 ~(field->mask << field->shift)) | (val << field->shift), clkgen_write()
39 .mask = _mask, \
/linux-4.4.14/include/net/
H A Ddsfield.h27 static inline void ipv4_change_dsfield(struct iphdr *iph,__u8 mask, ipv4_change_dsfield() argument
33 dsfield = (iph->tos & mask) | value; ipv4_change_dsfield()
43 static inline void ipv6_change_dsfield(struct ipv6hdr *ipv6h,__u8 mask, ipv6_change_dsfield() argument
48 *p = (*p & htons((((u16)mask << 4) | 0xf00f))) | htons((u16)value << 4); ipv6_change_dsfield()
/linux-4.4.14/include/net/tc_act/
H A Dtc_nat.h12 __be32 mask; member in struct:tcf_nat
/linux-4.4.14/include/uapi/linux/netfilter_bridge/
H A Debt_mark_m.h10 unsigned long mark, mask; member in struct:ebt_mark_m_info
/linux-4.4.14/include/uapi/linux/tc_act/
H A Dtc_nat.h23 __be32 mask; member in struct:tc_nat
/linux-4.4.14/include/uapi/linux/tc_ematch/
H A Dtc_em_cmp.h9 __u32 mask; member in struct:tcf_em_cmp
/linux-4.4.14/arch/arm/mach-omap1/
H A Dboard-nand.c26 unsigned long mask; omap1_nand_cmd_ctl() local
31 mask = (ctrl & NAND_CLE) ? 0x02 : 0; omap1_nand_cmd_ctl()
33 mask |= 0x04; omap1_nand_cmd_ctl()
35 writeb(cmd, this->IO_ADDR_W + mask); omap1_nand_cmd_ctl()
/linux-4.4.14/arch/arm/mach-integrator/
H A Dimpd1.h14 void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
/linux-4.4.14/drivers/media/rc/img-ir/
H A Dimg-ir-nec.c61 data_m = in->mask & 0xff; img_ir_nec_filter()
63 if ((in->data | in->mask) & 0xff000000) { img_ir_nec_filter()
67 addr_m = bitrev8(in->mask >> 24); img_ir_nec_filter()
69 addr_inv_m = bitrev8(in->mask >> 16); img_ir_nec_filter()
71 data_m = bitrev8(in->mask >> 8); img_ir_nec_filter()
73 data_inv_m = bitrev8(in->mask >> 0); img_ir_nec_filter()
74 } else if ((in->data | in->mask) & 0x00ff0000) { img_ir_nec_filter()
78 addr_m = (in->mask >> 16) & 0xff; img_ir_nec_filter()
80 addr_inv_m = (in->mask >> 8) & 0xff; img_ir_nec_filter()
87 addr_m = (in->mask >> 8) & 0xff; img_ir_nec_filter()
99 out->mask = data_inv_m << 24 | img_ir_nec_filter()
/linux-4.4.14/drivers/net/wireless/iwlwifi/
H A Diwl-io.h39 static inline void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask) iwl_set_bit() argument
41 iwl_trans_set_bits_mask(trans, reg, mask, mask); iwl_set_bit()
44 static inline void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask) iwl_clear_bit() argument
46 iwl_trans_set_bits_mask(trans, reg, mask, 0); iwl_clear_bit()
50 u32 bits, u32 mask, int timeout);
51 int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
63 u32 bits, u32 mask, int timeout);
64 void iwl_set_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
66 u32 bits, u32 mask);
67 void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
/linux-4.4.14/drivers/staging/sm750fb/
H A Dsm750_cursor.h14 u16 rop, const u8 *data, const u8 *mask);
16 u16 rop, const u8 *data, const u8 *mask);
/linux-4.4.14/drivers/media/pci/bt8xx/
H A Ddst_priv.h8 u32 mask; member in struct:dst_gpio_enable
13 u32 mask; member in struct:dst_gpio_output
/linux-4.4.14/fs/coda/
H A Dcoda_cache.h14 void coda_cache_enter(struct inode *inode, int mask);
17 int coda_cache_check(struct inode *inode, int mask);
/linux-4.4.14/include/linux/soc/mediatek/
H A Dinfracfg.h23 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask);
24 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask);
/linux-4.4.14/arch/ia64/sn/kernel/sn2/
H A Dptc_deadlock.S33 mask = r18 define
38 movl mask=WRITECOUNTMASK
52 and scr2=scr1,mask;; // mask of writecount bits
67 and scr2=scr1,mask;; // mask of writecount bits
78 and scr2=scr1,mask;; // mask of writecount bits
/linux-4.4.14/arch/arm/mach-gemini/
H A Dirq.c45 unsigned int mask; gemini_mask_irq() local
47 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); gemini_mask_irq()
48 mask &= ~(1 << d->irq); gemini_mask_irq()
49 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); gemini_mask_irq()
54 unsigned int mask; gemini_unmask_irq() local
56 mask = __raw_readl(IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); gemini_unmask_irq()
57 mask |= (1 << d->irq); gemini_unmask_irq()
58 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); gemini_unmask_irq()
/linux-4.4.14/drivers/pcmcia/
H A Dsa1100_assabet.c44 unsigned int mask; assabet_pcmcia_configure_socket() local
48 mask = 0; assabet_pcmcia_configure_socket()
56 mask = ASSABET_BCR_CF_PWR; assabet_pcmcia_configure_socket()
68 mask |= ASSABET_BCR_CF_RST; assabet_pcmcia_configure_socket()
70 mask |= ASSABET_BCR_CF_BUS_OFF; assabet_pcmcia_configure_socket()
73 ASSABET_BCR_CF_BUS_OFF, mask); assabet_pcmcia_configure_socket()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/subdev/
H A Dtimer.h62 #define nvkm_wait_nsec(d,n,addr,mask,data) \
64 if ((nvkm_rd32(d, (addr)) & (mask)) == (data)) \
67 #define nvkm_wait_usec(d,u,addr,mask,data) \
68 nvkm_wait_nsec((d), (u) * 1000, (addr), (mask), (data))
69 #define nvkm_wait_msec(d,m,addr,mask,data) \
70 nvkm_wait_usec((d), (m) * 1000, (addr), (mask), (data))
/linux-4.4.14/arch/unicore32/kernel/
H A Dirq.c46 unsigned int mask; puv3_gpio_type() local
49 mask = 1 << d->irq; puv3_gpio_type()
51 mask = GPIO_MASK(d->irq); puv3_gpio_type()
54 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask) puv3_gpio_type()
60 GPIO_IRQ_rising_edge |= mask; puv3_gpio_type()
62 GPIO_IRQ_rising_edge &= ~mask; puv3_gpio_type()
64 GPIO_IRQ_falling_edge |= mask; puv3_gpio_type()
66 GPIO_IRQ_falling_edge &= ~mask; puv3_gpio_type()
117 unsigned int mask, irq; puv3_gpio_handler() local
119 mask = readl(GPIO_GEDR); puv3_gpio_handler()
125 writel(mask, GPIO_GEDR); puv3_gpio_handler()
129 if (mask & 1) puv3_gpio_handler()
131 mask >>= 1; puv3_gpio_handler()
133 } while (mask); puv3_gpio_handler()
134 mask = readl(GPIO_GEDR); puv3_gpio_handler()
135 } while (mask); puv3_gpio_handler()
145 unsigned int mask = GPIO_MASK(d->irq); puv3_high_gpio_ack() local
147 writel(mask, GPIO_GEDR); puv3_high_gpio_ack()
152 unsigned int mask = GPIO_MASK(d->irq); puv3_high_gpio_mask() local
154 GPIO_IRQ_mask &= ~mask; puv3_high_gpio_mask()
156 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); puv3_high_gpio_mask()
157 writel(readl(GPIO_GFER) & ~mask, GPIO_GFER); puv3_high_gpio_mask()
162 unsigned int mask = GPIO_MASK(d->irq); puv3_high_gpio_unmask() local
164 GPIO_IRQ_mask |= mask; puv3_high_gpio_unmask()
/linux-4.4.14/arch/sh/boards/mach-sdk7786/
H A Dnmi.c53 unsigned int source, mask, tmp; sdk7786_nmi_init() local
58 mask = NMIMR_MAN_NMIM; sdk7786_nmi_init()
62 mask = NMIMR_AUX_NMIM; sdk7786_nmi_init()
66 mask = NMIMR_MAN_NMIM | NMIMR_AUX_NMIM; sdk7786_nmi_init()
71 source = mask = 0; sdk7786_nmi_init()
82 fpga_write_reg(NMIMR_MASK ^ mask, NMIMR); sdk7786_nmi_init()
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A Dwakeup-mask.h1 /* arch/arm/plat-samsung/include/plat/wakeup-mask.h
5 * Support for wakeup mask interrupts on newer SoCs
16 /* if no irq yet defined, but still want to mask */
20 * struct samsung_wakeup_mask - wakeup mask information
30 * samsung_sync_wakemask - sync wakeup mask information for pm
35 * Synchronise the wakeup mask information at suspend time from the list
/linux-4.4.14/arch/arm64/kernel/
H A Dsleep.S17 * @mask: register containing MPIDR mask
23 *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) {
25 * u64 mpidr_masked = mpidr & mask;
32 * Input registers: rs0, rs1, rs2, rs3, mpidr, mask
37 .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask
38 and \mpidr, \mpidr, \mask // mask out MPIDR bits
39 and \dst, \mpidr, #0xff // mask=aff0
41 and \mask, \mpidr, #0xff00 // mask = aff1
42 lsr \mask ,\mask, \rs1
43 orr \dst, \dst, \mask // dst|=(aff1>>rs1)
44 and \mask, \mpidr, #0xff0000 // mask = aff2
45 lsr \mask ,\mask, \rs2
46 orr \dst, \dst, \mask // dst|=(aff2>>rs2)
47 and \mask, \mpidr, #0xff00000000 // mask = aff3
48 lsr \mask ,\mask, \rs3
49 orr \dst, \dst, \mask // dst|=(aff3>>rs3)
/linux-4.4.14/net/netfilter/
H A Dnf_conntrack_broadcast.c33 __be32 mask = 0; nf_conntrack_broadcast_help() local
48 mask = ifa->ifa_mask; for_primary_ifa()
55 if (mask == 0)
65 exp->mask.src.u3.ip = mask;
66 exp->mask.src.u.udp.port = htons(0xFFFF);
/linux-4.4.14/sound/soc/
H A Dsoc-io.c66 unsigned int mask, unsigned int val, bool *change) snd_soc_component_update_bits_legacy()
80 new = (old & ~mask) | (val & mask); snd_soc_component_update_bits_legacy()
94 * @mask: Mask that specifies which bits to update
95 * @val: New value for the bits specified by mask
102 unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits()
108 ret = regmap_update_bits_check(component->regmap, reg, mask, snd_soc_component_update_bits()
112 mask, val, &change); snd_soc_component_update_bits()
125 * @mask: Mask that specifies which bits to update
126 * @val: New value for the bits specified by mask
138 unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits_async()
145 mask, val, &change); snd_soc_component_update_bits_async()
148 mask, val, &change); snd_soc_component_update_bits_async()
174 * @mask: Mask that specifies which bits to test
183 unsigned int reg, unsigned int mask, unsigned int value) snd_soc_component_test_bits()
191 new = (old & ~mask) | value; snd_soc_component_test_bits()
220 * @mask: register mask
228 unsigned int mask, unsigned int value) snd_soc_update_bits()
230 return snd_soc_component_update_bits(&codec->component, reg, mask, snd_soc_update_bits()
239 * @mask: register mask
248 unsigned int mask, unsigned int value) snd_soc_test_bits()
250 return snd_soc_component_test_bits(&codec->component, reg, mask, value); snd_soc_test_bits()
64 snd_soc_component_update_bits_legacy( struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int val, bool *change) snd_soc_component_update_bits_legacy() argument
101 snd_soc_component_update_bits(struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits() argument
137 snd_soc_component_update_bits_async(struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int val) snd_soc_component_update_bits_async() argument
182 snd_soc_component_test_bits(struct snd_soc_component *component, unsigned int reg, unsigned int mask, unsigned int value) snd_soc_component_test_bits() argument
227 snd_soc_update_bits(struct snd_soc_codec *codec, unsigned int reg, unsigned int mask, unsigned int value) snd_soc_update_bits() argument
247 snd_soc_test_bits(struct snd_soc_codec *codec, unsigned int reg, unsigned int mask, unsigned int value) snd_soc_test_bits() argument
/linux-4.4.14/drivers/pinctrl/sirf/
H A Dpinctrl-atlas6.c134 .mask = BIT(30) | BIT(31),
137 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
158 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
164 .mask = BIT(30) | BIT(31),
167 .mask = BIT(16) | BIT(17),
185 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) |
191 .mask = BIT(30) | BIT(31),
194 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
214 .mask = BIT(1) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) |
220 .mask = BIT(30) | BIT(31),
223 .mask = BIT(8),
241 .mask = BIT(12),
244 .mask = BIT(23),
247 .mask = BIT(4) | BIT(5),
264 .mask = BIT(4) | BIT(5),
278 .mask = BIT(15) | BIT(17),
292 .mask = BIT(10) | BIT(14),
295 .mask = BIT(16) | BIT(18),
312 .mask = BIT(16) | BIT(18),
326 .mask = BIT(30) | BIT(31),
329 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
346 .mask = BIT(30),
349 .mask = BIT(0) | BIT(2) | BIT(3),
366 .mask = BIT(10),
383 .mask = BIT(10),
400 .mask = BIT(19),
417 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
432 .mask = BIT(2) | BIT(3) | BIT(4),
447 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
464 .mask = BIT(2) | BIT(3) | BIT(4) | BIT(5),
478 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
495 .mask = BIT(2) | BIT(3),
512 .mask = BIT(24) | BIT(25) | BIT(26),
529 .mask = BIT(24) | BIT(25) | BIT(26),
546 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
563 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
580 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
597 .mask = BIT(20) | BIT(21),
610 .mask = BIT(15),
613 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
630 .mask = BIT(12) | BIT(13),
647 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
650 .mask = BIT(0) | BIT(1),
667 .mask = BIT(1),
684 .mask = BIT(27) | BIT(28) | BIT(29),
701 .mask = BIT(27) | BIT(28),
718 .mask = BIT(14),
732 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(8) | BIT(9)
752 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20)
756 .mask = BIT(23) | BIT(24) | BIT(25),
774 .mask = BIT(26) | BIT(27),
788 .mask = BIT(13) | BIT(15),
805 .mask = BIT(4),
822 .mask = BIT(5),
836 .mask = BIT(6),
850 .mask = BIT(7),
864 .mask = BIT(14),
878 .mask = BIT(8),
895 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8)
914 .mask = BIT(28),
949 .mask = BIT(9) | BIT(10) | BIT(11),
H A Dpinctrl-prima2.c138 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
144 .mask = BIT(31),
162 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
168 .mask = BIT(31),
171 .mask = BIT(16) | BIT(17),
189 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
195 .mask = BIT(31),
198 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
218 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
224 .mask = BIT(31),
227 .mask = BIT(23),
245 .mask = BIT(4) | BIT(5),
248 .mask = BIT(23) | BIT(28),
265 .mask = BIT(4) | BIT(5),
279 .mask = BIT(15) | BIT(17),
293 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
310 .mask = BIT(16) | BIT(18),
324 .mask = BIT(30) | BIT(31),
327 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
344 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
361 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
375 .mask = BIT(10),
392 .mask = BIT(10),
409 .mask = BIT(19),
426 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
441 .mask = BIT(11) | BIT(12) | BIT(14),
456 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
474 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
491 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
508 .mask = BIT(27) | BIT(28) | BIT(29),
522 .mask = BIT(24) | BIT(25) | BIT(26),
539 .mask = BIT(24) | BIT(25) | BIT(26),
556 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
573 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
590 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
607 .mask = BIT(20) | BIT(21),
621 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
638 .mask = BIT(25) | BIT(26),
652 .mask = BIT(29) | BIT(30) | BIT(31),
655 .mask = BIT(0) | BIT(1),
672 .mask = BIT(30) | BIT(31),
686 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
712 .mask = BIT(2) | BIT(3),
729 .mask = BIT(14),
743 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
763 .mask = BIT(26) | BIT(27),
777 .mask = BIT(13) | BIT(15),
791 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
796 .mask = BIT(12),
814 .mask = BIT(4),
831 .mask = BIT(5),
845 .mask = BIT(6),
859 .mask = BIT(7),
873 .mask = BIT(8),
887 .mask = BIT(22),
903 .mask = BIT(27),
938 .mask = BIT(9) | BIT(10) | BIT(11),
/linux-4.4.14/net/openvswitch/
H A Dflow_table.c60 bool full, const struct sw_flow_mask *mask) ovs_flow_mask_key()
62 int start = full ? 0 : mask->range.start; ovs_flow_mask_key()
63 int len = full ? sizeof *dst : range_n_bytes(&mask->range); ovs_flow_mask_key()
64 const long *m = (const long *)((const u8 *)&mask->key + start); ovs_flow_mask_key()
70 * if 'full' is false the memory outside of the 'mask->range' is left ovs_flow_mask_key()
72 * operations on 'dst' only use contents within 'mask->range'. ovs_flow_mask_key()
89 flow->mask = NULL; ovs_flow_alloc()
473 const struct sw_flow_mask *mask) masked_flow_lookup()
480 ovs_flow_mask_key(&masked_key, unmasked, false, mask); masked_flow_lookup()
481 hash = flow_hash(&masked_key, &mask->range); masked_flow_lookup()
484 if (flow->mask == mask && flow->flow_table.hash == hash && hlist_for_each_entry_rcu()
485 flow_cmp_masked_key(flow, &masked_key, &mask->range)) hlist_for_each_entry_rcu()
496 struct sw_flow_mask *mask; ovs_flow_tbl_lookup_stats() local
500 list_for_each_entry_rcu(mask, &tbl->mask_list, list) { ovs_flow_tbl_lookup_stats()
502 flow = masked_flow_lookup(ti, key, mask); ovs_flow_tbl_lookup_stats()
521 struct sw_flow_mask *mask; ovs_flow_tbl_lookup_exact() local
525 list_for_each_entry(mask, &tbl->mask_list, list) { ovs_flow_tbl_lookup_exact()
526 flow = masked_flow_lookup(ti, match->key, mask); ovs_flow_tbl_lookup_exact()
576 struct sw_flow_mask *mask; ovs_flow_tbl_num_masks() local
579 list_for_each_entry(mask, &table->mask_list, list) ovs_flow_tbl_num_masks()
591 /* Remove 'mask' from the mask list, if it is not needed any more. */ flow_mask_remove()
592 static void flow_mask_remove(struct flow_table *tbl, struct sw_flow_mask *mask) flow_mask_remove() argument
594 if (mask) { flow_mask_remove()
595 /* ovs-lock is required to protect mask-refcount and flow_mask_remove()
596 * mask list. flow_mask_remove()
599 BUG_ON(!mask->ref_count); flow_mask_remove()
600 mask->ref_count--; flow_mask_remove()
602 if (!mask->ref_count) { flow_mask_remove()
603 list_del_rcu(&mask->list); flow_mask_remove()
604 kfree_rcu(mask, rcu); flow_mask_remove()
623 /* RCU delete the mask. 'flow->mask' is not NULLed, as it should be ovs_flow_tbl_remove()
626 flow_mask_remove(table, flow->mask); ovs_flow_tbl_remove()
631 struct sw_flow_mask *mask; mask_alloc() local
633 mask = kmalloc(sizeof(*mask), GFP_KERNEL); mask_alloc()
634 if (mask) mask_alloc()
635 mask->ref_count = 1; mask_alloc()
637 return mask; mask_alloc()
652 const struct sw_flow_mask *mask) flow_mask_find()
659 if (mask_equal(mask, m)) flow_mask_find()
666 /* Add 'mask' into the mask list, if it is not already there. */ flow_mask_insert()
670 struct sw_flow_mask *mask; flow_mask_insert() local
671 mask = flow_mask_find(tbl, new); flow_mask_insert()
672 if (!mask) { flow_mask_insert()
673 /* Allocate a new mask if none exsits. */ flow_mask_insert()
674 mask = mask_alloc(); flow_mask_insert()
675 if (!mask) flow_mask_insert()
677 mask->key = new->key; flow_mask_insert()
678 mask->range = new->range; flow_mask_insert()
679 list_add_rcu(&mask->list, &tbl->mask_list); flow_mask_insert()
681 BUG_ON(!mask->ref_count); flow_mask_insert()
682 mask->ref_count++; flow_mask_insert()
685 flow->mask = mask; flow_mask_insert()
695 flow->flow_table.hash = flow_hash(&flow->key, &flow->mask->range); flow_key_insert()
737 const struct sw_flow_mask *mask) ovs_flow_tbl_insert()
741 err = flow_mask_insert(table, flow, mask); ovs_flow_tbl_insert()
59 ovs_flow_mask_key(struct sw_flow_key *dst, const struct sw_flow_key *src, bool full, const struct sw_flow_mask *mask) ovs_flow_mask_key() argument
471 masked_flow_lookup(struct table_instance *ti, const struct sw_flow_key *unmasked, const struct sw_flow_mask *mask) masked_flow_lookup() argument
651 flow_mask_find(const struct flow_table *tbl, const struct sw_flow_mask *mask) flow_mask_find() argument
736 ovs_flow_tbl_insert(struct flow_table *table, struct sw_flow *flow, const struct sw_flow_mask *mask) ovs_flow_tbl_insert() argument
/linux-4.4.14/drivers/usb/chipidea/
H A Dci.h291 * @mask: bitfield mask
295 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask) hw_read_id_reg() argument
297 return ioread32(ci->hw_bank.abs + offset) & mask; hw_read_id_reg()
304 * @mask: bitfield mask
308 u32 mask, u32 data) hw_write_id_reg()
310 if (~mask) hw_write_id_reg()
311 data = (ioread32(ci->hw_bank.abs + offset) & ~mask) hw_write_id_reg()
312 | (data & mask); hw_write_id_reg()
321 * @mask: bitfield mask
325 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) hw_read() argument
327 return ioread32(ci->hw_bank.regmap[reg]) & mask; hw_read()
354 * @mask: bitfield mask
358 u32 mask, u32 data) hw_write()
360 if (~mask) hw_write()
361 data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask) hw_write()
362 | (data & mask); hw_write()
371 * @mask: bitfield mask
376 u32 mask) hw_test_and_clear()
378 u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask; hw_test_and_clear()
388 * @mask: bitfield mask
394 u32 mask, u32 data) hw_test_and_write()
398 hw_write(ci, reg, mask, data); hw_test_and_write()
399 return (val & mask) >> __ffs(mask); hw_test_and_write()
431 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,
307 hw_write_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask, u32 data) hw_write_id_reg() argument
357 hw_write(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, u32 data) hw_write() argument
375 hw_test_and_clear(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask) hw_test_and_clear() argument
393 hw_test_and_write(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask, u32 data) hw_test_and_write() argument
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-at91.c153 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
154 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
155 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
156 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
157 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
159 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
161 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
163 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
165 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
363 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) at91_mux_disable_interrupt() argument
365 writel_relaxed(mask, pio + PIO_IDR); at91_mux_disable_interrupt()
373 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) at91_mux_set_pullup() argument
376 writel_relaxed(mask, pio + PIO_PPDDR); at91_mux_set_pullup()
378 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); at91_mux_set_pullup()
386 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) at91_mux_set_multidrive() argument
388 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); at91_mux_set_multidrive()
391 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) at91_mux_set_A_periph() argument
393 writel_relaxed(mask, pio + PIO_ASR); at91_mux_set_A_periph()
396 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) at91_mux_set_B_periph() argument
398 writel_relaxed(mask, pio + PIO_BSR); at91_mux_set_B_periph()
401 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) at91_mux_pio3_set_A_periph() argument
404 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, at91_mux_pio3_set_A_periph()
406 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, at91_mux_pio3_set_A_periph()
410 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) at91_mux_pio3_set_B_periph() argument
412 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, at91_mux_pio3_set_B_periph()
414 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, at91_mux_pio3_set_B_periph()
418 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) at91_mux_pio3_set_C_periph() argument
420 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); at91_mux_pio3_set_C_periph()
421 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); at91_mux_pio3_set_C_periph()
424 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) at91_mux_pio3_set_D_periph() argument
426 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); at91_mux_pio3_set_D_periph()
427 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); at91_mux_pio3_set_D_periph()
430 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) at91_mux_pio3_get_periph() argument
434 if (readl_relaxed(pio + PIO_PSR) & mask) at91_mux_pio3_get_periph()
437 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); at91_mux_pio3_get_periph()
438 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); at91_mux_pio3_get_periph()
443 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) at91_mux_get_periph() argument
447 if (readl_relaxed(pio + PIO_PSR) & mask) at91_mux_get_periph()
450 select = readl_relaxed(pio + PIO_ABSR) & mask; at91_mux_get_periph()
460 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) at91_mux_set_deglitch() argument
462 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); at91_mux_set_deglitch()
473 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) at91_mux_pio3_set_deglitch() argument
476 writel_relaxed(mask, pio + PIO_IFSCDR); at91_mux_pio3_set_deglitch()
477 at91_mux_set_deglitch(pio, mask, is_on); at91_mux_pio3_set_deglitch()
488 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, at91_mux_pio3_set_debounce() argument
492 writel_relaxed(mask, pio + PIO_IFSCER); at91_mux_pio3_set_debounce()
494 writel_relaxed(mask, pio + PIO_IFER); at91_mux_pio3_set_debounce()
496 writel_relaxed(mask, pio + PIO_IFSCDR); at91_mux_pio3_set_debounce()
504 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) at91_mux_pio3_set_pulldown() argument
507 writel_relaxed(mask, pio + PIO_PUDR); at91_mux_pio3_set_pulldown()
509 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); at91_mux_pio3_set_pulldown()
512 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) at91_mux_pio3_disable_schmitt_trig() argument
514 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); at91_mux_pio3_disable_schmitt_trig()
697 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) at91_mux_gpio_disable() argument
699 writel_relaxed(mask, pio + PIO_PDR); at91_mux_gpio_disable()
702 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) at91_mux_gpio_enable() argument
704 writel_relaxed(mask, pio + PIO_PER); at91_mux_gpio_enable()
705 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); at91_mux_gpio_enable()
716 unsigned mask; at91_pmx_set() local
739 mask = pin_to_mask(pin->pin); at91_pmx_set()
740 at91_mux_disable_interrupt(pio, mask); at91_pmx_set()
743 at91_mux_gpio_enable(pio, mask, 1); at91_pmx_set()
746 info->ops->mux_A_periph(pio, mask); at91_pmx_set()
749 info->ops->mux_B_periph(pio, mask); at91_pmx_set()
754 info->ops->mux_C_periph(pio, mask); at91_pmx_set()
759 info->ops->mux_D_periph(pio, mask); at91_pmx_set()
763 at91_mux_gpio_disable(pio, mask); at91_pmx_set()
803 unsigned mask; at91_gpio_request_enable() local
818 mask = 1 << (offset - chip->base); at91_gpio_request_enable()
821 offset, 'A' + range->id, offset - chip->base, mask); at91_gpio_request_enable()
823 writel_relaxed(mask, at91_chip->regbase + PIO_PER); at91_gpio_request_enable()
890 unsigned mask; at91_pinconf_set() local
908 mask = pin_to_mask(pin); at91_pinconf_set()
913 at91_mux_set_pullup(pio, mask, config & PULL_UP); at91_pinconf_set()
914 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); at91_pinconf_set()
916 info->ops->set_deglitch(pio, mask, config & DEGLITCH); at91_pinconf_set()
918 info->ops->set_debounce(pio, mask, config & DEBOUNCE, at91_pinconf_set()
921 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); at91_pinconf_set()
923 info->ops->disable_schmitt_trig(pio, mask); at91_pinconf_set()
943 #define DBG_SHOW_FLAG_MASKED(mask,flag) do { \
944 if ((config & mask) == flag) { \
1021 list = of_get_property(np, "atmel,mux-mask", &size); at91_pinctrl_mux_mask()
1023 dev_err(info->dev, "can not read the mux-mask of %d\n", size); at91_pinctrl_mux_mask()
1029 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); at91_pinctrl_mux_mask()
1040 ret = of_property_read_u32_array(np, "atmel,mux-mask", at91_pinctrl_mux_mask()
1043 dev_err(info->dev, "can not read the mux-mask of %d\n", size); at91_pinctrl_mux_mask()
1169 dev_dbg(&pdev->dev, "mux-mask\n"); at91_pinctrl_probe_dt()
1287 unsigned mask = 1 << offset; at91_gpio_get_direction() local
1291 return !(osr & mask); at91_gpio_get_direction()
1298 unsigned mask = 1 << offset; at91_gpio_direction_input() local
1300 writel_relaxed(mask, pio + PIO_ODR); at91_gpio_direction_input()
1308 unsigned mask = 1 << offset; at91_gpio_get() local
1312 return (pdsr & mask) != 0; at91_gpio_get()
1320 unsigned mask = 1 << offset; at91_gpio_set() local
1322 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); at91_gpio_set()
1326 unsigned long *mask, unsigned long *bits) at91_gpio_set_multiple()
1333 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); at91_gpio_set_multiple()
1334 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); at91_gpio_set_multiple()
1345 unsigned mask = 1 << offset; at91_gpio_direction_output() local
1347 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); at91_gpio_direction_output()
1348 writel_relaxed(mask, pio + PIO_OER); at91_gpio_direction_output()
1362 unsigned mask = pin_to_mask(i); at91_gpio_dbg_show() local
1368 mode = at91_gpio->ops->get_periph(pio, mask); at91_gpio_dbg_show()
1374 readl_relaxed(pio + PIO_OSR) & mask ? at91_gpio_dbg_show()
1377 readl_relaxed(pio + PIO_PDSR) & mask ? at91_gpio_dbg_show()
1407 unsigned mask = 1 << d->hwirq; gpio_irq_mask() local
1410 writel_relaxed(mask, pio + PIO_IDR); gpio_irq_mask()
1417 unsigned mask = 1 << d->hwirq; gpio_irq_unmask() local
1420 writel_relaxed(mask, pio + PIO_IER); gpio_irq_unmask()
1439 unsigned mask = 1 << d->hwirq; alt_gpio_irq_type() local
1444 writel_relaxed(mask, pio + PIO_ESR); alt_gpio_irq_type()
1445 writel_relaxed(mask, pio + PIO_REHLSR); alt_gpio_irq_type()
1449 writel_relaxed(mask, pio + PIO_ESR); alt_gpio_irq_type()
1450 writel_relaxed(mask, pio + PIO_FELLSR); alt_gpio_irq_type()
1454 writel_relaxed(mask, pio + PIO_LSR); alt_gpio_irq_type()
1455 writel_relaxed(mask, pio + PIO_FELLSR); alt_gpio_irq_type()
1459 writel_relaxed(mask, pio + PIO_LSR); alt_gpio_irq_type()
1460 writel_relaxed(mask, pio + PIO_REHLSR); alt_gpio_irq_type()
1468 writel_relaxed(mask, pio + PIO_AIMDR); alt_gpio_irq_type()
1477 writel_relaxed(mask, pio + PIO_AIMER); alt_gpio_irq_type()
1496 unsigned mask = 1 << d->hwirq; gpio_irq_set_wake() local
1502 wakeups[bank] |= mask; gpio_irq_set_wake()
1504 wakeups[bank] &= ~mask; gpio_irq_set_wake()
1325 at91_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, unsigned long *bits) at91_gpio_set_multiple() argument
/linux-4.4.14/arch/xtensa/include/asm/
H A Dbitops.h106 unsigned long mask = 1UL << (bit & 31); set_bit() local
117 : "a" (mask), "a" (p) set_bit()
124 unsigned long mask = 1UL << (bit & 31); clear_bit() local
135 : "a" (~mask), "a" (p) clear_bit()
142 unsigned long mask = 1UL << (bit & 31); change_bit() local
153 : "a" (mask), "a" (p) change_bit()
161 unsigned long mask = 1UL << (bit & 31); test_and_set_bit() local
172 : "a" (mask), "a" (p) test_and_set_bit()
175 return tmp & mask; test_and_set_bit()
182 unsigned long mask = 1UL << (bit & 31); test_and_clear_bit() local
193 : "a" (~mask), "a" (p) test_and_clear_bit()
196 return tmp & mask; test_and_clear_bit()
203 unsigned long mask = 1UL << (bit & 31); test_and_change_bit() local
214 : "a" (mask), "a" (p) test_and_change_bit()
217 return tmp & mask; test_and_change_bit()
/linux-4.4.14/drivers/bcma/
H A Ddriver_chipcommon.c19 u32 mask, u32 value) bcma_cc_write32_masked()
21 value &= mask; bcma_cc_write32_masked()
22 value |= bcma_cc_read32(cc, offset) & ~mask; bcma_cc_write32_masked()
205 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_irq_mask() argument
207 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); bcma_chipco_irq_mask()
210 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) bcma_chipco_irq_status() argument
212 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; bcma_chipco_irq_status()
215 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) bcma_chipco_gpio_in() argument
217 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; bcma_chipco_gpio_in()
220 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_gpio_out() argument
226 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); bcma_chipco_gpio_out()
233 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_gpio_outen() argument
239 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); bcma_chipco_gpio_outen()
250 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_gpio_control() argument
256 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); bcma_chipco_gpio_control()
263 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_gpio_intmask() argument
269 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); bcma_chipco_gpio_intmask()
275 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_gpio_polarity() argument
281 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); bcma_chipco_gpio_polarity()
287 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_gpio_pullup() argument
296 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); bcma_chipco_gpio_pullup()
302 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) bcma_chipco_gpio_pulldown() argument
311 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); bcma_chipco_gpio_pulldown()
18 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, u32 mask, u32 value) bcma_cc_write32_masked() argument
/linux-4.4.14/drivers/block/drbd/
H A Ddrbd_state.h12 * The NS macros expand to a mask and a value, that can be bit ored onto the
37 ({ union drbd_state mask; mask.i = 0; mask.T = T##_MASK; mask; }), \
40 ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \
41 mask.T2 = T2##_MASK; mask; }), \
45 ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \
46 mask.T2 = T2##_MASK; mask.T3 = T3##_MASK; mask; }), \
112 union drbd_state mask,
132 _conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val,
136 conn_request_state(struct drbd_connection *connection, union drbd_state mask, union drbd_state val,
145 * @mask: mask of state bits to change.
153 union drbd_state mask, drbd_request_state()
156 return _drbd_request_state(device, mask, val, CS_VERBOSE + CS_ORDERED); drbd_request_state()
152 drbd_request_state(struct drbd_device *device, union drbd_state mask, union drbd_state val) drbd_request_state() argument
/linux-4.4.14/arch/mips/paravirt/
H A Dparavirt-irq.c68 unsigned int mask = 0x100 << cd->bit; irq_core_set_enable_local() local
74 set_c0_status(mask); irq_core_set_enable_local()
76 clear_c0_status(mask); irq_core_set_enable_local()
175 u32 mask = 1u << data->irq; irq_pci_enable() local
177 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s); irq_pci_enable()
182 u32 mask = 1u << data->irq; irq_pci_disable() local
184 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c); irq_pci_disable()
193 u32 mask = 1u << data->irq; irq_pci_mask() local
195 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c); irq_pci_mask()
200 u32 mask = 1u << data->irq; irq_pci_unmask() local
202 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s); irq_pci_unmask()
218 u32 mask; irq_mbox_all() local
224 mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox); for_each_online_cpu()
225 __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); for_each_online_cpu()
241 u32 mask; irq_mbox_ack() local
246 mask = 1 << (get_ebase_cpunum() * MBOX_BITS_PER_CPU + mbox); irq_mbox_ack()
247 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1c + sizeof(u32)); irq_mbox_ack()
253 u32 mask; irq_mbox_ipi() local
257 mask = actions << (cpuid * MBOX_BITS_PER_CPU); irq_mbox_ipi()
258 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1s + sizeof(u32)); irq_mbox_ipi()
265 u32 mask; irq_mbox_cpu_onoffline() local
269 mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox); irq_mbox_cpu_onoffline()
270 __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); irq_mbox_cpu_onoffline()
/linux-4.4.14/drivers/net/ethernet/intel/i40e/
H A Di40e_diag.c34 * @mask: bits to be touched
37 u32 reg, u32 mask) i40e_diag_reg_pattern_test()
46 wr32(hw, reg, (pat & mask)); i40e_diag_reg_pattern_test()
48 if ((val & mask) != (pat & mask)) { i40e_diag_reg_pattern_test()
69 /* offset mask elements stride */
101 u32 reg, mask; i40e_diag_reg_test() local
121 mask = i40e_reg_list[i].mask; i40e_diag_reg_test()
125 ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); i40e_diag_reg_test()
36 i40e_diag_reg_pattern_test(struct i40e_hw *hw, u32 reg, u32 mask) i40e_diag_reg_pattern_test() argument
/linux-4.4.14/arch/powerpc/platforms/82xx/
H A Dpq2ads-pci-pic.c35 u32 mask; member in struct:pq2ads_pci_pic::__anon2386
50 setbits32(&priv->regs->mask, 1 << irq); pq2ads_pci_mask_irq()
66 clrbits32(&priv->regs->mask, 1 << irq); pq2ads_pci_unmask_irq()
84 u32 stat, mask, pend; pq2ads_pci_irq_demux() local
89 mask = in_be32(&priv->regs->mask); pq2ads_pci_irq_demux()
91 pend = stat & ~mask; pq2ads_pci_irq_demux()
147 /* PCI interrupt controller registers: status and mask */ pq2ads_pci_init_irq()
154 /* mask all PCI interrupts */ pq2ads_pci_init_irq()
155 out_be32(&priv->regs->mask, ~0); pq2ads_pci_init_irq()
/linux-4.4.14/arch/sparc/kernel/
H A Dleon_kernel.c43 #define LEON_IMASK(cpu) (&leon3_irqctrl_regs->mask[cpu])
71 unsigned long mask, oldmask; leon_eirq_setup() local
83 * controller have a mask-bit of their own, so this is safe. leon_eirq_setup()
86 mask = 1 << eirq; leon_eirq_setup()
88 LEON3_BYPASS_STORE_PA(LEON_IMASK(boot_cpu_id), (oldmask | mask)); leon_eirq_setup()
94 unsigned long mask; leon_get_irqmask() local
100 mask = 0; leon_get_irqmask()
102 mask = LEON_HARD_INT(irq); leon_get_irqmask()
104 return mask; leon_get_irqmask()
110 cpumask_t mask; irq_choose_cpu() local
112 cpumask_and(&mask, cpu_online_mask, affinity); irq_choose_cpu()
113 if (cpumask_equal(&mask, cpu_online_mask) || cpumask_empty(&mask)) irq_choose_cpu()
116 return cpumask_first(&mask); irq_choose_cpu()
125 unsigned long mask, oldmask, flags; leon_set_affinity() local
128 mask = (unsigned long)data->chip_data; leon_set_affinity()
138 LEON3_BYPASS_STORE_PA(LEON_IMASK(oldcpu), (oldmask & ~mask)); leon_set_affinity()
140 LEON3_BYPASS_STORE_PA(LEON_IMASK(newcpu), (oldmask | mask)); leon_set_affinity()
148 unsigned long mask, oldmask, flags; leon_unmask_irq() local
151 mask = (unsigned long)data->chip_data; leon_unmask_irq()
155 LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask | mask)); leon_unmask_irq()
161 unsigned long mask, oldmask, flags; leon_mask_irq() local
164 mask = (unsigned long)data->chip_data; leon_mask_irq()
168 LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask & ~mask)); leon_mask_irq()
188 unsigned long mask = (unsigned long)data->chip_data; leon_eoi_irq() local
190 if (mask & LEON_DO_ACK_HW) leon_eoi_irq()
191 LEON3_BYPASS_STORE_PA(LEON_IACK, mask & ~LEON_DO_ACK_HW); leon_eoi_irq()
215 unsigned long mask; leon_build_device_irq() local
219 mask = leon_get_irqmask(real_irq); leon_build_device_irq()
220 if (mask == 0) leon_build_device_irq()
228 mask |= LEON_DO_ACK_HW; leon_build_device_irq()
234 irq_set_chip_data(irq, (void *)mask); leon_build_device_irq()
251 unsigned long mask = (unsigned long)irq_get_chip_data(virq); leon_update_virq_handling() local
253 mask &= ~LEON_DO_ACK_HW; leon_update_virq_handling()
255 mask |= LEON_DO_ACK_HW; leon_update_virq_handling()
259 irq_set_chip_data(virq, (void *)mask); leon_update_virq_handling()
417 LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[boot_cpu_id], 0); leon_init_timers()
507 unsigned long mask, flags, *addr; leon_enable_irq_cpu() local
508 mask = leon_get_irqmask(irq_nr); leon_enable_irq_cpu()
511 LEON3_BYPASS_STORE_PA(addr, (LEON3_BYPASS_LOAD_PA(addr) | mask)); leon_enable_irq_cpu()
/linux-4.4.14/fs/notify/
H A Dfsnotify.c89 int __fsnotify_parent(struct path *path, struct dentry *dentry, __u32 mask) __fsnotify_parent() argument
106 else if (p_inode->i_fsnotify_mask & mask) { __fsnotify_parent()
107 /* we are notifying a parent so come up with the new mask which __fsnotify_parent()
109 mask |= FS_EVENT_ON_CHILD; __fsnotify_parent()
112 ret = fsnotify(p_inode, mask, path, FSNOTIFY_EVENT_PATH, __fsnotify_parent()
115 ret = fsnotify(p_inode, mask, dentry->d_inode, FSNOTIFY_EVENT_INODE, __fsnotify_parent()
128 __u32 mask, void *data, send_to_group()
142 if (mask & FS_MODIFY) { send_to_group()
154 inode_test_mask = (mask & ~FS_EVENT_ON_CHILD); send_to_group()
155 inode_test_mask &= inode_mark->mask; send_to_group()
161 vfsmount_test_mask = (mask & ~FS_EVENT_ON_CHILD); send_to_group()
163 vfsmount_test_mask &= vfsmount_mark->mask; send_to_group()
169 pr_debug("%s: group=%p to_tell=%p mask=%x inode_mark=%p" send_to_group()
172 __func__, group, to_tell, mask, inode_mark, send_to_group()
180 vfsmount_mark, mask, data, data_is, send_to_group()
190 int fsnotify(struct inode *to_tell, __u32 mask, void *data, int data_is, fsnotify() argument
199 __u32 test_mask = (mask & ~FS_EVENT_ON_CHILD); fsnotify()
221 if (!(mask & FS_MODIFY) && fsnotify()
228 if ((mask & FS_MODIFY) || fsnotify()
233 if (mnt && ((mask & FS_MODIFY) || fsnotify()
275 ret = send_to_group(to_tell, inode_mark, vfsmount_mark, mask, fsnotify()
278 if (ret && (mask & ALL_FSNOTIFY_PERM_EVENTS)) fsnotify()
125 send_to_group(struct inode *to_tell, struct fsnotify_mark *inode_mark, struct fsnotify_mark *vfsmount_mark, __u32 mask, void *data, int data_is, u32 cookie, const unsigned char *file_name) send_to_group() argument
/linux-4.4.14/drivers/gpu/drm/sti/
H A Dsti_mixer.c45 /* mask in CTL reg */
111 u32 mask, val; sti_mixer_set_plane_depth() local
143 mask = GAM_DEPTH_MASK_ID << (3 * i); sti_mixer_set_plane_depth()
144 if ((val & mask) == plane_id << (3 * i)) sti_mixer_set_plane_depth()
148 mask |= GAM_DEPTH_MASK_ID << (3 * (depth - 1)); sti_mixer_set_plane_depth()
153 dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n", sti_mixer_set_plane_depth()
154 plane_id, mask); sti_mixer_set_plane_depth()
156 val &= ~mask; sti_mixer_set_plane_depth()
212 u32 mask, val; sti_mixer_set_plane_status() local
217 mask = sti_mixer_get_plane_mask(plane); sti_mixer_set_plane_status()
218 if (!mask) { sti_mixer_set_plane_status()
219 DRM_ERROR("Can't find layer mask\n"); sti_mixer_set_plane_status()
224 val &= ~mask; sti_mixer_set_plane_status()
225 val |= status ? mask : 0; sti_mixer_set_plane_status()
/linux-4.4.14/arch/mips/rb532/
H A Dirq.c50 u32 mask; /* mask of valid bits in pending/mask registers */ member in struct:intr_group
62 .mask = 0x0000efff,
65 .mask = 0x00001fff,
68 .mask = 0x00000007,
71 .mask = 0x0003ffff,
74 .mask = 0xffffffff,
136 unsigned int group, intr_bit, mask, irq_nr = d->irq; rb532_disable_irq() local
148 mask = READ_MASK(addr); rb532_disable_irq()
149 mask |= intr_bit; rb532_disable_irq()
150 WRITE_MASK(addr, mask); rb532_disable_irq()
160 if (mask == intr_group[group].mask) rb532_disable_irq()
/linux-4.4.14/arch/arm/mach-footbridge/
H A Disa-irq.c35 unsigned int mask = 1 << (d->irq & 7); isa_mask_pic_lo_irq() local
37 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); isa_mask_pic_lo_irq()
42 unsigned int mask = 1 << (d->irq & 7); isa_ack_pic_lo_irq() local
44 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO); isa_ack_pic_lo_irq()
50 unsigned int mask = 1 << (d->irq & 7); isa_unmask_pic_lo_irq() local
52 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO); isa_unmask_pic_lo_irq()
63 unsigned int mask = 1 << (d->irq & 7); isa_mask_pic_hi_irq() local
65 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); isa_mask_pic_hi_irq()
70 unsigned int mask = 1 << (d->irq & 7); isa_ack_pic_hi_irq() local
72 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI); isa_ack_pic_hi_irq()
79 unsigned int mask = 1 << (d->irq & 7); isa_unmask_pic_hi_irq() local
81 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI); isa_unmask_pic_hi_irq()
144 outb(0xff, PIC_MASK_LO);/* mask all IRQs */ isa_init_irq()
145 outb(0xff, PIC_MASK_HI);/* mask all IRQs */ isa_init_irq()
/linux-4.4.14/drivers/iio/accel/
H A Dst_accel_core.c239 .mask = ST_ACCEL_1_ODR_MASK,
253 .mask = ST_ACCEL_1_ODR_MASK,
258 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
262 .mask = ST_ACCEL_1_FS_MASK,
288 .mask = ST_ACCEL_1_BDU_MASK,
310 .mask = ST_ACCEL_2_ODR_MASK,
320 .mask = ST_ACCEL_2_PW_MASK,
326 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
330 .mask = ST_ACCEL_2_FS_MASK,
351 .mask = ST_ACCEL_2_BDU_MASK,
370 .mask = ST_ACCEL_3_ODR_MASK,
386 .mask = ST_ACCEL_3_ODR_MASK,
391 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
395 .mask = ST_ACCEL_3_FS_MASK,
426 .mask = ST_ACCEL_3_BDU_MASK,
449 .mask = ST_ACCEL_4_ODR_MASK,
459 .mask = ST_ACCEL_4_PW_MASK,
465 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
469 .mask = ST_ACCEL_4_FS_MASK,
485 .mask = ST_ACCEL_4_BDU_MASK,
503 .mask = ST_ACCEL_5_ODR_MASK,
511 .mask = ST_ACCEL_5_PW_MASK,
517 .mask = ST_SENSORS_DEFAULT_AXIS_MASK,
521 .mask = ST_ACCEL_5_FS_MASK,
547 int *val2, long mask) st_accel_read_raw()
552 switch (mask) { st_accel_read_raw()
575 struct iio_chan_spec const *chan, int val, int val2, long mask) st_accel_write_raw()
579 switch (mask) { st_accel_write_raw()
545 st_accel_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *ch, int *val, int *val2, long mask) st_accel_read_raw() argument
574 st_accel_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) st_accel_write_raw() argument
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmsmac/
H A Dbrcms_trace_brcmsmac.h75 u32 mask),
76 TP_ARGS(dev, in_isr, macintstatus, mask),
81 __field(u32, mask)
87 __entry->mask = mask;
89 TP_printk("[%s] in_isr=%d macintstatus=%#x mask=%#x", __get_str(dev),
90 __entry->in_isr, __entry->macintstatus, __entry->mask)
/linux-4.4.14/arch/arm64/include/asm/
H A Dword-at-a-time.h32 unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits; has_zero() local
33 *bits = mask; has_zero()
34 return mask; has_zero()
45 static inline unsigned long find_zero(unsigned long mask) find_zero() argument
47 return fls64(mask) >> 3; find_zero()
50 #define zero_bytemask(mask) (mask)
/linux-4.4.14/drivers/s390/cio/
H A Dccwreq.c22 * lpm_adjust - adjust path mask
23 * @lpm: path mask to adjust
24 * @mask: mask of available paths
26 * Shift @lpm right until @lpm and @mask have at least one bit in common or
29 int lpm_adjust(int lpm, int mask) lpm_adjust() argument
31 while (lpm && ((lpm & mask) == 0)) lpm_adjust()
37 * Adjust path mask to use next path and reset retry count. Return resulting
38 * path mask.
45 req->mask = 0; ccwreq_next_path()
49 req->mask = lpm_adjust(req->mask >> 1, req->lpm); ccwreq_next_path()
51 return req->mask; ccwreq_next_path()
81 while (req->mask) { ccwreq_do()
89 rc = cio_start(sch, cp, (u8) req->mask); ccwreq_do()
125 req->mask = 0x8080; ccw_request_start()
127 req->mask = req->lpm; ccw_request_start()
130 req->mask = lpm_adjust(req->mask, req->lpm); ccw_request_start()
134 if (!req->mask) ccw_request_start()
241 data.lpm = (u8) req->mask; ccwreq_log_status()
/linux-4.4.14/fs/hfs/
H A Dbitmap.c32 u32 mask, start, len, n; hfs_find_set_zero_bits() local
48 mask = (1U << 31) >> i; hfs_find_set_zero_bits()
49 for (; i < 32; mask >>= 1, i++) { hfs_find_set_zero_bits()
50 if (!(n & mask)) hfs_find_set_zero_bits()
60 mask = 1 << 31; hfs_find_set_zero_bits()
61 for (i = 0; i < 32; mask >>= 1, i++) { hfs_find_set_zero_bits()
62 if (!(n & mask)) hfs_find_set_zero_bits()
76 n |= mask; hfs_find_set_zero_bits()
79 mask >>= 1; hfs_find_set_zero_bits()
80 if (!--len || n & mask) hfs_find_set_zero_bits()
99 mask = 1U << 31; hfs_find_set_zero_bits()
101 if (n & mask) hfs_find_set_zero_bits()
103 n |= mask; hfs_find_set_zero_bits()
104 mask >>= 1; hfs_find_set_zero_bits()
196 u32 mask; hfs_clear_vbm_bits() local
217 mask = 0xffffffffU << j; hfs_clear_vbm_bits()
219 mask |= 0xffffffffU >> (i + count); hfs_clear_vbm_bits()
220 *curr &= cpu_to_be32(mask); hfs_clear_vbm_bits()
223 *curr++ &= cpu_to_be32(mask); hfs_clear_vbm_bits()
234 mask = 0xffffffffU >> count; hfs_clear_vbm_bits()
235 *curr &= cpu_to_be32(mask); hfs_clear_vbm_bits()
/linux-4.4.14/arch/powerpc/sysdev/qe_lib/
H A Dqe_ic.c38 .mask = 0x00008000,
44 .mask = 0x00004000,
50 .mask = 0x00002000,
56 .mask = 0x00000040,
62 .mask = 0x00000020,
68 .mask = 0x00000010,
74 .mask = 0x00000008,
80 .mask = 0x00000004,
86 .mask = 0x00000002,
92 .mask = 0x10000000,
98 .mask = 0x00800000,
104 .mask = 0x00400000,
110 .mask = 0x00200000,
116 .mask = 0x00100000,
122 .mask = 0x80000000,
128 .mask = 0x40000000,
134 .mask = 0x20000000,
140 .mask = 0x10000000,
146 .mask = 0x08000000,
152 .mask = 0x00800000,
158 .mask = 0x00400000,
164 .mask = 0x00200000,
170 .mask = 0x00100000,
209 temp | qe_ic_info[src].mask); qe_ic_unmask_irq()
225 temp & ~qe_ic_info[src].mask); qe_ic_mask_irq()
230 * enabled, the mask register would have to be read back; however, qe_ic_mask_irq()
261 if (qe_ic_info[hw].mask == 0) { qe_ic_host_map()
/linux-4.4.14/drivers/staging/rdma/ehca/
H A Dehca_tools.h132 #define EHCA_BMASK_SHIFTPOS(mask) (((mask) >> 16) & 0xffff)
135 #define EHCA_BMASK_MASK(mask) (~0ULL >> ((64 - (mask)) & 0xffff))
138 * EHCA_BMASK_SET - return value shifted and masked by mask
140 * variable&=~EHCA_BMASK_SET(MY_MASK,-1) clears the bits from the mask
143 #define EHCA_BMASK_SET(mask, value) \
144 ((EHCA_BMASK_MASK(mask) & ((u64)(value))) << EHCA_BMASK_SHIFTPOS(mask))
147 * EHCA_BMASK_GET - extract a parameter from value by mask
149 #define EHCA_BMASK_GET(mask, value) \
150 (EHCA_BMASK_MASK(mask) & (((u64)(value)) >> EHCA_BMASK_SHIFTPOS(mask)))
/linux-4.4.14/drivers/ssb/
H A Ddriver_extif.c31 u32 mask, u32 value) extif_write32_masked()
33 value &= mask; extif_write32_masked()
34 value |= extif_read32(extif, offset) & ~mask; extif_write32_masked()
148 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask) ssb_extif_gpio_in() argument
150 return extif_read32(extif, SSB_EXTIF_GPIO_IN) & mask; ssb_extif_gpio_in()
153 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value) ssb_extif_gpio_out() argument
160 mask, value); ssb_extif_gpio_out()
166 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value) ssb_extif_gpio_outen() argument
173 mask, value); ssb_extif_gpio_outen()
179 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value) ssb_extif_gpio_polarity() argument
185 res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value); ssb_extif_gpio_polarity()
191 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value) ssb_extif_gpio_intmask() argument
197 res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value); ssb_extif_gpio_intmask()
30 extif_write32_masked(struct ssb_extif *extif, u16 offset, u32 mask, u32 value) extif_write32_masked() argument
/linux-4.4.14/security/apparmor/
H A Dresource.c28 AA_FS_FILE_STRING("mask", AA_FS_RLIMIT_MASK),
107 (profile->rlimits.mask & (1 << resource) && aa_task_setrlimit()
123 unsigned int mask = 0; __aa_transition_rlimits() local
130 if (old->rlimits.mask) { __aa_transition_rlimits()
131 for (i = 0, mask = 1; i < RLIM_NLIMITS; i++, mask <<= 1) { __aa_transition_rlimits()
132 if (old->rlimits.mask & mask) { __aa_transition_rlimits()
142 if (!new->rlimits.mask) __aa_transition_rlimits()
144 for (i = 0, mask = 1; i < RLIM_NLIMITS; i++, mask <<= 1) { __aa_transition_rlimits()
145 if (!(new->rlimits.mask & mask)) __aa_transition_rlimits()
/linux-4.4.14/arch/m68k/68000/
H A Dints.c74 * into one vector and look in the blasted mask register...
80 int mask; process_int() local
88 mask = 0x00000001; process_int()
91 mask = 0x00000010; process_int()
96 mask = 0x00000100; process_int()
99 mask = 0x00001000; process_int()
106 mask = 0x00010000; process_int()
109 mask = 0x00100000; process_int()
114 mask = 0x01000000; process_int()
117 mask = 0x10000000; process_int()
123 while (! (mask & pend)) { process_int()
124 mask <<=1; process_int()
129 pend &= ~mask; process_int()
/linux-4.4.14/drivers/net/phy/
H A Dmdio-mux-mmioreg.c24 uint8_t mask; member in struct:mdio_mux_mmioreg_state
34 * s->mask).
57 y = (x & ~s->mask) | desired_child; mdio_mux_mmioreg_switch_fn()
59 iowrite8((x & ~s->mask) | desired_child, p); mdio_mux_mmioreg_switch_fn()
96 iprop = of_get_property(np, "mux-mask", &len); mdio_mux_mmioreg_probe()
98 dev_err(&pdev->dev, "missing or invalid mux-mask property\n"); mdio_mux_mmioreg_probe()
105 s->mask = be32_to_cpup(iprop); mdio_mux_mmioreg_probe()
109 * set any bits outside of the 'mask'. mdio_mux_mmioreg_probe()
119 if (be32_to_cpup(iprop) & ~s->mask) { for_each_available_child_of_node()
/linux-4.4.14/arch/sparc/lib/
H A Datomic32.c117 unsigned long ___set_bit(unsigned long *addr, unsigned long mask) ___set_bit() argument
123 *addr = old | mask; ___set_bit()
126 return old & mask; ___set_bit()
130 unsigned long ___clear_bit(unsigned long *addr, unsigned long mask) ___clear_bit() argument
136 *addr = old & ~mask; ___clear_bit()
139 return old & mask; ___clear_bit()
143 unsigned long ___change_bit(unsigned long *addr, unsigned long mask) ___change_bit() argument
149 *addr = old ^ mask; ___change_bit()
152 return old & mask; ___change_bit()

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