126 	      .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 }    ),
128 	      .reg = { .offset = 1, .mask = 0x007FFFFC },
131 			.mask = MI_GLOBAL_GTT,
135 	      .reg = { .offset = 1, .mask = 0x007FFFFC },
138 			.mask = MI_GLOBAL_GTT,
161 			.mask = MI_GLOBAL_GTT,
168 			.mask = MI_GLOBAL_GTT,
174 			.mask = MI_REPORT_PERF_COUNT_GGTT,
180 			.mask = MI_GLOBAL_GTT,
188 			.mask = MEDIA_VFE_STATE_MMIO_ACCESS_MASK,
197 			.mask = (PIPE_CONTROL_MMIO_WRITE | PIPE_CONTROL_NOTIFY),
202 		        .mask = (PIPE_CONTROL_GLOBAL_GTT_IVB |
238 			.mask = MI_GLOBAL_GTT,
245 			.mask = MI_FLUSH_DW_NOTIFY,
250 			.mask = MI_FLUSH_DW_USE_GTT,
257 			.mask = MI_FLUSH_DW_STORE_INDEX,
265 			.mask = MI_GLOBAL_GTT,
282 			.mask = MI_GLOBAL_GTT,
289 			.mask = MI_FLUSH_DW_NOTIFY,
294 			.mask = MI_FLUSH_DW_USE_GTT,
301 			.mask = MI_FLUSH_DW_STORE_INDEX,
309 			.mask = MI_GLOBAL_GTT,
319 			.mask = MI_GLOBAL_GTT,
326 			.mask = MI_FLUSH_DW_NOTIFY,
331 			.mask = MI_FLUSH_DW_USE_GTT,
338 			.mask = MI_FLUSH_DW_STORE_INDEX,
411 	u32 mask;  member
470 	      .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,
473 	      .mask = ~(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE << 16 |
571 			u32 curr = desc->cmd.value & desc->cmd.mask;  in validate_cmds_sorted()
801 		u32 masked_cmd = desc->cmd.mask & cmd_header;  in find_cmd_in_table()
802 		u32 masked_value = desc->cmd.value & desc->cmd.mask;  in find_cmd_in_table()
825 	u32 mask;  in find_cmd()  local
831 	mask = ring->get_cmd_length_mask(cmd_header);  in find_cmd()
832 	if (!mask)  in find_cmd()
837 	default_desc->length.mask = mask;  in find_cmd()
1000 			const u32 reg_addr = cmd[offset] & desc->reg.mask;  in check_cmd()
1040 			if (reg->mask) {  in check_cmd()
1049 				     (cmd[offset + 1] & reg->mask) != reg->value)) {  in check_cmd()
1064 			if (desc->bits[i].mask == 0)  in check_cmd()
1078 				desc->bits[i].mask;  in check_cmd()
1083 						 desc->bits[i].mask,  in check_cmd()
1166 			length = ((*cmd & desc->length.mask) + LENGTH_BIAS);  in i915_parse_cmds()