1/*
2 * Interrupt controller support for MAX8998
3 *
4 * Copyright (C) 2010 Samsung Electronics Co.Ltd
5 * Author: Joonyoung Shim <jy0922.shim@samsung.com>
6 *
7 * This program is free software; you can redistribute  it and/or modify it
8 * under  the terms of  the GNU General  Public License as published by the
9 * Free Software Foundation;  either version 2 of the  License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/mfd/max8998-private.h>
19
20struct max8998_irq_data {
21	int reg;
22	int mask;
23};
24
25static struct max8998_irq_data max8998_irqs[] = {
26	[MAX8998_IRQ_DCINF] = {
27		.reg = 1,
28		.mask = MAX8998_IRQ_DCINF_MASK,
29	},
30	[MAX8998_IRQ_DCINR] = {
31		.reg = 1,
32		.mask = MAX8998_IRQ_DCINR_MASK,
33	},
34	[MAX8998_IRQ_JIGF] = {
35		.reg = 1,
36		.mask = MAX8998_IRQ_JIGF_MASK,
37	},
38	[MAX8998_IRQ_JIGR] = {
39		.reg = 1,
40		.mask = MAX8998_IRQ_JIGR_MASK,
41	},
42	[MAX8998_IRQ_PWRONF] = {
43		.reg = 1,
44		.mask = MAX8998_IRQ_PWRONF_MASK,
45	},
46	[MAX8998_IRQ_PWRONR] = {
47		.reg = 1,
48		.mask = MAX8998_IRQ_PWRONR_MASK,
49	},
50	[MAX8998_IRQ_WTSREVNT] = {
51		.reg = 2,
52		.mask = MAX8998_IRQ_WTSREVNT_MASK,
53	},
54	[MAX8998_IRQ_SMPLEVNT] = {
55		.reg = 2,
56		.mask = MAX8998_IRQ_SMPLEVNT_MASK,
57	},
58	[MAX8998_IRQ_ALARM1] = {
59		.reg = 2,
60		.mask = MAX8998_IRQ_ALARM1_MASK,
61	},
62	[MAX8998_IRQ_ALARM0] = {
63		.reg = 2,
64		.mask = MAX8998_IRQ_ALARM0_MASK,
65	},
66	[MAX8998_IRQ_ONKEY1S] = {
67		.reg = 3,
68		.mask = MAX8998_IRQ_ONKEY1S_MASK,
69	},
70	[MAX8998_IRQ_TOPOFFR] = {
71		.reg = 3,
72		.mask = MAX8998_IRQ_TOPOFFR_MASK,
73	},
74	[MAX8998_IRQ_DCINOVPR] = {
75		.reg = 3,
76		.mask = MAX8998_IRQ_DCINOVPR_MASK,
77	},
78	[MAX8998_IRQ_CHGRSTF] = {
79		.reg = 3,
80		.mask = MAX8998_IRQ_CHGRSTF_MASK,
81	},
82	[MAX8998_IRQ_DONER] = {
83		.reg = 3,
84		.mask = MAX8998_IRQ_DONER_MASK,
85	},
86	[MAX8998_IRQ_CHGFAULT] = {
87		.reg = 3,
88		.mask = MAX8998_IRQ_CHGFAULT_MASK,
89	},
90	[MAX8998_IRQ_LOBAT1] = {
91		.reg = 4,
92		.mask = MAX8998_IRQ_LOBAT1_MASK,
93	},
94	[MAX8998_IRQ_LOBAT2] = {
95		.reg = 4,
96		.mask = MAX8998_IRQ_LOBAT2_MASK,
97	},
98};
99
100static inline struct max8998_irq_data *
101irq_to_max8998_irq(struct max8998_dev *max8998, struct irq_data *data)
102{
103	return &max8998_irqs[data->hwirq];
104}
105
106static void max8998_irq_lock(struct irq_data *data)
107{
108	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
109
110	mutex_lock(&max8998->irqlock);
111}
112
113static void max8998_irq_sync_unlock(struct irq_data *data)
114{
115	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
116	int i;
117
118	for (i = 0; i < ARRAY_SIZE(max8998->irq_masks_cur); i++) {
119		/*
120		 * If there's been a change in the mask write it back
121		 * to the hardware.
122		 */
123		if (max8998->irq_masks_cur[i] != max8998->irq_masks_cache[i]) {
124			max8998->irq_masks_cache[i] = max8998->irq_masks_cur[i];
125			max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i,
126					max8998->irq_masks_cur[i]);
127		}
128	}
129
130	mutex_unlock(&max8998->irqlock);
131}
132
133static void max8998_irq_unmask(struct irq_data *data)
134{
135	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
136	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
137
138	max8998->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
139}
140
141static void max8998_irq_mask(struct irq_data *data)
142{
143	struct max8998_dev *max8998 = irq_data_get_irq_chip_data(data);
144	struct max8998_irq_data *irq_data = irq_to_max8998_irq(max8998, data);
145
146	max8998->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
147}
148
149static struct irq_chip max8998_irq_chip = {
150	.name = "max8998",
151	.irq_bus_lock = max8998_irq_lock,
152	.irq_bus_sync_unlock = max8998_irq_sync_unlock,
153	.irq_mask = max8998_irq_mask,
154	.irq_unmask = max8998_irq_unmask,
155};
156
157static irqreturn_t max8998_irq_thread(int irq, void *data)
158{
159	struct max8998_dev *max8998 = data;
160	u8 irq_reg[MAX8998_NUM_IRQ_REGS];
161	int ret;
162	int i;
163
164	ret = max8998_bulk_read(max8998->i2c, MAX8998_REG_IRQ1,
165			MAX8998_NUM_IRQ_REGS, irq_reg);
166	if (ret < 0) {
167		dev_err(max8998->dev, "Failed to read interrupt register: %d\n",
168				ret);
169		return IRQ_NONE;
170	}
171
172	/* Apply masking */
173	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++)
174		irq_reg[i] &= ~max8998->irq_masks_cur[i];
175
176	/* Report */
177	for (i = 0; i < MAX8998_IRQ_NR; i++) {
178		if (irq_reg[max8998_irqs[i].reg - 1] & max8998_irqs[i].mask) {
179			irq = irq_find_mapping(max8998->irq_domain, i);
180			if (WARN_ON(!irq)) {
181				disable_irq_nosync(max8998->irq);
182				return IRQ_NONE;
183			}
184			handle_nested_irq(irq);
185		}
186	}
187
188	return IRQ_HANDLED;
189}
190
191int max8998_irq_resume(struct max8998_dev *max8998)
192{
193	if (max8998->irq && max8998->irq_domain)
194		max8998_irq_thread(max8998->irq, max8998);
195	return 0;
196}
197
198static int max8998_irq_domain_map(struct irq_domain *d, unsigned int irq,
199					irq_hw_number_t hw)
200{
201	struct max8997_dev *max8998 = d->host_data;
202
203	irq_set_chip_data(irq, max8998);
204	irq_set_chip_and_handler(irq, &max8998_irq_chip, handle_edge_irq);
205	irq_set_nested_thread(irq, 1);
206	irq_set_noprobe(irq);
207
208	return 0;
209}
210
211static const struct irq_domain_ops max8998_irq_domain_ops = {
212	.map = max8998_irq_domain_map,
213};
214
215int max8998_irq_init(struct max8998_dev *max8998)
216{
217	int i;
218	int ret;
219	struct irq_domain *domain;
220
221	if (!max8998->irq) {
222		dev_warn(max8998->dev,
223			 "No interrupt specified, no interrupts\n");
224		return 0;
225	}
226
227	mutex_init(&max8998->irqlock);
228
229	/* Mask the individual interrupt sources */
230	for (i = 0; i < MAX8998_NUM_IRQ_REGS; i++) {
231		max8998->irq_masks_cur[i] = 0xff;
232		max8998->irq_masks_cache[i] = 0xff;
233		max8998_write_reg(max8998->i2c, MAX8998_REG_IRQM1 + i, 0xff);
234	}
235
236	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM1, 0xff);
237	max8998_write_reg(max8998->i2c, MAX8998_REG_STATUSM2, 0xff);
238
239	domain = irq_domain_add_simple(NULL, MAX8998_IRQ_NR,
240			max8998->irq_base, &max8998_irq_domain_ops, max8998);
241	if (!domain) {
242		dev_err(max8998->dev, "could not create irq domain\n");
243		return -ENODEV;
244	}
245	max8998->irq_domain = domain;
246
247	ret = request_threaded_irq(max8998->irq, NULL, max8998_irq_thread,
248				   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
249				   "max8998-irq", max8998);
250	if (ret) {
251		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
252			max8998->irq, ret);
253		return ret;
254	}
255
256	if (!max8998->ono)
257		return 0;
258
259	ret = request_threaded_irq(max8998->ono, NULL, max8998_irq_thread,
260				   IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING |
261				   IRQF_ONESHOT, "max8998-ono", max8998);
262	if (ret)
263		dev_err(max8998->dev, "Failed to request IRQ %d: %d\n",
264			max8998->ono, ret);
265
266	return 0;
267}
268
269void max8998_irq_exit(struct max8998_dev *max8998)
270{
271	if (max8998->ono)
272		free_irq(max8998->ono, max8998);
273
274	if (max8998->irq)
275		free_irq(max8998->irq, max8998);
276}
277