1/* 2 * Driver for the ST Microelectronics SPEAr1340 pinmux 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <vireshk@kernel.org> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12#include <linux/err.h> 13#include <linux/init.h> 14#include <linux/module.h> 15#include <linux/of_device.h> 16#include <linux/platform_device.h> 17#include "pinctrl-spear.h" 18 19#define DRIVER_NAME "spear1340-pinmux" 20 21/* pins */ 22static const struct pinctrl_pin_desc spear1340_pins[] = { 23 SPEAR_PIN_0_TO_101, 24 SPEAR_PIN_102_TO_245, 25 PINCTRL_PIN(246, "PLGPIO246"), 26 PINCTRL_PIN(247, "PLGPIO247"), 27 PINCTRL_PIN(248, "PLGPIO248"), 28 PINCTRL_PIN(249, "PLGPIO249"), 29 PINCTRL_PIN(250, "PLGPIO250"), 30 PINCTRL_PIN(251, "PLGPIO251"), 31}; 32 33/* In SPEAr1340 there are two levels of pad muxing */ 34/* - pads as gpio OR peripherals */ 35#define PAD_FUNCTION_EN_1 0x668 36#define PAD_FUNCTION_EN_2 0x66C 37#define PAD_FUNCTION_EN_3 0x670 38#define PAD_FUNCTION_EN_4 0x674 39#define PAD_FUNCTION_EN_5 0x690 40#define PAD_FUNCTION_EN_6 0x694 41#define PAD_FUNCTION_EN_7 0x698 42#define PAD_FUNCTION_EN_8 0x69C 43 44/* - If peripherals, then primary OR alternate peripheral */ 45#define PAD_SHARED_IP_EN_1 0x6A0 46#define PAD_SHARED_IP_EN_2 0x6A4 47 48/* 49 * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8 50 * registers with 32 bits each for handling gpio pads, register 8 has only 26 51 * relevant bits. 52 */ 53/* macro's for making pads as gpio's */ 54#define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE 55#define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF 56#define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF 57 58/* macro's for making pads as peripherals */ 59#define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE 60#define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000 61#define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000 62#define I2C1_REG0_MASK 0x01080000 63#define SPDIF_IN_REG0_MASK 0x00100000 64#define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000 65#define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000 66#define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000 67#define VIP_AND_CAM3_REG0_MASK 0xFC200000 68#define VIP_AND_CAM3_REG1_MASK 0x0000000F 69#define VIP_REG1_MASK 0x00001EF0 70#define VIP_AND_CAM2_REG1_MASK 0x007FE100 71#define VIP_AND_CAM1_REG1_MASK 0xFF800000 72#define VIP_AND_CAM1_REG2_MASK 0x00000003 73#define VIP_AND_CAM0_REG2_MASK 0x00001FFC 74#define SMI_REG2_MASK 0x0021E000 75#define SSP0_REG2_MASK 0x001E0000 76#define TS_AND_SSP0_CS2_REG2_MASK 0x00400000 77#define UART0_REG2_MASK 0x01800000 78#define UART1_REG2_MASK 0x06000000 79#define I2S_IN_REG2_MASK 0xF8000000 80#define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE 81#define I2S_OUT_REG3_MASK 0x000001EF 82#define I2S_IN_REG3_MASK 0x00000010 83#define GMAC_REG3_MASK 0xFFFFFE00 84#define GMAC_REG4_MASK 0x0000001F 85#define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20 86#define SSP0_CS3_REG4_MASK 0x00000020 87#define I2C0_REG4_MASK 0x000000C0 88#define CEC0_REG4_MASK 0x00000100 89#define CEC1_REG4_MASK 0x00000200 90#define SPDIF_OUT_REG4_MASK 0x00000400 91#define CLCD_REG4_MASK 0x7FFFF800 92#define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000 93#define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF 94#define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001 95#define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE 96#define MCIF_REG6_MASK 0xF8C00000 97#define MCIF_REG7_MASK 0x000043FF 98#define FSMC_8BIT_REG7_MASK 0x07FFBC00 99 100/* other registers */ 101#define PERIP_CFG 0x42C 102 /* PERIP_CFG register masks */ 103 #define SSP_CS_CTL_HW 0 104 #define SSP_CS_CTL_SW 1 105 #define SSP_CS_CTL_MASK 1 106 #define SSP_CS_CTL_SHIFT 21 107 #define SSP_CS_VAL_MASK 1 108 #define SSP_CS_VAL_SHIFT 20 109 #define SSP_CS_SEL_CS0 0 110 #define SSP_CS_SEL_CS1 1 111 #define SSP_CS_SEL_CS2 2 112 #define SSP_CS_SEL_MASK 3 113 #define SSP_CS_SEL_SHIFT 18 114 115 #define I2S_CHNL_2_0 (0) 116 #define I2S_CHNL_3_1 (1) 117 #define I2S_CHNL_5_1 (2) 118 #define I2S_CHNL_7_1 (3) 119 #define I2S_CHNL_PLAY_SHIFT (4) 120 #define I2S_CHNL_PLAY_MASK (3 << 4) 121 #define I2S_CHNL_REC_SHIFT (6) 122 #define I2S_CHNL_REC_MASK (3 << 6) 123 124 #define SPDIF_OUT_ENB_MASK (1 << 2) 125 #define SPDIF_OUT_ENB_SHIFT 2 126 127 #define MCIF_SEL_SD 1 128 #define MCIF_SEL_CF 2 129 #define MCIF_SEL_XD 3 130 #define MCIF_SEL_MASK 3 131 #define MCIF_SEL_SHIFT 0 132 133#define GMAC_CLK_CFG 0x248 134 #define GMAC_PHY_IF_GMII_VAL (0 << 3) 135 #define GMAC_PHY_IF_RGMII_VAL (1 << 3) 136 #define GMAC_PHY_IF_SGMII_VAL (2 << 3) 137 #define GMAC_PHY_IF_RMII_VAL (4 << 3) 138 #define GMAC_PHY_IF_SEL_MASK (7 << 3) 139 #define GMAC_PHY_INPUT_ENB_VAL 0 140 #define GMAC_PHY_SYNT_ENB_VAL 1 141 #define GMAC_PHY_CLK_MASK 1 142 #define GMAC_PHY_CLK_SHIFT 2 143 #define GMAC_PHY_125M_PAD_VAL 0 144 #define GMAC_PHY_PLL2_VAL 1 145 #define GMAC_PHY_OSC3_VAL 2 146 #define GMAC_PHY_INPUT_CLK_MASK 3 147 #define GMAC_PHY_INPUT_CLK_SHIFT 0 148 149#define PCIE_SATA_CFG 0x424 150 /* PCIE CFG MASks */ 151 #define PCIE_CFG_DEVICE_PRESENT (1 << 11) 152 #define PCIE_CFG_POWERUP_RESET (1 << 10) 153 #define PCIE_CFG_CORE_CLK_EN (1 << 9) 154 #define PCIE_CFG_AUX_CLK_EN (1 << 8) 155 #define SATA_CFG_TX_CLK_EN (1 << 4) 156 #define SATA_CFG_RX_CLK_EN (1 << 3) 157 #define SATA_CFG_POWERUP_RESET (1 << 2) 158 #define SATA_CFG_PM_CLK_EN (1 << 1) 159 #define PCIE_SATA_SEL_PCIE (0) 160 #define PCIE_SATA_SEL_SATA (1) 161 #define SATA_PCIE_CFG_MASK 0xF1F 162 #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \ 163 PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\ 164 PCIE_CFG_DEVICE_PRESENT) 165 #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \ 166 SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \ 167 SATA_CFG_TX_CLK_EN) 168 169/* Macro's for second level of pmx - pads as primary OR alternate peripheral */ 170/* Write 0 to enable FSMC_16_BIT */ 171#define KBD_ROW_COL_MASK (1 << 0) 172 173/* Write 0 to enable UART0_ENH */ 174#define GPT_MASK (1 << 1) /* Only clk & cpt */ 175 176/* Write 0 to enable PWM1 */ 177#define KBD_COL5_MASK (1 << 2) 178 179/* Write 0 to enable PWM2 */ 180#define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */ 181 182/* Write 0 to enable PWM3 */ 183#define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */ 184 185/* Write 0 to enable PWM0 */ 186#define SSP0_CS1_MASK (1 << 5) 187 188/* Write 0 to enable VIP */ 189#define CAM3_MASK (1 << 6) 190 191/* Write 0 to enable VIP */ 192#define CAM2_MASK (1 << 7) 193 194/* Write 0 to enable VIP */ 195#define CAM1_MASK (1 << 8) 196 197/* Write 0 to enable VIP */ 198#define CAM0_MASK (1 << 9) 199 200/* Write 0 to enable TS */ 201#define SSP0_CS2_MASK (1 << 10) 202 203/* Write 0 to enable FSMC PNOR */ 204#define MCIF_MASK (1 << 11) 205 206/* Write 0 to enable CLCD */ 207#define ARM_TRACE_MASK (1 << 12) 208 209/* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */ 210#define MIPHY_DBG_MASK (1 << 13) 211 212/* 213 * Pad multiplexing for making all pads as gpio's. This is done to override the 214 * values passed from bootloader and start from scratch. 215 */ 216static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 }; 217static struct spear_muxreg pads_as_gpio_muxreg[] = { 218 { 219 .reg = PAD_FUNCTION_EN_1, 220 .mask = PADS_AS_GPIO_REG0_MASK, 221 .val = 0x0, 222 }, { 223 .reg = PAD_FUNCTION_EN_2, 224 .mask = PADS_AS_GPIO_REGS_MASK, 225 .val = 0x0, 226 }, { 227 .reg = PAD_FUNCTION_EN_3, 228 .mask = PADS_AS_GPIO_REGS_MASK, 229 .val = 0x0, 230 }, { 231 .reg = PAD_FUNCTION_EN_4, 232 .mask = PADS_AS_GPIO_REGS_MASK, 233 .val = 0x0, 234 }, { 235 .reg = PAD_FUNCTION_EN_5, 236 .mask = PADS_AS_GPIO_REGS_MASK, 237 .val = 0x0, 238 }, { 239 .reg = PAD_FUNCTION_EN_6, 240 .mask = PADS_AS_GPIO_REGS_MASK, 241 .val = 0x0, 242 }, { 243 .reg = PAD_FUNCTION_EN_7, 244 .mask = PADS_AS_GPIO_REGS_MASK, 245 .val = 0x0, 246 }, { 247 .reg = PAD_FUNCTION_EN_8, 248 .mask = PADS_AS_GPIO_REG7_MASK, 249 .val = 0x0, 250 }, 251}; 252 253static struct spear_modemux pads_as_gpio_modemux[] = { 254 { 255 .muxregs = pads_as_gpio_muxreg, 256 .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg), 257 }, 258}; 259 260static struct spear_pingroup pads_as_gpio_pingroup = { 261 .name = "pads_as_gpio_grp", 262 .pins = pads_as_gpio_pins, 263 .npins = ARRAY_SIZE(pads_as_gpio_pins), 264 .modemuxs = pads_as_gpio_modemux, 265 .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux), 266}; 267 268static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" }; 269static struct spear_function pads_as_gpio_function = { 270 .name = "pads_as_gpio", 271 .groups = pads_as_gpio_grps, 272 .ngroups = ARRAY_SIZE(pads_as_gpio_grps), 273}; 274 275/* Pad multiplexing for fsmc_8bit device */ 276static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240, 277 241, 242, 243, 244, 245, 246, 247, 248, 249 }; 278static struct spear_muxreg fsmc_8bit_muxreg[] = { 279 { 280 .reg = PAD_FUNCTION_EN_8, 281 .mask = FSMC_8BIT_REG7_MASK, 282 .val = FSMC_8BIT_REG7_MASK, 283 } 284}; 285 286static struct spear_modemux fsmc_8bit_modemux[] = { 287 { 288 .muxregs = fsmc_8bit_muxreg, 289 .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), 290 }, 291}; 292 293static struct spear_pingroup fsmc_8bit_pingroup = { 294 .name = "fsmc_8bit_grp", 295 .pins = fsmc_8bit_pins, 296 .npins = ARRAY_SIZE(fsmc_8bit_pins), 297 .modemuxs = fsmc_8bit_modemux, 298 .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), 299}; 300 301/* Pad multiplexing for fsmc_16bit device */ 302static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 }; 303static struct spear_muxreg fsmc_16bit_muxreg[] = { 304 { 305 .reg = PAD_SHARED_IP_EN_1, 306 .mask = KBD_ROW_COL_MASK, 307 .val = 0, 308 }, { 309 .reg = PAD_FUNCTION_EN_1, 310 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 311 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 312 }, 313}; 314 315static struct spear_modemux fsmc_16bit_modemux[] = { 316 { 317 .muxregs = fsmc_16bit_muxreg, 318 .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), 319 }, 320}; 321 322static struct spear_pingroup fsmc_16bit_pingroup = { 323 .name = "fsmc_16bit_grp", 324 .pins = fsmc_16bit_pins, 325 .npins = ARRAY_SIZE(fsmc_16bit_pins), 326 .modemuxs = fsmc_16bit_modemux, 327 .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), 328}; 329 330/* pad multiplexing for fsmc_pnor device */ 331static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198, 332 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 333 215, 216, 217 }; 334static struct spear_muxreg fsmc_pnor_muxreg[] = { 335 { 336 .reg = PAD_SHARED_IP_EN_1, 337 .mask = MCIF_MASK, 338 .val = 0, 339 }, { 340 .reg = PAD_FUNCTION_EN_7, 341 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK, 342 .val = FSMC_PNOR_AND_MCIF_REG6_MASK, 343 }, 344}; 345 346static struct spear_modemux fsmc_pnor_modemux[] = { 347 { 348 .muxregs = fsmc_pnor_muxreg, 349 .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg), 350 }, 351}; 352 353static struct spear_pingroup fsmc_pnor_pingroup = { 354 .name = "fsmc_pnor_grp", 355 .pins = fsmc_pnor_pins, 356 .npins = ARRAY_SIZE(fsmc_pnor_pins), 357 .modemuxs = fsmc_pnor_modemux, 358 .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux), 359}; 360 361static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp", 362 "fsmc_pnor_grp" }; 363static struct spear_function fsmc_function = { 364 .name = "fsmc", 365 .groups = fsmc_grps, 366 .ngroups = ARRAY_SIZE(fsmc_grps), 367}; 368 369/* pad multiplexing for keyboard rows-cols device */ 370static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 371 10 }; 372static struct spear_muxreg keyboard_row_col_muxreg[] = { 373 { 374 .reg = PAD_SHARED_IP_EN_1, 375 .mask = KBD_ROW_COL_MASK, 376 .val = KBD_ROW_COL_MASK, 377 }, { 378 .reg = PAD_FUNCTION_EN_1, 379 .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 380 .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, 381 }, 382}; 383 384static struct spear_modemux keyboard_row_col_modemux[] = { 385 { 386 .muxregs = keyboard_row_col_muxreg, 387 .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg), 388 }, 389}; 390 391static struct spear_pingroup keyboard_row_col_pingroup = { 392 .name = "keyboard_row_col_grp", 393 .pins = keyboard_row_col_pins, 394 .npins = ARRAY_SIZE(keyboard_row_col_pins), 395 .modemuxs = keyboard_row_col_modemux, 396 .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux), 397}; 398 399/* pad multiplexing for keyboard col5 device */ 400static const unsigned keyboard_col5_pins[] = { 17 }; 401static struct spear_muxreg keyboard_col5_muxreg[] = { 402 { 403 .reg = PAD_SHARED_IP_EN_1, 404 .mask = KBD_COL5_MASK, 405 .val = KBD_COL5_MASK, 406 }, { 407 .reg = PAD_FUNCTION_EN_1, 408 .mask = PWM1_AND_KBD_COL5_REG0_MASK, 409 .val = PWM1_AND_KBD_COL5_REG0_MASK, 410 }, 411}; 412 413static struct spear_modemux keyboard_col5_modemux[] = { 414 { 415 .muxregs = keyboard_col5_muxreg, 416 .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg), 417 }, 418}; 419 420static struct spear_pingroup keyboard_col5_pingroup = { 421 .name = "keyboard_col5_grp", 422 .pins = keyboard_col5_pins, 423 .npins = ARRAY_SIZE(keyboard_col5_pins), 424 .modemuxs = keyboard_col5_modemux, 425 .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux), 426}; 427 428static const char *const keyboard_grps[] = { "keyboard_row_col_grp", 429 "keyboard_col5_grp" }; 430static struct spear_function keyboard_function = { 431 .name = "keyboard", 432 .groups = keyboard_grps, 433 .ngroups = ARRAY_SIZE(keyboard_grps), 434}; 435 436/* pad multiplexing for spdif_in device */ 437static const unsigned spdif_in_pins[] = { 19 }; 438static struct spear_muxreg spdif_in_muxreg[] = { 439 { 440 .reg = PAD_FUNCTION_EN_1, 441 .mask = SPDIF_IN_REG0_MASK, 442 .val = SPDIF_IN_REG0_MASK, 443 }, 444}; 445 446static struct spear_modemux spdif_in_modemux[] = { 447 { 448 .muxregs = spdif_in_muxreg, 449 .nmuxregs = ARRAY_SIZE(spdif_in_muxreg), 450 }, 451}; 452 453static struct spear_pingroup spdif_in_pingroup = { 454 .name = "spdif_in_grp", 455 .pins = spdif_in_pins, 456 .npins = ARRAY_SIZE(spdif_in_pins), 457 .modemuxs = spdif_in_modemux, 458 .nmodemuxs = ARRAY_SIZE(spdif_in_modemux), 459}; 460 461static const char *const spdif_in_grps[] = { "spdif_in_grp" }; 462static struct spear_function spdif_in_function = { 463 .name = "spdif_in", 464 .groups = spdif_in_grps, 465 .ngroups = ARRAY_SIZE(spdif_in_grps), 466}; 467 468/* pad multiplexing for spdif_out device */ 469static const unsigned spdif_out_pins[] = { 137 }; 470static struct spear_muxreg spdif_out_muxreg[] = { 471 { 472 .reg = PAD_FUNCTION_EN_5, 473 .mask = SPDIF_OUT_REG4_MASK, 474 .val = SPDIF_OUT_REG4_MASK, 475 }, { 476 .reg = PERIP_CFG, 477 .mask = SPDIF_OUT_ENB_MASK, 478 .val = SPDIF_OUT_ENB_MASK, 479 } 480}; 481 482static struct spear_modemux spdif_out_modemux[] = { 483 { 484 .muxregs = spdif_out_muxreg, 485 .nmuxregs = ARRAY_SIZE(spdif_out_muxreg), 486 }, 487}; 488 489static struct spear_pingroup spdif_out_pingroup = { 490 .name = "spdif_out_grp", 491 .pins = spdif_out_pins, 492 .npins = ARRAY_SIZE(spdif_out_pins), 493 .modemuxs = spdif_out_modemux, 494 .nmodemuxs = ARRAY_SIZE(spdif_out_modemux), 495}; 496 497static const char *const spdif_out_grps[] = { "spdif_out_grp" }; 498static struct spear_function spdif_out_function = { 499 .name = "spdif_out", 500 .groups = spdif_out_grps, 501 .ngroups = ARRAY_SIZE(spdif_out_grps), 502}; 503 504/* pad multiplexing for gpt_0_1 device */ 505static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 }; 506static struct spear_muxreg gpt_0_1_muxreg[] = { 507 { 508 .reg = PAD_SHARED_IP_EN_1, 509 .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, 510 .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, 511 }, { 512 .reg = PAD_FUNCTION_EN_1, 513 .mask = UART0_ENH_AND_GPT_REG0_MASK | 514 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | 515 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 516 .val = UART0_ENH_AND_GPT_REG0_MASK | 517 PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | 518 PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 519 }, 520}; 521 522static struct spear_modemux gpt_0_1_modemux[] = { 523 { 524 .muxregs = gpt_0_1_muxreg, 525 .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg), 526 }, 527}; 528 529static struct spear_pingroup gpt_0_1_pingroup = { 530 .name = "gpt_0_1_grp", 531 .pins = gpt_0_1_pins, 532 .npins = ARRAY_SIZE(gpt_0_1_pins), 533 .modemuxs = gpt_0_1_modemux, 534 .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux), 535}; 536 537static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" }; 538static struct spear_function gpt_0_1_function = { 539 .name = "gpt_0_1", 540 .groups = gpt_0_1_grps, 541 .ngroups = ARRAY_SIZE(gpt_0_1_grps), 542}; 543 544/* pad multiplexing for pwm0 device */ 545static const unsigned pwm0_pins[] = { 24 }; 546static struct spear_muxreg pwm0_muxreg[] = { 547 { 548 .reg = PAD_SHARED_IP_EN_1, 549 .mask = SSP0_CS1_MASK, 550 .val = 0, 551 }, { 552 .reg = PAD_FUNCTION_EN_1, 553 .mask = PWM0_AND_SSP0_CS1_REG0_MASK, 554 .val = PWM0_AND_SSP0_CS1_REG0_MASK, 555 }, 556}; 557 558static struct spear_modemux pwm0_modemux[] = { 559 { 560 .muxregs = pwm0_muxreg, 561 .nmuxregs = ARRAY_SIZE(pwm0_muxreg), 562 }, 563}; 564 565static struct spear_pingroup pwm0_pingroup = { 566 .name = "pwm0_grp", 567 .pins = pwm0_pins, 568 .npins = ARRAY_SIZE(pwm0_pins), 569 .modemuxs = pwm0_modemux, 570 .nmodemuxs = ARRAY_SIZE(pwm0_modemux), 571}; 572 573/* pad multiplexing for pwm1 device */ 574static const unsigned pwm1_pins[] = { 17 }; 575static struct spear_muxreg pwm1_muxreg[] = { 576 { 577 .reg = PAD_SHARED_IP_EN_1, 578 .mask = KBD_COL5_MASK, 579 .val = 0, 580 }, { 581 .reg = PAD_FUNCTION_EN_1, 582 .mask = PWM1_AND_KBD_COL5_REG0_MASK, 583 .val = PWM1_AND_KBD_COL5_REG0_MASK, 584 }, 585}; 586 587static struct spear_modemux pwm1_modemux[] = { 588 { 589 .muxregs = pwm1_muxreg, 590 .nmuxregs = ARRAY_SIZE(pwm1_muxreg), 591 }, 592}; 593 594static struct spear_pingroup pwm1_pingroup = { 595 .name = "pwm1_grp", 596 .pins = pwm1_pins, 597 .npins = ARRAY_SIZE(pwm1_pins), 598 .modemuxs = pwm1_modemux, 599 .nmodemuxs = ARRAY_SIZE(pwm1_modemux), 600}; 601 602/* pad multiplexing for pwm2 device */ 603static const unsigned pwm2_pins[] = { 21 }; 604static struct spear_muxreg pwm2_muxreg[] = { 605 { 606 .reg = PAD_SHARED_IP_EN_1, 607 .mask = GPT0_TMR0_CPT_MASK, 608 .val = 0, 609 }, { 610 .reg = PAD_FUNCTION_EN_1, 611 .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, 612 .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, 613 }, 614}; 615 616static struct spear_modemux pwm2_modemux[] = { 617 { 618 .muxregs = pwm2_muxreg, 619 .nmuxregs = ARRAY_SIZE(pwm2_muxreg), 620 }, 621}; 622 623static struct spear_pingroup pwm2_pingroup = { 624 .name = "pwm2_grp", 625 .pins = pwm2_pins, 626 .npins = ARRAY_SIZE(pwm2_pins), 627 .modemuxs = pwm2_modemux, 628 .nmodemuxs = ARRAY_SIZE(pwm2_modemux), 629}; 630 631/* pad multiplexing for pwm3 device */ 632static const unsigned pwm3_pins[] = { 22 }; 633static struct spear_muxreg pwm3_muxreg[] = { 634 { 635 .reg = PAD_SHARED_IP_EN_1, 636 .mask = GPT0_TMR1_CLK_MASK, 637 .val = 0, 638 }, { 639 .reg = PAD_FUNCTION_EN_1, 640 .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 641 .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, 642 }, 643}; 644 645static struct spear_modemux pwm3_modemux[] = { 646 { 647 .muxregs = pwm3_muxreg, 648 .nmuxregs = ARRAY_SIZE(pwm3_muxreg), 649 }, 650}; 651 652static struct spear_pingroup pwm3_pingroup = { 653 .name = "pwm3_grp", 654 .pins = pwm3_pins, 655 .npins = ARRAY_SIZE(pwm3_pins), 656 .modemuxs = pwm3_modemux, 657 .nmodemuxs = ARRAY_SIZE(pwm3_modemux), 658}; 659 660static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp", 661 "pwm3_grp" }; 662static struct spear_function pwm_function = { 663 .name = "pwm", 664 .groups = pwm_grps, 665 .ngroups = ARRAY_SIZE(pwm_grps), 666}; 667 668/* pad multiplexing for vip_mux device */ 669static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 }; 670static struct spear_muxreg vip_mux_muxreg[] = { 671 { 672 .reg = PAD_FUNCTION_EN_2, 673 .mask = VIP_REG1_MASK, 674 .val = VIP_REG1_MASK, 675 }, 676}; 677 678static struct spear_modemux vip_mux_modemux[] = { 679 { 680 .muxregs = vip_mux_muxreg, 681 .nmuxregs = ARRAY_SIZE(vip_mux_muxreg), 682 }, 683}; 684 685static struct spear_pingroup vip_mux_pingroup = { 686 .name = "vip_mux_grp", 687 .pins = vip_mux_pins, 688 .npins = ARRAY_SIZE(vip_mux_pins), 689 .modemuxs = vip_mux_modemux, 690 .nmodemuxs = ARRAY_SIZE(vip_mux_modemux), 691}; 692 693/* pad multiplexing for vip_mux_cam0 (disables cam0) device */ 694static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 695 73, 74, 75 }; 696static struct spear_muxreg vip_mux_cam0_muxreg[] = { 697 { 698 .reg = PAD_SHARED_IP_EN_1, 699 .mask = CAM0_MASK, 700 .val = 0, 701 }, { 702 .reg = PAD_FUNCTION_EN_3, 703 .mask = VIP_AND_CAM0_REG2_MASK, 704 .val = VIP_AND_CAM0_REG2_MASK, 705 }, 706}; 707 708static struct spear_modemux vip_mux_cam0_modemux[] = { 709 { 710 .muxregs = vip_mux_cam0_muxreg, 711 .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg), 712 }, 713}; 714 715static struct spear_pingroup vip_mux_cam0_pingroup = { 716 .name = "vip_mux_cam0_grp", 717 .pins = vip_mux_cam0_pins, 718 .npins = ARRAY_SIZE(vip_mux_cam0_pins), 719 .modemuxs = vip_mux_cam0_modemux, 720 .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux), 721}; 722 723/* pad multiplexing for vip_mux_cam1 (disables cam1) device */ 724static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 725 62, 63, 64 }; 726static struct spear_muxreg vip_mux_cam1_muxreg[] = { 727 { 728 .reg = PAD_SHARED_IP_EN_1, 729 .mask = CAM1_MASK, 730 .val = 0, 731 }, { 732 .reg = PAD_FUNCTION_EN_2, 733 .mask = VIP_AND_CAM1_REG1_MASK, 734 .val = VIP_AND_CAM1_REG1_MASK, 735 }, { 736 .reg = PAD_FUNCTION_EN_3, 737 .mask = VIP_AND_CAM1_REG2_MASK, 738 .val = VIP_AND_CAM1_REG2_MASK, 739 }, 740}; 741 742static struct spear_modemux vip_mux_cam1_modemux[] = { 743 { 744 .muxregs = vip_mux_cam1_muxreg, 745 .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg), 746 }, 747}; 748 749static struct spear_pingroup vip_mux_cam1_pingroup = { 750 .name = "vip_mux_cam1_grp", 751 .pins = vip_mux_cam1_pins, 752 .npins = ARRAY_SIZE(vip_mux_cam1_pins), 753 .modemuxs = vip_mux_cam1_modemux, 754 .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux), 755}; 756 757/* pad multiplexing for vip_mux_cam2 (disables cam2) device */ 758static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 759 51, 52, 53 }; 760static struct spear_muxreg vip_mux_cam2_muxreg[] = { 761 { 762 .reg = PAD_SHARED_IP_EN_1, 763 .mask = CAM2_MASK, 764 .val = 0, 765 }, { 766 .reg = PAD_FUNCTION_EN_2, 767 .mask = VIP_AND_CAM2_REG1_MASK, 768 .val = VIP_AND_CAM2_REG1_MASK, 769 }, 770}; 771 772static struct spear_modemux vip_mux_cam2_modemux[] = { 773 { 774 .muxregs = vip_mux_cam2_muxreg, 775 .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg), 776 }, 777}; 778 779static struct spear_pingroup vip_mux_cam2_pingroup = { 780 .name = "vip_mux_cam2_grp", 781 .pins = vip_mux_cam2_pins, 782 .npins = ARRAY_SIZE(vip_mux_cam2_pins), 783 .modemuxs = vip_mux_cam2_modemux, 784 .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux), 785}; 786 787/* pad multiplexing for vip_mux_cam3 (disables cam3) device */ 788static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 789 32, 33, 34 }; 790static struct spear_muxreg vip_mux_cam3_muxreg[] = { 791 { 792 .reg = PAD_SHARED_IP_EN_1, 793 .mask = CAM3_MASK, 794 .val = 0, 795 }, { 796 .reg = PAD_FUNCTION_EN_1, 797 .mask = VIP_AND_CAM3_REG0_MASK, 798 .val = VIP_AND_CAM3_REG0_MASK, 799 }, { 800 .reg = PAD_FUNCTION_EN_2, 801 .mask = VIP_AND_CAM3_REG1_MASK, 802 .val = VIP_AND_CAM3_REG1_MASK, 803 }, 804}; 805 806static struct spear_modemux vip_mux_cam3_modemux[] = { 807 { 808 .muxregs = vip_mux_cam3_muxreg, 809 .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg), 810 }, 811}; 812 813static struct spear_pingroup vip_mux_cam3_pingroup = { 814 .name = "vip_mux_cam3_grp", 815 .pins = vip_mux_cam3_pins, 816 .npins = ARRAY_SIZE(vip_mux_cam3_pins), 817 .modemuxs = vip_mux_cam3_modemux, 818 .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux), 819}; 820 821static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" , 822 "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" }; 823static struct spear_function vip_function = { 824 .name = "vip", 825 .groups = vip_grps, 826 .ngroups = ARRAY_SIZE(vip_grps), 827}; 828 829/* pad multiplexing for cam0 device */ 830static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 831}; 832static struct spear_muxreg cam0_muxreg[] = { 833 { 834 .reg = PAD_SHARED_IP_EN_1, 835 .mask = CAM0_MASK, 836 .val = CAM0_MASK, 837 }, { 838 .reg = PAD_FUNCTION_EN_3, 839 .mask = VIP_AND_CAM0_REG2_MASK, 840 .val = VIP_AND_CAM0_REG2_MASK, 841 }, 842}; 843 844static struct spear_modemux cam0_modemux[] = { 845 { 846 .muxregs = cam0_muxreg, 847 .nmuxregs = ARRAY_SIZE(cam0_muxreg), 848 }, 849}; 850 851static struct spear_pingroup cam0_pingroup = { 852 .name = "cam0_grp", 853 .pins = cam0_pins, 854 .npins = ARRAY_SIZE(cam0_pins), 855 .modemuxs = cam0_modemux, 856 .nmodemuxs = ARRAY_SIZE(cam0_modemux), 857}; 858 859static const char *const cam0_grps[] = { "cam0_grp" }; 860static struct spear_function cam0_function = { 861 .name = "cam0", 862 .groups = cam0_grps, 863 .ngroups = ARRAY_SIZE(cam0_grps), 864}; 865 866/* pad multiplexing for cam1 device */ 867static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 868}; 869static struct spear_muxreg cam1_muxreg[] = { 870 { 871 .reg = PAD_SHARED_IP_EN_1, 872 .mask = CAM1_MASK, 873 .val = CAM1_MASK, 874 }, { 875 .reg = PAD_FUNCTION_EN_2, 876 .mask = VIP_AND_CAM1_REG1_MASK, 877 .val = VIP_AND_CAM1_REG1_MASK, 878 }, { 879 .reg = PAD_FUNCTION_EN_3, 880 .mask = VIP_AND_CAM1_REG2_MASK, 881 .val = VIP_AND_CAM1_REG2_MASK, 882 }, 883}; 884 885static struct spear_modemux cam1_modemux[] = { 886 { 887 .muxregs = cam1_muxreg, 888 .nmuxregs = ARRAY_SIZE(cam1_muxreg), 889 }, 890}; 891 892static struct spear_pingroup cam1_pingroup = { 893 .name = "cam1_grp", 894 .pins = cam1_pins, 895 .npins = ARRAY_SIZE(cam1_pins), 896 .modemuxs = cam1_modemux, 897 .nmodemuxs = ARRAY_SIZE(cam1_modemux), 898}; 899 900static const char *const cam1_grps[] = { "cam1_grp" }; 901static struct spear_function cam1_function = { 902 .name = "cam1", 903 .groups = cam1_grps, 904 .ngroups = ARRAY_SIZE(cam1_grps), 905}; 906 907/* pad multiplexing for cam2 device */ 908static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 909}; 910static struct spear_muxreg cam2_muxreg[] = { 911 { 912 .reg = PAD_SHARED_IP_EN_1, 913 .mask = CAM2_MASK, 914 .val = CAM2_MASK, 915 }, { 916 .reg = PAD_FUNCTION_EN_2, 917 .mask = VIP_AND_CAM2_REG1_MASK, 918 .val = VIP_AND_CAM2_REG1_MASK, 919 }, 920}; 921 922static struct spear_modemux cam2_modemux[] = { 923 { 924 .muxregs = cam2_muxreg, 925 .nmuxregs = ARRAY_SIZE(cam2_muxreg), 926 }, 927}; 928 929static struct spear_pingroup cam2_pingroup = { 930 .name = "cam2_grp", 931 .pins = cam2_pins, 932 .npins = ARRAY_SIZE(cam2_pins), 933 .modemuxs = cam2_modemux, 934 .nmodemuxs = ARRAY_SIZE(cam2_modemux), 935}; 936 937static const char *const cam2_grps[] = { "cam2_grp" }; 938static struct spear_function cam2_function = { 939 .name = "cam2", 940 .groups = cam2_grps, 941 .ngroups = ARRAY_SIZE(cam2_grps), 942}; 943 944/* pad multiplexing for cam3 device */ 945static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 946}; 947static struct spear_muxreg cam3_muxreg[] = { 948 { 949 .reg = PAD_SHARED_IP_EN_1, 950 .mask = CAM3_MASK, 951 .val = CAM3_MASK, 952 }, { 953 .reg = PAD_FUNCTION_EN_1, 954 .mask = VIP_AND_CAM3_REG0_MASK, 955 .val = VIP_AND_CAM3_REG0_MASK, 956 }, { 957 .reg = PAD_FUNCTION_EN_2, 958 .mask = VIP_AND_CAM3_REG1_MASK, 959 .val = VIP_AND_CAM3_REG1_MASK, 960 }, 961}; 962 963static struct spear_modemux cam3_modemux[] = { 964 { 965 .muxregs = cam3_muxreg, 966 .nmuxregs = ARRAY_SIZE(cam3_muxreg), 967 }, 968}; 969 970static struct spear_pingroup cam3_pingroup = { 971 .name = "cam3_grp", 972 .pins = cam3_pins, 973 .npins = ARRAY_SIZE(cam3_pins), 974 .modemuxs = cam3_modemux, 975 .nmodemuxs = ARRAY_SIZE(cam3_modemux), 976}; 977 978static const char *const cam3_grps[] = { "cam3_grp" }; 979static struct spear_function cam3_function = { 980 .name = "cam3", 981 .groups = cam3_grps, 982 .ngroups = ARRAY_SIZE(cam3_grps), 983}; 984 985/* pad multiplexing for smi device */ 986static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 }; 987static struct spear_muxreg smi_muxreg[] = { 988 { 989 .reg = PAD_FUNCTION_EN_3, 990 .mask = SMI_REG2_MASK, 991 .val = SMI_REG2_MASK, 992 }, 993}; 994 995static struct spear_modemux smi_modemux[] = { 996 { 997 .muxregs = smi_muxreg, 998 .nmuxregs = ARRAY_SIZE(smi_muxreg), 999 }, 1000}; 1001 1002static struct spear_pingroup smi_pingroup = { 1003 .name = "smi_grp", 1004 .pins = smi_pins, 1005 .npins = ARRAY_SIZE(smi_pins), 1006 .modemuxs = smi_modemux, 1007 .nmodemuxs = ARRAY_SIZE(smi_modemux), 1008}; 1009 1010static const char *const smi_grps[] = { "smi_grp" }; 1011static struct spear_function smi_function = { 1012 .name = "smi", 1013 .groups = smi_grps, 1014 .ngroups = ARRAY_SIZE(smi_grps), 1015}; 1016 1017/* pad multiplexing for ssp0 device */ 1018static const unsigned ssp0_pins[] = { 80, 81, 82, 83 }; 1019static struct spear_muxreg ssp0_muxreg[] = { 1020 { 1021 .reg = PAD_FUNCTION_EN_3, 1022 .mask = SSP0_REG2_MASK, 1023 .val = SSP0_REG2_MASK, 1024 }, 1025}; 1026 1027static struct spear_modemux ssp0_modemux[] = { 1028 { 1029 .muxregs = ssp0_muxreg, 1030 .nmuxregs = ARRAY_SIZE(ssp0_muxreg), 1031 }, 1032}; 1033 1034static struct spear_pingroup ssp0_pingroup = { 1035 .name = "ssp0_grp", 1036 .pins = ssp0_pins, 1037 .npins = ARRAY_SIZE(ssp0_pins), 1038 .modemuxs = ssp0_modemux, 1039 .nmodemuxs = ARRAY_SIZE(ssp0_modemux), 1040}; 1041 1042/* pad multiplexing for ssp0_cs1 device */ 1043static const unsigned ssp0_cs1_pins[] = { 24 }; 1044static struct spear_muxreg ssp0_cs1_muxreg[] = { 1045 { 1046 .reg = PAD_SHARED_IP_EN_1, 1047 .mask = SSP0_CS1_MASK, 1048 .val = SSP0_CS1_MASK, 1049 }, { 1050 .reg = PAD_FUNCTION_EN_1, 1051 .mask = PWM0_AND_SSP0_CS1_REG0_MASK, 1052 .val = PWM0_AND_SSP0_CS1_REG0_MASK, 1053 }, 1054}; 1055 1056static struct spear_modemux ssp0_cs1_modemux[] = { 1057 { 1058 .muxregs = ssp0_cs1_muxreg, 1059 .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg), 1060 }, 1061}; 1062 1063static struct spear_pingroup ssp0_cs1_pingroup = { 1064 .name = "ssp0_cs1_grp", 1065 .pins = ssp0_cs1_pins, 1066 .npins = ARRAY_SIZE(ssp0_cs1_pins), 1067 .modemuxs = ssp0_cs1_modemux, 1068 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux), 1069}; 1070 1071/* pad multiplexing for ssp0_cs2 device */ 1072static const unsigned ssp0_cs2_pins[] = { 85 }; 1073static struct spear_muxreg ssp0_cs2_muxreg[] = { 1074 { 1075 .reg = PAD_SHARED_IP_EN_1, 1076 .mask = SSP0_CS2_MASK, 1077 .val = SSP0_CS2_MASK, 1078 }, { 1079 .reg = PAD_FUNCTION_EN_3, 1080 .mask = TS_AND_SSP0_CS2_REG2_MASK, 1081 .val = TS_AND_SSP0_CS2_REG2_MASK, 1082 }, 1083}; 1084 1085static struct spear_modemux ssp0_cs2_modemux[] = { 1086 { 1087 .muxregs = ssp0_cs2_muxreg, 1088 .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg), 1089 }, 1090}; 1091 1092static struct spear_pingroup ssp0_cs2_pingroup = { 1093 .name = "ssp0_cs2_grp", 1094 .pins = ssp0_cs2_pins, 1095 .npins = ARRAY_SIZE(ssp0_cs2_pins), 1096 .modemuxs = ssp0_cs2_modemux, 1097 .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux), 1098}; 1099 1100/* pad multiplexing for ssp0_cs3 device */ 1101static const unsigned ssp0_cs3_pins[] = { 132 }; 1102static struct spear_muxreg ssp0_cs3_muxreg[] = { 1103 { 1104 .reg = PAD_FUNCTION_EN_5, 1105 .mask = SSP0_CS3_REG4_MASK, 1106 .val = SSP0_CS3_REG4_MASK, 1107 }, 1108}; 1109 1110static struct spear_modemux ssp0_cs3_modemux[] = { 1111 { 1112 .muxregs = ssp0_cs3_muxreg, 1113 .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg), 1114 }, 1115}; 1116 1117static struct spear_pingroup ssp0_cs3_pingroup = { 1118 .name = "ssp0_cs3_grp", 1119 .pins = ssp0_cs3_pins, 1120 .npins = ARRAY_SIZE(ssp0_cs3_pins), 1121 .modemuxs = ssp0_cs3_modemux, 1122 .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux), 1123}; 1124 1125static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp", 1126 "ssp0_cs2_grp", "ssp0_cs3_grp" }; 1127static struct spear_function ssp0_function = { 1128 .name = "ssp0", 1129 .groups = ssp0_grps, 1130 .ngroups = ARRAY_SIZE(ssp0_grps), 1131}; 1132 1133/* pad multiplexing for uart0 device */ 1134static const unsigned uart0_pins[] = { 86, 87 }; 1135static struct spear_muxreg uart0_muxreg[] = { 1136 { 1137 .reg = PAD_FUNCTION_EN_3, 1138 .mask = UART0_REG2_MASK, 1139 .val = UART0_REG2_MASK, 1140 }, 1141}; 1142 1143static struct spear_modemux uart0_modemux[] = { 1144 { 1145 .muxregs = uart0_muxreg, 1146 .nmuxregs = ARRAY_SIZE(uart0_muxreg), 1147 }, 1148}; 1149 1150static struct spear_pingroup uart0_pingroup = { 1151 .name = "uart0_grp", 1152 .pins = uart0_pins, 1153 .npins = ARRAY_SIZE(uart0_pins), 1154 .modemuxs = uart0_modemux, 1155 .nmodemuxs = ARRAY_SIZE(uart0_modemux), 1156}; 1157 1158/* pad multiplexing for uart0_enh device */ 1159static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 }; 1160static struct spear_muxreg uart0_enh_muxreg[] = { 1161 { 1162 .reg = PAD_SHARED_IP_EN_1, 1163 .mask = GPT_MASK, 1164 .val = 0, 1165 }, { 1166 .reg = PAD_FUNCTION_EN_1, 1167 .mask = UART0_ENH_AND_GPT_REG0_MASK, 1168 .val = UART0_ENH_AND_GPT_REG0_MASK, 1169 }, 1170}; 1171 1172static struct spear_modemux uart0_enh_modemux[] = { 1173 { 1174 .muxregs = uart0_enh_muxreg, 1175 .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg), 1176 }, 1177}; 1178 1179static struct spear_pingroup uart0_enh_pingroup = { 1180 .name = "uart0_enh_grp", 1181 .pins = uart0_enh_pins, 1182 .npins = ARRAY_SIZE(uart0_enh_pins), 1183 .modemuxs = uart0_enh_modemux, 1184 .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux), 1185}; 1186 1187static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" }; 1188static struct spear_function uart0_function = { 1189 .name = "uart0", 1190 .groups = uart0_grps, 1191 .ngroups = ARRAY_SIZE(uart0_grps), 1192}; 1193 1194/* pad multiplexing for uart1 device */ 1195static const unsigned uart1_pins[] = { 88, 89 }; 1196static struct spear_muxreg uart1_muxreg[] = { 1197 { 1198 .reg = PAD_FUNCTION_EN_3, 1199 .mask = UART1_REG2_MASK, 1200 .val = UART1_REG2_MASK, 1201 }, 1202}; 1203 1204static struct spear_modemux uart1_modemux[] = { 1205 { 1206 .muxregs = uart1_muxreg, 1207 .nmuxregs = ARRAY_SIZE(uart1_muxreg), 1208 }, 1209}; 1210 1211static struct spear_pingroup uart1_pingroup = { 1212 .name = "uart1_grp", 1213 .pins = uart1_pins, 1214 .npins = ARRAY_SIZE(uart1_pins), 1215 .modemuxs = uart1_modemux, 1216 .nmodemuxs = ARRAY_SIZE(uart1_modemux), 1217}; 1218 1219static const char *const uart1_grps[] = { "uart1_grp" }; 1220static struct spear_function uart1_function = { 1221 .name = "uart1", 1222 .groups = uart1_grps, 1223 .ngroups = ARRAY_SIZE(uart1_grps), 1224}; 1225 1226/* pad multiplexing for i2s_in device */ 1227static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 }; 1228static struct spear_muxreg i2s_in_muxreg[] = { 1229 { 1230 .reg = PAD_FUNCTION_EN_3, 1231 .mask = I2S_IN_REG2_MASK, 1232 .val = I2S_IN_REG2_MASK, 1233 }, { 1234 .reg = PAD_FUNCTION_EN_4, 1235 .mask = I2S_IN_REG3_MASK, 1236 .val = I2S_IN_REG3_MASK, 1237 }, 1238}; 1239 1240static struct spear_modemux i2s_in_modemux[] = { 1241 { 1242 .muxregs = i2s_in_muxreg, 1243 .nmuxregs = ARRAY_SIZE(i2s_in_muxreg), 1244 }, 1245}; 1246 1247static struct spear_pingroup i2s_in_pingroup = { 1248 .name = "i2s_in_grp", 1249 .pins = i2s_in_pins, 1250 .npins = ARRAY_SIZE(i2s_in_pins), 1251 .modemuxs = i2s_in_modemux, 1252 .nmodemuxs = ARRAY_SIZE(i2s_in_modemux), 1253}; 1254 1255/* pad multiplexing for i2s_out device */ 1256static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 }; 1257static struct spear_muxreg i2s_out_muxreg[] = { 1258 { 1259 .reg = PAD_FUNCTION_EN_4, 1260 .mask = I2S_OUT_REG3_MASK, 1261 .val = I2S_OUT_REG3_MASK, 1262 }, 1263}; 1264 1265static struct spear_modemux i2s_out_modemux[] = { 1266 { 1267 .muxregs = i2s_out_muxreg, 1268 .nmuxregs = ARRAY_SIZE(i2s_out_muxreg), 1269 }, 1270}; 1271 1272static struct spear_pingroup i2s_out_pingroup = { 1273 .name = "i2s_out_grp", 1274 .pins = i2s_out_pins, 1275 .npins = ARRAY_SIZE(i2s_out_pins), 1276 .modemuxs = i2s_out_modemux, 1277 .nmodemuxs = ARRAY_SIZE(i2s_out_modemux), 1278}; 1279 1280static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" }; 1281static struct spear_function i2s_function = { 1282 .name = "i2s", 1283 .groups = i2s_grps, 1284 .ngroups = ARRAY_SIZE(i2s_grps), 1285}; 1286 1287/* pad multiplexing for gmac device */ 1288static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111, 1289 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 1290 126, 127, 128, 129, 130, 131 }; 1291#define GMAC_MUXREG \ 1292 { \ 1293 .reg = PAD_FUNCTION_EN_4, \ 1294 .mask = GMAC_REG3_MASK, \ 1295 .val = GMAC_REG3_MASK, \ 1296 }, { \ 1297 .reg = PAD_FUNCTION_EN_5, \ 1298 .mask = GMAC_REG4_MASK, \ 1299 .val = GMAC_REG4_MASK, \ 1300 } 1301 1302/* pad multiplexing for gmii device */ 1303static struct spear_muxreg gmii_muxreg[] = { 1304 GMAC_MUXREG, 1305 { 1306 .reg = GMAC_CLK_CFG, 1307 .mask = GMAC_PHY_IF_SEL_MASK, 1308 .val = GMAC_PHY_IF_GMII_VAL, 1309 }, 1310}; 1311 1312static struct spear_modemux gmii_modemux[] = { 1313 { 1314 .muxregs = gmii_muxreg, 1315 .nmuxregs = ARRAY_SIZE(gmii_muxreg), 1316 }, 1317}; 1318 1319static struct spear_pingroup gmii_pingroup = { 1320 .name = "gmii_grp", 1321 .pins = gmac_pins, 1322 .npins = ARRAY_SIZE(gmac_pins), 1323 .modemuxs = gmii_modemux, 1324 .nmodemuxs = ARRAY_SIZE(gmii_modemux), 1325}; 1326 1327/* pad multiplexing for rgmii device */ 1328static struct spear_muxreg rgmii_muxreg[] = { 1329 GMAC_MUXREG, 1330 { 1331 .reg = GMAC_CLK_CFG, 1332 .mask = GMAC_PHY_IF_SEL_MASK, 1333 .val = GMAC_PHY_IF_RGMII_VAL, 1334 }, 1335}; 1336 1337static struct spear_modemux rgmii_modemux[] = { 1338 { 1339 .muxregs = rgmii_muxreg, 1340 .nmuxregs = ARRAY_SIZE(rgmii_muxreg), 1341 }, 1342}; 1343 1344static struct spear_pingroup rgmii_pingroup = { 1345 .name = "rgmii_grp", 1346 .pins = gmac_pins, 1347 .npins = ARRAY_SIZE(gmac_pins), 1348 .modemuxs = rgmii_modemux, 1349 .nmodemuxs = ARRAY_SIZE(rgmii_modemux), 1350}; 1351 1352/* pad multiplexing for rmii device */ 1353static struct spear_muxreg rmii_muxreg[] = { 1354 GMAC_MUXREG, 1355 { 1356 .reg = GMAC_CLK_CFG, 1357 .mask = GMAC_PHY_IF_SEL_MASK, 1358 .val = GMAC_PHY_IF_RMII_VAL, 1359 }, 1360}; 1361 1362static struct spear_modemux rmii_modemux[] = { 1363 { 1364 .muxregs = rmii_muxreg, 1365 .nmuxregs = ARRAY_SIZE(rmii_muxreg), 1366 }, 1367}; 1368 1369static struct spear_pingroup rmii_pingroup = { 1370 .name = "rmii_grp", 1371 .pins = gmac_pins, 1372 .npins = ARRAY_SIZE(gmac_pins), 1373 .modemuxs = rmii_modemux, 1374 .nmodemuxs = ARRAY_SIZE(rmii_modemux), 1375}; 1376 1377/* pad multiplexing for sgmii device */ 1378static struct spear_muxreg sgmii_muxreg[] = { 1379 GMAC_MUXREG, 1380 { 1381 .reg = GMAC_CLK_CFG, 1382 .mask = GMAC_PHY_IF_SEL_MASK, 1383 .val = GMAC_PHY_IF_SGMII_VAL, 1384 }, 1385}; 1386 1387static struct spear_modemux sgmii_modemux[] = { 1388 { 1389 .muxregs = sgmii_muxreg, 1390 .nmuxregs = ARRAY_SIZE(sgmii_muxreg), 1391 }, 1392}; 1393 1394static struct spear_pingroup sgmii_pingroup = { 1395 .name = "sgmii_grp", 1396 .pins = gmac_pins, 1397 .npins = ARRAY_SIZE(gmac_pins), 1398 .modemuxs = sgmii_modemux, 1399 .nmodemuxs = ARRAY_SIZE(sgmii_modemux), 1400}; 1401 1402static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp", 1403 "sgmii_grp" }; 1404static struct spear_function gmac_function = { 1405 .name = "gmac", 1406 .groups = gmac_grps, 1407 .ngroups = ARRAY_SIZE(gmac_grps), 1408}; 1409 1410/* pad multiplexing for i2c0 device */ 1411static const unsigned i2c0_pins[] = { 133, 134 }; 1412static struct spear_muxreg i2c0_muxreg[] = { 1413 { 1414 .reg = PAD_FUNCTION_EN_5, 1415 .mask = I2C0_REG4_MASK, 1416 .val = I2C0_REG4_MASK, 1417 }, 1418}; 1419 1420static struct spear_modemux i2c0_modemux[] = { 1421 { 1422 .muxregs = i2c0_muxreg, 1423 .nmuxregs = ARRAY_SIZE(i2c0_muxreg), 1424 }, 1425}; 1426 1427static struct spear_pingroup i2c0_pingroup = { 1428 .name = "i2c0_grp", 1429 .pins = i2c0_pins, 1430 .npins = ARRAY_SIZE(i2c0_pins), 1431 .modemuxs = i2c0_modemux, 1432 .nmodemuxs = ARRAY_SIZE(i2c0_modemux), 1433}; 1434 1435static const char *const i2c0_grps[] = { "i2c0_grp" }; 1436static struct spear_function i2c0_function = { 1437 .name = "i2c0", 1438 .groups = i2c0_grps, 1439 .ngroups = ARRAY_SIZE(i2c0_grps), 1440}; 1441 1442/* pad multiplexing for i2c1 device */ 1443static const unsigned i2c1_pins[] = { 18, 23 }; 1444static struct spear_muxreg i2c1_muxreg[] = { 1445 { 1446 .reg = PAD_FUNCTION_EN_1, 1447 .mask = I2C1_REG0_MASK, 1448 .val = I2C1_REG0_MASK, 1449 }, 1450}; 1451 1452static struct spear_modemux i2c1_modemux[] = { 1453 { 1454 .muxregs = i2c1_muxreg, 1455 .nmuxregs = ARRAY_SIZE(i2c1_muxreg), 1456 }, 1457}; 1458 1459static struct spear_pingroup i2c1_pingroup = { 1460 .name = "i2c1_grp", 1461 .pins = i2c1_pins, 1462 .npins = ARRAY_SIZE(i2c1_pins), 1463 .modemuxs = i2c1_modemux, 1464 .nmodemuxs = ARRAY_SIZE(i2c1_modemux), 1465}; 1466 1467static const char *const i2c1_grps[] = { "i2c1_grp" }; 1468static struct spear_function i2c1_function = { 1469 .name = "i2c1", 1470 .groups = i2c1_grps, 1471 .ngroups = ARRAY_SIZE(i2c1_grps), 1472}; 1473 1474/* pad multiplexing for cec0 device */ 1475static const unsigned cec0_pins[] = { 135 }; 1476static struct spear_muxreg cec0_muxreg[] = { 1477 { 1478 .reg = PAD_FUNCTION_EN_5, 1479 .mask = CEC0_REG4_MASK, 1480 .val = CEC0_REG4_MASK, 1481 }, 1482}; 1483 1484static struct spear_modemux cec0_modemux[] = { 1485 { 1486 .muxregs = cec0_muxreg, 1487 .nmuxregs = ARRAY_SIZE(cec0_muxreg), 1488 }, 1489}; 1490 1491static struct spear_pingroup cec0_pingroup = { 1492 .name = "cec0_grp", 1493 .pins = cec0_pins, 1494 .npins = ARRAY_SIZE(cec0_pins), 1495 .modemuxs = cec0_modemux, 1496 .nmodemuxs = ARRAY_SIZE(cec0_modemux), 1497}; 1498 1499static const char *const cec0_grps[] = { "cec0_grp" }; 1500static struct spear_function cec0_function = { 1501 .name = "cec0", 1502 .groups = cec0_grps, 1503 .ngroups = ARRAY_SIZE(cec0_grps), 1504}; 1505 1506/* pad multiplexing for cec1 device */ 1507static const unsigned cec1_pins[] = { 136 }; 1508static struct spear_muxreg cec1_muxreg[] = { 1509 { 1510 .reg = PAD_FUNCTION_EN_5, 1511 .mask = CEC1_REG4_MASK, 1512 .val = CEC1_REG4_MASK, 1513 }, 1514}; 1515 1516static struct spear_modemux cec1_modemux[] = { 1517 { 1518 .muxregs = cec1_muxreg, 1519 .nmuxregs = ARRAY_SIZE(cec1_muxreg), 1520 }, 1521}; 1522 1523static struct spear_pingroup cec1_pingroup = { 1524 .name = "cec1_grp", 1525 .pins = cec1_pins, 1526 .npins = ARRAY_SIZE(cec1_pins), 1527 .modemuxs = cec1_modemux, 1528 .nmodemuxs = ARRAY_SIZE(cec1_modemux), 1529}; 1530 1531static const char *const cec1_grps[] = { "cec1_grp" }; 1532static struct spear_function cec1_function = { 1533 .name = "cec1", 1534 .groups = cec1_grps, 1535 .ngroups = ARRAY_SIZE(cec1_grps), 1536}; 1537 1538/* pad multiplexing for mcif devices */ 1539static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200, 1540 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 1541 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 1542 229, 230, 231, 232, 237 }; 1543#define MCIF_MUXREG \ 1544 { \ 1545 .reg = PAD_SHARED_IP_EN_1, \ 1546 .mask = MCIF_MASK, \ 1547 .val = MCIF_MASK, \ 1548 }, { \ 1549 .reg = PAD_FUNCTION_EN_7, \ 1550 .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ 1551 .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ 1552 }, { \ 1553 .reg = PAD_FUNCTION_EN_8, \ 1554 .mask = MCIF_REG7_MASK, \ 1555 .val = MCIF_REG7_MASK, \ 1556 } 1557 1558/* Pad multiplexing for sdhci device */ 1559static struct spear_muxreg sdhci_muxreg[] = { 1560 MCIF_MUXREG, 1561 { 1562 .reg = PERIP_CFG, 1563 .mask = MCIF_SEL_MASK, 1564 .val = MCIF_SEL_SD, 1565 }, 1566}; 1567 1568static struct spear_modemux sdhci_modemux[] = { 1569 { 1570 .muxregs = sdhci_muxreg, 1571 .nmuxregs = ARRAY_SIZE(sdhci_muxreg), 1572 }, 1573}; 1574 1575static struct spear_pingroup sdhci_pingroup = { 1576 .name = "sdhci_grp", 1577 .pins = mcif_pins, 1578 .npins = ARRAY_SIZE(mcif_pins), 1579 .modemuxs = sdhci_modemux, 1580 .nmodemuxs = ARRAY_SIZE(sdhci_modemux), 1581}; 1582 1583static const char *const sdhci_grps[] = { "sdhci_grp" }; 1584static struct spear_function sdhci_function = { 1585 .name = "sdhci", 1586 .groups = sdhci_grps, 1587 .ngroups = ARRAY_SIZE(sdhci_grps), 1588}; 1589 1590/* Pad multiplexing for cf device */ 1591static struct spear_muxreg cf_muxreg[] = { 1592 MCIF_MUXREG, 1593 { 1594 .reg = PERIP_CFG, 1595 .mask = MCIF_SEL_MASK, 1596 .val = MCIF_SEL_CF, 1597 }, 1598}; 1599 1600static struct spear_modemux cf_modemux[] = { 1601 { 1602 .muxregs = cf_muxreg, 1603 .nmuxregs = ARRAY_SIZE(cf_muxreg), 1604 }, 1605}; 1606 1607static struct spear_pingroup cf_pingroup = { 1608 .name = "cf_grp", 1609 .pins = mcif_pins, 1610 .npins = ARRAY_SIZE(mcif_pins), 1611 .modemuxs = cf_modemux, 1612 .nmodemuxs = ARRAY_SIZE(cf_modemux), 1613}; 1614 1615static const char *const cf_grps[] = { "cf_grp" }; 1616static struct spear_function cf_function = { 1617 .name = "cf", 1618 .groups = cf_grps, 1619 .ngroups = ARRAY_SIZE(cf_grps), 1620}; 1621 1622/* Pad multiplexing for xd device */ 1623static struct spear_muxreg xd_muxreg[] = { 1624 MCIF_MUXREG, 1625 { 1626 .reg = PERIP_CFG, 1627 .mask = MCIF_SEL_MASK, 1628 .val = MCIF_SEL_XD, 1629 }, 1630}; 1631 1632static struct spear_modemux xd_modemux[] = { 1633 { 1634 .muxregs = xd_muxreg, 1635 .nmuxregs = ARRAY_SIZE(xd_muxreg), 1636 }, 1637}; 1638 1639static struct spear_pingroup xd_pingroup = { 1640 .name = "xd_grp", 1641 .pins = mcif_pins, 1642 .npins = ARRAY_SIZE(mcif_pins), 1643 .modemuxs = xd_modemux, 1644 .nmodemuxs = ARRAY_SIZE(xd_modemux), 1645}; 1646 1647static const char *const xd_grps[] = { "xd_grp" }; 1648static struct spear_function xd_function = { 1649 .name = "xd", 1650 .groups = xd_grps, 1651 .ngroups = ARRAY_SIZE(xd_grps), 1652}; 1653 1654/* pad multiplexing for clcd device */ 1655static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145, 1656 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 1657 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 1658 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 1659 188, 189, 190, 191 }; 1660static struct spear_muxreg clcd_muxreg[] = { 1661 { 1662 .reg = PAD_SHARED_IP_EN_1, 1663 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, 1664 .val = 0, 1665 }, { 1666 .reg = PAD_FUNCTION_EN_5, 1667 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, 1668 .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, 1669 }, { 1670 .reg = PAD_FUNCTION_EN_6, 1671 .mask = CLCD_AND_ARM_TRACE_REG5_MASK, 1672 .val = CLCD_AND_ARM_TRACE_REG5_MASK, 1673 }, { 1674 .reg = PAD_FUNCTION_EN_7, 1675 .mask = CLCD_AND_ARM_TRACE_REG6_MASK, 1676 .val = CLCD_AND_ARM_TRACE_REG6_MASK, 1677 }, 1678}; 1679 1680static struct spear_modemux clcd_modemux[] = { 1681 { 1682 .muxregs = clcd_muxreg, 1683 .nmuxregs = ARRAY_SIZE(clcd_muxreg), 1684 }, 1685}; 1686 1687static struct spear_pingroup clcd_pingroup = { 1688 .name = "clcd_grp", 1689 .pins = clcd_pins, 1690 .npins = ARRAY_SIZE(clcd_pins), 1691 .modemuxs = clcd_modemux, 1692 .nmodemuxs = ARRAY_SIZE(clcd_modemux), 1693}; 1694 1695/* Disable cld runtime to save panel damage */ 1696static struct spear_muxreg clcd_sleep_muxreg[] = { 1697 { 1698 .reg = PAD_SHARED_IP_EN_1, 1699 .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, 1700 .val = 0, 1701 }, { 1702 .reg = PAD_FUNCTION_EN_5, 1703 .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, 1704 .val = 0x0, 1705 }, { 1706 .reg = PAD_FUNCTION_EN_6, 1707 .mask = CLCD_AND_ARM_TRACE_REG5_MASK, 1708 .val = 0x0, 1709 }, { 1710 .reg = PAD_FUNCTION_EN_7, 1711 .mask = CLCD_AND_ARM_TRACE_REG6_MASK, 1712 .val = 0x0, 1713 }, 1714}; 1715 1716static struct spear_modemux clcd_sleep_modemux[] = { 1717 { 1718 .muxregs = clcd_sleep_muxreg, 1719 .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg), 1720 }, 1721}; 1722 1723static struct spear_pingroup clcd_sleep_pingroup = { 1724 .name = "clcd_sleep_grp", 1725 .pins = clcd_pins, 1726 .npins = ARRAY_SIZE(clcd_pins), 1727 .modemuxs = clcd_sleep_modemux, 1728 .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux), 1729}; 1730 1731static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" }; 1732static struct spear_function clcd_function = { 1733 .name = "clcd", 1734 .groups = clcd_grps, 1735 .ngroups = ARRAY_SIZE(clcd_grps), 1736}; 1737 1738/* pad multiplexing for arm_trace device */ 1739static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164, 1740 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 1741 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 1742 193, 194, 195, 196, 197, 198, 199, 200 }; 1743static struct spear_muxreg arm_trace_muxreg[] = { 1744 { 1745 .reg = PAD_SHARED_IP_EN_1, 1746 .mask = ARM_TRACE_MASK, 1747 .val = ARM_TRACE_MASK, 1748 }, { 1749 .reg = PAD_FUNCTION_EN_5, 1750 .mask = CLCD_AND_ARM_TRACE_REG4_MASK, 1751 .val = CLCD_AND_ARM_TRACE_REG4_MASK, 1752 }, { 1753 .reg = PAD_FUNCTION_EN_6, 1754 .mask = CLCD_AND_ARM_TRACE_REG5_MASK, 1755 .val = CLCD_AND_ARM_TRACE_REG5_MASK, 1756 }, { 1757 .reg = PAD_FUNCTION_EN_7, 1758 .mask = CLCD_AND_ARM_TRACE_REG6_MASK, 1759 .val = CLCD_AND_ARM_TRACE_REG6_MASK, 1760 }, 1761}; 1762 1763static struct spear_modemux arm_trace_modemux[] = { 1764 { 1765 .muxregs = arm_trace_muxreg, 1766 .nmuxregs = ARRAY_SIZE(arm_trace_muxreg), 1767 }, 1768}; 1769 1770static struct spear_pingroup arm_trace_pingroup = { 1771 .name = "arm_trace_grp", 1772 .pins = arm_trace_pins, 1773 .npins = ARRAY_SIZE(arm_trace_pins), 1774 .modemuxs = arm_trace_modemux, 1775 .nmodemuxs = ARRAY_SIZE(arm_trace_modemux), 1776}; 1777 1778static const char *const arm_trace_grps[] = { "arm_trace_grp" }; 1779static struct spear_function arm_trace_function = { 1780 .name = "arm_trace", 1781 .groups = arm_trace_grps, 1782 .ngroups = ARRAY_SIZE(arm_trace_grps), 1783}; 1784 1785/* pad multiplexing for miphy_dbg device */ 1786static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 1787 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 1788 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 }; 1789static struct spear_muxreg miphy_dbg_muxreg[] = { 1790 { 1791 .reg = PAD_SHARED_IP_EN_1, 1792 .mask = MIPHY_DBG_MASK, 1793 .val = MIPHY_DBG_MASK, 1794 }, { 1795 .reg = PAD_FUNCTION_EN_5, 1796 .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, 1797 .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, 1798 }, 1799}; 1800 1801static struct spear_modemux miphy_dbg_modemux[] = { 1802 { 1803 .muxregs = miphy_dbg_muxreg, 1804 .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg), 1805 }, 1806}; 1807 1808static struct spear_pingroup miphy_dbg_pingroup = { 1809 .name = "miphy_dbg_grp", 1810 .pins = miphy_dbg_pins, 1811 .npins = ARRAY_SIZE(miphy_dbg_pins), 1812 .modemuxs = miphy_dbg_modemux, 1813 .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux), 1814}; 1815 1816static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" }; 1817static struct spear_function miphy_dbg_function = { 1818 .name = "miphy_dbg", 1819 .groups = miphy_dbg_grps, 1820 .ngroups = ARRAY_SIZE(miphy_dbg_grps), 1821}; 1822 1823/* pad multiplexing for pcie device */ 1824static const unsigned pcie_pins[] = { 250 }; 1825static struct spear_muxreg pcie_muxreg[] = { 1826 { 1827 .reg = PCIE_SATA_CFG, 1828 .mask = SATA_PCIE_CFG_MASK, 1829 .val = PCIE_CFG_VAL, 1830 }, 1831}; 1832 1833static struct spear_modemux pcie_modemux[] = { 1834 { 1835 .muxregs = pcie_muxreg, 1836 .nmuxregs = ARRAY_SIZE(pcie_muxreg), 1837 }, 1838}; 1839 1840static struct spear_pingroup pcie_pingroup = { 1841 .name = "pcie_grp", 1842 .pins = pcie_pins, 1843 .npins = ARRAY_SIZE(pcie_pins), 1844 .modemuxs = pcie_modemux, 1845 .nmodemuxs = ARRAY_SIZE(pcie_modemux), 1846}; 1847 1848static const char *const pcie_grps[] = { "pcie_grp" }; 1849static struct spear_function pcie_function = { 1850 .name = "pcie", 1851 .groups = pcie_grps, 1852 .ngroups = ARRAY_SIZE(pcie_grps), 1853}; 1854 1855/* pad multiplexing for sata device */ 1856static const unsigned sata_pins[] = { 250 }; 1857static struct spear_muxreg sata_muxreg[] = { 1858 { 1859 .reg = PCIE_SATA_CFG, 1860 .mask = SATA_PCIE_CFG_MASK, 1861 .val = SATA_CFG_VAL, 1862 }, 1863}; 1864 1865static struct spear_modemux sata_modemux[] = { 1866 { 1867 .muxregs = sata_muxreg, 1868 .nmuxregs = ARRAY_SIZE(sata_muxreg), 1869 }, 1870}; 1871 1872static struct spear_pingroup sata_pingroup = { 1873 .name = "sata_grp", 1874 .pins = sata_pins, 1875 .npins = ARRAY_SIZE(sata_pins), 1876 .modemuxs = sata_modemux, 1877 .nmodemuxs = ARRAY_SIZE(sata_modemux), 1878}; 1879 1880static const char *const sata_grps[] = { "sata_grp" }; 1881static struct spear_function sata_function = { 1882 .name = "sata", 1883 .groups = sata_grps, 1884 .ngroups = ARRAY_SIZE(sata_grps), 1885}; 1886 1887/* pingroups */ 1888static struct spear_pingroup *spear1340_pingroups[] = { 1889 &pads_as_gpio_pingroup, 1890 &fsmc_8bit_pingroup, 1891 &fsmc_16bit_pingroup, 1892 &fsmc_pnor_pingroup, 1893 &keyboard_row_col_pingroup, 1894 &keyboard_col5_pingroup, 1895 &spdif_in_pingroup, 1896 &spdif_out_pingroup, 1897 &gpt_0_1_pingroup, 1898 &pwm0_pingroup, 1899 &pwm1_pingroup, 1900 &pwm2_pingroup, 1901 &pwm3_pingroup, 1902 &vip_mux_pingroup, 1903 &vip_mux_cam0_pingroup, 1904 &vip_mux_cam1_pingroup, 1905 &vip_mux_cam2_pingroup, 1906 &vip_mux_cam3_pingroup, 1907 &cam0_pingroup, 1908 &cam1_pingroup, 1909 &cam2_pingroup, 1910 &cam3_pingroup, 1911 &smi_pingroup, 1912 &ssp0_pingroup, 1913 &ssp0_cs1_pingroup, 1914 &ssp0_cs2_pingroup, 1915 &ssp0_cs3_pingroup, 1916 &uart0_pingroup, 1917 &uart0_enh_pingroup, 1918 &uart1_pingroup, 1919 &i2s_in_pingroup, 1920 &i2s_out_pingroup, 1921 &gmii_pingroup, 1922 &rgmii_pingroup, 1923 &rmii_pingroup, 1924 &sgmii_pingroup, 1925 &i2c0_pingroup, 1926 &i2c1_pingroup, 1927 &cec0_pingroup, 1928 &cec1_pingroup, 1929 &sdhci_pingroup, 1930 &cf_pingroup, 1931 &xd_pingroup, 1932 &clcd_sleep_pingroup, 1933 &clcd_pingroup, 1934 &arm_trace_pingroup, 1935 &miphy_dbg_pingroup, 1936 &pcie_pingroup, 1937 &sata_pingroup, 1938}; 1939 1940/* functions */ 1941static struct spear_function *spear1340_functions[] = { 1942 &pads_as_gpio_function, 1943 &fsmc_function, 1944 &keyboard_function, 1945 &spdif_in_function, 1946 &spdif_out_function, 1947 &gpt_0_1_function, 1948 &pwm_function, 1949 &vip_function, 1950 &cam0_function, 1951 &cam1_function, 1952 &cam2_function, 1953 &cam3_function, 1954 &smi_function, 1955 &ssp0_function, 1956 &uart0_function, 1957 &uart1_function, 1958 &i2s_function, 1959 &gmac_function, 1960 &i2c0_function, 1961 &i2c1_function, 1962 &cec0_function, 1963 &cec1_function, 1964 &sdhci_function, 1965 &cf_function, 1966 &xd_function, 1967 &clcd_function, 1968 &arm_trace_function, 1969 &miphy_dbg_function, 1970 &pcie_function, 1971 &sata_function, 1972}; 1973 1974static void gpio_request_endisable(struct spear_pmx *pmx, int pin, 1975 bool enable) 1976{ 1977 unsigned int regoffset, regindex, bitoffset; 1978 unsigned int val; 1979 1980 /* pin++ as gpio configuration starts from 2nd bit of base register */ 1981 pin++; 1982 1983 regindex = pin / 32; 1984 bitoffset = pin % 32; 1985 1986 if (regindex <= 3) 1987 regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *); 1988 else 1989 regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *); 1990 1991 val = pmx_readl(pmx, regoffset); 1992 if (enable) 1993 val &= ~(0x1 << bitoffset); 1994 else 1995 val |= 0x1 << bitoffset; 1996 1997 pmx_writel(pmx, val, regoffset); 1998} 1999 2000static struct spear_pinctrl_machdata spear1340_machdata = { 2001 .pins = spear1340_pins, 2002 .npins = ARRAY_SIZE(spear1340_pins), 2003 .groups = spear1340_pingroups, 2004 .ngroups = ARRAY_SIZE(spear1340_pingroups), 2005 .functions = spear1340_functions, 2006 .nfunctions = ARRAY_SIZE(spear1340_functions), 2007 .gpio_request_endisable = gpio_request_endisable, 2008 .modes_supported = false, 2009}; 2010 2011static const struct of_device_id spear1340_pinctrl_of_match[] = { 2012 { 2013 .compatible = "st,spear1340-pinmux", 2014 }, 2015 {}, 2016}; 2017 2018static int spear1340_pinctrl_probe(struct platform_device *pdev) 2019{ 2020 return spear_pinctrl_probe(pdev, &spear1340_machdata); 2021} 2022 2023static int spear1340_pinctrl_remove(struct platform_device *pdev) 2024{ 2025 return spear_pinctrl_remove(pdev); 2026} 2027 2028static struct platform_driver spear1340_pinctrl_driver = { 2029 .driver = { 2030 .name = DRIVER_NAME, 2031 .of_match_table = spear1340_pinctrl_of_match, 2032 }, 2033 .probe = spear1340_pinctrl_probe, 2034 .remove = spear1340_pinctrl_remove, 2035}; 2036 2037static int __init spear1340_pinctrl_init(void) 2038{ 2039 return platform_driver_register(&spear1340_pinctrl_driver); 2040} 2041arch_initcall(spear1340_pinctrl_init); 2042 2043static void __exit spear1340_pinctrl_exit(void) 2044{ 2045 platform_driver_unregister(&spear1340_pinctrl_driver); 2046} 2047module_exit(spear1340_pinctrl_exit); 2048 2049MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); 2050MODULE_DESCRIPTION("ST Microelectronics SPEAr1340 pinctrl driver"); 2051MODULE_LICENSE("GPL v2"); 2052MODULE_DEVICE_TABLE(of, spear1340_pinctrl_of_match); 2053