39 	u32 mask = d->mask;  in irq_gc_mask_disable_reg()  local
42 	irq_reg_writel(gc, mask, ct->regs.disable);  in irq_gc_mask_disable_reg()
43 	*ct->mask_cache &= ~mask;  in irq_gc_mask_disable_reg()
58 	u32 mask = d->mask;  in irq_gc_mask_set_bit()  local
61 	*ct->mask_cache |= mask;  in irq_gc_mask_set_bit()
62 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_set_bit()
78 	u32 mask = d->mask;  in irq_gc_mask_clr_bit()  local
81 	*ct->mask_cache &= ~mask;  in irq_gc_mask_clr_bit()
82 	irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);  in irq_gc_mask_clr_bit()
98 	u32 mask = d->mask;  in irq_gc_unmask_enable_reg()  local
101 	irq_reg_writel(gc, mask, ct->regs.enable);  in irq_gc_unmask_enable_reg()
102 	*ct->mask_cache |= mask;  in irq_gc_unmask_enable_reg()
114 	u32 mask = d->mask;  in irq_gc_ack_set_bit()  local
117 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_set_bit()
130 	u32 mask = ~d->mask;  in irq_gc_ack_clr_bit()  local
133 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_ack_clr_bit()
145 	u32 mask = d->mask;  in irq_gc_mask_disable_reg_and_ack()  local
148 	irq_reg_writel(gc, mask, ct->regs.mask);  in irq_gc_mask_disable_reg_and_ack()
149 	irq_reg_writel(gc, mask, ct->regs.ack);  in irq_gc_mask_disable_reg_and_ack()
161 	u32 mask = d->mask;  in irq_gc_eoi()  local
164 	irq_reg_writel(gc, mask, ct->regs.eoi);  in irq_gc_eoi()
180 	u32 mask = d->mask;  in irq_gc_set_wake()  local
182 	if (!(mask & gc->wake_enabled))  in irq_gc_set_wake()
187 		gc->wake_active |= mask;  in irq_gc_set_wake()
189 		gc->wake_active &= ~mask;  in irq_gc_set_wake()
248 	u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;  in irq_gc_init_mask_cache()
254 			mskreg = ct[i].regs.mask;  in irq_gc_init_mask_cache()
406 		data->mask = 1 << idx;  in irq_map_generic_chip()
459 				d->mask = 1 << (i - gc->irq_base);  in irq_setup_generic_chip()