235 	u16 mask;  in vr41xx_set_irq_trigger()  local
238 		mask = 1 << pin;  in vr41xx_set_irq_trigger()
240 			giu_set(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
242 				giu_set(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
244 				giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
248 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
249 					giu_clear(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
252 					giu_clear(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
253 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
256 					giu_set(GIUFEDGEINHL, mask);  in vr41xx_set_irq_trigger()
257 					giu_set(GIUREDGEINHL, mask);  in vr41xx_set_irq_trigger()
265 			giu_clear(GIUINTTYPL, mask);  in vr41xx_set_irq_trigger()
266 			giu_clear(GIUINTHTSELL, mask);  in vr41xx_set_irq_trigger()
271 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_trigger()
273 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_trigger()
275 			giu_set(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
277 				giu_set(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
279 				giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
283 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
284 					giu_clear(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
287 					giu_clear(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
288 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
291 					giu_set(GIUFEDGEINHH, mask);  in vr41xx_set_irq_trigger()
292 					giu_set(GIUREDGEINHH, mask);  in vr41xx_set_irq_trigger()
300 			giu_clear(GIUINTTYPH, mask);  in vr41xx_set_irq_trigger()
301 			giu_clear(GIUINTHTSELH, mask);  in vr41xx_set_irq_trigger()
306 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_trigger()
313 	u16 mask;  in vr41xx_set_irq_level()  local
316 		mask = 1 << pin;  in vr41xx_set_irq_level()
318 			giu_set(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
320 			giu_clear(GIUINTALSELL, mask);  in vr41xx_set_irq_level()
321 		giu_write(GIUINTSTATL, mask);  in vr41xx_set_irq_level()
323 		mask = 1 << (pin - GIUINT_HIGH_OFFSET);  in vr41xx_set_irq_level()
325 			giu_set(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
327 			giu_clear(GIUINTALSELH, mask);  in vr41xx_set_irq_level()
328 		giu_write(GIUINTSTATH, mask);  in vr41xx_set_irq_level()
335 	u16 offset, mask, reg;  in giu_set_direction()  local
343 		mask = 1 << pin;  in giu_set_direction()
346 		mask = 1 << (pin - 16);  in giu_set_direction()
350 			mask = 1 << (pin - 32);  in giu_set_direction()
355 				mask = PIOEN0;  in giu_set_direction()
359 				mask = PIOEN1;  in giu_set_direction()
371 		reg |= mask;  in giu_set_direction()
373 		reg &= ~mask;  in giu_set_direction()
383 	u16 reg, mask;  in vr41xx_gpio_pullupdown()  local
392 	mask = 1 << pin;  in vr41xx_gpio_pullupdown()
399 			reg |= mask;  in vr41xx_gpio_pullupdown()
401 			reg &= ~mask;  in vr41xx_gpio_pullupdown()
405 		reg |= mask;  in vr41xx_gpio_pullupdown()
409 		reg &= ~mask;  in vr41xx_gpio_pullupdown()
421 	u16 reg, mask;  in vr41xx_gpio_get()  local
428 		mask = 1 << pin;  in vr41xx_gpio_get()
431 		mask = 1 << (pin - 16);  in vr41xx_gpio_get()
434 		mask = 1 << (pin - 32);  in vr41xx_gpio_get()
437 		mask = 1 << (pin - 48);  in vr41xx_gpio_get()
440 	if (reg & mask)  in vr41xx_gpio_get()
449 	u16 offset, mask, reg;  in vr41xx_gpio_set()  local
457 		mask = 1 << pin;  in vr41xx_gpio_set()
460 		mask = 1 << (pin - 16);  in vr41xx_gpio_set()
463 		mask = 1 << (pin - 32);  in vr41xx_gpio_set()
466 		mask = 1 << (pin - 48);  in vr41xx_gpio_set()
473 		reg |= mask;  in vr41xx_gpio_set()
475 		reg &= ~mask;  in vr41xx_gpio_set()