38 		.mask	= IPIC_SIMSR_H,
45 		.mask	= IPIC_SIMSR_H,
52 		.mask	= IPIC_SIMSR_H,
59 		.mask	= IPIC_SIMSR_H,
66 		.mask	= IPIC_SIMSR_H,
73 		.mask	= IPIC_SIMSR_H,
80 		.mask	= IPIC_SIMSR_H,
87 		.mask	= IPIC_SIMSR_H,
94 		.mask	= IPIC_SIMSR_H,
101 		.mask	= IPIC_SIMSR_H,
108 		.mask	= IPIC_SIMSR_H,
115 		.mask	= IPIC_SIMSR_H,
122 		.mask	= IPIC_SIMSR_H,
129 		.mask	= IPIC_SIMSR_H,
136 		.mask	= IPIC_SIMSR_H,
143 		.mask	= IPIC_SIMSR_H,
151 		.mask	= IPIC_SEMSR,
159 		.mask	= IPIC_SEMSR,
167 		.mask	= IPIC_SEMSR,
175 		.mask	= IPIC_SEMSR,
183 		.mask	= IPIC_SEMSR,
191 		.mask	= IPIC_SEMSR,
199 		.mask	= IPIC_SEMSR,
206 		.mask	= IPIC_SIMSR_H,
213 		.mask	= IPIC_SIMSR_H,
220 		.mask	= IPIC_SIMSR_H,
227 		.mask	= IPIC_SIMSR_H,
234 		.mask	= IPIC_SIMSR_H,
241 		.mask	= IPIC_SIMSR_H,
248 		.mask	= IPIC_SIMSR_H,
255 		.mask	= IPIC_SIMSR_H,
262 		.mask	= IPIC_SIMSR_H,
269 		.mask	= IPIC_SIMSR_H,
276 		.mask	= IPIC_SIMSR_H,
283 		.mask	= IPIC_SIMSR_H,
290 		.mask	= IPIC_SIMSR_H,
297 		.mask	= IPIC_SIMSR_H,
304 		.mask	= IPIC_SIMSR_H,
311 		.mask	= IPIC_SIMSR_H,
318 		.mask	= IPIC_SEMSR,
325 		.mask	= IPIC_SIMSR_L,
332 		.mask	= IPIC_SIMSR_L,
339 		.mask	= IPIC_SIMSR_L,
346 		.mask	= IPIC_SIMSR_L,
353 		.mask	= IPIC_SIMSR_L,
360 		.mask	= IPIC_SIMSR_L,
367 		.mask	= IPIC_SIMSR_L,
374 		.mask	= IPIC_SIMSR_L,
381 		.mask	= IPIC_SIMSR_L,
387 		.mask	= IPIC_SIMSR_L,
393 		.mask	= IPIC_SIMSR_L,
399 		.mask	= IPIC_SIMSR_L,
405 		.mask	= IPIC_SIMSR_L,
411 		.mask	= IPIC_SIMSR_L,
417 		.mask	= IPIC_SIMSR_L,
423 		.mask	= IPIC_SIMSR_L,
429 		.mask	= IPIC_SIMSR_L,
435 		.mask	= IPIC_SIMSR_L,
441 		.mask	= IPIC_SIMSR_L,
447 		.mask	= IPIC_SIMSR_L,
453 		.mask	= IPIC_SIMSR_L,
459 		.mask	= IPIC_SIMSR_L,
465 		.mask	= IPIC_SIMSR_L,
471 		.mask	= IPIC_SIMSR_L,
477 		.mask	= IPIC_SIMSR_L,
483 		.mask	= IPIC_SIMSR_L,
489 		.mask	= IPIC_SIMSR_L,
495 		.mask	= IPIC_SIMSR_L,
501 		.mask	= IPIC_SIMSR_L,
532 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_unmask_irq()
534 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_unmask_irq()
548 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq()
550 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq()
587 	temp = ipic_read(ipic->regs, ipic_info[src].mask);  in ipic_mask_irq_and_ack()
589 	ipic_write(ipic->regs, ipic_info[src].mask, temp);  in ipic_mask_irq_and_ack()
851 void ipic_clear_mcp_status(u32 mask)  in ipic_clear_mcp_status()  argument
853 	ipic_write(primary_ipic->regs, IPIC_SERMR, mask);  in ipic_clear_mcp_status()