295 static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)  in hw_read_id_reg()  argument
297 	return ioread32(ci->hw_bank.abs + offset) & mask;  in hw_read_id_reg()
308 			    u32 mask, u32 data)  in hw_write_id_reg()  argument
310 	if (~mask)  in hw_write_id_reg()
311 		data = (ioread32(ci->hw_bank.abs + offset) & ~mask)  in hw_write_id_reg()
312 			| (data & mask);  in hw_write_id_reg()
325 static inline u32 hw_read(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask)  in hw_read()  argument
327 	return ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_read()
358 			    u32 mask, u32 data)  in hw_write()  argument
360 	if (~mask)  in hw_write()
361 		data = (ioread32(ci->hw_bank.regmap[reg]) & ~mask)  in hw_write()
362 			| (data & mask);  in hw_write()
376 				    u32 mask)  in hw_test_and_clear()  argument
378 	u32 val = ioread32(ci->hw_bank.regmap[reg]) & mask;  in hw_test_and_clear()
394 				    u32 mask, u32 data)  in hw_test_and_write()  argument
398 	hw_write(ci, reg, mask, data);  in hw_test_and_write()
399 	return (val & mask) >> __ffs(mask);  in hw_test_and_write()
431 int hw_wait_reg(struct ci_hdrc *ci, enum ci_hw_regs reg, u32 mask,