68 	unsigned int mask = 0x100 << cd->bit;  in irq_core_set_enable_local()  local
74 		set_c0_status(mask);  in irq_core_set_enable_local()
76 		clear_c0_status(mask);  in irq_core_set_enable_local()
175 	u32 mask = 1u << data->irq;  in irq_pci_enable()  local
177 	__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);  in irq_pci_enable()
182 	u32 mask = 1u << data->irq;  in irq_pci_disable()  local
184 	__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);  in irq_pci_disable()
193 	u32 mask = 1u << data->irq;  in irq_pci_mask()  local
195 	__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c);  in irq_pci_mask()
200 	u32 mask = 1u << data->irq;  in irq_pci_unmask()  local
202 	__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s);  in irq_pci_unmask()
218 	u32 mask;  in irq_mbox_all()  local
224 		mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);  in irq_mbox_all()
225 		__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));  in irq_mbox_all()
241 	u32 mask;  in irq_mbox_ack()  local
246 	mask = 1 << (get_ebase_cpunum() * MBOX_BITS_PER_CPU + mbox);  in irq_mbox_ack()
247 	__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1c + sizeof(u32));  in irq_mbox_ack()
253 	u32 mask;  in irq_mbox_ipi()  local
257 	mask = actions << (cpuid * MBOX_BITS_PER_CPU);  in irq_mbox_ipi()
258 	__raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1s + sizeof(u32));  in irq_mbox_ipi()
265 	u32 mask;  in irq_mbox_cpu_onoffline()  local
269 	mask = 1 << (cpuid * MBOX_BITS_PER_CPU + mbox);  in irq_mbox_cpu_onoffline()
270 	__raw_writel(mask, base + (cpuid * mips_irq_cpu_stride));  in irq_mbox_cpu_onoffline()