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Searched refs:readl_relaxed (Results 1 – 200 of 298) sorted by relevance

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/linux-4.1.27/drivers/crypto/ux500/cryp/
Dcryp.c38 peripheralid2 = readl_relaxed(&device_data->base->periphId2); in cryp_check()
45 readl_relaxed(&device_data->base->periphId0)) in cryp_check()
47 readl_relaxed(&device_data->base->periphId1)) in cryp_check()
49 readl_relaxed(&device_data->base->periphId3)) in cryp_check()
51 readl_relaxed(&device_data->base->pcellId0)) in cryp_check()
53 readl_relaxed(&device_data->base->pcellId1)) in cryp_check()
55 readl_relaxed(&device_data->base->pcellId2)) in cryp_check()
57 readl_relaxed(&device_data->base->pcellId3))) { in cryp_check()
99 while (readl_relaxed(&device_data->base->sr) != in cryp_flush_inoutfifo()
309 ctx->din = readl_relaxed(&src_reg->din); in cryp_save_device_context()
[all …]
Dcryp_p.h24 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
27 writel_relaxed(((readl_relaxed(reg_name) & ~(mask)) |\
31 (readl_relaxed(reg_name) & (val))
34 writel_relaxed(((readl_relaxed(reg) & ~(mask)) | \
Dcryp_irq.c26 i = readl_relaxed(&device_data->base->imsc); in cryp_enable_irq_src()
37 i = readl_relaxed(&device_data->base->imsc); in cryp_disable_irq_src()
44 return (readl_relaxed(&device_data->base->mis) & irq_src) > 0; in cryp_pending_irq_src()
/linux-4.1.27/drivers/clk/berlin/
Dberlin2-avpll.c129 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled()
141 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable()
156 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable()
174 reg = readl_relaxed(vco->base + VCO_CTRL1); in berlin2_avpll_vco_recalc_rate()
231 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_is_enabled()
242 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_enable()
254 reg = readl_relaxed(ch->base + VCO_CTRL10); in berlin2_avpll_channel_disable()
269 reg = readl_relaxed(ch->base + VCO_CTRL30); in berlin2_avpll_channel_recalc_rate()
278 reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index)); in berlin2_avpll_channel_recalc_rate()
284 reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index)); in berlin2_avpll_channel_recalc_rate()
[all …]
Dberlin2-div.c84 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
102 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_enable()
121 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_disable()
139 reg = readl_relaxed(div->base + map->pll_switch_offs); in berlin2_div_set_parent()
148 reg = readl_relaxed(div->base + map->pll_select_offs); in berlin2_div_set_parent()
171 reg = readl_relaxed(div->base + map->pll_switch_offs); in berlin2_div_get_parent()
174 reg = readl_relaxed(div->base + map->pll_select_offs); in berlin2_div_get_parent()
196 divsw = readl_relaxed(div->base + map->div_switch_offs) & in berlin2_div_recalc_rate()
198 div3sw = readl_relaxed(div->base + map->div3_switch_offs) & in berlin2_div_recalc_rate()
210 reg = readl_relaxed(div->base + map->div_select_offs); in berlin2_div_recalc_rate()
Dberlin2-pll.c67 val = readl_relaxed(pll->base + SPLL_CTRL0); in berlin2_pll_recalc_rate()
75 val = readl_relaxed(pll->base + SPLL_CTRL1); in berlin2_pll_recalc_rate()
/linux-4.1.27/arch/arm/mach-imx/
Dclk-pllv3.c52 u32 val = readl_relaxed(pll->base) & BM_PLL_POWER; in clk_pllv3_wait_lock()
60 if (readl_relaxed(pll->base) & BM_PLL_LOCK) in clk_pllv3_wait_lock()
67 return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT; in clk_pllv3_wait_lock()
75 val = readl_relaxed(pll->base); in clk_pllv3_prepare()
90 val = readl_relaxed(pll->base); in clk_pllv3_unprepare()
102 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
129 val = readl_relaxed(pll->base); in clk_pllv3_set_rate()
149 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
183 val = readl_relaxed(pll->base); in clk_pllv3_sys_set_rate()
203 u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET); in clk_pllv3_av_recalc_rate()
[all …]
Dmmdc.c42 val = readl_relaxed(reg); in imx_mmdc_probe()
49 val = readl_relaxed(reg); in imx_mmdc_probe()
54 while (!(readl_relaxed(reg) & 1 << BP_MMDC_MAPSR_PSS) && --timeout) in imx_mmdc_probe()
Dsrc.c61 val = readl_relaxed(src_base + SRC_SCR); in imx_src_reset_module()
92 val = readl_relaxed(src_base + SRC_SCR); in imx_enable_cpu()
109 return readl_relaxed(src_base + SRC_GPR1 + cpu * 8 + 4); in imx_get_cpu_arg()
138 val = readl_relaxed(src_base + SRC_SCR); in imx_src_init()
Dgpc.c84 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); in imx_gpc_pre_suspend()
123 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4); in imx_gpc_mask_all()
144 val = readl_relaxed(reg); in imx_gpc_hwirq_unmask()
155 val = readl_relaxed(reg); in imx_gpc_hwirq_mask()
300 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR); in _imx6q_pm_pu_power_off()
308 val = readl_relaxed(gpc_base + GPC_CNTR); in _imx6q_pm_pu_power_off()
349 val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR); in imx6q_pm_pu_power_on()
354 val = readl_relaxed(gpc_base + GPC_CNTR); in imx6q_pm_pu_power_on()
Dpm-imx6.c200 u32 val = readl_relaxed(ccm_base + CGPR); in imx6q_set_int_mem_clk_lpm()
219 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
225 val = readl_relaxed(ccm_base + CCR); in imx6_enable_rbc()
246 val = readl_relaxed(ccm_base + CLPCR); in imx6q_enable_wb()
252 val = readl_relaxed(ccm_base + CCR); in imx6q_enable_wb()
260 u32 val = readl_relaxed(ccm_base + CLPCR); in imx6q_set_lpm()
529 readl_relaxed(pm_info->iomuxc_base.vbase + in imx6q_suspend_init()
Dclk-pfd.c63 u8 frac = (readl_relaxed(pfd->reg) >> (pfd->idx * 8)) & 0x3f; in clk_pfd_recalc_rate()
116 if (readl_relaxed(pfd->reg) & (1 << ((pfd->idx + 1) * 8 - 1))) in clk_pfd_is_enabled()
Dsystem.c110 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); in imx_init_l2cache()
Dclk-imx6sl.c135 if (readl_relaxed(ccm_base + CCSR) & BM_CCSR_PLL1_SW_CLK_SEL) { in imx6sl_get_arm_divider_for_wait()
138 if ((readl_relaxed(anatop_base + PLL_ARM) & in imx6sl_get_arm_divider_for_wait()
152 saved_pll_arm = val = readl_relaxed(anatop_base + PLL_ARM); in imx6sl_enable_pll_arm()
176 saved_arm_div = readl_relaxed(ccm_base + CACRR); in imx6sl_set_wait_clk()
Danatop.c124 digprog = readl_relaxed(anatop_base + offset); in imx_init_revision_from_anatop()
/linux-4.1.27/drivers/mmc/host/
Dsdhci-msm.c74 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & in msm_dll_poll_ck_out_en()
85 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) & in msm_dll_poll_ck_out_en()
105 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
119 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
125 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_config_cm_dll_phase()
133 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_config_cm_dll_phase()
281 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG); in msm_cm_dll_set_freq()
301 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) in msm_init_cm_dll()
305 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
309 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) in msm_init_cm_dll()
[all …]
Dmmci_qcom_dml.c65 config = readl_relaxed(base + DML_CONFIG); in dml_start_xfer()
77 config = readl_relaxed(base + DML_CONFIG); in dml_start_xfer()
85 config = readl_relaxed(base + DML_CONFIG); in dml_start_xfer()
90 config = readl_relaxed(base + DML_CONFIG); in dml_start_xfer()
Datmel-mci-regs.h145 readl_relaxed((port)->regs + reg)
Dsdhci-st.c321 ret = readl_relaxed(host->ioaddr + reg); in sdhci_st_readl()
326 ret = readl_relaxed(host->ioaddr + reg); in sdhci_st_readl()
/linux-4.1.27/drivers/gpio/
Dgpio-mvebu.c206 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); in mvebu_gpio_set()
221 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { in mvebu_gpio_get()
222 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ in mvebu_gpio_get()
223 readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); in mvebu_gpio_get()
225 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); in mvebu_gpio_get()
239 u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); in mvebu_gpio_blink()
263 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_input()
290 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); in mvebu_gpio_direction_output()
411 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); in mvebu_gpio_irq_set_type()
430 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); in mvebu_gpio_irq_set_type()
[all …]
Dgpio-omap.c104 l = readl_relaxed(reg); in omap_set_gpio_direction()
140 l = readl_relaxed(reg); in omap_set_gpio_dataout_mask()
153 return (readl_relaxed(reg) & (BIT(offset))) != 0; in omap_get_gpio_datain()
160 return (readl_relaxed(reg) & (BIT(offset))) != 0; in omap_get_gpio_dataout()
165 int l = readl_relaxed(base + reg); in omap_gpio_rmw()
234 val = readl_relaxed(reg); in omap2_set_gpio_debounce()
309 readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_set_gpio_trigger()
311 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
313 readl_relaxed(bank->base + bank->regs->risingdetect); in omap_set_gpio_trigger()
315 readl_relaxed(bank->base + bank->regs->fallingdetect); in omap_set_gpio_trigger()
[all …]
Dgpio-pxa.c199 gpdr = readl_relaxed(base + GPDR_OFFSET); in __gpio_is_occupied()
205 gafr = readl_relaxed(base + GAFR_OFFSET); in __gpio_is_occupied()
239 value = readl_relaxed(base + GPDR_OFFSET); in pxa_gpio_direction_input()
261 tmp = readl_relaxed(base + GPDR_OFFSET); in pxa_gpio_direction_output()
274 u32 gplr = readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET); in pxa_gpio_get()
350 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask; in update_edge_detect()
351 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask; in update_edge_detect()
379 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET); in pxa_gpio_irq_type()
418 gedr = readl_relaxed(c->regbase + GEDR_OFFSET); in pxa_gpio_demux_handler()
449 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); in pxa_mask_muxed_gpio()
[all …]
Dgpio-zynq.c166 data = readl_relaxed(gpio->base_addr + in zynq_gpio_get_value()
232 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_in()
261 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num)); in zynq_gpio_dir_out()
266 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num)); in zynq_gpio_dir_out()
380 int_type = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
382 int_pol = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
384 int_any = readl_relaxed(gpio->base_addr + in zynq_gpio_set_irq_type()
509 int_sts = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
511 int_enb = readl_relaxed(gpio->base_addr + in zynq_gpio_irqhandler()
Dgpio-spear-spics.c70 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
102 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_request()
118 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_free()
Dgpio-davinci.c92 temp = readl_relaxed(&g->dir); in __davinci_direction()
128 return (1 << offset) & readl_relaxed(&g->in_data); in davinci_gpio_get()
350 status = readl_relaxed(&g->intstat) & mask; in gpio_irq_handler()
/linux-4.1.27/arch/arm/mach-hisi/
Dhotplug.c108 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
118 val = readl_relaxed(ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
193 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
198 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
203 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0); in hix5hd2_set_cpu()
209 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20); in hix5hd2_set_cpu()
230 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
237 temp = readl_relaxed(ctrl_base + HIP01_PERI9); in hip01_set_cpu()
Dplatmcpm.c86 data = readl_relaxed(fabric + FAB_SF_MODE); in hip04_set_snoop_filter()
94 } while (data != readl_relaxed(fabric + FAB_SF_MODE)); in hip04_set_snoop_filter()
119 data = readl_relaxed(sys_status); in hip04_mcpm_power_up()
128 } while (data == readl_relaxed(sys_status)); in hip04_mcpm_power_up()
202 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); in hip04_mcpm_wait_for_powerdown()
217 data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); in hip04_mcpm_wait_for_powerdown()
Dplatsmp.c39 return readl_relaxed(ctrl_base + ((cpu - 1) << 2)); in hi3xxx_get_cpu_jump()
168 remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL); in hip01_boot_secondary()
/linux-4.1.27/drivers/watchdog/
Domap_wdt.c69 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload()
76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload()
87 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable()
91 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable()
101 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) in omap_wdt_disable()
105 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10) in omap_wdt_disable()
116 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) in omap_wdt_set_timer()
120 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04) in omap_wdt_set_timer()
143 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) in omap_wdt_start()
147 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01) in omap_wdt_start()
[all …]
Dsa1100_wdt.c57 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_open()
60 writel_relaxed(readl_relaxed(OIER) | OIER_E3, OIER); in sa1100dog_open()
83 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_write()
117 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
132 writel_relaxed(readl_relaxed(OSCR) + pre_margin, OSMR3); in sa1100dog_ioctl()
Dsp805_wdt.c114 load = readl_relaxed(wdt->base + WDTVALUE); in wdt_timeleft()
117 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) in wdt_timeleft()
152 readl_relaxed(wdt->base + WDTLOCK); in wdt_config()
181 readl_relaxed(wdt->base + WDTLOCK); in wdt_disable()
Dbcm2835_wdt.c55 cur = readl_relaxed(wdt->base + PM_RSTC); in bcm2835_wdt_start()
83 uint32_t ret = readl_relaxed(wdt->base + PM_WDOG); in bcm2835_wdt_get_timeleft()
/linux-4.1.27/drivers/clk/ti/
Dfapll.c86 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass()
96 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass()
107 u32 v = readl_relaxed(fd->base); in ti_fapll_clear_bypass()
121 while ((v = readl_relaxed(fd->base))) { in ti_fapll_wait_lock()
139 u32 v = readl_relaxed(fd->base); in ti_fapll_enable()
151 u32 v = readl_relaxed(fd->base); in ti_fapll_disable()
160 u32 v = readl_relaxed(fd->base); in ti_fapll_is_enabled()
178 v = readl_relaxed(fd->base); in ti_fapll_recalc_rate()
258 v = readl_relaxed(fd->base); in ti_fapll_set_rate()
283 u32 v = readl_relaxed(synth->fd->base + FAPLL_PWD_OFFSET); in ti_fapll_synth_enable()
[all …]
/linux-4.1.27/drivers/phy/
Dphy-qcom-ipq806x-sata.c67 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM3); in qcom_ipq806x_sata_phy_init()
71 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM0) & in qcom_ipq806x_sata_phy_init()
78 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM1) & in qcom_ipq806x_sata_phy_init()
87 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM2) & in qcom_ipq806x_sata_phy_init()
93 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
98 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
109 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_init()
122 reg = readl_relaxed(phy->mmio + SATA_PHY_P0_PARAM4); in qcom_ipq806x_sata_phy_exit()
Dphy-hix5hd2-sata.c85 val = readl_relaxed(priv->base + SATA_PHY0_CTLL); in hix5hd2_sata_phy_init()
94 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1); in hix5hd2_sata_phy_init()
101 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2); in hix5hd2_sata_phy_init()
109 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL); in hix5hd2_sata_phy_init()
Dphy-qcom-apq8064-sata.c88 if (readl_relaxed(addr) & mask) in read_poll_timeout()
94 return (readl_relaxed(addr) & mask) ? 0 : -ETIMEDOUT; in read_poll_timeout()
/linux-4.1.27/drivers/clocksource/
Dtimer-prima2.c64 WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & in sirfsoc_timer_interrupt()
83 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI); in sirfsoc_timer_read()
85 readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_read()
97 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_set_next_event()
102 now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO); in sirfsoc_timer_set_next_event()
110 u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); in sirfsoc_timer_set_mode()
138 readl_relaxed(sirfsoc_timer_base + in sirfsoc_clocksource_suspend()
Dtimer-atlas7.c59 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, in sirfsoc_timer_count_disable()
66 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, in sirfsoc_timer_count_enable()
92 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_timer_read()
95 cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_HI); in sirfsoc_timer_read()
96 cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_RLATCHED_LO); in sirfsoc_timer_read()
139 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); in sirfsoc_clocksource_suspend()
154 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_clocksource_resume()
277 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_atlas7_timer_init()
Dexynos_mct.c147 if (readl_relaxed(reg_base + stat_addr) & mask) { in exynos4_mct_write()
160 reg = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_frc_start()
178 u32 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_read_count_64()
182 lo = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); in exynos4_read_count_64()
183 hi2 = readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_U); in exynos4_read_count_64()
199 return readl_relaxed(reg_base + EXYNOS4_MCT_G_CNT_L); in exynos4_read_count_32()
253 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_stop()
266 tcon = readl_relaxed(reg_base + EXYNOS4_MCT_G_TCON); in exynos4_mct_comp0_start()
355 tmp = readl_relaxed(reg_base + offset); in exynos4_mct_tick_stop()
377 tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET); in exynos4_mct_tick_start()
[all …]
Dcadence_ttc_timer.c121 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
150 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET); in ttc_clock_event_interrupt()
166 return (cycle_t)readl_relaxed(timer->base_addr + in __ttc_clocksource_read()
172 return readl_relaxed(ttc_sched_clock_val_reg); in ttc_sched_clock_read()
214 ctrl_reg = readl_relaxed(timer->base_addr + in ttc_set_mode()
221 ctrl_reg = readl_relaxed(timer->base_addr + in ttc_set_mode()
269 readl_relaxed(ttccs->ttc.base_addr + in ttc_rate_change_clocksource_cb()
498 clksel = readl_relaxed(timer_baseaddr + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
506 clksel = readl_relaxed(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET); in ttc_timer_init()
Dqcom-timer.c53 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_interrupt()
64 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_next_event()
73 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND) in msm_timer_set_next_event()
85 ctrl = readl_relaxed(event_base + TIMER_ENABLE); in msm_timer_set_mode()
108 return readl_relaxed(source_base + TIMER_COUNT_VAL); in msm_read_timer_count()
Dbcm2835_timer.c54 return readl_relaxed(system_clock); in bcm2835_sched_read()
77 writel_relaxed(readl_relaxed(system_clock) + event, in bcm2835_time_set_next_event()
86 if (readl_relaxed(timer->control) & timer->match_mask) { in bcm2835_time_interrupt()
Darm_global_timer.c69 upper = readl_relaxed(gt_base + GT_COUNTER1); in gt_counter_read()
72 lower = readl_relaxed(gt_base + GT_COUNTER0); in gt_counter_read()
73 upper = readl_relaxed(gt_base + GT_COUNTER1); in gt_counter_read()
143 if (!(readl_relaxed(gt_base + GT_INT_STATUS) & in gt_clockevent_interrupt()
Dclksrc-dbx500-prcmu.c38 count = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); in clksrc_dbx500_prcmu_read()
39 count2 = readl_relaxed(base + PRCMU_TIMER_DOWNCOUNT); in clksrc_dbx500_prcmu_read()
Darm_arch_timer.c117 val = readl_relaxed(timer->base + CNTP_CTL); in arch_timer_reg_read()
120 val = readl_relaxed(timer->base + CNTP_TVAL); in arch_timer_reg_read()
127 val = readl_relaxed(timer->base + CNTV_CTL); in arch_timer_reg_read()
130 val = readl_relaxed(timer->base + CNTV_TVAL); in arch_timer_reg_read()
382 arch_timer_rate = readl_relaxed(cntbase + CNTFRQ); in arch_timer_detect_rate()
419 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); in arch_counter_get_cntvct_mem()
420 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO); in arch_counter_get_cntvct_mem()
421 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI); in arch_counter_get_cntvct_mem()
767 cnttidr = readl_relaxed(cntctlbase + CNTTIDR); in arch_timer_mem_init()
Dmmio.c25 return (cycle_t)readl_relaxed(to_mmio_clksrc(c)->reg); in clocksource_mmio_readl_up()
30 return ~(cycle_t)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask; in clocksource_mmio_readl_down()
Ddw_apb_timer_of.c111 return ~readl_relaxed(sched_io_base); in read_sched_clock()
Dtimer-keystone.c54 return readl_relaxed(timer.base + rg); in keystone_timer_readl()
/linux-4.1.27/drivers/thermal/
Ddove_thermal.c57 reg = readl_relaxed(priv->control); in dove_init_sensor()
73 reg = readl_relaxed(priv->control); in dove_init_sensor()
78 reg = readl_relaxed(priv->sensor); in dove_init_sensor()
84 reg = readl_relaxed(priv->sensor); in dove_init_sensor()
102 reg = readl_relaxed(priv->control + PMU_TEMP_DIOD_CTRL1_REG); in dove_get_temp()
114 reg = readl_relaxed(priv->sensor); in dove_get_temp()
Darmada_thermal.c78 reg = readl_relaxed(priv->control); in armadaxp_init_sensor()
88 reg = readl_relaxed(priv->control); in armadaxp_init_sensor()
94 reg = readl_relaxed(priv->sensor); in armadaxp_init_sensor()
104 reg = readl_relaxed(priv->control); in armada370_init_sensor()
140 unsigned long reg = readl_relaxed(priv->control); in armada380_init_sensor()
152 unsigned long reg = readl_relaxed(priv->sensor); in armada_is_valid()
171 reg = readl_relaxed(priv->sensor); in armada_get_temp()
Dspear_thermal.c49 *temp = (readl_relaxed(stdev->thermal_base) & 0x7F) * MD_FACTOR; in thermal_get_temp()
66 actual_mask = readl_relaxed(stdev->thermal_base); in spear_thermal_suspend()
90 actual_mask = readl_relaxed(stdev->thermal_base); in spear_thermal_resume()
170 actual_mask = readl_relaxed(stdev->thermal_base); in spear_thermal_exit()
Drockchip_thermal.c263 val = readl_relaxed(regs + TSADCV2_INT_PD); in rk_tsadcv2_irq_ack()
271 val = readl_relaxed(regs + TSADCV2_AUTO_CON); in rk_tsadcv2_control()
285 val = readl_relaxed(regs + TSADCV2_DATA(chn)); in rk_tsadcv2_get_temp()
302 val = readl_relaxed(regs + TSADCV2_AUTO_CON); in rk_tsadcv2_tshut_temp()
311 val = readl_relaxed(regs + TSADCV2_INT_EN); in rk_tsadcv2_tshut_mode()
Dkirkwood_thermal.c41 reg = readl_relaxed(priv->sensor); in kirkwood_get_temp()
/linux-4.1.27/drivers/mtd/nand/
Datmel_nand_ecc.h115 readl_relaxed((addr) + ATMEL_PMECC_##reg)
124 readl_relaxed((addr) + ATMEL_PMECC_REMx + ((sector) * 0x40) + ((n) * 4))
127 readl_relaxed((addr) + ATMEL_PMERRLOC_##reg)
136 readl_relaxed((addr) + ATMEL_PMERRLOC_SIGMAx + ((n) * 4))
139 readl_relaxed((addr) + ATMEL_PMERRLOC_ELx + ((n) * 4))
Datmel_nand_nfc.h61 readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
98 readl_relaxed((bitstatus) + nfc_base)
Dfsmc_nand.c477 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY) in fsmc_read_hwecc_ecc4()
488 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); in fsmc_read_hwecc_ecc4()
494 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); in fsmc_read_hwecc_ecc4()
500 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3)); in fsmc_read_hwecc_ecc4()
506 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS)); in fsmc_read_hwecc_ecc4()
526 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); in fsmc_read_hwecc_ecc1()
662 p[i] = readl_relaxed(chip->IO_ADDR_R); in fsmc_read_buf()
794 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF; in fsmc_bch8_correct_data()
837 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); in fsmc_bch8_correct_data()
838 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); in fsmc_bch8_correct_data()
[all …]
/linux-4.1.27/drivers/hwtracing/coresight/
Dcoresight-etb10.c103 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); in etb_get_buffer_depth()
162 ffcr = readl_relaxed(drvdata->base + ETB_FFCR); in etb_disable_hw()
198 read_ptr = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); in etb_dump_hw()
199 write_ptr = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); in etb_dump_hw()
212 if ((readl_relaxed(drvdata->base + ETB_STATUS_REG) in etb_dump_hw()
221 read_data = readl_relaxed(drvdata->base + in etb_dump_hw()
355 etb_rdr = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); in status_show()
356 etb_sr = readl_relaxed(drvdata->base + ETB_STATUS_REG); in status_show()
357 etb_rrp = readl_relaxed(drvdata->base + ETB_RAM_READ_POINTER); in status_show()
358 etb_rwp = readl_relaxed(drvdata->base + ETB_RAM_WRITE_POINTER); in status_show()
[all …]
Dcoresight-tmc.c151 ffcr = readl_relaxed(drvdata->base + TMC_FFCR); in tmc_flush_and_stop()
208 axictl = readl_relaxed(drvdata->base + TMC_AXICTL); in tmc_etr_enable_hw()
299 memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10); in tmc_etb_dump_hw()
312 read_data = readl_relaxed(drvdata->base + TMC_RRD); in tmc_etb_dump_hw()
336 rwp = readl_relaxed(drvdata->base + TMC_RWP); in tmc_etr_dump_hw()
337 val = readl_relaxed(drvdata->base + TMC_STS); in tmc_etr_dump_hw()
447 mode = readl_relaxed(drvdata->base + TMC_MODE); in tmc_read_prepare()
480 mode = readl_relaxed(drvdata->base + TMC_MODE); in tmc_read_unprepare()
585 tmc_rsz = readl_relaxed(drvdata->base + TMC_RSZ); in status_show()
586 tmc_sts = readl_relaxed(drvdata->base + TMC_STS); in status_show()
[all …]
Dcoresight-funnel.c56 functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); in funnel_enable_hw()
88 functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); in funnel_disable_hw()
147 functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); in get_funnel_ctrl_hw()
/linux-4.1.27/arch/arm/mach-vexpress/
Ddcscb.c49 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerup()
64 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerup()
78 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cpu_powerdown_prepare()
90 rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); in dcscb_cluster_powerdown_prepare()
151 cfg = readl_relaxed(dcscb_base + DCS_CFG_R); in dcscb_init()
Dtc2_pm.c123 return !(readl_relaxed(scc + RESET_CTRL) & mask); in tc2_core_in_reset()
139 readl_relaxed(scc + RESET_CTRL)); in tc2_pm_wait_for_powerdown()
223 a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf; in tc2_pm_init()
224 a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf; in tc2_pm_init()
228 sys_info = readl_relaxed(scc + SYS_INFO); in tc2_pm_init()
Dspc.c135 reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); in ve_spc_global_wakeup_irq()
168 reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK); in ve_spc_cpu_wakeup_irq()
248 ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT); in ve_spc_cpu_in_wfi()
264 perf = readl_relaxed(info->baseaddr + perf_cfg_reg); in ve_spc_get_performance()
381 uint32_t status = readl_relaxed(drv_data->baseaddr + PWC_STATUS); in ve_spc_irq_handler()
470 readl_relaxed(info->baseaddr + PWC_STATUS); in ve_spc_init()
/linux-4.1.27/drivers/char/hw_random/
Dmsm-rng.c58 val = readl_relaxed(rng->base + PRNG_CONFIG); in msm_rng_enable()
62 val = readl_relaxed(rng->base + PRNG_LFSR_CFG); in msm_rng_enable()
67 val = readl_relaxed(rng->base + PRNG_CONFIG); in msm_rng_enable()
71 val = readl_relaxed(rng->base + PRNG_CONFIG); in msm_rng_enable()
103 val = readl_relaxed(rng->base + PRNG_STATUS); in msm_rng_read()
107 val = readl_relaxed(rng->base + PRNG_DATA_OUT); in msm_rng_read()
/linux-4.1.27/drivers/bus/
Domap_l3_noc.c92 std_err_main = readl_relaxed(l3_targ_stderr); in l3_handle_target()
99 readl_relaxed(l3_targ_slvofslsb)); in l3_handle_target()
121 masterid = (readl_relaxed(l3_targ_mstaddr) & in l3_handle_target()
132 op_code = readl_relaxed(l3_targ_hdr) & 0x7; in l3_handle_target()
134 m_req_info = readl_relaxed(l3_targ_info) & 0xF; in l3_handle_target()
186 err_reg = readl_relaxed(base + flag_mux->offset + in l3_interrupt_handler()
213 mask_val = readl_relaxed(mask_reg); in l3_interrupt_handler()
330 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
336 mask_val = readl_relaxed(mask_regx); in l3_resume_noirq()
Domap-ocp2scp.c77 reg = readl_relaxed(regs + OCP2SCP_TIMING); in omap_ocp2scp_probe()
Darm-cci.c220 rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK; in probe_cci_revision()
244 return readl_relaxed(pmu->base + CCI_PMU_CNTR_BASE(idx) + offset); in pmu_read_register()
269 u32 n_cnts = (readl_relaxed(cci_ctrl_base + CCI_PMCR) & in pmu_get_max_counters()
505 val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; in cci_pmu_enable()
521 val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; in cci_pmu_disable()
1199 while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1) in cci_port_control()
/linux-4.1.27/drivers/irqchip/
Dirq-sirfsoc.c55 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); in sirfsoc_handle_irq()
97 sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); in sirfsoc_irq_suspend()
98 sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); in sirfsoc_irq_suspend()
99 sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_suspend()
100 sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); in sirfsoc_irq_suspend()
Dirq-mmp.c73 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_ack_irq()
83 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_ack_irq()
97 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_mask_irq()
102 r = readl_relaxed(data->reg_mask) | (1 << hwirq); in icu_mask_irq()
116 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); in icu_unmask_irq()
121 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); in icu_unmask_irq()
152 mask = readl_relaxed(data->reg_mask); in icu_mux_irq_demux()
154 status = readl_relaxed(data->reg_status) & ~mask; in icu_mux_irq_demux()
201 hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); in mmp_handle_irq()
212 hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL); in mmp2_handle_irq()
Dirq-gic-common.c39 val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); in gic_configure_irq()
49 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { in gic_configure_irq()
62 if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval) in gic_configure_irq()
Dirq-gic.c152 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); in gic_peek_irq()
256 val = readl_relaxed(reg) & ~mask; in gic_set_affinity()
271 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); in gic_handle_irq()
307 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); in gic_handle_cascade_irq()
352 mask = readl_relaxed(base + GIC_DIST_TARGET + i); in gic_get_cpumask()
465 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); in gic_dist_save()
469 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); in gic_dist_save()
473 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_dist_save()
537 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in gic_cpu_save()
541 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); in gic_cpu_save()
[all …]
Dirq-gic-v3.c86 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { in gic_do_wait_for_rwp()
169 val = readl_relaxed(rbase + GICR_WAKER); in gic_enable_redist()
178 val = readl_relaxed(rbase + GICR_WAKER); in gic_enable_redist()
184 val = readl_relaxed(rbase + GICR_WAKER); in gic_enable_redist()
208 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); in gic_peek_irq()
426 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_populate_rdist()
479 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); in gic_dist_supports_lpis()
806 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; in gic_of_init()
850 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); in gic_of_init()
Dirq-dw-apb-ictl.c40 stat = readl_relaxed(gc->reg_base + in dw_apb_ictl_handler()
117 reg = readl_relaxed(iobase + APB_INT_ENABLE_H); in dw_apb_ictl_init()
121 nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L)); in dw_apb_ictl_init()
Dirq-tegra.c155 lic->cpu_ier[i] = readl_relaxed(ictlr + ICTLR_CPU_IER); in tegra_ictlr_suspend()
156 lic->cpu_iep[i] = readl_relaxed(ictlr + ICTLR_CPU_IEP_CLASS); in tegra_ictlr_suspend()
157 lic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER); in tegra_ictlr_suspend()
158 lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS); in tegra_ictlr_suspend()
Dirq-hip04.c164 val = readl_relaxed(reg) & ~mask; in hip04_irq_set_affinity()
178 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); in hip04_handle_irq()
213 mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2); in hip04_get_cpumask()
393 nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f; in hip04_of_init()
Dirq-armada-370-xp.c422 msimask = readl_relaxed(per_cpu_int_base + in armada_370_xp_handle_msi_irq()
460 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE); in armada_370_xp_mpic_handle_cascade_irq()
464 irqsrc = readl_relaxed(main_int_base + in armada_370_xp_mpic_handle_cascade_irq()
491 irqstat = readl_relaxed(per_cpu_int_base + in armada_370_xp_handle_irq()
513 ipimask = readl_relaxed(per_cpu_int_base + in armada_370_xp_handle_irq()
Dirq-bcm2835.c186 while ((stat = readl_relaxed(intc.pending[bank]))) { in armctrl_handle_bank()
204 while ((stat = readl_relaxed(intc.pending[0]) & BANK0_VALID_MASK)) { in bcm2835_handle_irq()
Dirq-vt8500.c190 irqnr = readl_relaxed(base) & 0x3F; in vt8500_handle_irq()
196 stat = readl_relaxed(base + VT8500_ICIS + 4); in vt8500_handle_irq()
Dirq-orion.c42 u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) & in orion_handle_irq()
115 u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) & in orion_bridge_irq_handler()
Dirq-clps711x.c109 tmp = readl_relaxed(intmr); in clps711x_intc_mask()
120 tmp = readl_relaxed(intmr); in clps711x_intc_unmask()
Dirq-gic-v3-its.c366 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); in its_queue_full()
431 rd_idx = readl_relaxed(its->base + GITS_CREADR); in its_wait_for_range_completion()
1012 val = readl_relaxed(rbase + GICR_CTLR); in its_cpu_init_lpis()
1066 val = readl_relaxed(rbase + GICR_CTLR); in its_cpu_init_lpis()
1405 val = readl_relaxed(base + GITS_CTLR); in its_force_quiescent()
1415 val = readl_relaxed(base + GITS_CTLR); in its_force_quiescent()
1449 val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK; in its_probe()
1477 its->ite_size = ((readl_relaxed(its_base + GITS_TYPER) >> 4) & 0xf) + 1; in its_probe()
1569 return !!(readl_relaxed(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS); in gic_rdists_supports_plpis()
Dirq-nvic.c59 numbanks = (readl_relaxed(V7M_SCS_ICTR) & in nvic_of_init()
Dirq-mtk-sysirq.c43 value = readl_relaxed(chip_data->intpol_base + reg_index * 4); in mtk_sysirq_set_type()
Dirq-vic.c220 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { in handle_one_vic()
237 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) { in vic_handle_irq_cascaded()
/linux-4.1.27/arch/arm/mach-dove/
Dirq.c61 u &= readl_relaxed(PMU_INTERRUPT_CAUSE); in pmu_irq_ack()
126 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF); in dove_legacy_handle_irq()
127 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF); in dove_legacy_handle_irq()
133 stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF); in dove_legacy_handle_irq()
134 stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF); in dove_legacy_handle_irq()
/linux-4.1.27/drivers/rtc/
Drtc-digicolor.c73 reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE); in dc_rtc_read()
74 time1 = readl_relaxed(rtc->regs + DC_RTC_TIME); in dc_rtc_read()
77 time2 = readl_relaxed(rtc->regs + DC_RTC_TIME); in dc_rtc_read()
123 alarm_reg = readl_relaxed(rtc->regs + DC_RTC_ALARM); in dc_rtc_read_alarm()
124 reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE); in dc_rtc_read_alarm()
132 alarm->enabled = readl_relaxed(rtc->regs + DC_RTC_INTENABLE); in dc_rtc_read_alarm()
145 reference = readl_relaxed(rtc->regs + DC_RTC_REFERENCE); in dc_rtc_set_alarm()
/linux-4.1.27/arch/arm/mach-omap2/
Domap-wakeupgen.c65 return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 + in wakeupgen_readl()
221 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap4_irq_save_context()
223 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1); in omap4_irq_save_context()
227 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK); in omap4_irq_save_context()
229 val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN); in omap4_irq_save_context()
233 val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET); in omap4_irq_save_context()
254 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap5_irq_save_context()
256 val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0); in omap5_irq_save_context()
260 val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET); in omap5_irq_save_context()
296 val = readl_relaxed(sar_base + offset); in irq_sar_clear()
Domap4-common.c68 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1); in gic_dist_disabled()
73 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT); in gic_timer_retrigger()
74 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET); in gic_timer_retrigger()
75 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); in gic_timer_retrigger()
Dwd_timer.c53 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) in omap2_wd_timer_disable()
57 while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10) in omap2_wd_timer_disable()
Dsdrc.h39 return readl_relaxed(OMAP_SDRC_REGADDR(reg)); in sdrc_read_reg()
51 return readl_relaxed(OMAP_SMS_REGADDR(reg)); in sms_read_reg()
Domap-hotplug.c56 readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5; in omap4_cpu_die()
Dprcm_mpu44xx.c33 return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg)); in omap4_prcm_mpu_read_inst_reg()
Dcm2xxx_3xxx.h55 return readl_relaxed(cm_base + module + idx); in omap2_cm_read_mod_reg()
Dclkt2xxx_dpllcore.c141 tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg); in omap2_reprogram_dpllcore()
Dprminst44xx.c64 return readl_relaxed(_prm_bases[part] + inst + idx); in omap4_prminst_read_inst_reg()
Dprm2xxx_3xxx.h58 return readl_relaxed(prm_base + module + idx); in omap2_prm_read_mod_reg()
/linux-4.1.27/arch/arm/mm/
Dcache-l2x0.c65 while (readl_relaxed(reg) & mask) in l2c_wait_mask()
75 if (val == readl_relaxed(base + reg)) in l2c_write_sec()
133 if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN) in l2c_enable()
161 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); in l2c_save()
545 l2x0_saved_regs.tag_latency = readl_relaxed(base + in l2c310_save()
547 l2x0_saved_regs.data_latency = readl_relaxed(base + in l2c310_save()
549 l2x0_saved_regs.filter_end = readl_relaxed(base + in l2c310_save()
551 l2x0_saved_regs.filter_start = readl_relaxed(base + in l2c310_save()
554 revision = readl_relaxed(base + L2X0_CACHE_ID) & in l2c310_save()
559 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + in l2c310_save()
[all …]
/linux-4.1.27/drivers/video/fbdev/mmp/hw/
Dmmp_spi.c68 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
73 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
76 isr = readl_relaxed(reg_base + SPU_IRQ_ISR); in lcd_spi_write()
84 tmp = readl_relaxed(reg_base + LCD_SPU_SPI_CTRL); in lcd_spi_write()
111 tmp = readl_relaxed(reg_base + SPU_IOPAD_CONTROL); in lcd_spi_setup()
Dmmp_ctrl.c48 isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
49 imask = readl_relaxed(ctrl->reg_base + SPU_IRQ_ENA); in ctrl_handle_irq()
53 tmp = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
56 } while ((isr = readl_relaxed(ctrl->reg_base + SPU_IRQ_ISR)) & imask); in ctrl_handle_irq()
136 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_set_fmt()
180 tmp = readl_relaxed(ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_onoff()
191 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); in path_enabledisable()
271 tmp = readl_relaxed(ctrl_regs(path) + intf_ctrl(path->id)) & 0x1; in path_set_mode()
279 tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) & in path_set_mode()
312 tmp = readl_relaxed(ctrl_regs(path) + LCD_SCLK(path)); in path_set_mode()
[all …]
/linux-4.1.27/drivers/i2c/busses/
Di2c-st.c202 writel_relaxed(readl_relaxed(reg) | mask, reg); in st_i2c_set_bits()
207 writel_relaxed(readl_relaxed(reg) & ~mask, reg); in st_i2c_clr_bits()
247 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) in st_i2c_flush_rx_fifo()
250 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & in st_i2c_flush_rx_fifo()
254 readl_relaxed(i2c_dev->base + SSC_RBUF); in st_i2c_flush_rx_fifo()
346 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_wait_free_bus()
383 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_wr_fill_tx_fifo()
387 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); in st_i2c_wr_fill_tx_fifo()
412 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_rd_fill_tx_fifo()
416 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); in st_i2c_rd_fill_tx_fifo()
[all …]
Di2c-hix5hd2.c104 u32 val = readl_relaxed(priv->regs + HIX5I2C_SR); in hix5hd2_i2c_clr_pend_irq()
133 val = readl_relaxed(priv->regs + HIX5I2C_CTRL); in hix5hd2_i2c_drv_setrate()
238 data = readl_relaxed(priv->regs + HIX5I2C_RXR); in hix5hd2_rw_preprocess()
/linux-4.1.27/drivers/clk/mmp/
Dclk-apbc.c49 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
63 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
76 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
96 data = readl_relaxed(apbc->base); in clk_apbc_unprepare()
110 data = readl_relaxed(apbc->base); in clk_apbc_unprepare()
Dclk-apmu.c39 data = readl_relaxed(apmu->base) | apmu->enable_mask; in clk_apmu_enable()
57 data = readl_relaxed(apmu->base) & ~apmu->enable_mask; in clk_apmu_disable()
Dclk-frac.c58 val = readl_relaxed(factor->base); in clk_factor_recalc_rate()
97 val = readl_relaxed(factor->base); in clk_factor_set_rate()
/linux-4.1.27/arch/arm/plat-omap/
Dcounter_32k.c43 return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_32k_read_sched_clock()
63 cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_read_persistent_clock64()
92 if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) & in omap_init_clocksource_32k()
/linux-4.1.27/arch/arm/kernel/
Dsmp_scu.c33 unsigned int ncores = readl_relaxed(scu_base + SCU_CONFIG); in scu_get_core_count()
47 scu_ctrl = readl_relaxed(scu_base + 0x30); in scu_enable()
53 scu_ctrl = readl_relaxed(scu_base + SCU_CTRL); in scu_enable()
Dio.c20 value = readl_relaxed(reg) & ~mask; in atomic_io_modify_relaxed()
33 value = readl_relaxed(reg) & ~mask; in atomic_io_modify()
Dsmp_twd.c67 unsigned long ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL); in twd_set_next_event()
85 if (readl_relaxed(twd_base + TWD_TIMER_INTSTAT)) { in twd_timer_ack()
222 count = readl_relaxed(twd_base + TWD_TIMER_COUNTER); in twd_calibrate_rate()
/linux-4.1.27/arch/arm/mach-ks8695/
Dtime.c67 tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_mode()
89 tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_set_next_event()
134 tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_timer_setup()
165 reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON); in ks8695_restart()
/linux-4.1.27/drivers/pinctrl/
Dpinctrl-at91.c370 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); in at91_mux_get_pullup()
383 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; in at91_mux_get_multidrive()
404 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, in at91_mux_pio3_set_A_periph()
406 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_A_periph()
412 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, in at91_mux_pio3_set_B_periph()
414 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_B_periph()
420 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_C_periph()
421 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_C_periph()
426 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_D_periph()
427 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_D_periph()
[all …]
Dpinctrl-rockchip.c877 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
1407 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); in rockchip_irq_demux()
1431 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_demux()
1435 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
1447 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
1476 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
1490 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); in rockchip_irq_set_type()
1491 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); in rockchip_irq_set_type()
/linux-4.1.27/drivers/mailbox/
Dmailbox-altera.c74 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_full()
82 status = readl_relaxed(mbox->mbox_base + MAILBOX_STS_REG); in altera_mbox_pending()
90 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_rx_intmask()
102 mask = readl_relaxed(mbox->mbox_base + MAILBOX_INTMASK_REG); in altera_mbox_tx_intmask()
118 reg = readl_relaxed(mbox->mbox_base + MAILBOX_PTR_REG); in altera_mbox_is_sender()
134 readl_relaxed(mbox->mbox_base + MAILBOX_PTR_REG); in altera_mbox_rx_data()
136 readl_relaxed(mbox->mbox_base + MAILBOX_CMD_REG); in altera_mbox_rx_data()
Darm_mhu.c57 val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS); in mhu_rx_interrupt()
71 u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in mhu_last_tx_done()
92 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS); in mhu_startup()
/linux-4.1.27/drivers/clk/hisilicon/
Dclk-hix5hd2.c177 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
183 val = readl_relaxed(clk->phy_reg); in clk_ether_prepare()
206 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
221 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
226 val = readl_relaxed(clk->phy_reg); in clk_complex_enable()
239 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
244 val = readl_relaxed(clk->phy_reg); in clk_complex_disable()
Dclkgate-separated.c59 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_enable()
76 readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_disable()
87 reg = readl_relaxed(sclk->enable + CLKGATE_SEPERATED_STATUS); in clkgate_separated_is_enabled()
Dclk-hi3620.c381 val = readl_relaxed(mclk->clken_reg); in mmc_clk_set_timing()
385 val = readl_relaxed(mclk->sam_reg); in mmc_clk_set_timing()
389 val = readl_relaxed(mclk->drv_reg); in mmc_clk_set_timing()
393 val = readl_relaxed(mclk->div_reg); in mmc_clk_set_timing()
397 val = readl_relaxed(mclk->clken_reg); in mmc_clk_set_timing()
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
Dpll.c207 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) in wait_for_bit_change()
214 if (FLD_GET(readl_relaxed(reg), bitnum, bitnum) == value) in wait_for_bit_change()
240 u32 v = readl_relaxed(pll->base + PLL_STATUS); in dss_wait_hsdiv_ack()
279 l = readl_relaxed(base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
318 l = readl_relaxed(base + PLL_CONFIGURATION2); in dss_pll_write_config_type_a()
353 l = readl_relaxed(base + PLL_CONFIGURATION2); in dss_pll_write_config_type_b()
367 l = readl_relaxed(base + PLL_CONFIGURATION3); in dss_pll_write_config_type_b()
371 l = readl_relaxed(base + PLL_CONFIGURATION4); in dss_pll_write_config_type_b()
/linux-4.1.27/drivers/dma/
Dsa11x0-dma.c174 dcsr = readl_relaxed(base + DMA_DCSR_R); in sa11x0_dma_start_sg()
259 dcsr = readl_relaxed(p->base + DMA_DCSR_R); in sa11x0_dma_irq()
272 readl_relaxed(p->base + DMA_DDAR), in sa11x0_dma_irq()
273 readl_relaxed(p->base + DMA_DBSA), in sa11x0_dma_irq()
274 readl_relaxed(p->base + DMA_DBTA), in sa11x0_dma_irq()
275 readl_relaxed(p->base + DMA_DBSB), in sa11x0_dma_irq()
276 readl_relaxed(p->base + DMA_DBTB)); in sa11x0_dma_irq()
316 WARN_ON(readl_relaxed(p->base + DMA_DCSR_R) & in sa11x0_dma_start_txd()
410 dcsr = readl_relaxed(p->base + DMA_DCSR_R); in sa11x0_dma_pos()
418 return readl_relaxed(p->base + reg); in sa11x0_dma_pos()
[all …]
Dsirf-dma.c139 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) | in sirfsoc_dma_execute()
150 readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL), in sirfsoc_dma_execute()
311 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN) & in sirfsoc_dma_terminate_all()
313 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) in sirfsoc_dma_terminate_all()
342 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) in sirfsoc_dma_pause_chan()
364 writel_relaxed(readl_relaxed(sdma->base + SIRFSOC_DMA_CH_LOOP_CTRL) in sirfsoc_dma_resume_chan()
482 dma_pos = readl_relaxed(sdma->base + cid * 0x10 + SIRFSOC_DMA_CH_ADDR) in sirfsoc_dma_tx_status()
841 save->ctrl[ch] = readl_relaxed(sdma->base + in sirfsoc_dma_pm_suspend()
844 save->interrupt_en = readl_relaxed(sdma->base + SIRFSOC_DMA_INT_EN); in sirfsoc_dma_pm_suspend()
Dmv_xor.c84 return readl_relaxed(XOR_CURR_DESC(chan)); in mv_chan_get_current_desc()
95 u32 val = readl_relaxed(XOR_INTR_MASK(chan)); in mv_chan_unmask_interrupts()
102 u32 intr_cause = readl_relaxed(XOR_INTR_CAUSE(chan)); in mv_chan_get_intr_cause()
127 u32 config = readl_relaxed(XOR_CONFIG(chan)); in mv_set_mode()
167 u32 state = readl_relaxed(XOR_ACTIVATION(chan)); in mv_chan_is_busy()
636 val = readl_relaxed(XOR_CONFIG(chan)); in mv_dump_xor_regs()
639 val = readl_relaxed(XOR_ACTIVATION(chan)); in mv_dump_xor_regs()
642 val = readl_relaxed(XOR_INTR_CAUSE(chan)); in mv_dump_xor_regs()
645 val = readl_relaxed(XOR_INTR_MASK(chan)); in mv_dump_xor_regs()
648 val = readl_relaxed(XOR_ERROR_CAUSE(chan)); in mv_dump_xor_regs()
[all …]
Dk3dma.c120 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
124 val = readl_relaxed(phy->base + CX_CFG); in k3_dma_pause_dma()
156 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10); in k3_dma_get_curr_cnt()
163 return readl_relaxed(phy->base + CX_LLI); in k3_dma_get_curr_lli()
168 return readl_relaxed(d->base + CH_STAT); in k3_dma_get_chan_stat()
194 u32 stat = readl_relaxed(d->base + INT_STAT); in k3_dma_int_handler()
195 u32 tc1 = readl_relaxed(d->base + INT_TC1); in k3_dma_int_handler()
196 u32 err1 = readl_relaxed(d->base + INT_ERR1); in k3_dma_int_handler()
197 u32 err2 = readl_relaxed(d->base + INT_ERR2); in k3_dma_int_handler()
Dqcom_bam_dma.c469 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); in bam_chan_init_hw()
546 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); in bam_free_chan()
738 srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE)); in process_channel_irqs()
751 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS)); in process_channel_irqs()
804 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); in bam_dma_irq()
1028 val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)) >> NUM_EES_SHIFT; in bam_init()
1035 val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES)); in bam_init()
1040 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); in bam_init()
Dimx-sdma.c480 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
481 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
482 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
521 while (!(ret = readl_relaxed(sdma->regs + SDMA_H_INTR) & 1)) { in sdma_run_channel0()
583 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
595 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
672 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
/linux-4.1.27/arch/arm/mach-mmp/
Ddevices.c83 return readl_relaxed(base + offset); in u2o_get()
91 reg = readl_relaxed(base + offset); in u2o_set()
94 readl_relaxed(base + offset); in u2o_set()
102 reg = readl_relaxed(base + offset); in u2o_clear()
105 readl_relaxed(base + offset); in u2o_clear()
112 readl_relaxed(base + offset); in u2o_write()
/linux-4.1.27/arch/arm/mach-ux500/
Dpm.c97 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4); in prcmu_gic_pending_irq()
98 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); in prcmu_gic_pending_irq()
151 er = readl_relaxed(dist_base + in prcmu_copy_gic_settings()
/linux-4.1.27/arch/arm/mach-orion5x/
Dirq.c42 stat = readl_relaxed(MAIN_IRQ_CAUSE); in orion5x_legacy_handle_irq()
43 stat &= readl_relaxed(MAIN_IRQ_MASK); in orion5x_legacy_handle_irq()
/linux-4.1.27/drivers/clk/spear/
Dclk-vco-pll.c134 p = readl_relaxed(pll->vco->cfg_reg); in clk_pll_recalc_rate()
157 val = readl_relaxed(pll->vco->cfg_reg); in clk_pll_set_rate()
202 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; in clk_vco_recalc_rate()
204 val = readl_relaxed(vco->cfg_reg); in clk_vco_recalc_rate()
244 val = readl_relaxed(vco->mode_reg); in clk_vco_set_rate()
249 val = readl_relaxed(vco->cfg_reg); in clk_vco_set_rate()
Dclk-frac-synth.c78 val = readl_relaxed(frac->reg); in clk_frac_recalc_rate()
109 val = readl_relaxed(frac->reg) & ~DIV_FACTOR_MASK; in clk_frac_set_rate()
Dclk-aux-synth.c75 val = readl_relaxed(aux->reg); in clk_aux_recalc_rate()
113 val = readl_relaxed(aux->reg) & in clk_aux_set_rate()
Dclk-gpt-synth.c65 val = readl_relaxed(gpt->reg); in clk_gpt_recalc_rate()
/linux-4.1.27/drivers/media/rc/
Dir-hix5hd2.c95 while (readl_relaxed(priv->base + IR_BUSY)) { in hix5hd2_ir_config()
142 irq_sr = readl_relaxed(priv->base + IR_INTS); in hix5hd2_ir_rx_interrupt()
150 symb_num = readl_relaxed(priv->base + IR_DATAH); in hix5hd2_ir_rx_interrupt()
152 readl_relaxed(priv->base + IR_DATAL); in hix5hd2_ir_rx_interrupt()
162 symb_num = readl_relaxed(priv->base + IR_DATAH); in hix5hd2_ir_rx_interrupt()
164 symb_val = readl_relaxed(priv->base + IR_DATAL); in hix5hd2_ir_rx_interrupt()
/linux-4.1.27/drivers/spi/
Dspi-st-ssc4.c133 word = readl_relaxed(spi_st->base + SSC_RBUF); in ssc_read_rx_fifo()
174 ctl = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_transfer_one()
177 readl_relaxed(spi_st->base + SSC_RBUF); in spi_st_transfer_one()
260 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_setup()
292 readl_relaxed(spi_st->base + SSC_RBUF); in spi_st_setup()
372 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
377 var = readl_relaxed(spi_st->base + SSC_CTL); in spi_st_probe()
Dspi-qup.c160 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
183 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
221 state = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_fifo_read()
225 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_fifo_read()
257 state = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_fifo_write()
391 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
392 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
393 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
533 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
547 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
[all …]
Dspi-rockchip.c216 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) in flush_fifo()
217 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); in flush_fifo()
225 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) in wait_for_idle()
238 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) in get_fifo_len()
252 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); in tx_max()
260 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); in rx_max()
270 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; in rockchip_spi_set_cs()
365 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); in rockchip_spi_pio_reader()
570 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && in rockchip_spi_transfer_one()
571 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); in rockchip_spi_transfer_one()
Dspi-omap2-mcspi.c165 return readl_relaxed(mcspi->base + idx); in mcspi_read_reg()
180 return readl_relaxed(cs->base + idx); in mcspi_read_cs_reg()
354 while (!(readl_relaxed(reg) & bit)) { in mcspi_wait_for_reg_bit()
356 if (!(readl_relaxed(reg) & bit)) in mcspi_wait_for_reg_bit()
695 *rx++ = readl_relaxed(rx_reg); in omap2_mcspi_txrx_pio()
709 *rx++ = readl_relaxed(rx_reg); in omap2_mcspi_txrx_pio()
742 *rx++ = readl_relaxed(rx_reg); in omap2_mcspi_txrx_pio()
756 *rx++ = readl_relaxed(rx_reg); in omap2_mcspi_txrx_pio()
789 *rx++ = readl_relaxed(rx_reg); in omap2_mcspi_txrx_pio()
803 *rx++ = readl_relaxed(rx_reg); in omap2_mcspi_txrx_pio()
/linux-4.1.27/drivers/pinctrl/spear/
Dpinctrl-plgpio.c84 u32 val = readl_relaxed(reg_off); in is_plgpio_set()
93 u32 val = readl_relaxed(reg_off); in plgpio_reg_set()
102 u32 val = readl_relaxed(reg_off); in plgpio_reg_reset()
341 val = readl_relaxed(reg_off); in plgpio_irq_set_type()
373 pending = readl_relaxed(plgpio->base + plgpio->regs.mis + in plgpio_irq_handler()
629 readl_relaxed(plgpio->regs.enb + off); in plgpio_suspend()
632 readl_relaxed(plgpio->regs.eit + off); in plgpio_suspend()
633 plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata + in plgpio_suspend()
635 plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir + in plgpio_suspend()
637 plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off); in plgpio_suspend()
[all …]
/linux-4.1.27/drivers/clk/tegra/
Dclk-pll-out.c33 u32 val = readl_relaxed(pll_out->reg); in clk_pll_out_is_enabled()
51 val = readl_relaxed(pll_out->reg); in clk_pll_out_enable()
73 val = readl_relaxed(pll_out->reg); in clk_pll_out_disable()
Dclk-periph-gate.c32 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
39 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
Dclk-super.c49 val = readl_relaxed(mux->reg); in clk_super_get_parent()
83 val = readl_relaxed(mux->reg); in clk_super_set_parent()
Dclk-divider.c75 reg = readl_relaxed(divider->reg) >> divider->shift; in clk_frac_div_recalc_rate()
122 val = readl_relaxed(divider->reg); in clk_frac_div_set_rate()
Dclk-tegra114.c980 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
1000 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1018 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1024 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1033 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1041 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1334 readl_relaxed(clk_base + CPU_FINETRIM_SELECT); in tegra114_car_barrier()
1425 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra114_clock_assert_dfll_dvco_reset()
1442 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra114_clock_deassert_dfll_dvco_reset()
Dclk-tegra-fixed.c43 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
Dclk-tegra124.c1040 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2); in tegra124_utmi_param_configure()
1060 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1078 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1084 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1); in tegra124_utmi_param_configure()
1093 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
1101 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra124_utmi_param_configure()
Dclk-pll.c186 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
189 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
258 val = readl_relaxed(lock_addr); in clk_pll_wait_for_lock()
278 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in clk_pll_is_enabled()
302 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
320 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
1588 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
1589 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
/linux-4.1.27/drivers/video/fbdev/
Dsa1100fb.c706 if (readl_relaxed(fbi->base + LCCR0) != fbi->reg_lccr0 || in sa1100fb_activate_var()
707 readl_relaxed(fbi->base + LCCR1) != fbi->reg_lccr1 || in sa1100fb_activate_var()
708 readl_relaxed(fbi->base + LCCR2) != fbi->reg_lccr2 || in sa1100fb_activate_var()
709 readl_relaxed(fbi->base + LCCR3) != fbi->reg_lccr3 || in sa1100fb_activate_var()
710 readl_relaxed(fbi->base + DBAR1) != fbi->dbar1 || in sa1100fb_activate_var()
711 readl_relaxed(fbi->base + DBAR2) != fbi->dbar2) in sa1100fb_activate_var()
807 dev_dbg(fbi->dev, "DBAR1: 0x%08x\n", readl_relaxed(fbi->base + DBAR1)); in sa1100fb_enable_controller()
808 dev_dbg(fbi->dev, "DBAR2: 0x%08x\n", readl_relaxed(fbi->base + DBAR2)); in sa1100fb_enable_controller()
809 dev_dbg(fbi->dev, "LCCR0: 0x%08x\n", readl_relaxed(fbi->base + LCCR0)); in sa1100fb_enable_controller()
810 dev_dbg(fbi->dev, "LCCR1: 0x%08x\n", readl_relaxed(fbi->base + LCCR1)); in sa1100fb_enable_controller()
[all …]
/linux-4.1.27/drivers/soc/tegra/fuse/
Dtegra-apbmisc.c36 return readl_relaxed(apbmisc_base + 4); in tegra_read_chipid()
52 return readl_relaxed(strapping_base); in tegra_read_straps()
Dfuse-tegra.c92 reg = readl_relaxed(base + 0x48); in tegra_enable_fuse_clk()
Dfuse-tegra30.c73 val = readl_relaxed(fuse_base + FUSE_BEGIN + offset); in tegra30_fuse_readl()
Dfuse-tegra20.c175 return readl_relaxed(fuse_base + FUSE_BEGIN + offset); in tegra20_fuse_early()
/linux-4.1.27/drivers/clk/rockchip/
Dclk-pll.c137 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3)); in rockchip_rk3066_pll_recalc_rate()
144 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_recalc_rate()
147 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_recalc_rate()
279 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0)); in rockchip_rk3066_pll_init()
283 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1)); in rockchip_rk3066_pll_init()
286 pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2)); in rockchip_rk3066_pll_init()
/linux-4.1.27/drivers/crypto/ux500/hash/
Dhash_core.c656 __func__, readl_relaxed(&device_data->base->din), in hash_messagepad()
657 readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK); in hash_messagepad()
660 __func__, readl_relaxed(&device_data->base->din), in hash_messagepad()
661 readl_relaxed(&device_data->base->str) & HASH_STR_NBLW_MASK); in hash_messagepad()
1217 temp_cr = readl_relaxed(&device_data->base->cr); in hash_save_state()
1219 device_state->str_reg = readl_relaxed(&device_data->base->str); in hash_save_state()
1221 device_state->din_reg = readl_relaxed(&device_data->base->din); in hash_save_state()
1233 readl_relaxed(&device_data->base->csrx[count]); in hash_save_state()
1236 device_state->csfull = readl_relaxed(&device_data->base->csfull); in hash_save_state()
1237 device_state->csdatain = readl_relaxed(&device_data->base->csdatain); in hash_save_state()
[all …]
Dhash_alg.h99 writel_relaxed((readl_relaxed(reg_name) | mask), reg_name)
102 writel_relaxed((readl_relaxed(reg_name) & ~mask), reg_name)
/linux-4.1.27/drivers/input/keyboard/
Dspear-keyboard.c76 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
86 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
125 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
138 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_close()
304 mode_ctl_reg = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_suspend()
/linux-4.1.27/arch/arm/plat-orion/
Dgpio.c453 out = readl_relaxed(GPIO_OUT(ochip)); in orion_gpio_dbg_show()
454 io_conf = readl_relaxed(GPIO_IO_CONF(ochip)); in orion_gpio_dbg_show()
455 blink = readl_relaxed(GPIO_BLINK_EN(ochip)); in orion_gpio_dbg_show()
456 in_pol = readl_relaxed(GPIO_IN_POL(ochip)); in orion_gpio_dbg_show()
457 data_in = readl_relaxed(GPIO_DATA_IN(ochip)); in orion_gpio_dbg_show()
458 cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip)); in orion_gpio_dbg_show()
459 edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); in orion_gpio_dbg_show()
460 lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); in orion_gpio_dbg_show()
/linux-4.1.27/drivers/net/ethernet/hisilicon/
Dhip04_mdio.c37 for (i = 0; readl_relaxed(priv->base + MDIO_CMD_REG) & MDIO_START; i++) { in hip04_mdio_wait_ready()
63 val = readl_relaxed(priv->base + MDIO_STA_REG); in hip04_mdio_read()
70 val = readl_relaxed(priv->base + MDIO_RDATA_REG); in hip04_mdio_read()
Dhix5hd2_gmac.c422 start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR)); in hix5hd2_rx_refill()
424 end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR)); in hix5hd2_rx_refill()
466 start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR)); in hix5hd2_rx()
468 end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR)); in hix5hd2_rx()
528 start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR)); in hix5hd2_xmit_reclaim()
530 end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR)); in hix5hd2_xmit_reclaim()
578 ints = readl_relaxed(priv->base + RAW_PMU_INT); in hix5hd2_poll()
594 int ints = readl_relaxed(priv->base + RAW_PMU_INT); in hix5hd2_interrupt()
613 pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR)); in hix5hd2_net_xmit()
788 for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) { in hix5hd2_mdio_wait_ready()
[all …]
Dhip04_eth.c244 val = readl_relaxed(priv->base + PPE_CFG_STS_MODE); in hip04_config_fifo()
281 val = readl_relaxed(priv->base + GE_TRANSMIT_CONTROL_REG); in hip04_config_fifo()
288 val = readl_relaxed(priv->base + GE_RECV_CONTROL_REG); in hip04_config_fifo()
302 val = readl_relaxed(priv->base + GE_PORT_EN); in hip04_mac_enable()
329 val = readl_relaxed(priv->base + GE_PORT_EN); in hip04_mac_disable()
570 u32 ists = readl_relaxed(priv->base + PPE_INTSTS); in hip04_mac_interrupt()
/linux-4.1.27/arch/arm/mach-bcm/
Dboard_bcm2835.c64 val = readl_relaxed(wdt_regs + PM_RSTC); in bcm2835_restart()
87 val = readl_relaxed(wdt_regs + PM_RSTS); in bcm2835_power_off()
Dplatsmp-brcmstb.c93 return readl_relaxed(base); in pwr_ctrl_rd()
130 val = readl_relaxed(cpubiuctrl_block + cpu_rst_cfg_reg); in cpu_rst_cfg_set()
Dkona_smp.c184 while (!timeout && readl_relaxed(boot_reg) == boot_val) in bcm_boot_secondary()
/linux-4.1.27/arch/arm/mach-shmobile/
Dpm-rcar-gen2.c100 writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) | in rcar_gen2_pm_init()
108 writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) | in rcar_gen2_pm_init()
Dplatsmp-apmu.c43 while (readl_relaxed(p + WUPCR_OFFS) != 0) in apmu_power_on()
61 if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3) in apmu_power_off_poll()
/linux-4.1.27/arch/arm/mach-prima2/
Drtciobrg.c36 while (readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_CTRL)) in sirfsoc_rtc_iobrg_wait_sync()
62 return readl_relaxed(sirfsoc_rtciobrg_base + SIRFSOC_CPUIOBRG_DATA); in __sirfsoc_rtc_iobrg_readl()
/linux-4.1.27/arch/arm/plat-omap/include/plat/
Ddmtimer.h283 while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) in __omap_dm_timer_read()
286 return readl_relaxed(timer->func_base + (reg & 0xff)); in __omap_dm_timer_read()
293 while (readl_relaxed(timer->pend) & (reg >> WPSHIFT)) in __omap_dm_timer_write()
304 tidr = readl_relaxed(timer->io_base); in __omap_dm_timer_init_regs()
/linux-4.1.27/drivers/iommu/
Darm-smmu.c535 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) in __arm_smmu_tlb_sync()
653 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); in arm_smmu_context_fault()
663 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); in arm_smmu_context_fault()
666 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); in arm_smmu_context_fault()
669 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); in arm_smmu_context_fault()
700 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
701 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); in arm_smmu_global_fault()
702 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); in arm_smmu_global_fault()
703 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); in arm_smmu_global_fault()
1253 phys = readl_relaxed(cb_base + ARM_SMMU_CB_PAR_LO); in arm_smmu_iova_to_phys_hard()
[all …]
/linux-4.1.27/drivers/clk/mxs/
Dclk-imx28.c99 val = readl_relaxed(SAIF0); in clk_misc_init()
103 val = readl_relaxed(SAIF1); in clk_misc_init()
108 val = readl_relaxed(ENET); in clk_misc_init()
122 val = readl_relaxed(FRAC0); in clk_misc_init()
Dclk-frac.c46 div = readl_relaxed(frac->reg) >> frac->shift; in clk_frac_recalc_rate()
95 val = readl_relaxed(frac->reg); in clk_frac_set_rate()
Dclk-ref.c59 u8 frac = (readl_relaxed(ref->reg) >> (ref->idx * 8)) & 0x3f; in clk_ref_recalc_rate()
110 val = readl_relaxed(ref->reg); in clk_ref_set_rate()
Dclk.c24 while (readl_relaxed(reg) & (1 << shift)) in mxs_clk_wait()
/linux-4.1.27/drivers/spmi/
Dspmi-pmic-arb.c173 return readl_relaxed(dev->rd_base + offset); in pmic_arb_base_read()
223 status = readl_relaxed(base + offset); in pmic_arb_wait_for_done()
442 status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid)); in periph_interrupt()
467 status = readl_relaxed(intr + in pmic_arb_chained_irq()
505 status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); in qpnpint_irq_mask()
527 status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); in qpnpint_irq_unmask()
805 hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); in spmi_pmic_arb_probe()
849 regval = readl_relaxed(core + PMIC_ARB_REG_CHNL(chan)); in spmi_pmic_arb_probe()
907 pa->mapping_table[i] = readl_relaxed( in spmi_pmic_arb_probe()
/linux-4.1.27/drivers/clk/samsung/
Dclk-exynos5440.c101 status = readl_relaxed(reg_base + 0xbc); in exynos5440_clk_restart_notify()
102 val = readl_relaxed(reg_base + 0xcc); in exynos5440_clk_restart_notify()
Dclk-s3c2410-dclk.c63 val = readl_relaxed(S3C24XX_MISCCR) >> clkout->shift; in s3c24xx_clkout_get_parent()
174 dclk_con = readl_relaxed(s3c24xx_dclk->base); in s3c24xx_dclk_update_cmp()
219 s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base); in s3c24xx_dclk_suspend()
/linux-4.1.27/drivers/mfd/
Dmcp-sa11x0.c88 if (readl_relaxed(MCSR(m)) & MCSR_CWC) { in mcp_sa11x0_write()
115 if (readl_relaxed(MCSR(m)) & MCSR_CRC) { in mcp_sa11x0_read()
116 ret = readl_relaxed(MCDR2(m)) & 0xffff; in mcp_sa11x0_read()
/linux-4.1.27/drivers/cpufreq/
Dkirkwood-cpufreq.c63 reg = readl_relaxed(priv.base); in kirkwood_cpufreq_target()
80 reg = readl_relaxed(priv.base); in kirkwood_cpufreq_target()
/linux-4.1.27/arch/arm/mach-spear/include/mach/
Duncompress.h27 while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF) in putc()
/linux-4.1.27/arch/m68k/include/asm/
Dio.h9 #define readl_relaxed(addr) readl(addr) macro
/linux-4.1.27/include/linux/
Diopoll.h133 readx_poll_timeout(readl_relaxed, addr, val, cond, delay_us, timeout_us)
136 readx_poll_timeout_atomic(readl_relaxed, addr, val, cond, delay_us, timeout_us)
/linux-4.1.27/arch/unicore32/include/asm/
Dio.h44 #define readl_relaxed readl macro
/linux-4.1.27/arch/arm/mach-tegra/
Dirq.c44 pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET); in tegra_pending_sgi()
Dflowctrl.c54 readl_relaxed(tegra_flowctrl_base + offset); in flowctrl_update()
/linux-4.1.27/drivers/pwm/
Dpwm-spear.c67 return readl_relaxed(chip->mmio_base + (num << 4) + offset); in spear_pwm_readl()
215 val = readl_relaxed(pc->mmio_base + PWMMCR); in spear_pwm_probe()
Dpwm-rockchip.c68 val = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_set_enable_v1()
91 val = readl_relaxed(pc->base + pc->data->regs.ctrl); in rockchip_pwm_set_enable_v2()
Dpwm-atmel.c75 return readl_relaxed(chip->base + offset); in atmel_pwm_readl()
89 return readl_relaxed(chip->base + base + offset); in atmel_pwm_ch_readl()
/linux-4.1.27/drivers/net/irda/
Dpxaficp_ir.c295 si->last_oscr = readl_relaxed(OSCR); in pxa_irda_sir_irq()
306 si->last_oscr = readl_relaxed(OSCR); in pxa_irda_sir_irq()
322 si->last_oscr = readl_relaxed(OSCR); in pxa_irda_sir_irq()
376 si->last_oscr = readl_relaxed(OSCR); in pxa_irda_fir_dma_tx_irq()
476 si->last_oscr = readl_relaxed(OSCR); in pxa_irda_fir_irq()
552 while ((unsigned)(readl_relaxed(OSCR) - si->last_oscr)/4 < mtt) in pxa_irda_hard_xmit()
/linux-4.1.27/arch/arm/mach-pxa/
Dreset.c84 writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3); in do_hw_reset()
/linux-4.1.27/arch/nios2/include/asm/
Dio.h22 #define readl_relaxed(addr) readl(addr) macro
/linux-4.1.27/arch/arm64/include/asm/
Dio.h122 #define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32)__raw_readl(c)); __v; }) macro
137 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
/linux-4.1.27/drivers/pinctrl/vt8500/
Dpinctrl-wmt.c40 val = readl_relaxed(data->base + reg); in wmt_setbits()
50 val = readl_relaxed(data->base + reg); in wmt_clearbits()
507 val = readl_relaxed(data->base + reg_dir); in wmt_gpio_get_direction()
526 return !!(readl_relaxed(data->base + reg_data_in) & BIT(bit)); in wmt_gpio_get_value()
/linux-4.1.27/drivers/net/ethernet/cadence/
Dmacb.h431 readl_relaxed((port)->regs + MACB_##reg)
435 readl_relaxed((port)->regs + GEM_##reg)
439 readl_relaxed((queue)->bp->regs + (queue)->reg)
839 return !!(MACB_BFEXT(IDNUM, readl_relaxed(addr + MACB_MID)) >= 0x2); in macb_is_gem_hw()
/linux-4.1.27/arch/arc/include/asm/
Dio.h103 #define readl_relaxed readl macro
/linux-4.1.27/arch/ia64/include/asm/
Dmachvec.h150 # define platform_readl_relaxed ia64_mv.readl_relaxed
194 ia64_mv_readl_relaxed_t *readl_relaxed; member
Dio.h382 #define readl_relaxed(a) __readl_relaxed((a)) macro
390 #define __raw_readl_relaxed readl_relaxed
/linux-4.1.27/drivers/gpu/drm/armada/
Darmada_drm.h26 ov = v = readl_relaxed(ptr); in armada_updatel()
Darmada_crtc.c99 val &= readl_relaxed(reg); in armada_drm_crtc_update_regs()
386 val = readl_relaxed(base + LCD_SPU_ADV_REG); in armada_drm_crtc_irq()
421 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq()
453 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) in armada_drm_crtc_enable_irq()
702 readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); in armada_load_cursor_argb()
777 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_cursor_update()
/linux-4.1.27/drivers/tty/serial/
Dmsm_serial.h137 return readl_relaxed(port->membase + off); in msm_read()
/linux-4.1.27/include/linux/clk/
Dat91_pmc.h23 readl_relaxed(at91_pmc_base + field)
/linux-4.1.27/arch/arm/mach-ebsa110/include/mach/
Dio.h59 #define readl_relaxed(addr) readl(addr) macro
/linux-4.1.27/arch/m32r/include/asm/
Dio.h157 #define readl_relaxed readl macro
/linux-4.1.27/arch/sh/include/asm/
Dio.h40 #define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; }) macro
50 #define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
/linux-4.1.27/arch/arm/include/asm/
Dio.h299 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \ macro
308 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
/linux-4.1.27/drivers/soc/ti/
Dknav_qmss_queue.c408 return readl_relaxed(&qh->reg_peek[0].entry_count) + in knav_queue_get_count()
476 val = readl_relaxed(addr); in knav_queue_pdsp_wait()
655 val = readl_relaxed(&qh->reg_pop[0].ptr_size_thresh); in knav_queue_pop()
1505 val = readl_relaxed(&pdsp->regs->control) & ~PDSP_CTRL_ENABLE; in knav_queue_stop_pdsp()
1548 while (readl_relaxed(pdsp->command) != 0xffffffff) in knav_queue_start_pdsp()
1552 val = readl_relaxed(&pdsp->regs->control); in knav_queue_start_pdsp()
1557 val = readl_relaxed(&pdsp->regs->control) | PDSP_CTRL_ENABLE; in knav_queue_start_pdsp()

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