1/*
2 * Hisilicon HiP04 INTC
3 *
4 * Copyright (C) 2002-2014 ARM Limited.
5 * Copyright (c) 2013-2014 Hisilicon Ltd.
6 * Copyright (c) 2013-2014 Linaro Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Interrupt architecture for the HIP04 INTC:
13 *
14 * o There is one Interrupt Distributor, which receives interrupts
15 *   from system devices and sends them to the Interrupt Controllers.
16 *
17 * o There is one CPU Interface per CPU, which sends interrupts sent
18 *   by the Distributor, and interrupts generated locally, to the
19 *   associated CPU. The base address of the CPU interface is usually
20 *   aliased so that the same address points to different chips depending
21 *   on the CPU it is accessed from.
22 *
23 * Note that IRQs 0-31 are special - they are local to each CPU.
24 * As such, the enable set/clear, pending set/clear and active bit
25 * registers are banked per-cpu for these sources.
26 */
27
28#include <linux/init.h>
29#include <linux/kernel.h>
30#include <linux/err.h>
31#include <linux/module.h>
32#include <linux/list.h>
33#include <linux/smp.h>
34#include <linux/cpu.h>
35#include <linux/cpu_pm.h>
36#include <linux/cpumask.h>
37#include <linux/io.h>
38#include <linux/of.h>
39#include <linux/of_address.h>
40#include <linux/of_irq.h>
41#include <linux/irqdomain.h>
42#include <linux/interrupt.h>
43#include <linux/slab.h>
44#include <linux/irqchip/arm-gic.h>
45
46#include <asm/irq.h>
47#include <asm/exception.h>
48#include <asm/smp_plat.h>
49
50#include "irq-gic-common.h"
51#include "irqchip.h"
52
53#define HIP04_MAX_IRQS		510
54
55struct hip04_irq_data {
56	void __iomem *dist_base;
57	void __iomem *cpu_base;
58	struct irq_domain *domain;
59	unsigned int nr_irqs;
60};
61
62static DEFINE_RAW_SPINLOCK(irq_controller_lock);
63
64/*
65 * The GIC mapping of CPU interfaces does not necessarily match
66 * the logical CPU numbering.  Let's use a mapping as returned
67 * by the GIC itself.
68 */
69#define NR_HIP04_CPU_IF 16
70static u16 hip04_cpu_map[NR_HIP04_CPU_IF] __read_mostly;
71
72static struct hip04_irq_data hip04_data __read_mostly;
73
74static inline void __iomem *hip04_dist_base(struct irq_data *d)
75{
76	struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
77	return hip04_data->dist_base;
78}
79
80static inline void __iomem *hip04_cpu_base(struct irq_data *d)
81{
82	struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
83	return hip04_data->cpu_base;
84}
85
86static inline unsigned int hip04_irq(struct irq_data *d)
87{
88	return d->hwirq;
89}
90
91/*
92 * Routines to acknowledge, disable and enable interrupts
93 */
94static void hip04_mask_irq(struct irq_data *d)
95{
96	u32 mask = 1 << (hip04_irq(d) % 32);
97
98	raw_spin_lock(&irq_controller_lock);
99	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
100		       (hip04_irq(d) / 32) * 4);
101	raw_spin_unlock(&irq_controller_lock);
102}
103
104static void hip04_unmask_irq(struct irq_data *d)
105{
106	u32 mask = 1 << (hip04_irq(d) % 32);
107
108	raw_spin_lock(&irq_controller_lock);
109	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET +
110		       (hip04_irq(d) / 32) * 4);
111	raw_spin_unlock(&irq_controller_lock);
112}
113
114static void hip04_eoi_irq(struct irq_data *d)
115{
116	writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI);
117}
118
119static int hip04_irq_set_type(struct irq_data *d, unsigned int type)
120{
121	void __iomem *base = hip04_dist_base(d);
122	unsigned int irq = hip04_irq(d);
123	int ret;
124
125	/* Interrupt configuration for SGIs can't be changed */
126	if (irq < 16)
127		return -EINVAL;
128
129	/* SPIs have restrictions on the supported types */
130	if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
131			 type != IRQ_TYPE_EDGE_RISING)
132		return -EINVAL;
133
134	raw_spin_lock(&irq_controller_lock);
135
136	ret = gic_configure_irq(irq, type, base, NULL);
137
138	raw_spin_unlock(&irq_controller_lock);
139
140	return ret;
141}
142
143#ifdef CONFIG_SMP
144static int hip04_irq_set_affinity(struct irq_data *d,
145				  const struct cpumask *mask_val,
146				  bool force)
147{
148	void __iomem *reg;
149	unsigned int cpu, shift = (hip04_irq(d) % 2) * 16;
150	u32 val, mask, bit;
151
152	if (!force)
153		cpu = cpumask_any_and(mask_val, cpu_online_mask);
154	else
155		cpu = cpumask_first(mask_val);
156
157	if (cpu >= NR_HIP04_CPU_IF || cpu >= nr_cpu_ids)
158		return -EINVAL;
159
160	raw_spin_lock(&irq_controller_lock);
161	reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3);
162	mask = 0xffff << shift;
163	bit = hip04_cpu_map[cpu] << shift;
164	val = readl_relaxed(reg) & ~mask;
165	writel_relaxed(val | bit, reg);
166	raw_spin_unlock(&irq_controller_lock);
167
168	return IRQ_SET_MASK_OK;
169}
170#endif
171
172static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)
173{
174	u32 irqstat, irqnr;
175	void __iomem *cpu_base = hip04_data.cpu_base;
176
177	do {
178		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
179		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
180
181		if (likely(irqnr > 15 && irqnr <= HIP04_MAX_IRQS)) {
182			handle_domain_irq(hip04_data.domain, irqnr, regs);
183			continue;
184		}
185		if (irqnr < 16) {
186			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
187#ifdef CONFIG_SMP
188			handle_IPI(irqnr, regs);
189#endif
190			continue;
191		}
192		break;
193	} while (1);
194}
195
196static struct irq_chip hip04_irq_chip = {
197	.name			= "HIP04 INTC",
198	.irq_mask		= hip04_mask_irq,
199	.irq_unmask		= hip04_unmask_irq,
200	.irq_eoi		= hip04_eoi_irq,
201	.irq_set_type		= hip04_irq_set_type,
202#ifdef CONFIG_SMP
203	.irq_set_affinity	= hip04_irq_set_affinity,
204#endif
205};
206
207static u16 hip04_get_cpumask(struct hip04_irq_data *intc)
208{
209	void __iomem *base = intc->dist_base;
210	u32 mask, i;
211
212	for (i = mask = 0; i < 32; i += 2) {
213		mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2);
214		mask |= mask >> 16;
215		if (mask)
216			break;
217	}
218
219	if (!mask)
220		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
221
222	return mask;
223}
224
225static void __init hip04_irq_dist_init(struct hip04_irq_data *intc)
226{
227	unsigned int i;
228	u32 cpumask;
229	unsigned int nr_irqs = intc->nr_irqs;
230	void __iomem *base = intc->dist_base;
231
232	writel_relaxed(0, base + GIC_DIST_CTRL);
233
234	/*
235	 * Set all global interrupts to this CPU only.
236	 */
237	cpumask = hip04_get_cpumask(intc);
238	cpumask |= cpumask << 16;
239	for (i = 32; i < nr_irqs; i += 2)
240		writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3));
241
242	gic_dist_config(base, nr_irqs, NULL);
243
244	writel_relaxed(1, base + GIC_DIST_CTRL);
245}
246
247static void hip04_irq_cpu_init(struct hip04_irq_data *intc)
248{
249	void __iomem *dist_base = intc->dist_base;
250	void __iomem *base = intc->cpu_base;
251	unsigned int cpu_mask, cpu = smp_processor_id();
252	int i;
253
254	/*
255	 * Get what the GIC says our CPU mask is.
256	 */
257	BUG_ON(cpu >= NR_HIP04_CPU_IF);
258	cpu_mask = hip04_get_cpumask(intc);
259	hip04_cpu_map[cpu] = cpu_mask;
260
261	/*
262	 * Clear our mask from the other map entries in case they're
263	 * still undefined.
264	 */
265	for (i = 0; i < NR_HIP04_CPU_IF; i++)
266		if (i != cpu)
267			hip04_cpu_map[i] &= ~cpu_mask;
268
269	gic_cpu_config(dist_base, NULL);
270
271	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
272	writel_relaxed(1, base + GIC_CPU_CTRL);
273}
274
275#ifdef CONFIG_SMP
276static void hip04_raise_softirq(const struct cpumask *mask, unsigned int irq)
277{
278	int cpu;
279	unsigned long flags, map = 0;
280
281	raw_spin_lock_irqsave(&irq_controller_lock, flags);
282
283	/* Convert our logical CPU mask into a physical one. */
284	for_each_cpu(cpu, mask)
285		map |= hip04_cpu_map[cpu];
286
287	/*
288	 * Ensure that stores to Normal memory are visible to the
289	 * other CPUs before they observe us issuing the IPI.
290	 */
291	dmb(ishst);
292
293	/* this always happens on GIC0 */
294	writel_relaxed(map << 8 | irq, hip04_data.dist_base + GIC_DIST_SOFTINT);
295
296	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
297}
298#endif
299
300static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq,
301				irq_hw_number_t hw)
302{
303	if (hw < 32) {
304		irq_set_percpu_devid(irq);
305		irq_set_chip_and_handler(irq, &hip04_irq_chip,
306					 handle_percpu_devid_irq);
307		set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
308	} else {
309		irq_set_chip_and_handler(irq, &hip04_irq_chip,
310					 handle_fasteoi_irq);
311		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
312	}
313	irq_set_chip_data(irq, d->host_data);
314	return 0;
315}
316
317static int hip04_irq_domain_xlate(struct irq_domain *d,
318				  struct device_node *controller,
319				  const u32 *intspec, unsigned int intsize,
320				  unsigned long *out_hwirq,
321				  unsigned int *out_type)
322{
323	unsigned long ret = 0;
324
325	if (d->of_node != controller)
326		return -EINVAL;
327	if (intsize < 3)
328		return -EINVAL;
329
330	/* Get the interrupt number and add 16 to skip over SGIs */
331	*out_hwirq = intspec[1] + 16;
332
333	/* For SPIs, we need to add 16 more to get the irq ID number */
334	if (!intspec[0])
335		*out_hwirq += 16;
336
337	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
338
339	return ret;
340}
341
342#ifdef CONFIG_SMP
343static int hip04_irq_secondary_init(struct notifier_block *nfb,
344				    unsigned long action,
345				    void *hcpu)
346{
347	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
348		hip04_irq_cpu_init(&hip04_data);
349	return NOTIFY_OK;
350}
351
352/*
353 * Notifier for enabling the INTC CPU interface. Set an arbitrarily high
354 * priority because the GIC needs to be up before the ARM generic timers.
355 */
356static struct notifier_block hip04_irq_cpu_notifier = {
357	.notifier_call	= hip04_irq_secondary_init,
358	.priority	= 100,
359};
360#endif
361
362static const struct irq_domain_ops hip04_irq_domain_ops = {
363	.map	= hip04_irq_domain_map,
364	.xlate	= hip04_irq_domain_xlate,
365};
366
367static int __init
368hip04_of_init(struct device_node *node, struct device_node *parent)
369{
370	irq_hw_number_t hwirq_base = 16;
371	int nr_irqs, irq_base, i;
372
373	if (WARN_ON(!node))
374		return -ENODEV;
375
376	hip04_data.dist_base = of_iomap(node, 0);
377	WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n");
378
379	hip04_data.cpu_base = of_iomap(node, 1);
380	WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n");
381
382	/*
383	 * Initialize the CPU interface map to all CPUs.
384	 * It will be refined as each CPU probes its ID.
385	 */
386	for (i = 0; i < NR_HIP04_CPU_IF; i++)
387		hip04_cpu_map[i] = 0xffff;
388
389	/*
390	 * Find out how many interrupts are supported.
391	 * The HIP04 INTC only supports up to 510 interrupt sources.
392	 */
393	nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f;
394	nr_irqs = (nr_irqs + 1) * 32;
395	if (nr_irqs > HIP04_MAX_IRQS)
396		nr_irqs = HIP04_MAX_IRQS;
397	hip04_data.nr_irqs = nr_irqs;
398
399	nr_irqs -= hwirq_base; /* calculate # of irqs to allocate */
400
401	irq_base = irq_alloc_descs(-1, hwirq_base, nr_irqs, numa_node_id());
402	if (IS_ERR_VALUE(irq_base)) {
403		pr_err("failed to allocate IRQ numbers\n");
404		return -EINVAL;
405	}
406
407	hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base,
408						  hwirq_base,
409						  &hip04_irq_domain_ops,
410						  &hip04_data);
411
412	if (WARN_ON(!hip04_data.domain))
413		return -EINVAL;
414
415#ifdef CONFIG_SMP
416	set_smp_cross_call(hip04_raise_softirq);
417	register_cpu_notifier(&hip04_irq_cpu_notifier);
418#endif
419	set_handle_irq(hip04_handle_irq);
420
421	hip04_irq_dist_init(&hip04_data);
422	hip04_irq_cpu_init(&hip04_data);
423
424	return 0;
425}
426IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);
427