1/*
2 * OMAP4 specific common source file.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc.
5 * Author:
6 *	Santosh Shilimkar <santosh.shilimkar@ti.com>
7 *
8 *
9 * This program is free software,you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/irq.h>
18#include <linux/irqchip.h>
19#include <linux/platform_device.h>
20#include <linux/memblock.h>
21#include <linux/of_irq.h>
22#include <linux/of_platform.h>
23#include <linux/export.h>
24#include <linux/irqchip/arm-gic.h>
25#include <linux/of_address.h>
26#include <linux/reboot.h>
27#include <linux/genalloc.h>
28
29#include <asm/hardware/cache-l2x0.h>
30#include <asm/mach/map.h>
31#include <asm/memblock.h>
32#include <asm/smp_twd.h>
33
34#include "omap-wakeupgen.h"
35#include "soc.h"
36#include "iomap.h"
37#include "common.h"
38#include "prminst44xx.h"
39#include "prcm_mpu44xx.h"
40#include "omap4-sar-layout.h"
41#include "omap-secure.h"
42#include "sram.h"
43
44#ifdef CONFIG_CACHE_L2X0
45static void __iomem *l2cache_base;
46#endif
47
48static void __iomem *sar_ram_base;
49static void __iomem *gic_dist_base_addr;
50static void __iomem *twd_base;
51
52#define IRQ_LOCALTIMER		29
53
54void gic_dist_disable(void)
55{
56	if (gic_dist_base_addr)
57		writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
58}
59
60void gic_dist_enable(void)
61{
62	if (gic_dist_base_addr)
63		writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
64}
65
66bool gic_dist_disabled(void)
67{
68	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
69}
70
71void gic_timer_retrigger(void)
72{
73	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
74	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
75	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
76
77	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
78		/*
79		 * The local timer interrupt got lost while the distributor was
80		 * disabled.  Ack the pending interrupt, and retrigger it.
81		 */
82		pr_warn("%s: lost localtimer interrupt\n", __func__);
83		writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
84		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
85			writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
86			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
87			writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
88		}
89	}
90}
91
92#ifdef CONFIG_CACHE_L2X0
93
94void __iomem *omap4_get_l2cache_base(void)
95{
96	return l2cache_base;
97}
98
99void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
100{
101	unsigned smc_op;
102
103	switch (reg) {
104	case L2X0_CTRL:
105		smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
106		break;
107
108	case L2X0_AUX_CTRL:
109		smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
110		break;
111
112	case L2X0_DEBUG_CTRL:
113		smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
114		break;
115
116	case L310_PREFETCH_CTRL:
117		smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
118		break;
119
120	case L310_POWER_CTRL:
121		pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
122		return;
123
124	default:
125		WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
126		return;
127	}
128
129	omap_smc1(smc_op, val);
130}
131
132int __init omap_l2_cache_init(void)
133{
134	/* Static mapping, never released */
135	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
136	if (WARN_ON(!l2cache_base))
137		return -ENOMEM;
138	return 0;
139}
140#endif
141
142void __iomem *omap4_get_sar_ram_base(void)
143{
144	return sar_ram_base;
145}
146
147/*
148 * SAR RAM used to save and restore the HW
149 * context in low power modes
150 */
151static int __init omap4_sar_ram_init(void)
152{
153	unsigned long sar_base;
154
155	/*
156	 * To avoid code running on other OMAPs in
157	 * multi-omap builds
158	 */
159	if (cpu_is_omap44xx())
160		sar_base = OMAP44XX_SAR_RAM_BASE;
161	else if (soc_is_omap54xx())
162		sar_base = OMAP54XX_SAR_RAM_BASE;
163	else
164		return -ENOMEM;
165
166	/* Static mapping, never released */
167	sar_ram_base = ioremap(sar_base, SZ_16K);
168	if (WARN_ON(!sar_ram_base))
169		return -ENOMEM;
170
171	return 0;
172}
173omap_early_initcall(omap4_sar_ram_init);
174
175static const struct of_device_id intc_match[] = {
176	{ .compatible = "ti,omap4-wugen-mpu", },
177	{ .compatible = "ti,omap5-wugen-mpu", },
178	{ },
179};
180
181static struct device_node *intc_node;
182
183unsigned int omap4_xlate_irq(unsigned int hwirq)
184{
185	struct of_phandle_args irq_data;
186	unsigned int irq;
187
188	if (!intc_node)
189		intc_node = of_find_matching_node(NULL, intc_match);
190
191	if (WARN_ON(!intc_node))
192		return hwirq;
193
194	irq_data.np = intc_node;
195	irq_data.args_count = 3;
196	irq_data.args[0] = 0;
197	irq_data.args[1] = hwirq - OMAP44XX_IRQ_GIC_START;
198	irq_data.args[2] = IRQ_TYPE_LEVEL_HIGH;
199
200	irq = irq_create_of_mapping(&irq_data);
201	if (WARN_ON(!irq))
202		irq = hwirq;
203
204	return irq;
205}
206
207void __init omap_gic_of_init(void)
208{
209	struct device_node *np;
210
211	intc_node = of_find_matching_node(NULL, intc_match);
212	if (WARN_ON(!intc_node)) {
213		pr_err("No WUGEN found in DT, system will misbehave.\n");
214		pr_err("UPDATE YOUR DEVICE TREE!\n");
215	}
216
217	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
218	if (!cpu_is_omap446x())
219		goto skip_errata_init;
220
221	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
222	gic_dist_base_addr = of_iomap(np, 0);
223	WARN_ON(!gic_dist_base_addr);
224
225	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
226	twd_base = of_iomap(np, 0);
227	WARN_ON(!twd_base);
228
229skip_errata_init:
230	irqchip_init();
231}
232