1/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/jiffies.h>
19#include <linux/err.h>
20#include "clk.h"
21
22#define PLL_NUM_OFFSET		0x10
23#define PLL_DENOM_OFFSET	0x20
24
25#define BM_PLL_POWER		(0x1 << 12)
26#define BM_PLL_LOCK		(0x1 << 31)
27
28/**
29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw:	 clock source
31 * @base:	 base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL
33 * @div_mask:	 mask of divider bits
34 * @div_shift:	 shift of divider bits
35 *
36 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
37 * is actually a multiplier, and always sits at bit 0.
38 */
39struct clk_pllv3 {
40	struct clk_hw	hw;
41	void __iomem	*base;
42	bool		powerup_set;
43	u32		div_mask;
44	u32		div_shift;
45};
46
47#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
48
49static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
50{
51	unsigned long timeout = jiffies + msecs_to_jiffies(10);
52	u32 val = readl_relaxed(pll->base) & BM_PLL_POWER;
53
54	/* No need to wait for lock when pll is not powered up */
55	if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
56		return 0;
57
58	/* Wait for PLL to lock */
59	do {
60		if (readl_relaxed(pll->base) & BM_PLL_LOCK)
61			break;
62		if (time_after(jiffies, timeout))
63			break;
64		usleep_range(50, 500);
65	} while (1);
66
67	return readl_relaxed(pll->base) & BM_PLL_LOCK ? 0 : -ETIMEDOUT;
68}
69
70static int clk_pllv3_prepare(struct clk_hw *hw)
71{
72	struct clk_pllv3 *pll = to_clk_pllv3(hw);
73	u32 val;
74
75	val = readl_relaxed(pll->base);
76	if (pll->powerup_set)
77		val |= BM_PLL_POWER;
78	else
79		val &= ~BM_PLL_POWER;
80	writel_relaxed(val, pll->base);
81
82	return clk_pllv3_wait_lock(pll);
83}
84
85static void clk_pllv3_unprepare(struct clk_hw *hw)
86{
87	struct clk_pllv3 *pll = to_clk_pllv3(hw);
88	u32 val;
89
90	val = readl_relaxed(pll->base);
91	if (pll->powerup_set)
92		val &= ~BM_PLL_POWER;
93	else
94		val |= BM_PLL_POWER;
95	writel_relaxed(val, pll->base);
96}
97
98static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
99					   unsigned long parent_rate)
100{
101	struct clk_pllv3 *pll = to_clk_pllv3(hw);
102	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;
103
104	return (div == 1) ? parent_rate * 22 : parent_rate * 20;
105}
106
107static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
108				 unsigned long *prate)
109{
110	unsigned long parent_rate = *prate;
111
112	return (rate >= parent_rate * 22) ? parent_rate * 22 :
113					    parent_rate * 20;
114}
115
116static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
117		unsigned long parent_rate)
118{
119	struct clk_pllv3 *pll = to_clk_pllv3(hw);
120	u32 val, div;
121
122	if (rate == parent_rate * 22)
123		div = 1;
124	else if (rate == parent_rate * 20)
125		div = 0;
126	else
127		return -EINVAL;
128
129	val = readl_relaxed(pll->base);
130	val &= ~(pll->div_mask << pll->div_shift);
131	val |= (div << pll->div_shift);
132	writel_relaxed(val, pll->base);
133
134	return clk_pllv3_wait_lock(pll);
135}
136
137static const struct clk_ops clk_pllv3_ops = {
138	.prepare	= clk_pllv3_prepare,
139	.unprepare	= clk_pllv3_unprepare,
140	.recalc_rate	= clk_pllv3_recalc_rate,
141	.round_rate	= clk_pllv3_round_rate,
142	.set_rate	= clk_pllv3_set_rate,
143};
144
145static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
146					       unsigned long parent_rate)
147{
148	struct clk_pllv3 *pll = to_clk_pllv3(hw);
149	u32 div = readl_relaxed(pll->base) & pll->div_mask;
150
151	return parent_rate * div / 2;
152}
153
154static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
155				     unsigned long *prate)
156{
157	unsigned long parent_rate = *prate;
158	unsigned long min_rate = parent_rate * 54 / 2;
159	unsigned long max_rate = parent_rate * 108 / 2;
160	u32 div;
161
162	if (rate > max_rate)
163		rate = max_rate;
164	else if (rate < min_rate)
165		rate = min_rate;
166	div = rate * 2 / parent_rate;
167
168	return parent_rate * div / 2;
169}
170
171static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
172		unsigned long parent_rate)
173{
174	struct clk_pllv3 *pll = to_clk_pllv3(hw);
175	unsigned long min_rate = parent_rate * 54 / 2;
176	unsigned long max_rate = parent_rate * 108 / 2;
177	u32 val, div;
178
179	if (rate < min_rate || rate > max_rate)
180		return -EINVAL;
181
182	div = rate * 2 / parent_rate;
183	val = readl_relaxed(pll->base);
184	val &= ~pll->div_mask;
185	val |= div;
186	writel_relaxed(val, pll->base);
187
188	return clk_pllv3_wait_lock(pll);
189}
190
191static const struct clk_ops clk_pllv3_sys_ops = {
192	.prepare	= clk_pllv3_prepare,
193	.unprepare	= clk_pllv3_unprepare,
194	.recalc_rate	= clk_pllv3_sys_recalc_rate,
195	.round_rate	= clk_pllv3_sys_round_rate,
196	.set_rate	= clk_pllv3_sys_set_rate,
197};
198
199static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
200					      unsigned long parent_rate)
201{
202	struct clk_pllv3 *pll = to_clk_pllv3(hw);
203	u32 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
204	u32 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
205	u32 div = readl_relaxed(pll->base) & pll->div_mask;
206
207	return (parent_rate * div) + ((parent_rate / mfd) * mfn);
208}
209
210static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
211				    unsigned long *prate)
212{
213	unsigned long parent_rate = *prate;
214	unsigned long min_rate = parent_rate * 27;
215	unsigned long max_rate = parent_rate * 54;
216	u32 div;
217	u32 mfn, mfd = 1000000;
218	s64 temp64;
219
220	if (rate > max_rate)
221		rate = max_rate;
222	else if (rate < min_rate)
223		rate = min_rate;
224
225	div = rate / parent_rate;
226	temp64 = (u64) (rate - div * parent_rate);
227	temp64 *= mfd;
228	do_div(temp64, parent_rate);
229	mfn = temp64;
230
231	return parent_rate * div + parent_rate / mfd * mfn;
232}
233
234static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
235		unsigned long parent_rate)
236{
237	struct clk_pllv3 *pll = to_clk_pllv3(hw);
238	unsigned long min_rate = parent_rate * 27;
239	unsigned long max_rate = parent_rate * 54;
240	u32 val, div;
241	u32 mfn, mfd = 1000000;
242	s64 temp64;
243
244	if (rate < min_rate || rate > max_rate)
245		return -EINVAL;
246
247	div = rate / parent_rate;
248	temp64 = (u64) (rate - div * parent_rate);
249	temp64 *= mfd;
250	do_div(temp64, parent_rate);
251	mfn = temp64;
252
253	val = readl_relaxed(pll->base);
254	val &= ~pll->div_mask;
255	val |= div;
256	writel_relaxed(val, pll->base);
257	writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
258	writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
259
260	return clk_pllv3_wait_lock(pll);
261}
262
263static const struct clk_ops clk_pllv3_av_ops = {
264	.prepare	= clk_pllv3_prepare,
265	.unprepare	= clk_pllv3_unprepare,
266	.recalc_rate	= clk_pllv3_av_recalc_rate,
267	.round_rate	= clk_pllv3_av_round_rate,
268	.set_rate	= clk_pllv3_av_set_rate,
269};
270
271static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
272						unsigned long parent_rate)
273{
274	return 500000000;
275}
276
277static const struct clk_ops clk_pllv3_enet_ops = {
278	.prepare	= clk_pllv3_prepare,
279	.unprepare	= clk_pllv3_unprepare,
280	.recalc_rate	= clk_pllv3_enet_recalc_rate,
281};
282
283struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
284			  const char *parent_name, void __iomem *base,
285			  u32 div_mask)
286{
287	struct clk_pllv3 *pll;
288	const struct clk_ops *ops;
289	struct clk *clk;
290	struct clk_init_data init;
291
292	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
293	if (!pll)
294		return ERR_PTR(-ENOMEM);
295
296	switch (type) {
297	case IMX_PLLV3_SYS:
298		ops = &clk_pllv3_sys_ops;
299		break;
300	case IMX_PLLV3_USB_VF610:
301		pll->div_shift = 1;
302	case IMX_PLLV3_USB:
303		ops = &clk_pllv3_ops;
304		pll->powerup_set = true;
305		break;
306	case IMX_PLLV3_AV:
307		ops = &clk_pllv3_av_ops;
308		break;
309	case IMX_PLLV3_ENET:
310		ops = &clk_pllv3_enet_ops;
311		break;
312	default:
313		ops = &clk_pllv3_ops;
314	}
315	pll->base = base;
316	pll->div_mask = div_mask;
317
318	init.name = name;
319	init.ops = ops;
320	init.flags = 0;
321	init.parent_names = &parent_name;
322	init.num_parents = 1;
323
324	pll->hw.init = &init;
325
326	clk = clk_register(NULL, &pll->hw);
327	if (IS_ERR(clk))
328		kfree(pll);
329
330	return clk;
331}
332