Searched refs:engine (Results 1 - 200 of 965) sorted by relevance

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/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/engine/
H A Dbsp.h3 #include <core/engine.h>
H A Dcipher.h3 #include <core/engine.h>
H A Dmsppp.h3 #include <core/engine.h>
H A Dsec.h3 #include <core/engine.h>
H A Dvp.h3 #include <core/engine.h>
H A Dmspdec.h3 #include <core/engine.h>
H A Dmsvld.h3 #include <core/engine.h>
H A Dce.h3 #include <core/engine.h>
H A Ddmaobj.h3 #include <core/engine.h>
H A Ddisp.h3 #include <core/engine.h>
H A Dpm.h3 #include <core/engine.h>
H A Dsw.h25 #include <core/engine.h>
H A Dxtensa.h3 #include <core/engine.h>
H A Dfalcon.h29 #include <core/engine.h>
H A Dmpeg.h24 #include <core/engine.h>
H A Dgr.h24 #include <core/engine.h>
/linux-4.1.27/drivers/video/fbdev/via/
H A Daccel.c27 static int viafb_set_bpp(void __iomem *engine, u8 bpp) viafb_set_bpp() argument
33 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; viafb_set_bpp()
48 writel(gemode, engine + VIA_REG_GEMODE); viafb_set_bpp()
53 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, hw_bitblt_1() argument
93 ret = viafb_set_bpp(engine, dst_bpp); hw_bitblt_1()
105 writel(tmp, engine + 0x08); hw_bitblt_1()
114 writel(tmp, engine + 0x0C); hw_bitblt_1()
122 writel(tmp, engine + 0x10); hw_bitblt_1()
125 writel(fg_color, engine + 0x18); hw_bitblt_1()
128 writel(bg_color, engine + 0x1C); hw_bitblt_1()
138 writel(tmp, engine + 0x30); hw_bitblt_1()
147 writel(tmp, engine + 0x34); hw_bitblt_1()
159 writel(tmp, engine + 0x38); hw_bitblt_1()
172 writel(ge_cmd, engine); hw_bitblt_1()
181 writel(src_mem[i], engine + VIA_MMIO_BLTBASE); hw_bitblt_1()
186 static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height, hw_bitblt_2() argument
226 ret = viafb_set_bpp(engine, dst_bpp); hw_bitblt_2()
240 writel(tmp, engine + 0x08); hw_bitblt_2()
248 writel(tmp, engine + 0x0C); hw_bitblt_2()
256 writel(tmp, engine + 0x10); hw_bitblt_2()
264 writel(tmp, engine + 0x14); hw_bitblt_2()
274 writel(tmp, engine + 0x18); hw_bitblt_2()
283 writel(tmp, engine + 0x1C); hw_bitblt_2()
287 writel(fg_color, engine + 0x58); hw_bitblt_2()
289 writel(fg_color, engine + 0x4C); hw_bitblt_2()
290 writel(bg_color, engine + 0x50); hw_bitblt_2()
304 writel(ge_cmd, engine); hw_bitblt_2()
313 writel(src_mem[i], engine + VIA_MMIO_BLTBASE); hw_bitblt_2()
321 void __iomem *engine; viafb_setup_engine() local
324 engine = viapar->shared->vdev->engine_mmio; viafb_setup_engine()
325 if (!engine) { viafb_setup_engine()
368 * As for the size: the engine can handle three frames, viafb_setup_engine()
383 void __iomem *engine = viapar->shared->vdev->engine_mmio; viafb_reset_engine() local
388 /* Initialize registers to reset the 2D engine */ viafb_reset_engine()
398 writel(0x0, engine + i); viafb_reset_engine()
407 writel(0x00100000, engine + VIA_REG_CR_TRANSET); viafb_reset_engine()
408 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
409 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
413 writel(0x00100000, engine + VIA_REG_TRANSET); viafb_reset_engine()
414 writel(0x00000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
415 writel(0x00333004, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
416 writel(0x60000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
417 writel(0x61000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
418 writel(0x62000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
419 writel(0x63000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
420 writel(0x64000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
421 writel(0x7D000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
423 writel(0xFE020000, engine + VIA_REG_TRANSET); viafb_reset_engine()
424 writel(0x00000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
449 writel(0x00100000, engine + VIA_REG_CR_TRANSET); viafb_reset_engine()
450 writel(vq_high, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
451 writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
452 writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
453 writel(vq_len, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
454 writel(0x74301001, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
455 writel(0x00000000, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
458 writel(0x00FE0000, engine + VIA_REG_TRANSET); viafb_reset_engine()
459 writel(0x080003FE, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
460 writel(0x0A00027C, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
461 writel(0x0B000260, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
462 writel(0x0C000274, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
463 writel(0x0D000264, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
464 writel(0x0E000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
465 writel(0x0F000020, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
466 writel(0x1000027E, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
467 writel(0x110002FE, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
468 writel(0x200F0060, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
470 writel(0x00000006, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
471 writel(0x40008C0F, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
472 writel(0x44000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
473 writel(0x45080C04, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
474 writel(0x46800408, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
476 writel(vq_high, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
477 writel(vq_start_low, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
478 writel(vq_end_low, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
479 writel(vq_len, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
484 writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE); viafb_reset_engine()
485 writel(0x0, engine + VIA_REG_CURSOR_POS); viafb_reset_engine()
486 writel(0x0, engine + VIA_REG_CURSOR_ORG); viafb_reset_engine()
487 writel(0x0, engine + VIA_REG_CURSOR_BG); viafb_reset_engine()
488 writel(0x0, engine + VIA_REG_CURSOR_FG); viafb_reset_engine()
522 void __iomem *engine = viapar->shared->vdev->engine_mmio; viafb_wait_engine_idle() local
531 while (!(readl(engine + VIA_REG_STATUS) & viafb_wait_engine_idle()
540 while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) { viafb_wait_engine_idle()
H A Dviafbdev.h57 /* All the information will be needed to set engine */
66 int (*hw_bitblt)(void __iomem *engine, u8 op, u32 width, u32 height,
84 /* All the information will be needed to set engine */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
H A Dparent.c26 #include <core/engine.h>
34 struct nvkm_engine *engine; nvkm_parent_sclass() local
41 *pengine = &parent->engine->subdev.object; nvkm_parent_sclass()
49 mask = nv_parent(parent)->engine; nvkm_parent_sclass()
54 engine = nv_engine(nv_client(parent)->device); nvkm_parent_sclass()
56 engine = nvkm_engine(parent, i); nvkm_parent_sclass()
58 if (engine) { nvkm_parent_sclass()
59 oclass = engine->sclass; nvkm_parent_sclass()
62 *pengine = nv_object(engine); nvkm_parent_sclass()
80 struct nvkm_engine *engine; nvkm_parent_lclass() local
92 mask = nv_parent(parent)->engine; nvkm_parent_lclass()
94 engine = nvkm_engine(parent, i); nvkm_parent_lclass()
95 if (engine && (oclass = engine->sclass)) { nvkm_parent_lclass()
110 nvkm_parent_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_parent_create_() argument
119 ret = nvkm_object_create_(parent, engine, oclass, pclass | nvkm_parent_create_()
132 nclass->engine = engine ? nv_engine(engine) : NULL; nvkm_parent_create_()
137 object->engine = engcls; nvkm_parent_create_()
H A Dengine.c24 #include <core/engine.h>
43 struct nvkm_engine *engine; nvkm_engine_create_() local
48 engine = *pobject; nvkm_engine_create_()
54 int engidx = nv_engidx(engine); nvkm_engine_create_()
58 nv_debug(engine, "engine disabled by hw/fw\n"); nvkm_engine_create_()
62 nv_warn(engine, "ignoring hw/fw engine disable\n"); nvkm_engine_create_()
67 nv_warn(engine, "disabled, %s=1 to enable\n", iname); nvkm_engine_create_()
72 INIT_LIST_HEAD(&engine->contexts); nvkm_engine_create_()
73 spin_lock_init(&engine->lock); nvkm_engine_create_()
H A Dobject.c25 #include <core/engine.h>
33 nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_object_create_() argument
44 nvkm_object_ref(engine, (struct nvkm_object **)&object->engine); nvkm_object_create_()
60 _nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_object_ctor() argument
66 return nvkm_object_create(parent, engine, oclass, 0, pobject); _nvkm_object_ctor()
77 nvkm_object_ref(NULL, (struct nvkm_object **)&object->engine); nvkm_object_destroy()
103 nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_object_ctor() argument
111 ret = ofuncs->ctor(parent, engine, oclass, data, size, &object); nvkm_object_ctor()
179 if (object->engine) { nvkm_object_inc()
180 mutex_lock(&nv_subdev(object->engine)->mutex); nvkm_object_inc()
181 ret = nvkm_object_inc(&object->engine->subdev.object); nvkm_object_inc()
182 mutex_unlock(&nv_subdev(object->engine)->mutex); nvkm_object_inc()
184 nv_error(object, "engine failed, %d\n", ret); nvkm_object_inc()
200 if (object->engine) { nvkm_object_inc()
201 mutex_lock(&nv_subdev(object->engine)->mutex); nvkm_object_inc()
202 nvkm_object_dec(&object->engine->subdev.object, false); nvkm_object_inc()
203 mutex_unlock(&nv_subdev(object->engine)->mutex); nvkm_object_inc()
225 if (object->engine) { nvkm_object_decf()
226 mutex_lock(&nv_subdev(object->engine)->mutex); nvkm_object_decf()
227 nvkm_object_dec(&object->engine->subdev.object, false); nvkm_object_decf()
228 mutex_unlock(&nv_subdev(object->engine)->mutex); nvkm_object_decf()
252 if (object->engine) { nvkm_object_decs()
253 mutex_lock(&nv_subdev(object->engine)->mutex); nvkm_object_decs()
254 ret = nvkm_object_dec(&object->engine->subdev.object, true); nvkm_object_decs()
255 mutex_unlock(&nv_subdev(object->engine)->mutex); nvkm_object_decs()
257 nv_warn(object, "engine failed suspend, %d\n", ret); nvkm_object_decs()
274 if (object->engine) { nvkm_object_decs()
275 mutex_lock(&nv_subdev(object->engine)->mutex); nvkm_object_decs()
276 rret = nvkm_object_inc(&object->engine->subdev.object); nvkm_object_decs()
277 mutex_unlock(&nv_subdev(object->engine)->mutex); nvkm_object_decs()
279 nv_fatal(object, "engine failed to reinit, %d\n", rret); nvkm_object_decs()
324 object->parent, object->engine, nvkm_object_debug()
H A Dengctx.c25 #include <core/engine.h>
30 struct nvkm_engine *engine, void **pobject) nvkm_engctx_exists()
35 list_for_each_entry(engctx, &engine->contexts, head) { nvkm_engctx_exists()
53 struct nvkm_engine *engine = nv_engine(engobj); nvkm_engctx_create_() local
58 /* check if this engine already has a context for the parent object, nvkm_engctx_create_()
61 spin_lock_irqsave(&engine->lock, save); nvkm_engctx_create_()
62 ret = nvkm_engctx_exists(parent, engine, pobject); nvkm_engctx_create_()
63 spin_unlock_irqrestore(&engine->lock, save); nvkm_engctx_create_()
87 spin_lock_irqsave(&engine->lock, save); nvkm_engctx_create_()
88 ret = nvkm_engctx_exists(parent, engine, pobject); nvkm_engctx_create_()
90 spin_unlock_irqrestore(&engine->lock, save); nvkm_engctx_create_()
96 atomic_inc(&client->vm->engref[nv_engidx(engine)]); nvkm_engctx_create_()
97 list_add(&nv_engctx(engctx)->head, &engine->contexts); nvkm_engctx_create_()
99 spin_unlock_irqrestore(&engine->lock, save); nvkm_engctx_create_()
106 struct nvkm_engine *engine = engctx->gpuobj.object.engine; nvkm_engctx_destroy() local
111 spin_lock_irqsave(&engine->lock, save); nvkm_engctx_destroy()
113 spin_unlock_irqrestore(&engine->lock, save); nvkm_engctx_destroy()
116 atomic_dec(&client->vm->engref[nv_engidx(engine)]); nvkm_engctx_destroy()
128 struct nvkm_subdev *subdev = nv_subdev(object->engine); nvkm_engctx_init()
138 pardev = nv_subdev(parent->engine); nvkm_engctx_init()
159 struct nvkm_subdev *subdev = nv_subdev(object->engine); nvkm_engctx_fini()
165 pardev = nv_subdev(parent->engine); nvkm_engctx_fini()
183 _nvkm_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_engctx_ctor() argument
190 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 256, 256, _nvkm_engctx_ctor()
215 nvkm_engctx_get(struct nvkm_engine *engine, u64 addr) nvkm_engctx_get() argument
220 spin_lock_irqsave(&engine->lock, flags); nvkm_engctx_get()
221 list_for_each_entry(engctx, &engine->contexts, head) { nvkm_engctx_get()
227 spin_unlock_irqrestore(&engine->lock, flags); nvkm_engctx_get()
235 struct nvkm_engine *engine = nv_engine(object->engine); nvkm_engctx_put() local
237 spin_unlock_irqrestore(&engine->lock, engctx->save); nvkm_engctx_put()
29 nvkm_engctx_exists(struct nvkm_object *parent, struct nvkm_engine *engine, void **pobject) nvkm_engctx_exists() argument
H A Dgpuobj.c25 #include <core/engine.h>
51 nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_gpuobj_create_() argument
100 ret = nvkm_object_create_(parent, engine, oclass, pclass | nvkm_gpuobj_create_()
143 _nvkm_gpuobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_gpuobj_ctor() argument
151 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, args->pargpu, _nvkm_gpuobj_ctor()
217 struct nvkm_object *engine = parent; nvkm_gpuobj_new() local
225 if (!nv_iclass(engine, NV_SUBDEV_CLASS)) nvkm_gpuobj_new()
226 engine = &engine->engine->subdev.object; nvkm_gpuobj_new()
227 BUG_ON(engine == NULL); nvkm_gpuobj_new()
229 return nvkm_object_ctor(parent, engine, &_nvkm_gpuobj_oclass, nvkm_gpuobj_new()
306 ret = nvkm_object_create(parent, &parent->engine->subdev.object, nvkm_gpuobj_dup()
H A Dioctl.c26 #include <core/engine.h>
93 struct nvkm_object *engine; nvkm_ioctl_new() local
119 ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass); nvkm_ioctl_new()
125 /* make sure engine init has been completed *before* any objects nvkm_ioctl_new()
129 if (engine) { nvkm_ioctl_new()
130 ret = nvkm_object_inc(engine); nvkm_ioctl_new()
135 /* if engine requires it, create a context object to insert nvkm_ioctl_new()
138 if (engine && nv_engine(engine)->cclass) { nvkm_ioctl_new()
139 ret = nvkm_object_ctor(&parent->object, engine, nvkm_ioctl_new()
140 nv_engine(engine)->cclass, nvkm_ioctl_new()
149 ret = nvkm_object_ctor(engctx, engine, oclass, data, size, &object); nvkm_ioctl_new()
176 if (engine) nvkm_ioctl_new()
177 nvkm_object_dec(engine, false); nvkm_ioctl_new()
H A Dramht.c23 #include <core/engine.h>
96 ret = nvkm_gpuobj_create(parent, parent->engine ? nvkm_ramht_new()
97 &parent->engine->subdev.object : parent, /* <nv50 ramht */ nvkm_ramht_new()
H A Dnamedb.c165 nvkm_namedb_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_namedb_create_() argument
173 ret = nvkm_parent_create_(parent, engine, oclass, pclass | nvkm_namedb_create_()
186 _nvkm_namedb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_namedb_ctor() argument
193 ret = nvkm_namedb_create(parent, engine, oclass, 0, NULL, 0, &object); _nvkm_namedb_ctor()
H A Dprintk.c65 if (object->engine == NULL) { nv_printk_()
70 subdev = &object->engine->subdev.object; nv_printk_()
H A Dsubdev.c96 nvkm_subdev_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_subdev_create_() argument
104 ret = nvkm_object_create_(parent, engine, oclass, pclass | nvkm_subdev_create_()
/linux-4.1.27/drivers/crypto/
H A Dpicoxcell_crypto.c93 struct spacc_engine *engine; member in struct:spacc_req
142 struct spacc_engine *engine; member in struct:spacc_alg
150 struct spacc_engine *engine; member in struct:spacc_generic_ctx
187 static inline int spacc_fifo_cmd_full(struct spacc_engine *engine) spacc_fifo_cmd_full() argument
189 u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET); spacc_fifo_cmd_full()
205 return is_cipher_ctx ? ctx->engine->cipher_ctx_base + spacc_ctx_page_addr()
206 (indx * ctx->engine->cipher_pg_sz) : spacc_ctx_page_addr()
207 ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz); spacc_ctx_page_addr()
241 unsigned indx = ctx->engine->next_ctx++; spacc_load_ctx()
247 ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1; spacc_load_ctx()
252 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET); spacc_load_ctx()
257 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET); spacc_load_ctx()
289 static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine, spacc_sg_to_ddt() argument
301 mapped_ents = dma_map_sg(engine->dev, payload, nents, dir); spacc_sg_to_ddt()
306 ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys); spacc_sg_to_ddt()
317 dma_unmap_sg(engine->dev, payload, nents, dir); spacc_sg_to_ddt()
325 struct spacc_engine *engine = req->engine; spacc_aead_make_ddts() local
334 src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr); spacc_aead_make_ddts()
338 dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr); spacc_aead_make_ddts()
340 dma_pool_free(engine->req_pool, src_ddt, req->src_addr); spacc_aead_make_ddts()
347 assoc_ents = dma_map_sg(engine->dev, areq->assoc, spacc_aead_make_ddts()
350 src_ents = dma_map_sg(engine->dev, areq->src, nents, spacc_aead_make_ddts()
352 dst_ents = dma_map_sg(engine->dev, areq->dst, nents, spacc_aead_make_ddts()
355 src_ents = dma_map_sg(engine->dev, areq->src, nents, spacc_aead_make_ddts()
364 iv_addr = dma_map_single(engine->dev, iv, ivsize, spacc_aead_make_ddts()
410 struct spacc_engine *engine = aead_ctx->generic.engine; spacc_aead_free_ddts() local
415 dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE); spacc_aead_free_ddts()
416 dma_unmap_sg(engine->dev, areq->dst, spacc_aead_free_ddts()
420 dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL); spacc_aead_free_ddts()
422 dma_unmap_sg(engine->dev, areq->assoc, spacc_aead_free_ddts()
425 dma_unmap_single(engine->dev, req->giv_pa, ivsize, DMA_BIDIRECTIONAL); spacc_aead_free_ddts()
427 dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr); spacc_aead_free_ddts()
428 dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr); spacc_aead_free_ddts()
437 dma_unmap_sg(req->engine->dev, payload, nents, dir); spacc_free_ddt()
438 dma_pool_free(req->engine->req_pool, ddt, ddt_addr); spacc_free_ddt()
472 * IPSec engine only supports 128 and 256 bit AES keys. If we get a spacc_aead_aes_setkey()
601 struct spacc_engine *engine = ctx->generic.engine; spacc_aead_submit() local
612 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET); spacc_aead_submit()
613 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET); spacc_aead_submit()
614 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET); spacc_aead_submit()
636 writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET); spacc_aead_submit()
637 writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET); spacc_aead_submit()
638 writel(ctx->auth_size, engine->regs + SPA_ICV_LEN_REG_OFFSET); spacc_aead_submit()
639 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET); spacc_aead_submit()
640 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET); spacc_aead_submit()
649 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT); spacc_aead_submit()
651 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET); spacc_aead_submit()
658 static void spacc_push(struct spacc_engine *engine) spacc_push() argument
662 while (!list_empty(&engine->pending) && spacc_push()
663 engine->in_flight + 1 <= engine->fifo_sz) { spacc_push()
665 ++engine->in_flight; spacc_push()
666 req = list_first_entry(&engine->pending, struct spacc_req, spacc_push()
668 list_move_tail(&req->list, &engine->in_progress); spacc_push()
675 * Setup an AEAD request for processing. This will configure the engine, load
685 struct spacc_engine *engine = to_spacc_alg(alg)->engine; spacc_aead_setup() local
696 dev_req->engine = engine; spacc_aead_setup()
705 spin_lock_irqsave(&engine->hw_lock, flags); spacc_aead_setup()
706 if (unlikely(spacc_fifo_cmd_full(engine)) || spacc_aead_setup()
707 engine->in_flight + 1 > engine->fifo_sz) { spacc_aead_setup()
710 spin_unlock_irqrestore(&engine->hw_lock, flags); spacc_aead_setup()
713 list_add_tail(&dev_req->list, &engine->pending); spacc_aead_setup()
715 list_add_tail(&dev_req->list, &engine->pending); spacc_aead_setup()
716 spacc_push(engine); spacc_aead_setup()
718 spin_unlock_irqrestore(&engine->hw_lock, flags); spacc_aead_setup()
776 struct spacc_engine *engine = spacc_alg->engine; spacc_aead_cra_init() local
779 ctx->generic.engine = engine; spacc_aead_cra_init()
784 dev_warn(engine->dev, "failed to allocate fallback for %s\n", spacc_aead_cra_init()
856 * IPSec engine only supports 128 and 256 bit AES keys. If we get a spacc_aes_setkey()
949 struct spacc_engine *engine = ctx->generic.engine; spacc_ablk_submit() local
956 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET); spacc_ablk_submit()
957 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET); spacc_ablk_submit()
958 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET); spacc_ablk_submit()
960 writel(ablk_req->nbytes, engine->regs + SPA_PROC_LEN_REG_OFFSET); spacc_ablk_submit()
961 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET); spacc_ablk_submit()
962 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET); spacc_ablk_submit()
963 writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET); spacc_ablk_submit()
969 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT); spacc_ablk_submit()
971 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET); spacc_ablk_submit()
1004 struct spacc_engine *engine = to_spacc_alg(alg)->engine; spacc_ablk_setup() local
1011 dev_req->engine = engine; spacc_ablk_setup()
1019 * Create the DDT's for the engine. If we share the same source and spacc_ablk_setup()
1023 dev_req->src_ddt = spacc_sg_to_ddt(engine, req->src, spacc_ablk_setup()
1028 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst, spacc_ablk_setup()
1033 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst, spacc_ablk_setup()
1043 spin_lock_irqsave(&engine->hw_lock, flags); spacc_ablk_setup()
1045 * Check if the engine will accept the operation now. If it won't then spacc_ablk_setup()
1049 if (unlikely(spacc_fifo_cmd_full(engine)) || spacc_ablk_setup()
1050 engine->in_flight + 1 > engine->fifo_sz) { spacc_ablk_setup()
1053 spin_unlock_irqrestore(&engine->hw_lock, flags); spacc_ablk_setup()
1056 list_add_tail(&dev_req->list, &engine->pending); spacc_ablk_setup()
1058 list_add_tail(&dev_req->list, &engine->pending); spacc_ablk_setup()
1059 spacc_push(engine); spacc_ablk_setup()
1061 spin_unlock_irqrestore(&engine->hw_lock, flags); spacc_ablk_setup()
1082 struct spacc_engine *engine = spacc_alg->engine; spacc_ablk_cra_init() local
1085 ctx->generic.engine = engine; spacc_ablk_cra_init()
1090 dev_warn(engine->dev, "failed to allocate fallback for %s\n", spacc_ablk_cra_init()
1130 static inline int spacc_fifo_stat_empty(struct spacc_engine *engine) spacc_fifo_stat_empty() argument
1132 return readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET) & spacc_fifo_stat_empty()
1136 static void spacc_process_done(struct spacc_engine *engine) spacc_process_done() argument
1141 spin_lock_irqsave(&engine->hw_lock, flags); spacc_process_done()
1143 while (!spacc_fifo_stat_empty(engine)) { spacc_process_done()
1144 req = list_first_entry(&engine->in_progress, struct spacc_req, spacc_process_done()
1146 list_move_tail(&req->list, &engine->completed); spacc_process_done()
1147 --engine->in_flight; spacc_process_done()
1150 writel(~0, engine->regs + SPA_STAT_POP_REG_OFFSET); spacc_process_done()
1151 req->result = (readl(engine->regs + SPA_STATUS_REG_OFFSET) & spacc_process_done()
1165 dev_warn(engine->dev, spacc_process_done()
1171 dev_warn(engine->dev, spacc_process_done()
1179 tasklet_schedule(&engine->complete); spacc_process_done()
1181 spin_unlock_irqrestore(&engine->hw_lock, flags); spacc_process_done()
1186 struct spacc_engine *engine = (struct spacc_engine *)dev; spacc_spacc_irq() local
1187 u32 spacc_irq_stat = readl(engine->regs + SPA_IRQ_STAT_REG_OFFSET); spacc_spacc_irq()
1189 writel(spacc_irq_stat, engine->regs + SPA_IRQ_STAT_REG_OFFSET); spacc_spacc_irq()
1190 spacc_process_done(engine); spacc_spacc_irq()
1197 struct spacc_engine *engine = (struct spacc_engine *)data; spacc_packet_timeout() local
1199 spacc_process_done(engine); spacc_packet_timeout()
1214 struct spacc_engine *engine = (struct spacc_engine *)data; spacc_spacc_complete() local
1219 spin_lock_irqsave(&engine->hw_lock, flags); spacc_spacc_complete()
1221 list_splice_init(&engine->completed, &completed); spacc_spacc_complete()
1222 spacc_push(engine); spacc_spacc_complete()
1223 if (engine->in_flight) spacc_spacc_complete()
1224 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT); spacc_spacc_complete()
1226 spin_unlock_irqrestore(&engine->hw_lock, flags); spacc_spacc_complete()
1238 struct spacc_engine *engine = platform_get_drvdata(pdev); spacc_suspend() local
1245 clk_disable(engine->clk); spacc_suspend()
1253 struct spacc_engine *engine = platform_get_drvdata(pdev); spacc_resume() local
1255 return clk_enable(engine->clk); spacc_resume()
1273 struct spacc_engine *engine = spacc_dev_to_engine(dev); spacc_stat_irq_thresh_show() local
1275 return snprintf(buf, PAGE_SIZE, "%u\n", engine->stat_irq_thresh); spacc_stat_irq_thresh_show()
1282 struct spacc_engine *engine = spacc_dev_to_engine(dev); spacc_stat_irq_thresh_store() local
1288 thresh = clamp(thresh, 1UL, engine->fifo_sz - 1); spacc_stat_irq_thresh_store()
1290 engine->stat_irq_thresh = thresh; spacc_stat_irq_thresh_store()
1291 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET, spacc_stat_irq_thresh_store()
1292 engine->regs + SPA_IRQ_CTRL_REG_OFFSET); spacc_stat_irq_thresh_store()
1697 struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine), spacc_probe() local
1699 if (!engine) spacc_probe()
1703 engine->max_ctxs = SPACC_CRYPTO_IPSEC_MAX_CTXS; spacc_probe()
1704 engine->cipher_pg_sz = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ; spacc_probe()
1705 engine->hash_pg_sz = SPACC_CRYPTO_IPSEC_HASH_PG_SZ; spacc_probe()
1706 engine->fifo_sz = SPACC_CRYPTO_IPSEC_FIFO_SZ; spacc_probe()
1707 engine->algs = ipsec_engine_algs; spacc_probe()
1708 engine->num_algs = ARRAY_SIZE(ipsec_engine_algs); spacc_probe()
1710 engine->max_ctxs = SPACC_CRYPTO_L2_MAX_CTXS; spacc_probe()
1711 engine->cipher_pg_sz = SPACC_CRYPTO_L2_CIPHER_PG_SZ; spacc_probe()
1712 engine->hash_pg_sz = SPACC_CRYPTO_L2_HASH_PG_SZ; spacc_probe()
1713 engine->fifo_sz = SPACC_CRYPTO_L2_FIFO_SZ; spacc_probe()
1714 engine->algs = l2_engine_algs; spacc_probe()
1715 engine->num_algs = ARRAY_SIZE(l2_engine_algs); spacc_probe()
1720 engine->name = dev_name(&pdev->dev); spacc_probe()
1723 engine->regs = devm_ioremap_resource(&pdev->dev, mem); spacc_probe()
1724 if (IS_ERR(engine->regs)) spacc_probe()
1725 return PTR_ERR(engine->regs); spacc_probe()
1729 dev_err(&pdev->dev, "no memory/irq resource for engine\n"); spacc_probe()
1734 engine->name, engine)) { spacc_probe()
1735 dev_err(engine->dev, "failed to request IRQ\n"); spacc_probe()
1739 engine->dev = &pdev->dev; spacc_probe()
1740 engine->cipher_ctx_base = engine->regs + SPA_CIPH_KEY_BASE_REG_OFFSET; spacc_probe()
1741 engine->hash_key_base = engine->regs + SPA_HASH_KEY_BASE_REG_OFFSET; spacc_probe()
1743 engine->req_pool = dmam_pool_create(engine->name, engine->dev, spacc_probe()
1745 if (!engine->req_pool) spacc_probe()
1748 spin_lock_init(&engine->hw_lock); spacc_probe()
1750 engine->clk = clk_get(&pdev->dev, "ref"); spacc_probe()
1751 if (IS_ERR(engine->clk)) { spacc_probe()
1754 return PTR_ERR(engine->clk); spacc_probe()
1757 if (clk_enable(engine->clk)) { spacc_probe()
1759 clk_put(engine->clk); spacc_probe()
1765 clk_disable(engine->clk); spacc_probe()
1766 clk_put(engine->clk); spacc_probe()
1776 engine->stat_irq_thresh = (engine->fifo_sz / 2); spacc_probe()
1783 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET, spacc_probe()
1784 engine->regs + SPA_IRQ_CTRL_REG_OFFSET); spacc_probe()
1786 engine->regs + SPA_IRQ_EN_REG_OFFSET); spacc_probe()
1788 setup_timer(&engine->packet_timeout, spacc_packet_timeout, spacc_probe()
1789 (unsigned long)engine); spacc_probe()
1791 INIT_LIST_HEAD(&engine->pending); spacc_probe()
1792 INIT_LIST_HEAD(&engine->completed); spacc_probe()
1793 INIT_LIST_HEAD(&engine->in_progress); spacc_probe()
1794 engine->in_flight = 0; spacc_probe()
1795 tasklet_init(&engine->complete, spacc_spacc_complete, spacc_probe()
1796 (unsigned long)engine); spacc_probe()
1798 platform_set_drvdata(pdev, engine); spacc_probe()
1800 INIT_LIST_HEAD(&engine->registered_algs); spacc_probe()
1801 for (i = 0; i < engine->num_algs; ++i) { spacc_probe()
1802 engine->algs[i].engine = engine; spacc_probe()
1803 err = crypto_register_alg(&engine->algs[i].alg); spacc_probe()
1805 list_add_tail(&engine->algs[i].entry, spacc_probe()
1806 &engine->registered_algs); spacc_probe()
1810 dev_err(engine->dev, "failed to register alg \"%s\"\n", spacc_probe()
1811 engine->algs[i].alg.cra_name); spacc_probe()
1813 dev_dbg(engine->dev, "registered alg \"%s\"\n", spacc_probe()
1814 engine->algs[i].alg.cra_name); spacc_probe()
1823 struct spacc_engine *engine = platform_get_drvdata(pdev); spacc_remove() local
1825 del_timer_sync(&engine->packet_timeout); spacc_remove()
1828 list_for_each_entry_safe(alg, next, &engine->registered_algs, entry) { spacc_remove()
1833 clk_disable(engine->clk); spacc_remove()
1834 clk_put(engine->clk); spacc_remove()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv50.h3 #include <engine/gr.h>
H A Dnv2a.c4 #include <engine/fifo.h>
11 nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv2a_gr_context_ctor() argument
18 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, nv2a_gr_context_ctor()
87 * PGRAPH engine/subdev functions
91 nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv2a_gr_ctor() argument
98 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv2a_gr_ctor()
H A Dnv20.h3 #include <engine/gr.h>
H A Dnv20.c7 #include <engine/fifo.h>
40 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv20_gr_context_ctor() argument
47 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, nv20_gr_context_ctor()
105 struct nv20_gr_priv *priv = (void *)object->engine; nv20_gr_context_init()
120 struct nv20_gr_priv *priv = (void *)object->engine; nv20_gr_context_fini()
154 * PGRAPH engine/subdev functions
158 nv20_gr_tile_prog(struct nvkm_engine *engine, int i) nv20_gr_tile_prog() argument
160 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; nv20_gr_tile_prog()
161 struct nvkm_fifo *pfifo = nvkm_fifo(engine); nv20_gr_tile_prog()
162 struct nv20_gr_priv *priv = (void *)engine; nv20_gr_tile_prog()
179 if (nv_device(engine)->chipset != 0x34) { nv20_gr_tile_prog()
191 struct nvkm_engine *engine = nv_engine(subdev); nv20_gr_intr() local
206 engctx = nvkm_engctx_get(engine, chid); nv20_gr_intr()
237 nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv20_gr_ctor() argument
244 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv20_gr_ctor()
273 struct nvkm_engine *engine = nv_engine(object); nv20_gr_init() local
274 struct nv20_gr_priv *priv = (void *)engine; nv20_gr_init()
329 engine->tile_prog(engine, i); nv20_gr_init()
H A Dnv25.c4 #include <engine/fifo.h>
35 nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv25_gr_context_ctor() argument
42 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, nv25_gr_context_ctor()
120 * PGRAPH engine/subdev functions
124 nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv25_gr_ctor() argument
131 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv25_gr_ctor()
H A Dnv34.c4 #include <engine/fifo.h>
37 nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv34_gr_context_ctor() argument
44 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc, nv34_gr_context_ctor()
121 * PGRAPH engine/subdev functions
125 nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv34_gr_ctor() argument
132 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv34_gr_ctor()
H A Dnv35.c4 #include <engine/fifo.h>
37 nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv35_gr_context_ctor() argument
44 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c, nv35_gr_context_ctor()
121 * PGRAPH engine/subdev functions
125 nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv35_gr_ctor() argument
132 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv35_gr_ctor()
H A Dnv40.h3 #include <engine/gr.h>
H A Dnv40.c31 #include <engine/fifo.h>
55 nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_gr_object_ctor() argument
62 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv40_gr_object_ctor()
136 nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_gr_context_ctor() argument
140 struct nv40_gr_priv *priv = (void *)engine; nv40_gr_context_ctor()
144 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, nv40_gr_context_ctor()
158 struct nv40_gr_priv *priv = (void *)object->engine; nv40_gr_context_fini()
202 * PGRAPH engine/subdev functions
206 nv40_gr_tile_prog(struct nvkm_engine *engine, int i) nv40_gr_tile_prog() argument
208 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; nv40_gr_tile_prog()
209 struct nvkm_fifo *pfifo = nvkm_fifo(engine); nv40_gr_tile_prog()
210 struct nv40_gr_priv *priv = (void *)engine; nv40_gr_tile_prog()
287 struct nvkm_engine *engine = nv_engine(subdev); nv40_gr_intr() local
303 engctx = nvkm_engctx_get(engine, inst); nv40_gr_intr()
340 nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_gr_ctor() argument
347 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv40_gr_ctor()
368 struct nvkm_engine *engine = nv_engine(object); nv40_gr_init() local
370 struct nv40_gr_priv *priv = (void *)engine; nv40_gr_init()
474 engine->tile_prog(engine, i); nv40_gr_init()
H A Dnv30.c5 #include <engine/fifo.h>
39 nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv30_gr_context_ctor() argument
46 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, nv30_gr_context_ctor()
123 * PGRAPH engine/subdev functions
127 nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv30_gr_ctor() argument
134 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv30_gr_ctor()
155 struct nvkm_engine *engine = nv_engine(object); nv30_gr_init() local
156 struct nv20_gr_priv *priv = (void *)engine; nv30_gr_init()
203 engine->tile_prog(engine, i); nv30_gr_init()
H A Dnv50.c29 #include <engine/fifo.h>
55 nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_gr_object_ctor() argument
62 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv50_gr_object_ctor()
142 nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_gr_context_ctor() argument
146 struct nv50_gr_priv *priv = (void *)engine; nv50_gr_context_ctor()
150 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, nv50_gr_context_ctor()
174 * PGRAPH engine/subdev functions
239 g84_gr_tlb_flush(struct nvkm_engine *engine) g84_gr_tlb_flush() argument
241 struct nvkm_timer *ptimer = nvkm_timer(engine); g84_gr_tlb_flush()
242 struct nv50_gr_priv *priv = (void *)engine; g84_gr_tlb_flush()
658 /* M2MF: Memory to memory copy engine. */ nv50_gr_trap_handler()
787 struct nvkm_engine *engine = nv_engine(subdev); nv50_gr_intr() local
801 engctx = nvkm_engctx_get(engine, inst); nv50_gr_intr()
849 nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_gr_ctor() argument
856 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv50_gr_ctor()
H A Dnv04.c24 #include <engine/gr.h>
30 #include <engine/fifo.h>
365 return (void *)nv_object(chan)->engine; nv04_gr_priv()
376 * 2d engine settings are kept inside the grobjs themselves. The grobjs are
449 struct nv04_gr_priv *priv = (void *)object->engine; nv04_gr_set_ctx1()
531 struct nv04_gr_priv *priv = (void *)object->engine; nv04_gr_mthd_surf3d_clip_h()
552 struct nv04_gr_priv *priv = (void *)object->engine; nv04_gr_mthd_surf3d_clip_v()
951 nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_gr_object_ctor() argument
958 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv04_gr_object_ctor()
1114 struct nvkm_object *engine, nv04_gr_context_ctor()
1119 struct nv04_gr_priv *priv = (void *)engine; nv04_gr_context_ctor()
1124 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); nv04_gr_context_ctor()
1149 struct nv04_gr_priv *priv = (void *)object->engine; nv04_gr_context_dtor()
1163 struct nv04_gr_priv *priv = (void *)object->engine; nv04_gr_context_fini()
1189 * PGRAPH engine/subdev functions
1311 nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_gr_ctor() argument
1318 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv04_gr_ctor()
1334 struct nvkm_engine *engine = nv_engine(object); nv04_gr_init() local
1335 struct nv04_gr_priv *priv = (void *)engine; nv04_gr_init()
1113 nv04_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_gr_context_ctor() argument
H A Dnv10.c24 #include <engine/gr.h>
30 #include <engine/fifo.h>
408 return (void *)nv_object(chan)->engine; nv10_gr_priv()
1021 nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv10_gr_context_ctor() argument
1026 struct nv10_gr_priv *priv = (void *)engine; nv10_gr_context_ctor()
1031 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); nv10_gr_context_ctor()
1076 struct nv10_gr_priv *priv = (void *)object->engine; nv10_gr_context_dtor()
1090 struct nv10_gr_priv *priv = (void *)object->engine; nv10_gr_context_fini()
1116 * PGRAPH engine/subdev functions
1120 nv10_gr_tile_prog(struct nvkm_engine *engine, int i) nv10_gr_tile_prog() argument
1122 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; nv10_gr_tile_prog()
1123 struct nvkm_fifo *pfifo = nvkm_fifo(engine); nv10_gr_tile_prog()
1124 struct nv10_gr_priv *priv = (void *)engine; nv10_gr_tile_prog()
1212 nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv10_gr_ctor() argument
1219 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); nv10_gr_ctor()
1252 struct nvkm_engine *engine = nv_engine(object); nv10_gr_init() local
1254 struct nv10_gr_priv *priv = (void *)engine; nv10_gr_init()
1284 engine->tile_prog(engine, i); nv10_gr_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv31.h3 #include <engine/mpeg.h>
H A Dnv31.c28 #include <engine/fifo.h>
39 struct nvkm_object *engine, nv31_mpeg_object_ctor()
46 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv31_mpeg_object_ctor()
63 struct nv31_mpeg_priv *priv = (void *)object->engine; nv31_mpeg_mthd_dma()
128 struct nvkm_object *engine, nv31_mpeg_context_ctor()
132 struct nv31_mpeg_priv *priv = (void *)engine; nv31_mpeg_context_ctor()
137 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); nv31_mpeg_context_ctor()
157 struct nv31_mpeg_priv *priv = (void *)object->engine; nv31_mpeg_context_dtor()
179 * PMPEG engine/subdev functions
183 nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i) nv31_mpeg_tile_prog() argument
185 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; nv31_mpeg_tile_prog()
186 struct nv31_mpeg_priv *priv = (void *)engine; nv31_mpeg_tile_prog()
238 nv31_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv31_mpeg_ctor() argument
245 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv31_mpeg_ctor()
261 struct nvkm_engine *engine = nv_engine(object); nv31_mpeg_init() local
275 engine->tile_prog(engine, i); nv31_mpeg_init()
38 nv31_mpeg_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv31_mpeg_object_ctor() argument
127 nv31_mpeg_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv31_mpeg_context_ctor() argument
H A Dnv44.c24 #include <engine/mpeg.h>
28 #include <engine/fifo.h>
44 struct nvkm_object *engine, nv44_mpeg_context_ctor()
51 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 264 * 4, nv44_mpeg_context_ctor()
65 struct nv44_mpeg_priv *priv = (void *)object->engine; nv44_mpeg_context_fini()
90 * PMPEG engine/subdev functions
97 struct nvkm_engine *engine = nv_engine(subdev); nv44_mpeg_intr() local
109 engctx = nvkm_engctx_get(engine, inst); nv44_mpeg_intr()
156 nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv44_mpeg_ctor() argument
163 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv44_mpeg_ctor()
43 nv44_mpeg_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv44_mpeg_context_ctor() argument
H A Dnv50.c24 #include <engine/mpeg.h>
43 struct nvkm_object *engine, nv50_mpeg_object_ctor()
50 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, nv50_mpeg_object_ctor()
85 struct nvkm_object *engine, nv50_mpeg_context_ctor()
93 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, nv50_mpeg_context_ctor()
119 * PMPEG engine/subdev functions
165 nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_mpeg_ctor() argument
172 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv50_mpeg_ctor()
42 nv50_mpeg_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_mpeg_object_ctor() argument
84 nv50_mpeg_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_mpeg_context_ctor() argument
H A Dg84.c24 #include <engine/mpeg.h>
62 * PMPEG engine/subdev functions
66 g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_mpeg_ctor() argument
73 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); g84_mpeg_ctor()
H A Dnv40.c36 struct nv31_mpeg_priv *priv = (void *)object->engine; nv40_mpeg_mthd_dma()
86 * PMPEG engine/subdev functions
105 nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_mpeg_ctor() argument
112 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); nv40_mpeg_ctor()
/linux-4.1.27/drivers/video/fbdev/msm/
H A DMakefile6 # MDP DMA/PPP engine
/linux-4.1.27/drivers/gpu/drm/via/
H A Dvia_dmablit.c205 * Fire a blit engine.
209 via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine) via_fire_dmablit() argument
213 VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0); via_fire_dmablit()
214 VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0); via_fire_dmablit()
215 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | via_fire_dmablit()
217 VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE); via_fire_dmablit()
218 VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0); via_fire_dmablit()
219 VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start); via_fire_dmablit()
221 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); via_fire_dmablit()
222 VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04); via_fire_dmablit()
290 via_abort_dmablit(struct drm_device *dev, int engine) via_abort_dmablit() argument
294 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); via_abort_dmablit()
298 via_dmablit_engine_off(struct drm_device *dev, int engine) via_dmablit_engine_off() argument
302 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); via_dmablit_engine_off()
310 * task. Basically the task of the interrupt handler is to submit a new blit to the engine, while
315 via_dmablit_handler(struct drm_device *dev, int engine, int from_irq) via_dmablit_handler() argument
318 drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; via_dmablit_handler()
324 DRM_DEBUG("DMA blit handler called. engine = %d, from_irq = %d, blitq = 0x%lx\n", via_dmablit_handler()
325 engine, from_irq, (unsigned long) blitq); via_dmablit_handler()
333 ((status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD); via_dmablit_handler()
352 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); via_dmablit_handler()
364 via_abort_dmablit(dev, engine); via_dmablit_handler()
371 via_fire_dmablit(dev, blitq->blits[cur], engine); via_dmablit_handler()
381 via_dmablit_engine_off(dev, engine); via_dmablit_handler()
398 via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue) via_dmablit_active() argument
430 via_dmablit_sync(struct drm_device *dev, uint32_t handle, int engine) via_dmablit_sync() argument
434 drm_via_blitq_t *blitq = dev_priv->blit_queues + engine; via_dmablit_sync()
438 if (via_dmablit_active(blitq, engine, handle, &queue)) { via_dmablit_sync()
440 !via_dmablit_active(blitq, engine, handle, NULL)); via_dmablit_sync()
442 DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n", via_dmablit_sync()
443 handle, engine, ret); via_dmablit_sync()
450 * A timer that regularly polls the blit engine in cases where we don't have interrupts:
464 int engine = (int) via_dmablit_timer() local
467 DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine, via_dmablit_timer()
470 via_dmablit_handler(dev, engine, 0); via_dmablit_timer()
480 via_dmablit_handler(dev, engine, 0); via_dmablit_timer()
491 * blit engine only and may not be called on each interrupt.
505 DRM_DEBUG("Workqueue task called for blit engine %ld\n", (unsigned long) via_dmablit_workqueue()
681 via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine) via_dmablit_grab_slot() argument
731 int engine; via_dmablit() local
739 engine = (xfer->to_fb) ? 0 : 1; via_dmablit()
740 blitq = dev_priv->blit_queues + engine; via_dmablit()
741 if (0 != (ret = via_dmablit_grab_slot(blitq, engine))) via_dmablit()
761 xfer->sync.engine = engine; via_dmablit()
763 via_dmablit_handler(dev, engine, 0); via_dmablit()
781 if (sync->engine >= VIA_NUM_BLIT_ENGINES) via_dma_blit_sync()
784 err = via_dmablit_sync(dev, sync->sync_handle, sync->engine); via_dma_blit_sync()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dgk104.h3 #include <engine/fifo.h>
H A Dgk104.c67 struct gk104_fifo_engn engine[FIFO_ENGINE_NR]; member in struct:gk104_fifo_priv
83 u32 engine; member in struct:gk104_fifo_chan
96 gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine) gk104_fifo_runlist_update() argument
99 struct gk104_fifo_engn *engn = &priv->engine[engine]; gk104_fifo_runlist_update()
109 if (chan && chan->state == RUNNING && chan->engine == engine) { gk104_fifo_runlist_update()
118 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); gk104_fifo_runlist_update()
121 (engine * 0x08)) & 0x00100000), gk104_fifo_runlist_update()
123 nv_error(priv, "runlist %d update timeout\n", engine); gk104_fifo_runlist_update()
137 switch (nv_engidx(object->engine)) { gk104_fifo_context_attach()
173 struct gk104_fifo_priv *priv = (void *)parent->engine; gk104_fifo_context_detach()
178 switch (nv_engidx(object->engine)) { gk104_fifo_context_detach()
209 gk104_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_fifo_chan_ctor() argument
217 struct gk104_fifo_priv *priv = (void *)engine; gk104_fifo_chan_ctor()
226 "ioffset %016llx ilength %08x engine %08x\n", gk104_fifo_chan_ctor()
228 args->v0.ilength, args->v0.engine); gk104_fifo_chan_ctor()
233 if (args->v0.engine & (1 << i)) { gk104_fifo_chan_ctor()
235 args->v0.engine = (1 << i); gk104_fifo_chan_ctor()
242 nv_error(priv, "unsupported engines 0x%08x\n", args->v0.engine); gk104_fifo_chan_ctor()
246 ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, gk104_fifo_chan_ctor()
258 chan->engine = i; gk104_fifo_chan_ctor()
289 struct gk104_fifo_priv *priv = (void *)object->engine; gk104_fifo_chan_init()
298 nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); gk104_fifo_chan_init()
303 gk104_fifo_runlist_update(priv, chan->engine); gk104_fifo_chan_init()
313 struct gk104_fifo_priv *priv = (void *)object->engine; gk104_fifo_chan_fini()
319 gk104_fifo_runlist_update(priv, chan->engine); gk104_fifo_chan_fini()
349 gk104_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_fifo_context_ctor() argument
356 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, gk104_fifo_context_ctor()
402 * PFIFO engine
436 struct nvkm_object *engine; gk104_fifo_recover_work() local
451 if ((engine = (void *)nvkm_engine(priv, engn))) { gk104_fifo_recover_work()
452 nv_ofuncs(engine)->fini(engine, false); gk104_fifo_recover_work()
453 WARN_ON(nv_ofuncs(engine)->init(engine)); gk104_fifo_recover_work()
463 gk104_fifo_recover(struct gk104_fifo_priv *priv, struct nvkm_engine *engine, gk104_fifo_recover() argument
469 nv_error(priv, "%s engine fault on channel %d, recovering...\n", gk104_fifo_recover()
470 nv_subdev(engine)->name, chid); gk104_fifo_recover()
476 priv->mask |= 1ULL << nv_engidx(engine); gk104_fifo_recover()
542 struct nvkm_engine *engine; gk104_fifo_intr_sched_ctxsw() local
560 if (!(engine = gk104_fifo_engine(priv, engn))) gk104_fifo_intr_sched_ctxsw()
562 gk104_fifo_recover(priv, engine, chan); gk104_fifo_intr_sched_ctxsw()
723 struct nvkm_engine *engine = NULL; gk104_fifo_intr_fault() local
747 engine = nvkm_engine(priv, eu->data2); gk104_fifo_intr_fault()
748 if (engine) gk104_fifo_intr_fault()
749 engctx = nvkm_engctx_get(engine, inst); gk104_fifo_intr_fault()
778 gk104_fifo_recover(priv, engine, (void *)object); gk104_fifo_intr_fault()
887 wake_up(&priv->engine[engn].wait); gk104_fifo_intr_runlist()
1070 nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); gk104_fifo_dtor()
1071 nvkm_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); gk104_fifo_dtor()
1078 gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_fifo_ctor() argument
1086 ret = nvkm_fifo_create(parent, engine, oclass, 0, gk104_fifo_ctor()
1096 0, &priv->engine[i].runlist[0]); gk104_fifo_ctor()
1101 0, &priv->engine[i].runlist[1]); gk104_fifo_ctor()
1105 init_waitqueue_head(&priv->engine[i].wait); gk104_fifo_ctor()
H A Dnv50.h3 #include <engine/fifo.h>
H A Dnv40.c71 struct nv04_fifo_priv *priv = (void *)parent->engine; nv40_fifo_object_attach()
81 switch (nv_engidx(object->engine)) { nv40_fifo_object_attach()
107 struct nv04_fifo_priv *priv = (void *)parent->engine; nv40_fifo_context_attach()
112 switch (nv_engidx(engctx->engine)) { nv40_fifo_context_attach()
144 struct nv04_fifo_priv *priv = (void *)parent->engine; nv40_fifo_context_detach()
149 switch (nv_engidx(engctx->engine)) { nv40_fifo_context_detach()
177 nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_fifo_chan_ctor() argument
184 struct nv04_fifo_priv *priv = (void *)engine; nv40_fifo_chan_ctor()
196 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, nv40_fifo_chan_ctor()
264 * PFIFO engine
268 nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_fifo_ctor() argument
276 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); nv40_fifo_ctor()
H A Dnv04.c58 struct nv04_fifo_priv *priv = (void *)parent->engine; nv04_fifo_object_attach()
68 switch (nv_engidx(object->engine)) { nv04_fifo_object_attach()
95 struct nv04_fifo_priv *priv = (void *)parent->engine; nv04_fifo_object_detach()
111 struct nvkm_object *engine, nv04_fifo_chan_ctor()
118 struct nv04_fifo_priv *priv = (void *)engine; nv04_fifo_chan_ctor()
130 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, nv04_fifo_chan_ctor()
162 struct nv04_fifo_priv *priv = (void *)object->engine; nv04_fifo_chan_dtor()
176 struct nv04_fifo_priv *priv = (void *)object->engine; nv04_fifo_chan_init()
195 struct nv04_fifo_priv *priv = (void *)object->engine; nv04_fifo_chan_fini()
267 struct nvkm_object *engine, nv04_fifo_context_ctor()
274 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, nv04_fifo_context_ctor()
297 * PFIFO engine
365 u32 engine; nv04_fifo_swmthd() local
379 if (nv_engidx(bind->object->engine) == NVDEV_ENGINE_SW) { nv04_fifo_swmthd()
380 engine = 0x0000000f << (subc * 4); nv04_fifo_swmthd()
384 nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); nv04_fifo_swmthd()
390 engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); nv04_fifo_swmthd()
391 if (unlikely(((engine >> (subc * 4)) & 0xf) != 0)) nv04_fifo_swmthd()
559 nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_fifo_ctor() argument
567 ret = nvkm_fifo_create(parent, engine, oclass, 0, 15, &priv); nv04_fifo_ctor()
110 nv04_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_fifo_chan_ctor() argument
266 nv04_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv04_fifo_context_ctor() argument
H A Dbase.c24 #include <engine/fifo.h>
30 #include <engine/dmaobj.h>
56 struct nvkm_object *engine, nvkm_fifo_channel_create_()
61 struct nvkm_device *device = nv_device(engine); nvkm_fifo_channel_create_()
62 struct nvkm_fifo *priv = (void *)engine; nvkm_fifo_channel_create_()
69 ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, nvkm_fifo_channel_create_()
80 dmaeng = (void *)chan->pushdma->base.engine; nvkm_fifo_channel_create_()
118 struct nvkm_fifo *priv = (void *)nv_object(chan)->engine; nvkm_fifo_channel_destroy()
203 struct nvkm_fifo *fifo = (void *)object->engine; _nvkm_fifo_channel_ntfy()
256 nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_fifo_create_() argument
263 ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", nvkm_fifo_create_()
55 nvkm_fifo_channel_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int bar, u32 addr, u32 size, u32 pushbuf, u64 engmask, int len, void **ptr) nvkm_fifo_channel_create_() argument
H A Dnv10.c54 struct nvkm_object *engine, nv10_fifo_chan_ctor()
61 struct nv04_fifo_priv *priv = (void *)engine; nv10_fifo_chan_ctor()
73 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, nv10_fifo_chan_ctor()
138 * PFIFO engine
142 nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv10_fifo_ctor() argument
150 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); nv10_fifo_ctor()
53 nv10_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv10_fifo_chan_ctor() argument
H A Dnv17.c59 struct nvkm_object *engine, nv17_fifo_chan_ctor()
66 struct nv04_fifo_priv *priv = (void *)engine; nv17_fifo_chan_ctor()
78 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, nv17_fifo_chan_ctor()
145 * PFIFO engine
149 nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv17_fifo_ctor() argument
157 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); nv17_fifo_ctor()
58 nv17_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv17_fifo_chan_ctor() argument
H A Dnv50.c81 switch (nv_engidx(object->engine)) { nv50_fifo_context_attach()
106 struct nv50_fifo_priv *priv = (void *)parent->engine; nv50_fifo_context_detach()
112 switch (nv_engidx(object->engine)) { nv50_fifo_context_detach()
169 switch (nv_engidx(object->engine)) { nv50_fifo_object_attach()
189 nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, nv50_fifo_chan_ctor_dma() argument
209 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, nv50_fifo_chan_ctor_dma()
250 nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, nv50_fifo_chan_ctor_ind() argument
272 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, nv50_fifo_chan_ctor_ind()
323 struct nv50_fifo_priv *priv = (void *)object->engine; nv50_fifo_chan_init()
342 struct nv50_fifo_priv *priv = (void *)object->engine; nv50_fifo_chan_fini()
390 nv50_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_fifo_context_ctor() argument
397 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, nv50_fifo_context_ctor()
451 * PFIFO engine
455 nv50_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_fifo_ctor() argument
462 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); nv50_fifo_ctor()
H A Dgf100.c24 #include <engine/fifo.h>
117 switch (nv_engidx(object->engine)) { gf100_fifo_context_attach()
149 struct gf100_fifo_priv *priv = (void *)parent->engine; gf100_fifo_context_detach()
154 switch (nv_engidx(object->engine)) { gf100_fifo_context_detach()
181 gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_fifo_chan_ctor() argument
189 struct gf100_fifo_priv *priv = (void *)engine; gf100_fifo_chan_ctor()
204 ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, gf100_fifo_chan_ctor()
254 struct gf100_fifo_priv *priv = (void *)object->engine; gf100_fifo_chan_init()
278 struct gf100_fifo_priv *priv = (void *)object->engine; gf100_fifo_chan_fini()
316 gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_fifo_context_ctor() argument
323 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, gf100_fifo_context_ctor()
370 * PFIFO engine
411 struct nvkm_object *engine; gf100_fifo_recover_work() local
426 if ((engine = (void *)nvkm_engine(priv, engn))) { gf100_fifo_recover_work()
427 nv_ofuncs(engine)->fini(engine, false); gf100_fifo_recover_work()
428 WARN_ON(nv_ofuncs(engine)->init(engine)); gf100_fifo_recover_work()
438 gf100_fifo_recover(struct gf100_fifo_priv *priv, struct nvkm_engine *engine, gf100_fifo_recover() argument
444 nv_error(priv, "%s engine fault on channel %d, recovering...\n", gf100_fifo_recover()
445 nv_subdev(engine)->name, chid); gf100_fifo_recover()
451 priv->mask |= 1ULL << nv_engidx(engine); gf100_fifo_recover()
491 struct nvkm_engine *engine; gf100_fifo_intr_sched_ctxsw() local
507 if (!(engine = gf100_fifo_engine(priv, engn))) gf100_fifo_intr_sched_ctxsw()
509 gf100_fifo_recover(priv, engine, chan); gf100_fifo_intr_sched_ctxsw()
609 struct nvkm_engine *engine = NULL; gf100_fifo_intr_fault() local
633 engine = nvkm_engine(priv, eu->data2); gf100_fifo_intr_fault()
634 if (engine) gf100_fifo_intr_fault()
635 engctx = nvkm_engctx_get(engine, inst); gf100_fifo_intr_fault()
663 gf100_fifo_recover(priv, engine, (void *)object); gf100_fifo_intr_fault()
856 gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_fifo_ctor() argument
863 ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &priv); gf100_fifo_ctor()
H A Dgm204.c35 gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm204_fifo_ctor() argument
39 int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); gm204_fifo_ctor()
H A Dg84.c51 switch (nv_engidx(object->engine)) { g84_fifo_context_attach()
84 struct nv50_fifo_priv *priv = (void *)parent->engine; g84_fifo_context_detach()
90 switch (nv_engidx(object->engine)) { g84_fifo_context_detach()
139 switch (nv_engidx(object->engine)) { g84_fifo_object_attach()
162 g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, g84_fifo_chan_ctor_dma() argument
182 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, g84_fifo_chan_ctor_dma()
235 g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, g84_fifo_chan_ctor_ind() argument
257 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, g84_fifo_chan_ctor_ind()
312 struct nv50_fifo_priv *priv = (void *)object->engine; g84_fifo_chan_init()
364 g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_fifo_context_ctor() argument
371 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000, g84_fifo_context_ctor()
418 * PFIFO engine
443 g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_fifo_ctor() argument
450 ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &priv); g84_fifo_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sw/
H A Dnv04.c24 #include <engine/sw.h>
25 #include <engine/fifo.h>
75 nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_sw_context_ctor() argument
82 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); nv04_sw_context_ctor()
102 * software engine/subdev functions
112 nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_sw_ctor() argument
119 ret = nvkm_sw_create(parent, engine, oclass, &priv); nv04_sw_ctor()
H A Dnv10.c24 #include <engine/sw.h>
64 nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv10_sw_context_ctor() argument
71 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); nv10_sw_context_ctor()
91 * software engine/subdev functions
95 nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv10_sw_ctor() argument
102 ret = nvkm_sw_create(parent, engine, oclass, &priv); nv10_sw_ctor()
H A Dnv50.h3 #include <engine/sw.h>
H A Dnv50.c29 #include <engine/disp.h>
125 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; nv50_sw_vblsem_release()
156 nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_sw_context_ctor() argument
165 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); nv50_sw_context_ctor()
200 * software engine/subdev functions
204 nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_sw_ctor() argument
212 ret = nvkm_sw_create(parent, engine, oclass, &priv); nv50_sw_ctor()
H A Dgf100.c53 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; gf100_sw_mthd_mp_control()
102 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; gf100_sw_vblsem_release()
127 * software engine/subdev functions
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/bsp/
H A Dg84.c24 #include <engine/bsp.h>
25 #include <engine/xtensa.h>
57 * BSP engine/subdev functions
61 g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_bsp_ctor() argument
68 ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true, g84_bsp_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
H A Dg98.c24 #include <engine/mspdec.h>
25 #include <engine/falcon.h>
60 * PMSPDEC engine/subdev functions
79 g98_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g98_mspdec_ctor() argument
86 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, g98_mspdec_ctor()
H A Dgf100.c24 #include <engine/mspdec.h>
25 #include <engine/falcon.h>
59 * PMSPDEC engine/subdev functions
78 gf100_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_mspdec_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, gf100_mspdec_ctor()
H A Dgk104.c24 #include <engine/mspdec.h>
25 #include <engine/falcon.h>
59 * PMSPDEC engine/subdev functions
78 gk104_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_mspdec_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, gk104_mspdec_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
H A Dg98.c24 #include <engine/msppp.h>
25 #include <engine/falcon.h>
60 * PMSPPP engine/subdev functions
79 g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g98_msppp_ctor() argument
86 ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, g98_msppp_ctor()
H A Dgf100.c24 #include <engine/msppp.h>
25 #include <engine/falcon.h>
59 * PMSPPP engine/subdev functions
78 gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_msppp_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, gf100_msppp_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
H A Dg98.c24 #include <engine/msvld.h>
25 #include <engine/falcon.h>
61 * PMSVLD engine/subdev functions
80 g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g98_msvld_ctor() argument
87 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, g98_msvld_ctor()
H A Dgf100.c24 #include <engine/msvld.h>
25 #include <engine/falcon.h>
59 * PMSVLD engine/subdev functions
78 gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_msvld_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, gf100_msvld_ctor()
H A Dgk104.c24 #include <engine/msvld.h>
25 #include <engine/falcon.h>
59 * PMSVLD engine/subdev functions
78 gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_msvld_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, gk104_msvld_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/vp/
H A Dg84.c24 #include <engine/vp.h>
25 #include <engine/xtensa.h>
57 * PVP engine/subdev functions
61 g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_vp_ctor() argument
68 ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true, g84_vp_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
H A Dg84.c24 #include <engine/cipher.h>
25 #include <engine/fifo.h>
41 struct nvkm_object *engine, g84_cipher_object_ctor()
48 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, g84_cipher_object_ctor()
95 * PCIPHER engine/subdev functions
112 struct nvkm_engine *engine = nv_engine(subdev); g84_cipher_intr() local
121 engctx = nvkm_engctx_get(engine, inst); g84_cipher_intr()
139 g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_cipher_ctor() argument
146 ret = nvkm_engine_create(parent, engine, oclass, true, g84_cipher_ctor()
40 g84_cipher_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) g84_cipher_object_ctor() argument
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
H A Dengine.h31 nv_engidx(struct nvkm_engine *engine) nv_engidx() argument
33 return nv_subidx(&engine->subdev); nv_engidx()
H A Dparent.h7 struct nvkm_engine *engine; member in struct:nvkm_sclass
15 u64 engine; member in struct:nvkm_parent
H A Ddevice.h3 #include <core/engine.h>
7 struct nvkm_engine engine; member in struct:nvkm_device
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
H A Dgk104.c24 #include <engine/ce.h>
63 * PCE engine/subdev functions
80 gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_ce0_ctor() argument
87 ret = nvkm_engine_create(parent, engine, oclass, true, gk104_ce0_ctor()
101 gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_ce1_ctor() argument
108 ret = nvkm_engine_create(parent, engine, oclass, true, gk104_ce1_ctor()
122 gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_ce2_ctor() argument
129 ret = nvkm_engine_create(parent, engine, oclass, true, gk104_ce2_ctor()
H A Dgm204.c24 #include <engine/ce.h>
63 * PCE engine/subdev functions
80 gm204_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm204_ce0_ctor() argument
87 ret = nvkm_engine_create(parent, engine, oclass, true, gm204_ce0_ctor()
101 gm204_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm204_ce1_ctor() argument
108 ret = nvkm_engine_create(parent, engine, oclass, true, gm204_ce1_ctor()
122 gm204_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm204_ce2_ctor() argument
129 ret = nvkm_engine_create(parent, engine, oclass, true, gm204_ce2_ctor()
H A Dgt215.c24 #include <engine/ce.h>
25 #include <engine/falcon.h>
26 #include <engine/fifo.h>
66 * PCE engine/subdev functions
81 struct nvkm_engine *engine = nv_engine(subdev); gt215_ce_intr() local
94 engctx = nvkm_engctx_get(engine, inst); gt215_ce_intr()
116 gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gt215_ce_ctor() argument
124 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable, gt215_ce_ctor()
H A Dgf100.c24 #include <engine/ce.h>
25 #include <engine/falcon.h>
75 * PCE engine/subdev functions
93 gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_ce0_ctor() argument
100 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true, gf100_ce0_ctor()
118 gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_ce1_ctor() argument
125 ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true, gf100_ce1_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
H A Dg98.c24 #include <engine/sec.h>
25 #include <engine/falcon.h>
30 #include <engine/fifo.h>
64 * PSEC engine/subdev functions
79 struct nvkm_engine *engine = nv_engine(subdev); g98_sec_intr() local
92 engctx = nvkm_engctx_get(engine, inst); g98_sec_intr()
114 g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g98_sec_ctor() argument
121 ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true, g98_sec_ctor()
/linux-4.1.27/include/linux/platform_data/
H A Ddma-imx-sdma.h8 * address space of the SDMA engine.
57 * struct sdma_platform_data - platform specific data for SDMA engine
H A Deth-netx.h22 unsigned int xcno; /* number of xmac/xpec engine this eth uses */
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/
H A Dpriv.h3 #include <engine/dmaobj.h>
H A Dbase.c39 nv_oclass(nv_object(dmaobj)->engine); nvkm_dmaobj_bind()
58 struct nvkm_object *engine, nvkm_dmaobj_create_()
74 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); nvkm_dmaobj_create_()
147 _nvkm_dmaeng_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_dmaeng_ctor() argument
155 ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ", _nvkm_dmaeng_ctor()
57 nvkm_dmaobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void **pdata, u32 *psize, int length, void **pobject) nvkm_dmaobj_create_() argument
H A Dnv04.c84 nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_dmaobj_ctor() argument
88 struct nvkm_dmaeng *dmaeng = (void *)engine; nv04_dmaobj_ctor()
89 struct nv04_mmu_priv *mmu = nv04_mmu(engine); nv04_dmaobj_ctor()
93 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); nv04_dmaobj_ctor()
H A Dgf100.c73 gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_dmaobj_ctor() argument
77 struct nvkm_dmaeng *dmaeng = (void *)engine; gf100_dmaobj_ctor()
85 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); gf100_dmaobj_ctor()
H A Dgf110.c78 gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf110_dmaobj_ctor() argument
82 struct nvkm_dmaeng *dmaeng = (void *)engine; gf110_dmaobj_ctor()
90 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); gf110_dmaobj_ctor()
H A Dnv50.c85 nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_dmaobj_ctor() argument
89 struct nvkm_dmaeng *dmaeng = (void *)engine; nv50_dmaobj_ctor()
97 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); nv50_dmaobj_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
H A Dpad.c46 struct nvkm_object *engine, nvkm_i2c_pad_create_()
64 ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject); nvkm_i2c_pad_create_()
74 _nvkm_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_i2c_pad_ctor() argument
80 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); _nvkm_i2c_pad_ctor()
45 nvkm_i2c_pad_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int index, int size, void **pobject) nvkm_i2c_pad_create_() argument
H A Dpadg94.c61 g94_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g94_i2c_pad_ctor() argument
68 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); g94_i2c_pad_ctor()
H A Dpadgm204.c61 gm204_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm204_i2c_pad_ctor() argument
68 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); gm204_i2c_pad_ctor()
H A Dgf110.c51 gf110_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf110_i2c_port_ctor() argument
59 ret = nvkm_i2c_port_create(parent, engine, oclass, index, gf110_i2c_port_ctor()
H A Dnv04.c85 nv04_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_i2c_port_ctor() argument
93 ret = nvkm_i2c_port_create(parent, engine, oclass, index, nv04_i2c_port_ctor()
H A Dnv4e.c78 nv4e_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv4e_i2c_port_ctor() argument
86 ret = nvkm_i2c_port_create(parent, engine, oclass, index, nv4e_i2c_port_ctor()
H A Dnv50.c78 nv50_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_i2c_port_ctor() argument
86 ret = nvkm_i2c_port_create(parent, engine, oclass, index, nv50_i2c_port_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvif/
H A Ddevice.h54 #include <engine/fifo.h>
55 #include <engine/gr.h>
56 #include <engine/sw.h>
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv50.c149 struct nvkm_engine *engine; nv50_fb_intr() local
188 engine = nvkm_engine(subdev, en->data2); nv50_fb_intr()
190 if (!engine && en->data2 == NVDEV_ENGINE_BSP) nv50_fb_intr()
191 engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD); nv50_fb_intr()
192 if (!engine && en->data2 == NVDEV_ENGINE_CIPHER) nv50_fb_intr()
193 engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC); nv50_fb_intr()
194 if (!engine && en->data2 == NVDEV_ENGINE_VP) nv50_fb_intr()
195 engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC); nv50_fb_intr()
196 if (engine) { nv50_fb_intr()
197 engctx = nvkm_engctx_get(engine, chan); nv50_fb_intr()
242 nv50_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_fb_ctor() argument
250 ret = nvkm_fb_create(parent, engine, oclass, &priv); nv50_fb_ctor()
H A Dramgm107.c31 gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm107_ram_ctor() argument
38 ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram); gm107_ram_ctor()
H A Dramnv10.c27 nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv10_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv10_ram_create()
H A Dramnv4e.c27 nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv4e_ram_create() argument
35 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv4e_ram_create()
H A Dgk20a.c43 gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_fb_ctor() argument
50 ret = nvkm_fb_create(parent, engine, oclass, &priv); gk20a_fb_ctor()
H A Dramnv04.c28 nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv04_ram_create() argument
37 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv04_ram_create()
H A Dramnv1a.c29 nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv1a_ram_create() argument
45 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv1a_ram_create()
H A Dramnv20.c27 nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv20_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv20_ram_create()
H A Dramnv41.c27 nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv41_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv41_ram_create()
H A Dramnv44.c27 nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv44_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv44_ram_create()
H A Dramnv49.c27 nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, nv49_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); nv49_ram_create()
H A Dgf100.c85 gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_fb_ctor() argument
93 ret = nvkm_fb_create(parent, engine, oclass, &priv); gf100_fb_ctor()
H A Dnv04.c55 nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_fb_ctor() argument
63 ret = nvkm_fb_create(parent, engine, oclass, &priv); nv04_fb_ctor()
H A Drammcp77.c32 mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, mcp77_ram_ctor() argument
42 ret = nvkm_ram_create(parent, engine, oclass, &priv); mcp77_ram_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
H A Dnv04.c37 #include <engine/dmaobj.h>
38 #include <engine/fifo.h>
39 #include <engine/sw.h>
40 #include <engine/gr.h>
41 #include <engine/disp.h>
H A Dgm100.c46 #include <engine/dmaobj.h>
47 #include <engine/fifo.h>
48 #include <engine/sw.h>
49 #include <engine/gr.h>
50 #include <engine/disp.h>
51 #include <engine/ce.h>
52 #include <engine/bsp.h>
53 #include <engine/msvld.h>
54 #include <engine/mspdec.h>
55 #include <engine/msppp.h>
56 #include <engine/pm.h>
H A Dnv30.c38 #include <engine/dmaobj.h>
39 #include <engine/fifo.h>
40 #include <engine/sw.h>
41 #include <engine/gr.h>
42 #include <engine/mpeg.h>
43 #include <engine/disp.h>
H A Dgk104.c46 #include <engine/dmaobj.h>
47 #include <engine/fifo.h>
48 #include <engine/sw.h>
49 #include <engine/gr.h>
50 #include <engine/disp.h>
51 #include <engine/ce.h>
52 #include <engine/bsp.h>
53 #include <engine/msvld.h>
54 #include <engine/mspdec.h>
55 #include <engine/msppp.h>
56 #include <engine/pm.h>
H A Dnv20.c39 #include <engine/dmaobj.h>
40 #include <engine/fifo.h>
41 #include <engine/sw.h>
42 #include <engine/gr.h>
43 #include <engine/disp.h>
H A Dgf100.c46 #include <engine/dmaobj.h>
47 #include <engine/fifo.h>
48 #include <engine/sw.h>
49 #include <engine/gr.h>
50 #include <engine/mspdec.h>
51 #include <engine/bsp.h>
52 #include <engine/msvld.h>
53 #include <engine/msppp.h>
54 #include <engine/ce.h>
55 #include <engine/disp.h>
56 #include <engine/pm.h>
H A Dnv50.c44 #include <engine/dmaobj.h>
45 #include <engine/fifo.h>
46 #include <engine/sw.h>
47 #include <engine/gr.h>
48 #include <engine/mpeg.h>
49 #include <engine/vp.h>
50 #include <engine/cipher.h>
51 #include <engine/sec.h>
52 #include <engine/bsp.h>
53 #include <engine/msvld.h>
54 #include <engine/mspdec.h>
55 #include <engine/msppp.h>
56 #include <engine/ce.h>
57 #include <engine/disp.h>
58 #include <engine/pm.h>
H A Dnv10.c38 #include <engine/dmaobj.h>
39 #include <engine/fifo.h>
40 #include <engine/sw.h>
41 #include <engine/gr.h>
42 #include <engine/disp.h>
H A Dbase.c167 return nv_rd08(object->engine, addr); nvkm_devobj_rd08()
173 return nv_rd16(object->engine, addr); nvkm_devobj_rd16()
179 return nv_rd32(object->engine, addr); nvkm_devobj_rd32()
185 nv_wr08(object->engine, addr, data); nvkm_devobj_wr08()
191 nv_wr16(object->engine, addr, data); nvkm_devobj_wr16()
197 nv_wr32(object->engine, addr, data); nvkm_devobj_wr32()
282 nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, argument
511 * nvkm_device: engine functions
518 if (device->engine == NULL) { nv_device()
522 device = &nv_object(obj)->engine->subdev.object; nv_device()
641 nvkm_engine_destroy(&device->engine); nvkm_device_dtor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dnv50.c29 #include <core/engine.h>
154 struct nvkm_engine *engine; nv50_vm_flush() local
165 engine = nvkm_engine(priv, i); nv50_vm_flush()
166 if (engine && engine->tlb_flush) { nv50_vm_flush()
167 engine->tlb_flush(engine); nv50_vm_flush()
189 nv_error(priv, "vm flush timeout: engine %d\n", vme); nv50_vm_flush()
206 nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_mmu_ctor() argument
213 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); nv50_mmu_ctor()
H A Dnv41.c85 nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv41_mmu_ctor() argument
95 return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, nv41_mmu_ctor()
99 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", nv41_mmu_ctor()
H A Dnv04.c84 nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_mmu_ctor() argument
92 ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART", nv04_mmu_ctor()
/linux-4.1.27/drivers/video/fbdev/aty/
H A Dmach64_accel.c16 /* this is for DMA GUI engine! work in progress */
41 /* reset engine */ aty_reset_engine()
45 /* enable engine */ aty_reset_engine()
48 /* ensure engine is not locked up by clearing any FIFO or */ aty_reset_engine()
74 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ aty_init_engine()
80 /* On GTC (RagePro), we need to reset the 3D engine before */ aty_init_engine()
84 /* Reset engine, enable, and clear any engine errors */ aty_init_engine()
92 /* ---- Setup standard engine context ---- */ aty_init_engine()
178 /* insure engine is idle before leaving */ aty_init_engine()
212 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ atyfb_copyarea()
264 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ atyfb_fillrect()
333 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ atyfb_imageblit()
/linux-4.1.27/drivers/dma/sh/
H A Dusb-dmac.c94 * @engine: base DMA engine object
101 struct dma_device engine; member in struct:usb_dmac
109 #define to_usb_dmac(d) container_of(d, struct usb_dmac, engine)
381 * DMA engine operations
739 vchan_init(&uchan->vc, &dmac->engine); usb_dmac_chan_probe()
769 struct dma_device *engine; usb_dmac_probe() local
814 INIT_LIST_HEAD(&dmac->engine.channels); usb_dmac_probe()
829 * Register the DMA engine device. usb_dmac_probe()
833 engine = &dmac->engine; usb_dmac_probe()
834 dma_cap_set(DMA_SLAVE, engine->cap_mask); usb_dmac_probe()
836 engine->dev = &pdev->dev; usb_dmac_probe()
838 engine->src_addr_widths = widths; usb_dmac_probe()
839 engine->dst_addr_widths = widths; usb_dmac_probe()
840 engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); usb_dmac_probe()
841 engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; usb_dmac_probe()
843 engine->device_alloc_chan_resources = usb_dmac_alloc_chan_resources; usb_dmac_probe()
844 engine->device_free_chan_resources = usb_dmac_free_chan_resources; usb_dmac_probe()
845 engine->device_prep_slave_sg = usb_dmac_prep_slave_sg; usb_dmac_probe()
846 engine->device_terminate_all = usb_dmac_chan_terminate_all; usb_dmac_probe()
847 engine->device_tx_status = usb_dmac_tx_status; usb_dmac_probe()
848 engine->device_issue_pending = usb_dmac_issue_pending; usb_dmac_probe()
850 ret = dma_async_device_register(engine); usb_dmac_probe()
877 dma_async_device_unregister(&dmac->engine); usb_dmac_remove()
H A Drcar-dmac.c171 * @engine: base DMA engine object
179 struct dma_device engine; member in struct:rcar_dmac
189 #define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine)
938 * DMA engine operations
1559 * Initialize the DMA engine channel and add it to the DMA engine rcar_dmac_chan_probe()
1562 chan->device = &dmac->engine; rcar_dmac_chan_probe()
1565 list_add_tail(&chan->device_node, &dmac->engine.channels); rcar_dmac_chan_probe()
1597 struct dma_device *engine; rcar_dmac_probe() local
1676 INIT_LIST_HEAD(&dmac->engine.channels); rcar_dmac_probe()
1692 * Register the DMA engine device. rcar_dmac_probe()
1696 engine = &dmac->engine; rcar_dmac_probe()
1697 dma_cap_set(DMA_MEMCPY, engine->cap_mask); rcar_dmac_probe()
1698 dma_cap_set(DMA_SLAVE, engine->cap_mask); rcar_dmac_probe()
1700 engine->dev = &pdev->dev; rcar_dmac_probe()
1701 engine->copy_align = ilog2(RCAR_DMAC_MEMCPY_XFER_SIZE); rcar_dmac_probe()
1703 engine->src_addr_widths = widths; rcar_dmac_probe()
1704 engine->dst_addr_widths = widths; rcar_dmac_probe()
1705 engine->directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); rcar_dmac_probe()
1706 engine->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; rcar_dmac_probe()
1708 engine->device_alloc_chan_resources = rcar_dmac_alloc_chan_resources; rcar_dmac_probe()
1709 engine->device_free_chan_resources = rcar_dmac_free_chan_resources; rcar_dmac_probe()
1710 engine->device_prep_dma_memcpy = rcar_dmac_prep_dma_memcpy; rcar_dmac_probe()
1711 engine->device_prep_slave_sg = rcar_dmac_prep_slave_sg; rcar_dmac_probe()
1712 engine->device_prep_dma_cyclic = rcar_dmac_prep_dma_cyclic; rcar_dmac_probe()
1713 engine->device_config = rcar_dmac_device_config; rcar_dmac_probe()
1714 engine->device_terminate_all = rcar_dmac_chan_terminate_all; rcar_dmac_probe()
1715 engine->device_tx_status = rcar_dmac_tx_status; rcar_dmac_probe()
1716 engine->device_issue_pending = rcar_dmac_issue_pending; rcar_dmac_probe()
1718 ret = dma_async_device_register(engine); rcar_dmac_probe()
1735 dma_async_device_unregister(&dmac->engine); rcar_dmac_remove()
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dr600_dma.c34 * DMA engine. The programming model is very similar
35 * to the 3D engine (ring buffer, IBs, etc.), but the
37 * different form the PM4 format used by the 3D engine.
93 * r600_dma_stop - stop the async dma engine
97 * Stop the async dma engine (r6xx-evergreen).
113 * r600_dma_resume - setup and start the async dma engine
187 * r600_dma_fini - tear down the async dma engine
191 * Stop the async dma engine and free the ring (r6xx-evergreen).
200 * r600_dma_is_lockup - Check if the DMA engine is locked up
205 * Check if the async DMA engine is locked up.
206 * Returns true if the engine appears to be locked up, false if not.
221 * r600_dma_ring_test - simple async dma engine test
226 * Test the DMA engine by writing using it to write an
329 * r600_dma_ib_test - test an IB on the DMA engine
393 * r600_dma_ring_ib_execute - Schedule an IB on the DMA engine
427 * r600_copy_dma - copy pages using the DMA engine
435 * Copy GPU paging using the DMA engine (r6xx).
H A Devergreen_dma.c60 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
95 * evergreen_copy_dma - copy pages using the DMA engine
103 * Copy GPU paging using the DMA engine (evergreen-cayman).
163 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
168 * Check if the async DMA engine is locked up.
169 * Returns true if the engine appears to be locked up, false if not.
H A Dsi_dma.c33 * si_dma_is_lockup - Check if the DMA engine is locked up
38 * Check if the async DMA engine is locked up.
39 * Returns true if the engine appears to be locked up, false if not.
219 * si_copy_dma - copy pages using the DMA engine
227 * Copy GPU paging using the DMA engine (SI).
H A Drv770_dma.c30 * rv770_copy_dma - copy pages using the DMA engine
38 * Copy GPU paging using the DMA engine (r7xx).
/linux-4.1.27/drivers/gpu/drm/omapdrm/
H A Domap_dmm_tiler.c73 /* lookup table for registers w/ per-engine instances */
85 struct refill_engine *engine = txn->engine_handle; alloc_dma() local
97 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE); alloc_dma()
103 static int wait_status(struct refill_engine *engine, uint32_t wait_mask) wait_status() argument
105 struct dmm *dmm = engine->dmm; wait_status()
110 r = readl(dmm->base + reg[PAT_STATUS][engine->id]); wait_status()
127 static void release_engine(struct refill_engine *engine) release_engine() argument
132 list_add(&engine->idle_node, &omap_dmm->idle_head); release_engine()
168 struct refill_engine *engine = NULL; dmm_txn_init() local
173 /* wait until an engine is available */ dmm_txn_init()
179 /* grab an idle engine */ dmm_txn_init()
182 engine = list_entry(dmm->idle_head.next, struct refill_engine, dmm_txn_init()
184 list_del(&engine->idle_node); dmm_txn_init()
188 BUG_ON(!engine); dmm_txn_init()
190 txn = &engine->txn; dmm_txn_init()
191 engine->tcm = tcm; dmm_txn_init()
192 txn->engine_handle = engine; dmm_txn_init()
194 txn->current_va = engine->refill_va; dmm_txn_init()
195 txn->current_pa = engine->refill_pa; dmm_txn_init()
210 struct refill_engine *engine = txn->engine_handle; dmm_txn_append() local
223 pat->area.y0 += engine->tcm->y_offset; dmm_txn_append()
224 pat->area.y1 += engine->tcm->y_offset; dmm_txn_append()
228 .lut_id = engine->tcm->lut_id, dmm_txn_append()
240 page_to_phys(pages[n]) : engine->dmm->dummy_pa; dmm_txn_append()
254 struct refill_engine *engine = txn->engine_handle; dmm_txn_commit() local
255 struct dmm *dmm = engine->dmm; dmm_txn_commit()
258 dev_err(engine->dmm->dev, "need at least one txn\n"); dmm_txn_commit()
266 writel(0x0, dmm->base + reg[PAT_DESCR][engine->id]); dmm_txn_commit()
268 /* wait for engine ready: */ dmm_txn_commit()
269 ret = wait_status(engine, DMM_PATSTATUS_READY); dmm_txn_commit()
276 engine->async = wait ? false : true; dmm_txn_commit()
277 reinit_completion(&engine->compl); dmm_txn_commit()
282 writel(engine->refill_pa, dmm_txn_commit()
283 dmm->base + reg[PAT_DESCR][engine->id]); dmm_txn_commit()
286 if (!wait_for_completion_timeout(&engine->compl, dmm_txn_commit()
294 /* only place engine back on list if we are done with it */ dmm_txn_commit()
296 release_engine(engine); dmm_txn_commit()
677 /* Enable all interrupts for each refill engine except omap_dmm_probe()
/linux-4.1.27/drivers/leds/
H A Dleds-lp5523.c39 0x00 engine 1 program
40 0x10 engine 2 program
41 0x20 engine 3 program
42 0x30 engine 1 muxing info
43 0x40 engine 2 muxing info
44 0x50 engine 3 muxing info
231 /* stop engine */ lp5523_run_engine()
239 * To run the engine, lp5523_run_engine()
251 /* change operation mode to RUN only when each engine is loading */ lp5523_run_engine()
279 /* one pattern per engine setting LED MUX start and stop addresses */ lp5523_init_program_engine()
286 /* hardcode 32 bytes of memory for each engine from program memory */ lp5523_init_program_engine()
299 /* write LED MUX address space for each engine */ lp5523_init_program_engine()
314 /* Let the programs run for couple of ms and check the engine status */ lp5523_init_program_engine()
321 "cound not configure LED engine, status = 0x%.2x\n", lp5523_init_program_engine()
386 * 1) set engine mode to "LOAD" lp5523_firmware_loaded()
422 struct lp55xx_engine *engine = &chip->engines[nr - 1]; store_engine_mode() local
430 engine->mode = LP55XX_ENGINE_RUN; store_engine_mode()
434 engine->mode = LP55XX_ENGINE_LOAD; store_engine_mode()
437 engine->mode = LP55XX_ENGINE_DISABLED; store_engine_mode()
501 struct lp55xx_engine *engine = &chip->engines[nr - 1]; lp5523_load_mux() local
523 engine->led_mux = mux; lp5523_load_mux()
533 struct lp55xx_engine *engine = &chip->engines[nr - 1]; store_engine_leds() local
545 if (engine->mode != LP55XX_ENGINE_LOAD) store_engine_leds()
838 MODULE_DESCRIPTION("LP5523 LED engine");
H A Dleds-lp5521.c180 /* stop engine */ lp5521_run_engine()
189 * To run the engine, lp5521_run_engine()
201 /* change operation mode to RUN only when each engine is loading */ lp5521_run_engine()
285 * 1) set engine mode to "LOAD" lp5521_firmware_loaded()
405 struct lp55xx_engine *engine = &chip->engines[nr - 1]; store_engine_mode() local
413 engine->mode = LP55XX_ENGINE_RUN; store_engine_mode()
417 engine->mode = LP55XX_ENGINE_LOAD; store_engine_mode()
420 engine->mode = LP55XX_ENGINE_DISABLED; store_engine_mode()
616 MODULE_DESCRIPTION("LP5521 LED engine");
H A Dleds-lp8501.c166 /* stop engine */ lp8501_run_engine()
174 * To run the engine, lp8501_run_engine()
186 /* change operation mode to RUN only when each engine is loading */ lp8501_run_engine()
267 * 1) set engine mode to "LOAD" lp8501_firmware_loaded()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dxtensa.c22 #include <engine/xtensa.h>
42 _nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_xtensa_engctx_ctor() argument
49 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000, _nvkm_xtensa_engctx_ctor()
65 nv_warn(xtensa, "Watchdog interrupt, engine hung.\n"); _nvkm_xtensa_intr()
75 nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_xtensa_create_() argument
83 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, nvkm_xtensa_create_()
H A Dfalcon.c22 #include <engine/falcon.h>
80 /* enable engine, and determine its capabilities */ _nvkm_falcon_init()
116 /* no default ucode provided by the engine implementation, try and _nvkm_falcon_init()
117 * locate a "self-bootstrapping" firmware image for the engine _nvkm_falcon_init()
136 * images for the engine _nvkm_falcon_init()
261 nvkm_falcon_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_falcon_create_() argument
269 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, nvkm_falcon_create_()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dbase.c26 #include <core/engine.h>
46 nvkm_instobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_instobj_create_() argument
53 ret = nvkm_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS, nvkm_instobj_create_()
75 return nvkm_object_ctor(parent, &parent->engine->subdev.object, nvkm_instmem_alloc()
131 nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_instmem_create_() argument
137 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "INSTMEM", nvkm_instmem_create_()
H A Dnv04.c63 nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_instobj_ctor() argument
76 ret = nvkm_instobj_create(parent, engine, oclass, &node); nv04_instobj_ctor()
136 nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_instmem_ctor() argument
143 ret = nvkm_instmem_create(parent, engine, oclass, &priv); nv04_instmem_ctor()
H A Dnv40.c27 #include <engine/gr/nv40.h>
48 nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_instmem_ctor() argument
56 ret = nvkm_instmem_create(parent, engine, oclass, &priv); nv40_instmem_ctor()
76 * from engine/gr/nv40.c nv40_instmem_ctor()
H A Dnv50.c91 nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_instobj_ctor() argument
103 ret = nvkm_instobj_create(parent, engine, oclass, &node); nv50_instobj_ctor()
143 nv50_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_instmem_ctor() argument
150 ret = nvkm_instmem_create(parent, engine, oclass, &priv); nv50_instmem_ctor()
H A Dgk20a.c203 gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_instobj_ctor_dma() argument
212 ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node), gk20a_instobj_ctor_dma()
245 gk20a_instobj_ctor_iommu(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_instobj_ctor_iommu() argument
255 ret = nvkm_instobj_create_(parent, engine, oclass, gk20a_instobj_ctor_iommu()
324 gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_instobj_ctor() argument
342 ret = gk20a_instobj_ctor_iommu(parent, engine, oclass, gk20a_instobj_ctor()
345 ret = gk20a_instobj_ctor_dma(parent, engine, oclass, gk20a_instobj_ctor()
390 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_instmem_ctor() argument
398 ret = nvkm_instmem_create(parent, engine, oclass, &priv); gk20a_instmem_ctor()
/linux-4.1.27/drivers/dma/
H A Ddmaengine.h2 * The contents of this file are private to DMA engine drivers, and is not
3 * part of the API to be used by DMA engine users.
22 * dma_cookie_assign - assign a DMA engine cookie to the descriptor
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dbase.c112 struct nvkm_pm *ppm = (void *)object->engine; nvkm_perfctr_query()
170 struct nvkm_pm *ppm = (void *)object->engine; nvkm_perfctr_sample()
266 nvkm_perfctr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_perfctr_ctor() argument
273 struct nvkm_pm *ppm = (void *)engine; nvkm_perfctr_ctor()
295 ret = nvkm_object_create(parent, engine, oclass, 0, &ctr); nvkm_perfctr_ctor()
334 struct nvkm_pm *ppm = (void *)object->engine; nvkm_perfctx_dtor()
342 nvkm_perfctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_perfctx_ctor() argument
346 struct nvkm_pm *ppm = (void *)engine; nvkm_perfctx_ctor()
350 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0, 0, 0, &ctx); nvkm_perfctx_ctor()
378 * PPM engine/subdev functions
462 nvkm_pm_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_pm_create_() argument
468 ret = nvkm_engine_create_(parent, engine, oclass, true, "PPM", nvkm_pm_create_()
H A Dgk110.c27 gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk110_pm_ctor() argument
34 ret = nvkm_pm_create(parent, engine, oclass, &priv); gk110_pm_ctor()
H A Dgt215.c56 gt215_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gt215_pm_ctor() argument
60 int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object); gt215_pm_ctor()
H A Dgk104.c89 gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_pm_ctor() argument
97 ret = nvkm_pm_create(parent, engine, oclass, &priv); gk104_pm_ctor()
H A Dpriv.h3 #include <engine/pm.h>
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dpriv.h3 #include <engine/disp.h>
H A Dg94.c78 * Display engine implementation
82 g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g94_disp_ctor() argument
89 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", g94_disp_ctor()
H A Dgk110.c49 * Display engine implementation
53 gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk110_disp_ctor() argument
61 ret = nvkm_disp_create(parent, engine, oclass, heads, gk110_disp_ctor()
H A Dgm107.c49 * Display engine implementation
53 gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm107_disp_ctor() argument
61 ret = nvkm_disp_create(parent, engine, oclass, heads, gm107_disp_ctor()
H A Dgm204.c50 * Display engine implementation
54 gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm204_disp_ctor() argument
62 ret = nvkm_disp_create(parent, engine, oclass, heads, gm204_disp_ctor()
H A Dgt200.c94 * Display engine implementation
98 gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gt200_disp_ctor() argument
105 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", gt200_disp_ctor()
H A Dgt215.c49 * Display engine implementation
53 gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gt215_disp_ctor() argument
60 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", gt215_disp_ctor()
H A Dconn.c82 struct nvkm_object *engine, nvkm_connector_create_()
103 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); nvkm_connector_create_()
148 struct nvkm_object *engine, _nvkm_connector_ctor()
155 ret = nvkm_connector_create(parent, engine, oclass, info, index, &conn); _nvkm_connector_ctor()
81 nvkm_connector_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, struct nvbios_connE *info, int index, int length, void **pobject) nvkm_connector_create_() argument
147 _nvkm_connector_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) _nvkm_connector_ctor() argument
H A Dnv04.c83 struct nv04_disp_priv *priv = (void *)object->engine; nv04_disp_mthd()
125 * Display engine implementation
177 nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_disp_ctor() argument
184 ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY", nv04_disp_ctor()
H A Doutp.c61 struct nvkm_object *engine, nvkm_output_create_()
75 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); nvkm_output_create_()
116 struct nvkm_object *engine, _nvkm_output_ctor()
123 ret = nvkm_output_create(parent, engine, oclass, dcbE, index, &outp); _nvkm_output_ctor()
60 nvkm_output_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, struct dcb_output *dcbE, int index, int length, void **pobject) nvkm_output_create_() argument
115 _nvkm_output_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *dcbE, u32 index, struct nvkm_object **pobject) _nvkm_output_ctor() argument
H A Dpiornv50.c40 struct nvkm_object *engine, nv50_pior_tmds_ctor()
48 ret = nvkm_output_create(parent, engine, oclass, info, index, &outp); nv50_pior_tmds_ctor()
107 struct nvkm_object *engine, nv50_pior_dp_ctor()
115 ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); nv50_pior_dp_ctor()
39 nv50_pior_tmds_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) nv50_pior_tmds_ctor() argument
106 nv50_pior_dp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) nv50_pior_dp_ctor() argument
H A Dnv50.c34 #include <engine/dmaobj.h>
54 struct nvkm_object *engine, nv50_disp_chan_create_()
68 ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, nv50_disp_chan_create_()
145 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_chan_ntfy()
169 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_chan_rd32()
177 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_chan_wr32()
207 struct nvkm_object *engine, nv50_disp_dmac_create_()
214 ret = nv50_disp_chan_create_(parent, engine, oclass, head, nv50_disp_dmac_create_()
259 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_dmac_init()
292 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_dmac_fini()
489 struct nvkm_object *engine, nv50_disp_core_ctor()
507 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, nv50_disp_core_ctor()
519 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_core_init()
556 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_core_fini()
645 struct nvkm_object *engine, nv50_disp_base_ctor()
652 struct nv50_disp_priv *priv = (void *)engine; nv50_disp_base_ctor()
666 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, nv50_disp_base_ctor()
735 struct nvkm_object *engine, nv50_disp_ovly_ctor()
742 struct nv50_disp_priv *priv = (void *)engine; nv50_disp_ovly_ctor()
756 ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, nv50_disp_ovly_ctor()
787 struct nvkm_object *engine, nv50_disp_pioc_create_()
791 return nv50_disp_chan_create_(parent, engine, oclass, head, nv50_disp_pioc_create_()
805 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_pioc_init()
834 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_pioc_fini()
855 struct nvkm_object *engine, nv50_disp_oimm_ctor()
862 struct nv50_disp_priv *priv = (void *)engine; nv50_disp_oimm_ctor()
875 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, nv50_disp_oimm_ctor()
903 struct nvkm_object *engine, nv50_disp_curs_ctor()
910 struct nv50_disp_priv *priv = (void *)engine; nv50_disp_curs_ctor()
923 ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, nv50_disp_curs_ctor()
984 const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine); nv50_disp_main_mthd()
989 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_main_mthd()
1106 struct nvkm_object *engine, nv50_disp_main_ctor()
1110 struct nv50_disp_priv *priv = (void *)engine; nv50_disp_main_ctor()
1114 ret = nvkm_parent_create(parent, engine, oclass, 0, nv50_disp_main_ctor()
1135 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_main_init()
1191 /* point at display engine memory area (hash table, objects) */ nv50_disp_main_init()
1203 struct nv50_disp_priv *priv = (void *)object->engine; nv50_disp_main_fini()
1246 struct nvkm_object *engine, nv50_disp_data_ctor()
1250 struct nv50_disp_priv *priv = (void *)engine; nv50_disp_data_ctor()
1264 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, nv50_disp_data_ctor()
1286 * Display engine implementation
1964 nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_disp_ctor() argument
1971 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", nv50_disp_ctor()
53 nv50_disp_chan_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int head, int length, void **pobject) nv50_disp_chan_create_() argument
206 nv50_disp_dmac_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, u32 pushbuf, int head, int length, void **pobject) nv50_disp_dmac_create_() argument
488 nv50_disp_core_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_core_ctor() argument
644 nv50_disp_base_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_base_ctor() argument
734 nv50_disp_ovly_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_ovly_ctor() argument
786 nv50_disp_pioc_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, int head, int length, void **pobject) nv50_disp_pioc_create_() argument
854 nv50_disp_oimm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_oimm_ctor() argument
902 nv50_disp_curs_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_curs_ctor() argument
1105 nv50_disp_main_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_main_ctor() argument
1245 nv50_disp_data_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) nv50_disp_data_ctor() argument
H A Dg84.c218 * Display engine implementation
222 g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, g84_disp_ctor() argument
229 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", g84_disp_ctor()
H A Dgk104.c214 * Display engine implementation
218 gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk104_disp_ctor() argument
226 ret = nvkm_disp_create(parent, engine, oclass, heads, gk104_disp_ctor()
H A Doutpdp.c213 struct nvkm_object *engine, nvkm_output_dp_create_()
225 ret = nvkm_output_create_(parent, engine, oclass, info, index, nvkm_output_dp_create_()
288 struct nvkm_object *engine, _nvkm_output_dp_ctor()
295 ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); _nvkm_output_dp_ctor()
212 nvkm_output_dp_create_(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, struct dcb_output *info, int index, int length, void **pobject) nvkm_output_dp_create_() argument
287 _nvkm_output_dp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *info, u32 index, struct nvkm_object **pobject) _nvkm_output_dp_ctor() argument
/linux-4.1.27/arch/ia64/include/asm/
H A Dagp.h12 * To avoid memory-attribute aliasing issues, we require that the AGPGART engine operate
/linux-4.1.27/include/linux/
H A Dedma.h2 * TI EDMA DMA engine driver
H A Dccp.h76 /***** AES engine *****/
168 /***** XTS-AES engine *****/
222 /***** SHA engine *****/
278 /***** RSA engine *****/
306 /***** Passthru engine *****/
367 /***** ECC engine *****/
517 * @engine: CCP operation to perform
518 * @engine_error: CCP engine return code
519 * @u: engine specific structures, refer to specific engine struct below
524 * - engine, callback
539 enum ccp_engine engine; member in struct:ccp_cmd
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
H A Dgk20a.c25 gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_bar_ctor() argument
32 ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject); gk20a_bar_ctor()
H A Dbase.c37 nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_barobj_ctor() argument
47 ret = nvkm_object_create(parent, engine, oclass, 0, &barobj); nvkm_barobj_ctor()
110 int ret = nvkm_object_ctor(parent, &parent->engine->subdev.object, nvkm_bar_alloc()
118 nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_bar_create_() argument
124 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL", nvkm_bar_create_()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
H A Dbase.c41 nvkm_fuse_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_fuse_create_() argument
47 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "FUSE", nvkm_fuse_create_()
H A Dgm107.c39 gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm107_fuse_ctor() argument
46 ret = nvkm_fuse_create(parent, engine, oclass, &priv); gm107_fuse_ctor()
H A Dgf100.c52 gf100_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_fuse_ctor() argument
59 ret = nvkm_fuse_create(parent, engine, oclass, &priv); gf100_fuse_ctor()
H A Dnv50.c50 nv50_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv50_fuse_ctor() argument
57 ret = nvkm_fuse_create(parent, engine, oclass, &priv); nv50_fuse_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
H A Dnv40.c31 nv40_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv40_volt_ctor() argument
38 ret = nvkm_volt_create(parent, engine, oclass, &priv); nv40_volt_ctor()
/linux-4.1.27/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_dev_enet.h49 /* DMA engine has internal SRAM */
93 /* DMA engine has internal SRAM */
/linux-4.1.27/drivers/staging/sm750fb/
H A Dddk750_power.h36 * This function enable/disable the 2D engine.
H A Dddk750_chip.h60 unsigned short setAllEngOff; /* 0 = leave all engine state untouched.
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
H A Dnv04.c53 nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_mc_ctor() argument
60 ret = nvkm_mc_create(parent, engine, oclass, &priv); nv04_mc_ctor()
/linux-4.1.27/drivers/ata/
H A Dpata_sl82c105.c130 * sl82c105_reset_engine - Reset the DMA engine
133 * The sl82c105 has some serious problems with the DMA engine
135 * recommended fix is to reset the engine each use using a chip
150 * sl82c105_bmdma_start - DMA engine begin
153 * Reset the DMA engine each use as recommended by the errata
175 * sl82c105_bmdma_end - DMA engine stop
178 * Reset the DMA engine each use as recommended by the errata
182 * during DMA operation. In both cases we need to reset the engine,
/linux-4.1.27/drivers/video/fbdev/sis/
H A Dsis_accel.h50 /* Definitions for the SIS engine communication. */
56 /* SiS300 engine commands */
65 /* Additional engine commands for 315 */
146 bit 31 2D engine: 1 is idle,
147 bit 30 3D engine: 1 is idle,
161 /* (do three times, because 2D engine seems quite unsure about whether or not it's idle) */
273 bit 29 = 1: 2D engine is idle
274 bit 28 = 1: 3D engine is idle
/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_lrc.c49 * shouldn't we just need a set of those per engine command streamer? This is
51 * rings, the engine cs shifts to a new "ring buffer" with every context
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
75 * more complex, because we don't know at creation time which engine is going
80 * gets populated for a given engine once we receive an execbuffer. If later
82 * engine, we allocate/populate a new ringbuffer and context backing object and
99 * for the appropriate engine: this structure contains a copy of the context's
103 * If the engine's request queue was empty before the request was added, the
343 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; execlists_submit_contexts()
344 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; execlists_submit_contexts()
355 ringbuf1 = to1->engine[ring->id].ringbuf; execlists_submit_contexts()
356 ctx_obj1 = to1->engine[ring->id].state; execlists_submit_contexts()
410 ringbuf = req0->ctx->engine[ring->id].ringbuf; execlists_context_unqueue()
440 head_req->ctx->engine[ring->id].state; execlists_check_remove_request()
660 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; intel_execlists_submission()
761 ctx->engine[ring->id].state; intel_execlists_retire_requests()
837 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; intel_lr_context_pin()
838 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; intel_lr_context_pin()
842 if (ctx->engine[ring->id].pin_count++ == 0) { intel_lr_context_pin()
860 ctx->engine[ring->id].pin_count = 0; intel_lr_context_pin()
868 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; intel_lr_context_unpin()
869 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; intel_lr_context_unpin()
873 if (--ctx->engine[ring->id].pin_count == 0) { intel_lr_context_unpin()
915 request->ringbuf = ctx->engine[ring->id].ringbuf; logical_ring_alloc_request()
933 * The request queue is per-engine, so can contain requests logical_ring_wait_request()
938 if (ctx->engine[ring->id].ringbuf != ringbuf) logical_ring_wait_request()
1097 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; intel_logical_ring_workarounds_emit()
1384 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; intel_lr_context_render_state_init()
1846 * takes care of the bits that are LRC related: the per-engine backing
1854 struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; intel_lr_context_free()
1858 ctx->engine[i].ringbuf; intel_lr_context_free()
1865 WARN_ON(ctx->engine[ring->id].pin_count); intel_lr_context_free()
1917 * @ring: engine to be used with the context.
1938 WARN_ON(ctx->engine[ring->id].state); intel_lr_context_deferred_create()
2003 ctx->engine[ring->id].ringbuf = ringbuf; intel_lr_context_deferred_create()
2004 ctx->engine[ring->id].state = ctx_obj; intel_lr_context_deferred_create()
2013 ctx->engine[ring->id].ringbuf = NULL; intel_lr_context_deferred_create()
2014 ctx->engine[ring->id].state = NULL; intel_lr_context_deferred_create()
2047 ctx->engine[ring->id].state; for_each_ring()
2049 ctx->engine[ring->id].ringbuf; for_each_ring()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dbase.c126 /* right now there's no other expected responses from the engine, nvkm_pmu_recv()
242 nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_pmu_create_() argument
248 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU", nvkm_pmu_create_()
260 _nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, _nvkm_pmu_ctor() argument
265 int ret = nvkm_pmu_create(parent, engine, oclass, &pmu); _nvkm_pmu_ctor()
/linux-4.1.27/include/linux/fsl/bestcomm/
H A Dbestcomm_priv.h5 * to be used by the BestComm engine driver itself and by the intermediate
57 u32 exec_status; /* used internally by BestComm engine */
58 u32 mvtp; /* used internally by BestComm engine */
66 * This holds all info needed globaly to handle the engine
121 * lasts words, the engine tries to prefetch the next but there is no
/linux-4.1.27/drivers/isdn/sc/
H A Dmessage.c102 * Make sure we only send CEPID messages when the engine is up sendmessage()
106 pr_debug("%s: Attempt to send CM message with engine up\n", sendmessage()
112 pr_debug("%s: Attempt to send CE message with engine down\n", sendmessage()
/linux-4.1.27/arch/mips/include/asm/mach-pmcs-msp71xx/
H A Dmsp_cic_int.h53 #define MSP_INT_SEC 7 /* IRQ for Sec engine, C_IRQ5 */
76 /* Sec engine mailbox IRQ */
86 /* Cascaded IRQ for sec engine */
/linux-4.1.27/drivers/media/platform/xilinx/
H A Dxilinx-dma.h38 * @output: DMA engine at the output of the pipeline
72 * @dma: DMA engine channel
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
H A Dnv04.c65 nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_bus_ctor() argument
73 ret = nvkm_bus_create(parent, engine, oclass, &priv); nv04_bus_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv04.c76 nv04_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, nv04_clk_ctor() argument
83 ret = nvkm_clk_create(parent, engine, oclass, nv04_domain, nv04_clk_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dbase.c77 nvkm_devinit_create_(struct nvkm_object *parent, struct nvkm_object *engine, nvkm_devinit_create_() argument
85 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "DEVINIT", nvkm_devinit_create_()
H A Dgf100.c94 gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_devinit_ctor() argument
103 ret = nvkm_devinit_create(parent, engine, oclass, &priv); gf100_devinit_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
H A Dgf100.c97 gf100_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gf100_ibus_ctor() argument
104 ret = nvkm_ibus_create(parent, engine, oclass, &priv); gf100_ibus_ctor()
H A Dgk20a.c77 gk20a_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gk20a_ibus_ctor() argument
84 ret = nvkm_ibus_create(parent, engine, oclass, &priv); gk20a_ibus_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dgm107.c62 gm107_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gm107_therm_ctor() argument
69 ret = nvkm_therm_create(parent, engine, oclass, &priv); gm107_therm_ctor()
H A Dgt215.c69 gt215_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, gt215_therm_ctor() argument
76 ret = nvkm_therm_create(parent, engine, oclass, &priv); gt215_therm_ctor()
/linux-4.1.27/crypto/async_tx/
H A Dasync_memcpy.c2 * copy offload engine support
34 * async_memcpy - attempt to copy memory with a dma engine.
/linux-4.1.27/drivers/media/platform/s5p-g2d/
H A Dg2d-hw.c110 /* Start G2D engine */ g2d_start()
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Daccel_2d.c44 * psb_spank - reset the 2D engine
47 * Soft reset the graphics engine and then reload the necessary registers.
320 * Wait for the 2D engine to quiesce so that we can do CPU
335 * First idle the 2D engine. psbfb_sync()

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