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Searched refs:engine (Results 1 – 200 of 323) sorted by relevance

12

/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
DKbuild1 nvkm-y += nvkm/engine/gr/ctxnv40.o
2 nvkm-y += nvkm/engine/gr/ctxnv50.o
3 nvkm-y += nvkm/engine/gr/ctxgf100.o
4 nvkm-y += nvkm/engine/gr/ctxgf108.o
5 nvkm-y += nvkm/engine/gr/ctxgf104.o
6 nvkm-y += nvkm/engine/gr/ctxgf110.o
7 nvkm-y += nvkm/engine/gr/ctxgf117.o
8 nvkm-y += nvkm/engine/gr/ctxgf119.o
9 nvkm-y += nvkm/engine/gr/ctxgk104.o
10 nvkm-y += nvkm/engine/gr/ctxgk20a.o
[all …]
Dnv20.c40 nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv20_gr_context_ctor() argument
47 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0, in nv20_gr_context_ctor()
105 struct nv20_gr_priv *priv = (void *)object->engine; in nv20_gr_context_init()
120 struct nv20_gr_priv *priv = (void *)object->engine; in nv20_gr_context_fini()
158 nv20_gr_tile_prog(struct nvkm_engine *engine, int i) in nv20_gr_tile_prog() argument
160 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv20_gr_tile_prog()
161 struct nvkm_fifo *pfifo = nvkm_fifo(engine); in nv20_gr_tile_prog()
162 struct nv20_gr_priv *priv = (void *)engine; in nv20_gr_tile_prog()
179 if (nv_device(engine)->chipset != 0x34) { in nv20_gr_tile_prog()
191 struct nvkm_engine *engine = nv_engine(subdev); in nv20_gr_intr() local
[all …]
Dnv40.c55 nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_gr_object_ctor() argument
62 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, in nv40_gr_object_ctor()
136 nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_gr_context_ctor() argument
140 struct nv40_gr_priv *priv = (void *)engine; in nv40_gr_context_ctor()
144 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, in nv40_gr_context_ctor()
158 struct nv40_gr_priv *priv = (void *)object->engine; in nv40_gr_context_fini()
206 nv40_gr_tile_prog(struct nvkm_engine *engine, int i) in nv40_gr_tile_prog() argument
208 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv40_gr_tile_prog()
209 struct nvkm_fifo *pfifo = nvkm_fifo(engine); in nv40_gr_tile_prog()
210 struct nv40_gr_priv *priv = (void *)engine; in nv40_gr_tile_prog()
[all …]
Dnv30.c39 nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv30_gr_context_ctor() argument
46 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48, in nv30_gr_context_ctor()
127 nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv30_gr_ctor() argument
134 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv30_gr_ctor()
155 struct nvkm_engine *engine = nv_engine(object); in nv30_gr_init() local
156 struct nv20_gr_priv *priv = (void *)engine; in nv30_gr_init()
203 engine->tile_prog(engine, i); in nv30_gr_init()
Dnv04.c365 return (void *)nv_object(chan)->engine; in nv04_gr_priv()
449 struct nv04_gr_priv *priv = (void *)object->engine; in nv04_gr_set_ctx1()
531 struct nv04_gr_priv *priv = (void *)object->engine; in nv04_gr_mthd_surf3d_clip_h()
552 struct nv04_gr_priv *priv = (void *)object->engine; in nv04_gr_mthd_surf3d_clip_v()
951 nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_gr_object_ctor() argument
958 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, in nv04_gr_object_ctor()
1114 struct nvkm_object *engine, in nv04_gr_context_ctor() argument
1119 struct nv04_gr_priv *priv = (void *)engine; in nv04_gr_context_ctor()
1124 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); in nv04_gr_context_ctor()
1149 struct nv04_gr_priv *priv = (void *)object->engine; in nv04_gr_context_dtor()
[all …]
Dnv2a.c11 nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv2a_gr_context_ctor() argument
18 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0, in nv2a_gr_context_ctor()
91 nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv2a_gr_ctor() argument
98 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv2a_gr_ctor()
Dnv50.c55 nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_gr_object_ctor() argument
62 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, in nv50_gr_object_ctor()
142 nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_gr_context_ctor() argument
146 struct nv50_gr_priv *priv = (void *)engine; in nv50_gr_context_ctor()
150 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size, in nv50_gr_context_ctor()
239 g84_gr_tlb_flush(struct nvkm_engine *engine) in g84_gr_tlb_flush() argument
241 struct nvkm_timer *ptimer = nvkm_timer(engine); in g84_gr_tlb_flush()
242 struct nv50_gr_priv *priv = (void *)engine; in g84_gr_tlb_flush()
787 struct nvkm_engine *engine = nv_engine(subdev); in nv50_gr_intr() local
801 engctx = nvkm_engctx_get(engine, inst); in nv50_gr_intr()
[all …]
Dnv25.c35 nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv25_gr_context_ctor() argument
42 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724, in nv25_gr_context_ctor()
124 nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv25_gr_ctor() argument
131 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv25_gr_ctor()
Dnv10.c408 return (void *)nv_object(chan)->engine; in nv10_gr_priv()
1021 nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv10_gr_context_ctor() argument
1026 struct nv10_gr_priv *priv = (void *)engine; in nv10_gr_context_ctor()
1031 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); in nv10_gr_context_ctor()
1076 struct nv10_gr_priv *priv = (void *)object->engine; in nv10_gr_context_dtor()
1090 struct nv10_gr_priv *priv = (void *)object->engine; in nv10_gr_context_fini()
1120 nv10_gr_tile_prog(struct nvkm_engine *engine, int i) in nv10_gr_tile_prog() argument
1122 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv10_gr_tile_prog()
1123 struct nvkm_fifo *pfifo = nvkm_fifo(engine); in nv10_gr_tile_prog()
1124 struct nv10_gr_priv *priv = (void *)engine; in nv10_gr_tile_prog()
[all …]
Dnv35.c37 nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv35_gr_context_ctor() argument
44 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c, in nv35_gr_context_ctor()
125 nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv35_gr_ctor() argument
132 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv35_gr_ctor()
Dnv34.c37 nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv34_gr_context_ctor() argument
44 ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc, in nv34_gr_context_ctor()
125 nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv34_gr_ctor() argument
132 ret = nvkm_gr_create(parent, engine, oclass, true, &priv); in nv34_gr_ctor()
/linux-4.1.27/drivers/video/fbdev/via/
Daccel.c27 static int viafb_set_bpp(void __iomem *engine, u8 bpp) in viafb_set_bpp() argument
33 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
48 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
53 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, in hw_bitblt_1() argument
93 ret = viafb_set_bpp(engine, dst_bpp); in hw_bitblt_1()
105 writel(tmp, engine + 0x08); in hw_bitblt_1()
114 writel(tmp, engine + 0x0C); in hw_bitblt_1()
122 writel(tmp, engine + 0x10); in hw_bitblt_1()
125 writel(fg_color, engine + 0x18); in hw_bitblt_1()
128 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
DKbuild1 nvkm-y += nvkm/engine/disp/base.o
2 nvkm-y += nvkm/engine/disp/conn.o
3 nvkm-y += nvkm/engine/disp/outp.o
4 nvkm-y += nvkm/engine/disp/outpdp.o
5 nvkm-y += nvkm/engine/disp/nv04.o
6 nvkm-y += nvkm/engine/disp/nv50.o
7 nvkm-y += nvkm/engine/disp/g84.o
8 nvkm-y += nvkm/engine/disp/g94.o
9 nvkm-y += nvkm/engine/disp/gt200.o
10 nvkm-y += nvkm/engine/disp/gt215.o
[all …]
Dnv50.c54 struct nvkm_object *engine, in nv50_disp_chan_create_() argument
68 ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, in nv50_disp_chan_create_()
145 struct nv50_disp_priv *priv = (void *)object->engine; in nv50_disp_chan_ntfy()
169 struct nv50_disp_priv *priv = (void *)object->engine; in nv50_disp_chan_rd32()
177 struct nv50_disp_priv *priv = (void *)object->engine; in nv50_disp_chan_wr32()
207 struct nvkm_object *engine, in nv50_disp_dmac_create_() argument
214 ret = nv50_disp_chan_create_(parent, engine, oclass, head, in nv50_disp_dmac_create_()
259 struct nv50_disp_priv *priv = (void *)object->engine; in nv50_disp_dmac_init()
292 struct nv50_disp_priv *priv = (void *)object->engine; in nv50_disp_dmac_fini()
489 struct nvkm_object *engine, in nv50_disp_core_ctor() argument
[all …]
Doutp.c61 struct nvkm_object *engine, in nvkm_output_create_() argument
75 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); in nvkm_output_create_()
116 struct nvkm_object *engine, in _nvkm_output_ctor() argument
123 ret = nvkm_output_create(parent, engine, oclass, dcbE, index, &outp); in _nvkm_output_ctor()
Dpiornv50.c40 struct nvkm_object *engine, in nv50_pior_tmds_ctor() argument
48 ret = nvkm_output_create(parent, engine, oclass, info, index, &outp); in nv50_pior_tmds_ctor()
107 struct nvkm_object *engine, in nv50_pior_dp_ctor() argument
115 ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); in nv50_pior_dp_ctor()
Dconn.c82 struct nvkm_object *engine, in nvkm_connector_create_() argument
103 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); in nvkm_connector_create_()
148 struct nvkm_object *engine, in _nvkm_connector_ctor() argument
155 ret = nvkm_connector_create(parent, engine, oclass, info, index, &conn); in _nvkm_connector_ctor()
Dnv04.c83 struct nv04_disp_priv *priv = (void *)object->engine; in nv04_disp_mthd()
177 nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_disp_ctor() argument
184 ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY", in nv04_disp_ctor()
Doutpdp.c213 struct nvkm_object *engine, in nvkm_output_dp_create_() argument
225 ret = nvkm_output_create_(parent, engine, oclass, info, index, in nvkm_output_dp_create_()
288 struct nvkm_object *engine, in _nvkm_output_dp_ctor() argument
295 ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); in _nvkm_output_dp_ctor()
Dgm107.c53 gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm107_disp_ctor() argument
61 ret = nvkm_disp_create(parent, engine, oclass, heads, in gm107_disp_ctor()
Dgt215.c53 gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gt215_disp_ctor() argument
60 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", in gt215_disp_ctor()
Dgk110.c53 gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk110_disp_ctor() argument
61 ret = nvkm_disp_create(parent, engine, oclass, heads, in gk110_disp_ctor()
Dgt200.c98 gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gt200_disp_ctor() argument
105 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", in gt200_disp_ctor()
Dgm204.c54 gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm204_disp_ctor() argument
62 ret = nvkm_disp_create(parent, engine, oclass, heads, in gm204_disp_ctor()
Dbase.c103 struct nvkm_disp *disp = (void *)object->engine; in nvkm_disp_ntfy()
186 nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_disp_create_() argument
200 ret = nvkm_engine_create_(parent, engine, oclass, true, intname, in nvkm_disp_create_()
Dg94.c82 g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g94_disp_ctor() argument
89 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", in g94_disp_ctor()
Dgk104.c218 gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_disp_ctor() argument
226 ret = nvkm_disp_create(parent, engine, oclass, heads, in gk104_disp_ctor()
Dg84.c222 g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g84_disp_ctor() argument
229 ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", in g84_disp_ctor()
Dgf110.c94 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_dmac_init()
127 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_dmac_fini()
295 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_core_init()
326 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_core_fini()
542 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_pioc_init()
568 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_pioc_fini()
660 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_main_init()
729 struct nv50_disp_priv *priv = (void *)object->engine; in gf110_disp_main_fini()
1254 gf110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf110_disp_ctor() argument
1262 ret = nvkm_disp_create(parent, engine, oclass, heads, in gf110_disp_ctor()
/linux-4.1.27/drivers/crypto/
Dpicoxcell_crypto.c93 struct spacc_engine *engine; member
142 struct spacc_engine *engine; member
150 struct spacc_engine *engine; member
187 static inline int spacc_fifo_cmd_full(struct spacc_engine *engine) in spacc_fifo_cmd_full() argument
189 u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET); in spacc_fifo_cmd_full()
205 return is_cipher_ctx ? ctx->engine->cipher_ctx_base + in spacc_ctx_page_addr()
206 (indx * ctx->engine->cipher_pg_sz) : in spacc_ctx_page_addr()
207 ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz); in spacc_ctx_page_addr()
241 unsigned indx = ctx->engine->next_ctx++; in spacc_load_ctx()
247 ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1; in spacc_load_ctx()
[all …]
DKconfig17 Some VIA processors come with an integrated crypto engine
53 tristate "Support for the Geode LX AES engine"
59 engine for the CryptoAPI AES algorithm.
233 Driver for the IXP4xx NPE crypto engine.
257 tristate "Support for OMAP AES hw engine"
266 tristate "Support for OMAP DES3DES hw engine"
330 Driver for ST-Ericsson UX500 crypto engine.
424 tristate "Qualcomm crypto engine accelerator"
435 This driver supports Qualcomm crypto engine accelerator
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
DKbuild1 nvkm-y += nvkm/engine/falcon.o
2 nvkm-y += nvkm/engine/xtensa.o
4 include $(src)/nvkm/engine/bsp/Kbuild
5 include $(src)/nvkm/engine/ce/Kbuild
6 include $(src)/nvkm/engine/cipher/Kbuild
7 include $(src)/nvkm/engine/device/Kbuild
8 include $(src)/nvkm/engine/disp/Kbuild
9 include $(src)/nvkm/engine/dmaobj/Kbuild
10 include $(src)/nvkm/engine/fifo/Kbuild
11 include $(src)/nvkm/engine/gr/Kbuild
[all …]
Dxtensa.c42 _nvkm_xtensa_engctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_xtensa_engctx_ctor() argument
49 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x1000, in _nvkm_xtensa_engctx_ctor()
75 nvkm_xtensa_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_xtensa_create_() argument
83 ret = nvkm_engine_create_(parent, engine, oclass, enable, iname, in nvkm_xtensa_create_()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/core/
Dengctx.c30 struct nvkm_engine *engine, void **pobject) in nvkm_engctx_exists() argument
35 list_for_each_entry(engctx, &engine->contexts, head) { in nvkm_engctx_exists()
53 struct nvkm_engine *engine = nv_engine(engobj); in nvkm_engctx_create_() local
61 spin_lock_irqsave(&engine->lock, save); in nvkm_engctx_create_()
62 ret = nvkm_engctx_exists(parent, engine, pobject); in nvkm_engctx_create_()
63 spin_unlock_irqrestore(&engine->lock, save); in nvkm_engctx_create_()
87 spin_lock_irqsave(&engine->lock, save); in nvkm_engctx_create_()
88 ret = nvkm_engctx_exists(parent, engine, pobject); in nvkm_engctx_create_()
90 spin_unlock_irqrestore(&engine->lock, save); in nvkm_engctx_create_()
96 atomic_inc(&client->vm->engref[nv_engidx(engine)]); in nvkm_engctx_create_()
[all …]
Dparent.c34 struct nvkm_engine *engine; in nvkm_parent_sclass() local
41 *pengine = &parent->engine->subdev.object; in nvkm_parent_sclass()
49 mask = nv_parent(parent)->engine; in nvkm_parent_sclass()
54 engine = nv_engine(nv_client(parent)->device); in nvkm_parent_sclass()
56 engine = nvkm_engine(parent, i); in nvkm_parent_sclass()
58 if (engine) { in nvkm_parent_sclass()
59 oclass = engine->sclass; in nvkm_parent_sclass()
62 *pengine = nv_object(engine); in nvkm_parent_sclass()
80 struct nvkm_engine *engine; in nvkm_parent_lclass() local
92 mask = nv_parent(parent)->engine; in nvkm_parent_lclass()
[all …]
Dobject.c33 nvkm_object_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_object_create_() argument
44 nvkm_object_ref(engine, (struct nvkm_object **)&object->engine); in nvkm_object_create_()
60 _nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_object_ctor() argument
66 return nvkm_object_create(parent, engine, oclass, 0, pobject); in _nvkm_object_ctor()
77 nvkm_object_ref(NULL, (struct nvkm_object **)&object->engine); in nvkm_object_destroy()
103 nvkm_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_object_ctor() argument
111 ret = ofuncs->ctor(parent, engine, oclass, data, size, &object); in nvkm_object_ctor()
179 if (object->engine) { in nvkm_object_inc()
180 mutex_lock(&nv_subdev(object->engine)->mutex); in nvkm_object_inc()
181 ret = nvkm_object_inc(&object->engine->subdev.object); in nvkm_object_inc()
[all …]
Dengine.c43 struct nvkm_engine *engine; in nvkm_engine_create_() local
48 engine = *pobject; in nvkm_engine_create_()
54 int engidx = nv_engidx(engine); in nvkm_engine_create_()
58 nv_debug(engine, "engine disabled by hw/fw\n"); in nvkm_engine_create_()
62 nv_warn(engine, "ignoring hw/fw engine disable\n"); in nvkm_engine_create_()
67 nv_warn(engine, "disabled, %s=1 to enable\n", iname); in nvkm_engine_create_()
72 INIT_LIST_HEAD(&engine->contexts); in nvkm_engine_create_()
73 spin_lock_init(&engine->lock); in nvkm_engine_create_()
Dgpuobj.c51 nvkm_gpuobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_gpuobj_create_() argument
100 ret = nvkm_object_create_(parent, engine, oclass, pclass | in nvkm_gpuobj_create_()
143 _nvkm_gpuobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_gpuobj_ctor() argument
151 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, args->pargpu, in _nvkm_gpuobj_ctor()
217 struct nvkm_object *engine = parent; in nvkm_gpuobj_new() local
225 if (!nv_iclass(engine, NV_SUBDEV_CLASS)) in nvkm_gpuobj_new()
226 engine = &engine->engine->subdev.object; in nvkm_gpuobj_new()
227 BUG_ON(engine == NULL); in nvkm_gpuobj_new()
229 return nvkm_object_ctor(parent, engine, &_nvkm_gpuobj_oclass, in nvkm_gpuobj_new()
306 ret = nvkm_object_create(parent, &parent->engine->subdev.object, in nvkm_gpuobj_dup()
Dioctl.c93 struct nvkm_object *engine; in nvkm_ioctl_new() local
119 ret = nvkm_parent_sclass(&parent->object, _oclass, &engine, &oclass); in nvkm_ioctl_new()
129 if (engine) { in nvkm_ioctl_new()
130 ret = nvkm_object_inc(engine); in nvkm_ioctl_new()
138 if (engine && nv_engine(engine)->cclass) { in nvkm_ioctl_new()
139 ret = nvkm_object_ctor(&parent->object, engine, in nvkm_ioctl_new()
140 nv_engine(engine)->cclass, in nvkm_ioctl_new()
149 ret = nvkm_object_ctor(engctx, engine, oclass, data, size, &object); in nvkm_ioctl_new()
176 if (engine) in nvkm_ioctl_new()
177 nvkm_object_dec(engine, false); in nvkm_ioctl_new()
Dnamedb.c165 nvkm_namedb_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_namedb_create_() argument
173 ret = nvkm_parent_create_(parent, engine, oclass, pclass | in nvkm_namedb_create_()
186 _nvkm_namedb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_namedb_ctor() argument
193 ret = nvkm_namedb_create(parent, engine, oclass, 0, NULL, 0, &object); in _nvkm_namedb_ctor()
Dprintk.c65 if (object->engine == NULL) { in nv_printk_()
70 subdev = &object->engine->subdev.object; in nv_printk_()
Dramht.c96 ret = nvkm_gpuobj_create(parent, parent->engine ? in nvkm_ramht_new()
97 &parent->engine->subdev.object : parent, /* <nv50 ramht */ in nvkm_ramht_new()
Dsubdev.c96 nvkm_subdev_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_subdev_create_() argument
104 ret = nvkm_object_create_(parent, engine, oclass, pclass | in nvkm_subdev_create_()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
DKbuild1 nvkm-y += nvkm/engine/device/acpi.o
2 nvkm-y += nvkm/engine/device/base.o
3 nvkm-y += nvkm/engine/device/ctrl.o
4 nvkm-y += nvkm/engine/device/nv04.o
5 nvkm-y += nvkm/engine/device/nv10.o
6 nvkm-y += nvkm/engine/device/nv20.o
7 nvkm-y += nvkm/engine/device/nv30.o
8 nvkm-y += nvkm/engine/device/nv40.o
9 nvkm-y += nvkm/engine/device/nv50.o
10 nvkm-y += nvkm/engine/device/gf100.o
[all …]
Dbase.c167 return nv_rd08(object->engine, addr); in nvkm_devobj_rd08()
173 return nv_rd16(object->engine, addr); in nvkm_devobj_rd16()
179 return nv_rd32(object->engine, addr); in nvkm_devobj_rd32()
185 nv_wr08(object->engine, addr, data); in nvkm_devobj_wr08()
191 nv_wr16(object->engine, addr, data); in nvkm_devobj_wr16()
197 nv_wr32(object->engine, addr, data); in nvkm_devobj_wr32()
282 nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, argument
518 if (device->engine == NULL) {
522 device = &nv_object(obj)->engine->subdev.object;
641 nvkm_engine_destroy(&device->engine);
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
DKbuild1 nvkm-y += nvkm/engine/fifo/base.o
2 nvkm-y += nvkm/engine/fifo/nv04.o
3 nvkm-y += nvkm/engine/fifo/nv10.o
4 nvkm-y += nvkm/engine/fifo/nv17.o
5 nvkm-y += nvkm/engine/fifo/nv40.o
6 nvkm-y += nvkm/engine/fifo/nv50.o
7 nvkm-y += nvkm/engine/fifo/g84.o
8 nvkm-y += nvkm/engine/fifo/gf100.o
9 nvkm-y += nvkm/engine/fifo/gk104.o
10 nvkm-y += nvkm/engine/fifo/gk20a.o
[all …]
Dgk104.c67 struct gk104_fifo_engn engine[FIFO_ENGINE_NR]; member
83 u32 engine; member
96 gk104_fifo_runlist_update(struct gk104_fifo_priv *priv, u32 engine) in gk104_fifo_runlist_update() argument
99 struct gk104_fifo_engn *engn = &priv->engine[engine]; in gk104_fifo_runlist_update()
109 if (chan && chan->state == RUNNING && chan->engine == engine) { in gk104_fifo_runlist_update()
118 nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); in gk104_fifo_runlist_update()
121 (engine * 0x08)) & 0x00100000), in gk104_fifo_runlist_update()
123 nv_error(priv, "runlist %d update timeout\n", engine); in gk104_fifo_runlist_update()
137 switch (nv_engidx(object->engine)) { in gk104_fifo_context_attach()
173 struct gk104_fifo_priv *priv = (void *)parent->engine; in gk104_fifo_context_detach()
[all …]
Dgf100.c117 switch (nv_engidx(object->engine)) { in gf100_fifo_context_attach()
149 struct gf100_fifo_priv *priv = (void *)parent->engine; in gf100_fifo_context_detach()
154 switch (nv_engidx(object->engine)) { in gf100_fifo_context_detach()
181 gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_fifo_chan_ctor() argument
189 struct gf100_fifo_priv *priv = (void *)engine; in gf100_fifo_chan_ctor()
204 ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, in gf100_fifo_chan_ctor()
254 struct gf100_fifo_priv *priv = (void *)object->engine; in gf100_fifo_chan_init()
278 struct gf100_fifo_priv *priv = (void *)object->engine; in gf100_fifo_chan_fini()
316 gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_fifo_context_ctor() argument
323 ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, in gf100_fifo_context_ctor()
[all …]
Dnv40.c71 struct nv04_fifo_priv *priv = (void *)parent->engine; in nv40_fifo_object_attach()
81 switch (nv_engidx(object->engine)) { in nv40_fifo_object_attach()
107 struct nv04_fifo_priv *priv = (void *)parent->engine; in nv40_fifo_context_attach()
112 switch (nv_engidx(engctx->engine)) { in nv40_fifo_context_attach()
144 struct nv04_fifo_priv *priv = (void *)parent->engine; in nv40_fifo_context_detach()
149 switch (nv_engidx(engctx->engine)) { in nv40_fifo_context_detach()
177 nv40_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_fifo_chan_ctor() argument
184 struct nv04_fifo_priv *priv = (void *)engine; in nv40_fifo_chan_ctor()
196 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, in nv40_fifo_chan_ctor()
268 nv40_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_fifo_ctor() argument
[all …]
Dnv04.c58 struct nv04_fifo_priv *priv = (void *)parent->engine; in nv04_fifo_object_attach()
68 switch (nv_engidx(object->engine)) { in nv04_fifo_object_attach()
95 struct nv04_fifo_priv *priv = (void *)parent->engine; in nv04_fifo_object_detach()
111 struct nvkm_object *engine, in nv04_fifo_chan_ctor() argument
118 struct nv04_fifo_priv *priv = (void *)engine; in nv04_fifo_chan_ctor()
130 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, in nv04_fifo_chan_ctor()
162 struct nv04_fifo_priv *priv = (void *)object->engine; in nv04_fifo_chan_dtor()
176 struct nv04_fifo_priv *priv = (void *)object->engine; in nv04_fifo_chan_init()
195 struct nv04_fifo_priv *priv = (void *)object->engine; in nv04_fifo_chan_fini()
267 struct nvkm_object *engine, in nv04_fifo_context_ctor() argument
[all …]
Dbase.c56 struct nvkm_object *engine, in nvkm_fifo_channel_create_() argument
61 struct nvkm_device *device = nv_device(engine); in nvkm_fifo_channel_create_()
62 struct nvkm_fifo *priv = (void *)engine; in nvkm_fifo_channel_create_()
69 ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL, in nvkm_fifo_channel_create_()
80 dmaeng = (void *)chan->pushdma->base.engine; in nvkm_fifo_channel_create_()
118 struct nvkm_fifo *priv = (void *)nv_object(chan)->engine; in nvkm_fifo_channel_destroy()
203 struct nvkm_fifo *fifo = (void *)object->engine; in _nvkm_fifo_channel_ntfy()
256 nvkm_fifo_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_fifo_create_() argument
263 ret = nvkm_engine_create_(parent, engine, oclass, true, "PFIFO", in nvkm_fifo_create_()
Dnv50.c81 switch (nv_engidx(object->engine)) { in nv50_fifo_context_attach()
106 struct nv50_fifo_priv *priv = (void *)parent->engine; in nv50_fifo_context_detach()
112 switch (nv_engidx(object->engine)) { in nv50_fifo_context_detach()
169 switch (nv_engidx(object->engine)) { in nv50_fifo_object_attach()
189 nv50_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_fifo_chan_ctor_dma() argument
209 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, in nv50_fifo_chan_ctor_dma()
250 nv50_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_fifo_chan_ctor_ind() argument
272 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, in nv50_fifo_chan_ctor_ind()
323 struct nv50_fifo_priv *priv = (void *)object->engine; in nv50_fifo_chan_init()
342 struct nv50_fifo_priv *priv = (void *)object->engine; in nv50_fifo_chan_fini()
[all …]
Dg84.c51 switch (nv_engidx(object->engine)) { in g84_fifo_context_attach()
84 struct nv50_fifo_priv *priv = (void *)parent->engine; in g84_fifo_context_detach()
90 switch (nv_engidx(object->engine)) { in g84_fifo_context_detach()
139 switch (nv_engidx(object->engine)) { in g84_fifo_object_attach()
162 g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, in g84_fifo_chan_ctor_dma() argument
182 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, in g84_fifo_chan_ctor_dma()
235 g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine, in g84_fifo_chan_ctor_ind() argument
257 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, in g84_fifo_chan_ctor_ind()
312 struct nv50_fifo_priv *priv = (void *)object->engine; in g84_fifo_chan_init()
364 g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g84_fifo_context_ctor() argument
[all …]
Dnv10.c54 struct nvkm_object *engine, in nv10_fifo_chan_ctor() argument
61 struct nv04_fifo_priv *priv = (void *)engine; in nv10_fifo_chan_ctor()
73 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, in nv10_fifo_chan_ctor()
142 nv10_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv10_fifo_ctor() argument
150 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); in nv10_fifo_ctor()
Dnv17.c59 struct nvkm_object *engine, in nv17_fifo_chan_ctor() argument
66 struct nv04_fifo_priv *priv = (void *)engine; in nv17_fifo_chan_ctor()
78 ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0x800000, in nv17_fifo_chan_ctor()
149 nv17_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv17_fifo_ctor() argument
157 ret = nvkm_fifo_create(parent, engine, oclass, 0, 31, &priv); in nv17_fifo_ctor()
Dgm204.c35 gm204_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm204_fifo_ctor() argument
39 int ret = gk104_fifo_ctor(parent, engine, oclass, data, size, pobject); in gm204_fifo_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/pm/
DKbuild1 nvkm-y += nvkm/engine/pm/base.o
2 nvkm-y += nvkm/engine/pm/daemon.o
3 nvkm-y += nvkm/engine/pm/nv40.o
4 nvkm-y += nvkm/engine/pm/nv50.o
5 nvkm-y += nvkm/engine/pm/g84.o
6 nvkm-y += nvkm/engine/pm/gt215.o
7 nvkm-y += nvkm/engine/pm/gf100.o
8 nvkm-y += nvkm/engine/pm/gk104.o
9 nvkm-y += nvkm/engine/pm/gk110.o
Dbase.c112 struct nvkm_pm *ppm = (void *)object->engine; in nvkm_perfctr_query()
170 struct nvkm_pm *ppm = (void *)object->engine; in nvkm_perfctr_sample()
266 nvkm_perfctr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_perfctr_ctor() argument
273 struct nvkm_pm *ppm = (void *)engine; in nvkm_perfctr_ctor()
295 ret = nvkm_object_create(parent, engine, oclass, 0, &ctr); in nvkm_perfctr_ctor()
334 struct nvkm_pm *ppm = (void *)object->engine; in nvkm_perfctx_dtor()
342 nvkm_perfctx_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_perfctx_ctor() argument
346 struct nvkm_pm *ppm = (void *)engine; in nvkm_perfctx_ctor()
350 ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0, 0, 0, &ctx); in nvkm_perfctx_ctor()
462 nvkm_pm_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_pm_create_() argument
[all …]
Dgk110.c27 gk110_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk110_pm_ctor() argument
34 ret = nvkm_pm_create(parent, engine, oclass, &priv); in gk110_pm_ctor()
Dgt215.c56 gt215_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gt215_pm_ctor() argument
60 int ret = nv40_pm_ctor(parent, engine, oclass, data, size, object); in gt215_pm_ctor()
Dgk104.c89 gk104_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_pm_ctor() argument
97 ret = nvkm_pm_create(parent, engine, oclass, &priv); in gk104_pm_ctor()
Dnv40.c98 nv40_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_pm_ctor() argument
106 ret = nvkm_pm_create(parent, engine, oclass, &priv); in nv40_pm_ctor()
Dgf100.c101 gf100_pm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_pm_ctor() argument
109 ret = nvkm_pm_create(parent, engine, oclass, &priv); in gf100_pm_ctor()
/linux-4.1.27/drivers/gpu/drm/via/
Dvia_dmablit.c209 via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine) in via_fire_dmablit() argument
213 VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0); in via_fire_dmablit()
214 VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0); in via_fire_dmablit()
215 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | in via_fire_dmablit()
217 VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE); in via_fire_dmablit()
218 VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0); in via_fire_dmablit()
219 VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start); in via_fire_dmablit()
221 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); in via_fire_dmablit()
222 VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04); in via_fire_dmablit()
290 via_abort_dmablit(struct drm_device *dev, int engine) in via_abort_dmablit() argument
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv31.c39 struct nvkm_object *engine, in nv31_mpeg_object_ctor() argument
46 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, in nv31_mpeg_object_ctor()
63 struct nv31_mpeg_priv *priv = (void *)object->engine; in nv31_mpeg_mthd_dma()
128 struct nvkm_object *engine, in nv31_mpeg_context_ctor() argument
132 struct nv31_mpeg_priv *priv = (void *)engine; in nv31_mpeg_context_ctor()
137 ret = nvkm_object_create(parent, engine, oclass, 0, &chan); in nv31_mpeg_context_ctor()
157 struct nv31_mpeg_priv *priv = (void *)object->engine; in nv31_mpeg_context_dtor()
183 nv31_mpeg_tile_prog(struct nvkm_engine *engine, int i) in nv31_mpeg_tile_prog() argument
185 struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i]; in nv31_mpeg_tile_prog()
186 struct nv31_mpeg_priv *priv = (void *)engine; in nv31_mpeg_tile_prog()
[all …]
DKbuild1 nvkm-y += nvkm/engine/mpeg/nv31.o
2 nvkm-y += nvkm/engine/mpeg/nv40.o
3 nvkm-y += nvkm/engine/mpeg/nv44.o
4 nvkm-y += nvkm/engine/mpeg/nv50.o
5 nvkm-y += nvkm/engine/mpeg/g84.o
Dnv44.c44 struct nvkm_object *engine, in nv44_mpeg_context_ctor() argument
51 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 264 * 4, in nv44_mpeg_context_ctor()
65 struct nv44_mpeg_priv *priv = (void *)object->engine; in nv44_mpeg_context_fini()
97 struct nvkm_engine *engine = nv_engine(subdev); in nv44_mpeg_intr() local
109 engctx = nvkm_engctx_get(engine, inst); in nv44_mpeg_intr()
156 nv44_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv44_mpeg_ctor() argument
163 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); in nv44_mpeg_ctor()
Dnv50.c43 struct nvkm_object *engine, in nv50_mpeg_object_ctor() argument
50 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, in nv50_mpeg_object_ctor()
85 struct nvkm_object *engine, in nv50_mpeg_context_ctor() argument
93 ret = nvkm_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, in nv50_mpeg_context_ctor()
165 nv50_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_mpeg_ctor() argument
172 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); in nv50_mpeg_ctor()
Dnv40.c36 struct nv31_mpeg_priv *priv = (void *)object->engine; in nv40_mpeg_mthd_dma()
105 nv40_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_mpeg_ctor() argument
112 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); in nv40_mpeg_ctor()
Dg84.c66 g84_mpeg_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g84_mpeg_ctor() argument
73 ret = nvkm_mpeg_create(parent, engine, oclass, &priv); in g84_mpeg_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/
DKbuild1 nvkm-y += nvkm/engine/dmaobj/base.o
2 nvkm-y += nvkm/engine/dmaobj/nv04.o
3 nvkm-y += nvkm/engine/dmaobj/nv50.o
4 nvkm-y += nvkm/engine/dmaobj/gf100.o
5 nvkm-y += nvkm/engine/dmaobj/gf110.o
Dbase.c39 nv_oclass(nv_object(dmaobj)->engine); in nvkm_dmaobj_bind()
58 struct nvkm_object *engine, in nvkm_dmaobj_create_() argument
74 ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject); in nvkm_dmaobj_create_()
147 _nvkm_dmaeng_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_dmaeng_ctor() argument
155 ret = nvkm_engine_create(parent, engine, oclass, true, "DMAOBJ", in _nvkm_dmaeng_ctor()
Dnv04.c84 nv04_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_dmaobj_ctor() argument
88 struct nvkm_dmaeng *dmaeng = (void *)engine; in nv04_dmaobj_ctor()
89 struct nv04_mmu_priv *mmu = nv04_mmu(engine); in nv04_dmaobj_ctor()
93 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); in nv04_dmaobj_ctor()
Dgf110.c78 gf110_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf110_dmaobj_ctor() argument
82 struct nvkm_dmaeng *dmaeng = (void *)engine; in gf110_dmaobj_ctor()
90 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); in gf110_dmaobj_ctor()
Dgf100.c73 gf100_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_dmaobj_ctor() argument
77 struct nvkm_dmaeng *dmaeng = (void *)engine; in gf100_dmaobj_ctor()
85 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); in gf100_dmaobj_ctor()
Dnv50.c85 nv50_dmaobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_dmaobj_ctor() argument
89 struct nvkm_dmaeng *dmaeng = (void *)engine; in nv50_dmaobj_ctor()
97 ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); in nv50_dmaobj_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dnv50.c149 struct nvkm_engine *engine; in nv50_fb_intr() local
188 engine = nvkm_engine(subdev, en->data2); in nv50_fb_intr()
190 if (!engine && en->data2 == NVDEV_ENGINE_BSP) in nv50_fb_intr()
191 engine = nvkm_engine(subdev, NVDEV_ENGINE_MSVLD); in nv50_fb_intr()
192 if (!engine && en->data2 == NVDEV_ENGINE_CIPHER) in nv50_fb_intr()
193 engine = nvkm_engine(subdev, NVDEV_ENGINE_SEC); in nv50_fb_intr()
194 if (!engine && en->data2 == NVDEV_ENGINE_VP) in nv50_fb_intr()
195 engine = nvkm_engine(subdev, NVDEV_ENGINE_MSPDEC); in nv50_fb_intr()
196 if (engine) { in nv50_fb_intr()
197 engctx = nvkm_engctx_get(engine, chan); in nv50_fb_intr()
[all …]
Dramgm107.c31 gm107_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm107_ram_ctor() argument
38 ret = gf100_ram_create(parent, engine, oclass, 0x021c14, &ram); in gm107_ram_ctor()
Dramnv4e.c27 nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv4e_ram_create() argument
35 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv4e_ram_create()
Dramnv10.c27 nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv10_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv10_ram_create()
Dgk20a.c43 gk20a_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_fb_ctor() argument
50 ret = nvkm_fb_create(parent, engine, oclass, &priv); in gk20a_fb_ctor()
Dramnv04.c28 nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_ram_create() argument
37 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv04_ram_create()
Dramnv1a.c29 nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv1a_ram_create() argument
45 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv1a_ram_create()
Dramnv20.c27 nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv20_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv20_ram_create()
Dramnv44.c27 nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv44_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv44_ram_create()
Dramnv49.c27 nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv49_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv49_ram_create()
Dramnv41.c27 nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv41_ram_create() argument
36 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv41_ram_create()
Dnv04.c55 nv04_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_fb_ctor() argument
63 ret = nvkm_fb_create(parent, engine, oclass, &priv); in nv04_fb_ctor()
Drammcp77.c32 mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in mcp77_ram_ctor() argument
42 ret = nvkm_ram_create(parent, engine, oclass, &priv); in mcp77_ram_ctor()
Dgf100.c85 gf100_fb_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_fb_ctor() argument
93 ret = nvkm_fb_create(parent, engine, oclass, &priv); in gf100_fb_ctor()
Dbase.c108 nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_fb_create_() argument
129 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", in nvkm_fb_create_()
Dramnv40.c172 nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_ram_create() argument
181 ret = nvkm_ram_create(parent, engine, oclass, &ram); in nv40_ram_create()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
DKbuild1 nvkm-y += nvkm/engine/ce/gt215.o
2 nvkm-y += nvkm/engine/ce/gf100.o
3 nvkm-y += nvkm/engine/ce/gk104.o
4 nvkm-y += nvkm/engine/ce/gm204.o
Dgk104.c80 gk104_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_ce0_ctor() argument
87 ret = nvkm_engine_create(parent, engine, oclass, true, in gk104_ce0_ctor()
101 gk104_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_ce1_ctor() argument
108 ret = nvkm_engine_create(parent, engine, oclass, true, in gk104_ce1_ctor()
122 gk104_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_ce2_ctor() argument
129 ret = nvkm_engine_create(parent, engine, oclass, true, in gk104_ce2_ctor()
Dgm204.c80 gm204_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm204_ce0_ctor() argument
87 ret = nvkm_engine_create(parent, engine, oclass, true, in gm204_ce0_ctor()
101 gm204_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm204_ce1_ctor() argument
108 ret = nvkm_engine_create(parent, engine, oclass, true, in gm204_ce1_ctor()
122 gm204_ce2_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm204_ce2_ctor() argument
129 ret = nvkm_engine_create(parent, engine, oclass, true, in gm204_ce2_ctor()
Dgt215.c81 struct nvkm_engine *engine = nv_engine(subdev); in gt215_ce_intr() local
94 engctx = nvkm_engctx_get(engine, inst); in gt215_ce_intr()
116 gt215_ce_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gt215_ce_ctor() argument
124 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, enable, in gt215_ce_ctor()
Dgf100.c93 gf100_ce0_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_ce0_ctor() argument
100 ret = nvkm_falcon_create(parent, engine, oclass, 0x104000, true, in gf100_ce0_ctor()
118 gf100_ce1_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_ce1_ctor() argument
125 ret = nvkm_falcon_create(parent, engine, oclass, 0x105000, true, in gf100_ce1_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sw/
DKbuild1 nvkm-y += nvkm/engine/sw/nv04.o
2 nvkm-y += nvkm/engine/sw/nv10.o
3 nvkm-y += nvkm/engine/sw/nv50.o
4 nvkm-y += nvkm/engine/sw/gf100.o
Dnv10.c64 nv10_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv10_sw_context_ctor() argument
71 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); in nv10_sw_context_ctor()
95 nv10_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv10_sw_ctor() argument
102 ret = nvkm_sw_create(parent, engine, oclass, &priv); in nv10_sw_ctor()
Dnv04.c75 nv04_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_sw_context_ctor() argument
82 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); in nv04_sw_context_ctor()
112 nv04_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_sw_ctor() argument
119 ret = nvkm_sw_create(parent, engine, oclass, &priv); in nv04_sw_ctor()
Dnv50.c125 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; in nv50_sw_vblsem_release()
156 nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_sw_context_ctor() argument
165 ret = nvkm_sw_context_create(parent, engine, oclass, &chan); in nv50_sw_context_ctor()
204 nv50_sw_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_sw_ctor() argument
212 ret = nvkm_sw_create(parent, engine, oclass, &priv); in nv50_sw_ctor()
Dgf100.c53 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; in gf100_sw_mthd_mp_control()
102 struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine; in gf100_sw_vblsem_release()
/linux-4.1.27/drivers/dma/
DKconfig2 # DMA engine configuration
21 say N here. This enables DMA engine core and driver debugging.
29 the DMA engine core and drivers.
64 which can provide DMA engine support
73 Enable support for the Intel(R) I/OAT DMA engine present
116 tristate "Freescale RAID engine Support"
129 tristate "Freescale MPC512x built-in DMA engine support"
133 Enable support for the Freescale MPC512x built-in DMA engine.
138 bool "Marvell XOR engine support"
144 Enable support for the Marvell XOR engine.
[all …]
/linux-4.1.27/drivers/gpu/drm/omapdrm/
Domap_dmm_tiler.c85 struct refill_engine *engine = txn->engine_handle; in alloc_dma() local
97 BUG_ON((txn->current_va - engine->refill_va) > REFILL_BUFFER_SIZE); in alloc_dma()
103 static int wait_status(struct refill_engine *engine, uint32_t wait_mask) in wait_status() argument
105 struct dmm *dmm = engine->dmm; in wait_status()
110 r = readl(dmm->base + reg[PAT_STATUS][engine->id]); in wait_status()
127 static void release_engine(struct refill_engine *engine) in release_engine() argument
132 list_add(&engine->idle_node, &omap_dmm->idle_head); in release_engine()
168 struct refill_engine *engine = NULL; in dmm_txn_init() local
182 engine = list_entry(dmm->idle_head.next, struct refill_engine, in dmm_txn_init()
184 list_del(&engine->idle_node); in dmm_txn_init()
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c41 struct nvkm_object *engine, in g84_cipher_object_ctor() argument
48 ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent, in g84_cipher_object_ctor()
112 struct nvkm_engine *engine = nv_engine(subdev); in g84_cipher_intr() local
121 engctx = nvkm_engctx_get(engine, inst); in g84_cipher_intr()
139 g84_cipher_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g84_cipher_ctor() argument
146 ret = nvkm_engine_create(parent, engine, oclass, true, in g84_cipher_ctor()
DKbuild1 nvkm-y += nvkm/engine/cipher/g84.o
/linux-4.1.27/drivers/dma/sh/
Dusb-dmac.c101 struct dma_device engine; member
109 #define to_usb_dmac(d) container_of(d, struct usb_dmac, engine)
739 vchan_init(&uchan->vc, &dmac->engine); in usb_dmac_chan_probe()
769 struct dma_device *engine; in usb_dmac_probe() local
814 INIT_LIST_HEAD(&dmac->engine.channels); in usb_dmac_probe()
833 engine = &dmac->engine; in usb_dmac_probe()
834 dma_cap_set(DMA_SLAVE, engine->cap_mask); in usb_dmac_probe()
836 engine->dev = &pdev->dev; in usb_dmac_probe()
838 engine->src_addr_widths = widths; in usb_dmac_probe()
839 engine->dst_addr_widths = widths; in usb_dmac_probe()
[all …]
Drcar-dmac.c179 struct dma_device engine; member
189 #define to_rcar_dmac(d) container_of(d, struct rcar_dmac, engine)
1562 chan->device = &dmac->engine; in rcar_dmac_chan_probe()
1565 list_add_tail(&chan->device_node, &dmac->engine.channels); in rcar_dmac_chan_probe()
1597 struct dma_device *engine; in rcar_dmac_probe() local
1676 INIT_LIST_HEAD(&dmac->engine.channels); in rcar_dmac_probe()
1696 engine = &dmac->engine; in rcar_dmac_probe()
1697 dma_cap_set(DMA_MEMCPY, engine->cap_mask); in rcar_dmac_probe()
1698 dma_cap_set(DMA_SLAVE, engine->cap_mask); in rcar_dmac_probe()
1700 engine->dev = &pdev->dev; in rcar_dmac_probe()
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv50.c154 struct nvkm_engine *engine; in nv50_vm_flush() local
165 engine = nvkm_engine(priv, i); in nv50_vm_flush()
166 if (engine && engine->tlb_flush) { in nv50_vm_flush()
167 engine->tlb_flush(engine); in nv50_vm_flush()
206 nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_mmu_ctor() argument
213 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); in nv50_mmu_ctor()
Dnv41.c85 nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv41_mmu_ctor() argument
95 return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, in nv41_mmu_ctor()
99 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", in nv41_mmu_ctor()
Dnv04.c84 nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_mmu_ctor() argument
92 ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART", in nv04_mmu_ctor()
Dnv44.c156 nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv44_mmu_ctor() argument
166 return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, in nv44_mmu_ctor()
170 ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", in nv44_mmu_ctor()
Dgf100.c202 gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_mmu_ctor() argument
209 ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); in gf100_mmu_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
DKbuild1 nvkm-y += nvkm/engine/msvld/g98.o
2 nvkm-y += nvkm/engine/msvld/gf100.o
3 nvkm-y += nvkm/engine/msvld/gk104.o
Dg98.c80 g98_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g98_msvld_ctor() argument
87 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, in g98_msvld_ctor()
Dgk104.c78 gk104_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_msvld_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, in gk104_msvld_ctor()
Dgf100.c78 gf100_msvld_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_msvld_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x084000, true, in gf100_msvld_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
DKbuild1 nvkm-y += nvkm/engine/mspdec/g98.o
2 nvkm-y += nvkm/engine/mspdec/gf100.o
3 nvkm-y += nvkm/engine/mspdec/gk104.o
Dgk104.c78 gk104_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_mspdec_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, in gk104_mspdec_ctor()
Dg98.c79 g98_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g98_mspdec_ctor() argument
86 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, in g98_mspdec_ctor()
Dgf100.c78 gf100_mspdec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_mspdec_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x085000, true, in gf100_mspdec_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dpad.c46 struct nvkm_object *engine, in nvkm_i2c_pad_create_() argument
64 ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject); in nvkm_i2c_pad_create_()
74 _nvkm_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_i2c_pad_ctor() argument
80 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); in _nvkm_i2c_pad_ctor()
Dpadgm204.c61 gm204_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm204_i2c_pad_ctor() argument
68 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); in gm204_i2c_pad_ctor()
Dpadg94.c61 g94_i2c_pad_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g94_i2c_pad_ctor() argument
68 ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); in g94_i2c_pad_ctor()
Dg94.c196 g94_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g94_i2c_port_ctor() argument
204 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in g94_i2c_port_ctor()
224 g94_aux_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g94_aux_port_ctor() argument
232 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in g94_aux_port_ctor()
Dgf110.c51 gf110_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf110_i2c_port_ctor() argument
59 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in gf110_i2c_port_ctor()
Dnv4e.c78 nv4e_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv4e_i2c_port_ctor() argument
86 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in nv4e_i2c_port_ctor()
Danx9805.c126 struct nvkm_object *engine, in anx9805_aux_chan_ctor() argument
134 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in anx9805_aux_chan_ctor()
242 struct nvkm_object *engine, in anx9805_ddc_port_ctor() argument
250 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in anx9805_ddc_port_ctor()
Dnv04.c85 nv04_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_i2c_port_ctor() argument
93 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in nv04_i2c_port_ctor()
Dnv50.c78 nv50_i2c_port_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_i2c_port_ctor() argument
86 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in nv50_i2c_port_ctor()
Dbase.c109 nvkm_i2c_port_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_i2c_port_create_() argument
120 ret = nvkm_object_create_(parent, engine, oclass, 0, size, pobject); in nvkm_i2c_port_create_()
510 nvkm_i2c_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_i2c_create_() argument
522 ret = nvkm_subdev_create(parent, engine, oclass, 0, "I2C", "i2c", &i2c); in nvkm_i2c_create_()
609 _nvkm_i2c_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_i2c_ctor() argument
616 ret = nvkm_i2c_create(parent, engine, oclass, &i2c); in _nvkm_i2c_ctor()
Dgm204.c164 struct nvkm_object *engine, in gm204_aux_port_ctor() argument
172 ret = nvkm_i2c_port_create(parent, engine, oclass, index, in gm204_aux_port_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dbase.c37 nvkm_barobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_barobj_ctor() argument
47 ret = nvkm_object_create(parent, engine, oclass, 0, &barobj); in nvkm_barobj_ctor()
110 int ret = nvkm_object_ctor(parent, &parent->engine->subdev.object, in nvkm_bar_alloc()
118 nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_bar_create_() argument
124 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL", in nvkm_bar_create_()
Dgk20a.c25 gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_bar_ctor() argument
32 ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject); in gk20a_bar_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dbase.c46 nvkm_instobj_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_instobj_create_() argument
53 ret = nvkm_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS, in nvkm_instobj_create_()
75 return nvkm_object_ctor(parent, &parent->engine->subdev.object, in nvkm_instmem_alloc()
131 nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_instmem_create_() argument
137 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "INSTMEM", in nvkm_instmem_create_()
Dgk20a.c203 gk20a_instobj_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_instobj_ctor_dma() argument
212 ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node), in gk20a_instobj_ctor_dma()
245 gk20a_instobj_ctor_iommu(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_instobj_ctor_iommu() argument
255 ret = nvkm_instobj_create_(parent, engine, oclass, in gk20a_instobj_ctor_iommu()
324 gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_instobj_ctor() argument
342 ret = gk20a_instobj_ctor_iommu(parent, engine, oclass, in gk20a_instobj_ctor()
345 ret = gk20a_instobj_ctor_dma(parent, engine, oclass, in gk20a_instobj_ctor()
390 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_instmem_ctor() argument
398 ret = nvkm_instmem_create(parent, engine, oclass, &priv); in gk20a_instmem_ctor()
Dnv50.c91 nv50_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_instobj_ctor() argument
103 ret = nvkm_instobj_create(parent, engine, oclass, &node); in nv50_instobj_ctor()
143 nv50_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_instmem_ctor() argument
150 ret = nvkm_instmem_create(parent, engine, oclass, &priv); in nv50_instmem_ctor()
Dnv04.c63 nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_instobj_ctor() argument
76 ret = nvkm_instobj_create(parent, engine, oclass, &node); in nv04_instobj_ctor()
136 nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_instmem_ctor() argument
143 ret = nvkm_instmem_create(parent, engine, oclass, &priv); in nv04_instmem_ctor()
Dnv40.c48 nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_instmem_ctor() argument
56 ret = nvkm_instmem_create(parent, engine, oclass, &priv); in nv40_instmem_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
Dg98.c79 struct nvkm_engine *engine = nv_engine(subdev); in g98_sec_intr() local
92 engctx = nvkm_engctx_get(engine, inst); in g98_sec_intr()
114 g98_sec_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g98_sec_ctor() argument
121 ret = nvkm_falcon_create(parent, engine, oclass, 0x087000, true, in g98_sec_ctor()
DKbuild1 nvkm-y += nvkm/engine/sec/g98.o
/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_lrc.c343 struct drm_i915_gem_object *ctx_obj0 = to0->engine[ring->id].state; in execlists_submit_contexts()
344 struct intel_ringbuffer *ringbuf0 = to0->engine[ring->id].ringbuf; in execlists_submit_contexts()
355 ringbuf1 = to1->engine[ring->id].ringbuf; in execlists_submit_contexts()
356 ctx_obj1 = to1->engine[ring->id].state; in execlists_submit_contexts()
410 ringbuf = req0->ctx->engine[ring->id].ringbuf; in execlists_context_unqueue()
440 head_req->ctx->engine[ring->id].state; in execlists_check_remove_request()
660 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; in intel_execlists_submission()
761 ctx->engine[ring->id].state; in intel_execlists_retire_requests()
837 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; in intel_lr_context_pin()
838 struct intel_ringbuffer *ringbuf = ctx->engine[ring->id].ringbuf; in intel_lr_context_pin()
[all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
DKbuild1 nvkm-y += nvkm/engine/msppp/g98.o
2 nvkm-y += nvkm/engine/msppp/gf100.o
Dg98.c79 g98_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g98_msppp_ctor() argument
86 ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, in g98_msppp_ctor()
Dgf100.c78 gf100_msppp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_msppp_ctor() argument
85 ret = nvkm_falcon_create(parent, engine, oclass, 0x086000, true, in gf100_msppp_ctor()
/linux-4.1.27/Documentation/netlabel/
Dcipso_ipv4.txt9 The NetLabel CIPSO/IPv4 protocol engine is based on the IETF Commercial IP
17 The CIPSO/IPv4 protocol engine applies the CIPSO IP option to packets by
28 The CIPSO/IPv4 protocol engine validates every CIPSO IP option it finds at the
37 The CIPSO/IPv4 protocol engine contains a mechanism to translate CIPSO security
48 CIPSO/IPv4 protocol engine supports this caching mechanism.
Dintroduction.txt20 engine will handle those tasks as well. Other kernel subsystems should
24 Detailed information about each NetLabel protocol engine can be found in this
D00-INDEX4 - documentation on the IPv4 CIPSO protocol engine.
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
Dbase.c41 nvkm_fuse_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_fuse_create_() argument
47 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "FUSE", in nvkm_fuse_create_()
Dgm107.c39 gm107_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm107_fuse_ctor() argument
46 ret = nvkm_fuse_create(parent, engine, oclass, &priv); in gm107_fuse_ctor()
Dnv50.c50 nv50_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_fuse_ctor() argument
57 ret = nvkm_fuse_create(parent, engine, oclass, &priv); in nv50_fuse_ctor()
Dgf100.c52 gf100_fuse_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_fuse_ctor() argument
59 ret = nvkm_fuse_create(parent, engine, oclass, &priv); in gf100_fuse_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
Dnv40.c31 nv40_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv40_volt_ctor() argument
38 ret = nvkm_volt_create(parent, engine, oclass, &priv); in nv40_volt_ctor()
Dgk20a.c149 gk20a_volt_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_volt_ctor() argument
158 ret = nvkm_volt_create(parent, engine, oclass, &priv); in gk20a_volt_ctor()
/linux-4.1.27/Documentation/leds/
Dleds-lp5562.txt13 All four channels can be also controlled using the engine micro programs.
20 Therefore each channel should be mapped to the engine number.
24 Unlike the LP5521/LP5523/55231, LP5562 has unique feature for the engine mux,
36 the engine selection and loading the firmware.
42 echo "RGB" > /sys/bus/i2c/devices/xxxx/engine_mux # engine mux for RGB
Dleds-lp55xx.txt66 (1) Select an engine number (1/2/3)
72 select_engine : Select which engine is used for running program
77 It is used for selecting LED output(s) at each engine number.
80 For example, run blinking pattern in engine #1 of LP5521
87 For example, run blinking pattern in engine #3 of LP55231
96 To start blinking patterns in engine #2 and #3 simultaneously,
117 Inside the callback, the selected engine is loaded and memory is updated.
148 run_engine : Control the selected engine
Dleds-lp5521.txt17 All three channels can be also controlled using the engine micro programs.
27 enginex_load : store program (visible only in engine load mode)
35 To stop the engine:
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
Dnv04.c53 nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_mc_ctor() argument
60 ret = nvkm_mc_create(parent, engine, oclass, &priv); in nv04_mc_ctor()
Dbase.c112 nvkm_mc_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_mc_create_() argument
120 ret = nvkm_subdev_create_(parent, engine, bclass, 0, "PMC", in nvkm_mc_create_()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/vp/
Dg84.c61 g84_vp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g84_vp_ctor() argument
68 ret = nvkm_xtensa_create(parent, engine, oclass, 0xf000, true, in g84_vp_ctor()
DKbuild1 nvkm-y += nvkm/engine/vp/g84.o
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/bsp/
Dg84.c61 g84_bsp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in g84_bsp_ctor() argument
68 ret = nvkm_xtensa_create(parent, engine, oclass, 0x103000, true, in g84_bsp_ctor()
DKbuild1 nvkm-y += nvkm/engine/bsp/g84.o
/linux-4.1.27/Documentation/devicetree/bindings/crypto/
Dpicochip-spacc.txt7 - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
8 "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dengine.h31 nv_engidx(struct nvkm_engine *engine) in nv_engidx() argument
33 return nv_subidx(&engine->subdev); in nv_engidx()
Dparent.h7 struct nvkm_engine *engine; member
15 u64 engine; member
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgk20a.c77 gk20a_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_ibus_ctor() argument
84 ret = nvkm_ibus_create(parent, engine, oclass, &priv); in gk20a_ibus_ctor()
Dgf100.c97 gf100_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_ibus_ctor() argument
104 ret = nvkm_ibus_create(parent, engine, oclass, &priv); in gf100_ibus_ctor()
Dgk104.c114 gk104_ibus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk104_ibus_ctor() argument
121 ret = nvkm_ibus_create(parent, engine, oclass, &priv); in gk104_ibus_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dbase.c77 nvkm_devinit_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_devinit_create_() argument
85 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "DEVINIT", in nvkm_devinit_create_()
Dgf100.c94 gf100_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf100_devinit_ctor() argument
103 ret = nvkm_devinit_create(parent, engine, oclass, &priv); in gf100_devinit_ctor()
Dnv50.c147 nv50_devinit_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_devinit_ctor() argument
154 ret = nvkm_devinit_create(parent, engine, oclass, &priv); in nv50_devinit_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dbase.c210 nvkm_gpio_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_gpio_create_() argument
217 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "GPIO", in nvkm_gpio_create_()
238 _nvkm_gpio_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_gpio_ctor() argument
245 ret = nvkm_gpio_create(parent, engine, oclass, &gpio); in _nvkm_gpio_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dbase.c242 nvkm_pmu_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_pmu_create_() argument
248 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PMU", in nvkm_pmu_create_()
260 _nvkm_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in _nvkm_pmu_ctor() argument
265 int ret = nvkm_pmu_create(parent, engine, oclass, &pmu); in _nvkm_pmu_ctor()
Dgk20a.c203 gk20a_pmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gk20a_pmu_ctor() argument
210 ret = nvkm_pmu_create(parent, engine, oclass, &priv); in gk20a_pmu_ctor()
/linux-4.1.27/Documentation/crypto/
Dasync-tx-api.txt29 the details of different hardware offload engine implementations. Code
44 operation will be offloaded when an engine is available and carried out
78 resources, under control of the offload engine driver, to be reused as
82 acknowledged by the application before the offload engine driver is allowed to
92 async_<operation> call. Offload engine drivers batch operations to
107 context if the offload engine driver supports interrupts, or it is
178 Primarily this requirement arises from cases where a DMA engine driver
220 drivers/dma/dmaengine.c: offload engine channel management routines
221 drivers/dma/: location for offload engine drivers
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dnv04.c65 nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_bus_ctor() argument
73 ret = nvkm_bus_create(parent, engine, oclass, &priv); in nv04_bus_ctor()
/linux-4.1.27/Documentation/dmaengine/
Dclient.txt73 DMA-engine are:
115 added and the descriptor must then be submitted. Some DMA engine
133 Therefore, it is important that DMA engine drivers drop any
143 added, it must be placed on the DMA engine drivers pending queue.
148 This returns a cookie can be used to check the progress of DMA engine
149 activity via other DMA engine calls not covered in this document.
196 Not all DMA engine drivers can return reliable information for
197 a running DMA channel. It is recommended that DMA engine users
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dgm107.c62 gm107_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm107_therm_ctor() argument
69 ret = nvkm_therm_create(parent, engine, oclass, &priv); in gm107_therm_ctor()
Dgt215.c69 gt215_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gt215_therm_ctor() argument
76 ret = nvkm_therm_create(parent, engine, oclass, &priv); in gt215_therm_ctor()
Dgf110.c141 gf110_therm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gf110_therm_ctor() argument
148 ret = nvkm_therm_create(parent, engine, oclass, &priv); in gf110_therm_ctor()
Dnv50.c156 struct nvkm_object *engine, in nv50_therm_ctor() argument
163 ret = nvkm_therm_create(parent, engine, oclass, &priv); in nv50_therm_ctor()
Dnv40.c185 struct nvkm_object *engine, in nv40_therm_ctor() argument
192 ret = nvkm_therm_create(parent, engine, oclass, &priv); in nv40_therm_ctor()
/linux-4.1.27/Documentation/devicetree/bindings/ata/
Dcavium-compact-flash.txt20 - cavium,dma-engine-handle: Optional, a phandle for the DMA Engine connected
29 cavium,dma-engine-handle = <&dma0>;
/linux-4.1.27/arch/powerpc/platforms/pasemi/
DKconfig24 bool "Force DMA engine to use IOMMU"
28 DMA engine. Otherwise the kernel will use it only when
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv04.c76 nv04_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv04_clk_ctor() argument
83 ret = nvkm_clk_create(parent, engine, oclass, nv04_domain, in nv04_clk_ctor()
/linux-4.1.27/Documentation/devicetree/bindings/dma/
Dmv-xor.txt7 registers for the XOR engine.
11 XOR engine has. Those sub-nodes have the following required
/linux-4.1.27/drivers/leds/
Dleds-lp5523.c422 struct lp55xx_engine *engine = &chip->engines[nr - 1]; in store_engine_mode() local
430 engine->mode = LP55XX_ENGINE_RUN; in store_engine_mode()
434 engine->mode = LP55XX_ENGINE_LOAD; in store_engine_mode()
437 engine->mode = LP55XX_ENGINE_DISABLED; in store_engine_mode()
501 struct lp55xx_engine *engine = &chip->engines[nr - 1]; in lp5523_load_mux() local
523 engine->led_mux = mux; in lp5523_load_mux()
533 struct lp55xx_engine *engine = &chip->engines[nr - 1]; in store_engine_leds() local
545 if (engine->mode != LP55XX_ENGINE_LOAD) in store_engine_leds()
Dleds-lp5521.c405 struct lp55xx_engine *engine = &chip->engines[nr - 1]; in store_engine_mode() local
413 engine->mode = LP55XX_ENGINE_RUN; in store_engine_mode()
417 engine->mode = LP55XX_ENGINE_LOAD; in store_engine_mode()
420 engine->mode = LP55XX_ENGINE_DISABLED; in store_engine_mode()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dbase.c99 nvkm_ltc_create_(struct nvkm_object *parent, struct nvkm_object *engine, in nvkm_ltc_create_() argument
106 ret = nvkm_subdev_create_(parent, engine, oclass, 0, "PLTCG", in nvkm_ltc_create_()
Dgm107.c109 gm107_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in gm107_ltc_ctor() argument
118 ret = nvkm_ltc_create(parent, engine, oclass, &priv); in gm107_ltc_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/
DKbuild3 include $(src)/nvkm/engine/Kbuild
/linux-4.1.27/drivers/net/ethernet/packetengines/
DKconfig2 # Packet engine device configuration
16 the questions about packet engine devices. If you say Y, you will
/linux-4.1.27/drivers/mfd/
Djz4740-adc.c98 static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine, in jz4740_adc_set_enabled() argument
108 val |= BIT(engine); in jz4740_adc_set_enabled()
110 val &= ~BIT(engine); in jz4740_adc_set_enabled()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mxm/
Dnv50.c205 nv50_mxm_ctor(struct nvkm_object *parent, struct nvkm_object *engine, in nv50_mxm_ctor() argument
212 ret = nvkm_mxm_create(parent, engine, oclass, &priv); in nv50_mxm_ctor()
/linux-4.1.27/Documentation/
DIntel-IOMMU.txt22 device scope relationships between PCI devices and which DMA engine controls
58 option intel_iommu=igfx_off to turn off the integrated graphics engine.
70 When errors are reported, the DMA engine signals via an interrupt. The fault
/linux-4.1.27/Documentation/video4linux/
DREADME.cpia278 frame rate achieved by the camera. If the compression engine is able to
81 The compression engine starts out at maximum compression, and will
83 as the compression engine can keep up with the frame rate, after a short time
85 At low alternate settings, the compression engine may not be able to
/linux-4.1.27/drivers/dma/hsu/
DKconfig1 # DMA engine configuration for hsu
/linux-4.1.27/Documentation/ABI/removed/
Dnet_dma6 that will be offloaded to a DMA copy engine. Removed due to
/linux-4.1.27/Documentation/fb/
Daty128fb.txt55 noaccel - do not use acceleration engine. It is default.
56 accel - use acceleration engine. Not finished.

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