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Searched refs:nv_rd32 (Results 1 – 145 of 145) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv50.c47 return nv_rd32(priv, 0x1540); in nv50_gr_units()
255 for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
260 for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
265 for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
275 tmp = nv_rd32(priv, 0x400700); in g84_gr_tlb_flush()
281 nv_rd32(priv, 0x400380)); in g84_gr_tlb_flush()
283 nv_rd32(priv, 0x400384)); in g84_gr_tlb_flush()
285 nv_rd32(priv, 0x400388)); in g84_gr_tlb_flush()
433 u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); in nv50_priv_prop_trap()
434 u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); in nv50_priv_prop_trap()
[all …]
Dnv40.c47 return nv_rd32(priv, 0x1540); in nv40_gr_units()
165 if (nv_rd32(priv, 0x40032c) == inst) { in nv40_gr_context_fini()
172 u32 insn = nv_rd32(priv, 0x400308); in nv40_gr_context_fini()
181 if (nv_rd32(priv, 0x400330) == inst) in nv40_gr_context_fini()
291 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); in nv40_gr_intr()
292 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); in nv40_gr_intr()
293 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); in nv40_gr_intr()
294 u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff; in nv40_gr_intr()
295 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); in nv40_gr_intr()
298 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); in nv40_gr_intr()
[all …]
Dgf100.c778 trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); in gf100_gr_trap_gpc_rop()
779 trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); in gf100_gr_trap_gpc_rop()
780 trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); in gf100_gr_trap_gpc_rop()
781 trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); in gf100_gr_trap_gpc_rop()
840 u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); in gf100_gr_trap_mp()
841 u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); in gf100_gr_trap_mp()
858 u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); in gf100_gr_trap_tpc()
861 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); in gf100_gr_trap_tpc()
873 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); in gf100_gr_trap_tpc()
880 u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); in gf100_gr_trap_tpc()
[all …]
Dnv20.c125 if (nv_rd32(priv, 0x400144) & 0x00010000) in nv20_gr_context_fini()
126 chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; in nv20_gr_context_fini()
195 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); in nv20_gr_intr()
196 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); in nv20_gr_intr()
197 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); in nv20_gr_intr()
198 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); in nv20_gr_intr()
202 u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); in nv20_gr_intr()
203 u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; in nv20_gr_intr()
331 nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); in nv20_gr_init()
333 nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324)); in nv20_gr_init()
[all …]
Dnv10.c420 state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \
503 xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); in nv17_gr_mthd_lma_window()
504 xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); in nv17_gr_mthd_lma_window()
609 if (nv_rd32(priv, 0x400144) & 0x00010000) { in nv10_gr_channel()
610 int chid = nv_rd32(priv, 0x400148) >> 24; in nv10_gr_channel()
645 xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); in nv10_gr_load_pipe()
646 xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); in nv10_gr_load_pipe()
879 int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; in nv10_gr_load_dma_vtxbuf()
891 ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER); in nv10_gr_load_dma_vtxbuf()
893 ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i)); in nv10_gr_load_dma_vtxbuf()
[all …]
Dnv04.c450 int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; in nv04_gr_set_ctx1()
1038 if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { in nv04_gr_channel()
1039 int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; in nv04_gr_channel()
1068 chan->nv04[i] = nv_rd32(priv, nv04_gr_ctx_regs[i]); in nv04_gr_unload_context()
1092 chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; in nv04_gr_context_switch()
1203 nv_rd32(gr, NV04_PGRAPH_STATUS)); in nv04_gr_idle()
1256 u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); in nv04_gr_intr()
1257 u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); in nv04_gr_intr()
1258 u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); in nv04_gr_intr()
1259 u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); in nv04_gr_intr()
[all …]
Dnv30.c211 nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); in nv30_gr_init()
212 nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); in nv30_gr_init()
215 nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200)); in nv30_gr_init()
217 nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204)); in nv30_gr_init()
Dgm204.c267 tmp = nv_rd32(priv, 0x100c80); /*XXX: mask? */ in gm204_gr_init()
311 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); in gm204_gr_init()
312 nv_wr32(priv, GPC_BCAST(0x033c), nv_rd32(priv, 0x100804)); in gm204_gr_init()
Dctxgm204.c941 const u32 fbp_count = nv_rd32(priv, 0x12006c); in gm204_grctx_generate_rop_active_fbps()
Dgk104.c252 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); in gk104_gr_init()
Dctxgk104.c946 const u32 fbp_count = nv_rd32(priv, 0x120074); in gk104_grctx_generate_rop_active_fbps()
Dgm107.c374 nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); in gm107_gr_init()
Dctxnv50.c302 u32 units = nv_rd32 (ctx->device, 0x1540); in nv50_gr_construct_mmio()
1193 u32 units = nv_rd32 (ctx->device, 0x1540); in nv50_gr_construct_xfer1()
3276 u32 units = nv_rd32 (ctx->device, 0x1540); in nv50_gr_construct_xfer2()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgf100.c33 u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400)); in gf100_ibus_intr_hub()
34 u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400)); in gf100_ibus_intr_hub()
35 u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0400)); in gf100_ibus_intr_hub()
43 u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400)); in gf100_ibus_intr_rop()
44 u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400)); in gf100_ibus_intr_rop()
45 u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0400)); in gf100_ibus_intr_rop()
53 u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400)); in gf100_ibus_intr_gpc()
54 u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400)); in gf100_ibus_intr_gpc()
55 u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0400)); in gf100_ibus_intr_gpc()
64 u32 intr0 = nv_rd32(priv, 0x121c58); in gf100_ibus_intr()
[all …]
Dgk104.c33 u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800)); in gk104_ibus_intr_hub()
34 u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800)); in gk104_ibus_intr_hub()
35 u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0800)); in gk104_ibus_intr_hub()
43 u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800)); in gk104_ibus_intr_rop()
44 u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800)); in gk104_ibus_intr_rop()
45 u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0800)); in gk104_ibus_intr_rop()
53 u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800)); in gk104_ibus_intr_gpc()
54 u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800)); in gk104_ibus_intr_gpc()
55 u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0800)); in gk104_ibus_intr_gpc()
64 u32 intr0 = nv_rd32(priv, 0x120058); in gk104_ibus_intr()
[all …]
Dgk20a.c40 nv_rd32(priv, 0x122204); in gk20a_ibus_init_priv_ring()
47 u32 status0 = nv_rd32(priv, 0x120058); in gk20a_ibus_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dbase.c44 addr = nv_rd32(pmu, 0x10a4a0); in nvkm_pmu_send()
61 } while (nv_rd32(pmu, 0x10a580) != 0x00000001); in nvkm_pmu_send()
93 u32 addr = nv_rd32(pmu, 0x10a4cc); in nvkm_pmu_recv()
94 if (addr == nv_rd32(pmu, 0x10a4c8)) in nvkm_pmu_recv()
100 } while (nv_rd32(pmu, 0x10a580) != 0x00000002); in nvkm_pmu_recv()
105 process = nv_rd32(pmu, 0x10a1c4); in nvkm_pmu_recv()
106 message = nv_rd32(pmu, 0x10a1c4); in nvkm_pmu_recv()
107 data0 = nv_rd32(pmu, 0x10a1c4); in nvkm_pmu_recv()
108 data1 = nv_rd32(pmu, 0x10a1c4); in nvkm_pmu_recv()
141 u32 disp = nv_rd32(pmu, 0x10a01c); in nvkm_pmu_intr()
[all …]
Dmemx.c66 } while (nv_rd32(pmu, 0x10a580) != 0x00000003); in nvkm_memx_init()
82 finish = nv_rd32(pmu, 0x10a1c0) & 0x00ffffff; in nvkm_memx_fini()
130 heads = nv_rd32(pmu, 0x610050); in nvkm_memx_wait_vblank()
134 x = nv_rd32(pmu, 0x610b40 + (0x540 * i)); in nvkm_memx_wait_vblank()
182 res[i] = nv_rd32(pmu, 0x10a1c4); in nvkm_memx_train_result()
Dgk104.c33 nv_rd32(pmu, 0x000200); in gk104_pmu_pgob()
50 nv_rd32(pmu, 0x000200); in gk104_pmu_pgob()
Dgk110.c58 nv_rd32(pmu, 0x000200); in gk110_pmu_pgob()
78 nv_rd32(pmu, 0x000200); in gk110_pmu_pgob()
Dgk20a.c101 status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
102 status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/pm/
Dgf100.c68 case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break; in gf100_perfctr_read()
69 case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break; in gf100_perfctr_read()
70 case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break; in gf100_perfctr_read()
71 case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break; in gf100_perfctr_read()
73 cntr->base.clk = nv_rd32(priv, dom->addr + 0x070); in gf100_perfctr_read()
125 mask = (1 << nv_rd32(priv, 0x022430)) - 1; in gf100_pm_ctor()
126 mask &= ~nv_rd32(priv, 0x022504); in gf100_pm_ctor()
127 mask &= ~nv_rd32(priv, 0x022584); in gf100_pm_ctor()
135 mask = (1 << nv_rd32(priv, 0x022438)) - 1; in gf100_pm_ctor()
136 mask &= ~nv_rd32(priv, 0x022548); in gf100_pm_ctor()
[all …]
Dgk104.c114 mask = (1 << nv_rd32(priv, 0x022430)) - 1; in gk104_pm_ctor()
115 mask &= ~nv_rd32(priv, 0x022504); in gk104_pm_ctor()
116 mask &= ~nv_rd32(priv, 0x022584); in gk104_pm_ctor()
124 mask = (1 << nv_rd32(priv, 0x022438)) - 1; in gk104_pm_ctor()
125 mask &= ~nv_rd32(priv, 0x022548); in gk104_pm_ctor()
126 mask &= ~nv_rd32(priv, 0x0225c8); in gk104_pm_ctor()
Dnv40.c52 case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break; in nv40_perfctr_read()
53 case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break; in nv40_perfctr_read()
54 case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break; in nv40_perfctr_read()
55 case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break; in nv40_perfctr_read()
57 cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr); in nv40_perfctr_read()
Ddaemon.c56 ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10)); in pwr_perfctr_next()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf110.c117 nv_rd32(priv, 0x610490 + (chid * 0x10))); in gf110_disp_dmac_init()
136 nv_rd32(priv, 0x610490 + (chid * 0x10))); in gf110_disp_dmac_fini()
316 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490)); in gf110_disp_core_init()
333 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490)); in gf110_disp_core_fini()
558 nv_rd32(priv, 0x610490 + (chid * 0x10))); in gf110_disp_pioc_init()
575 nv_rd32(priv, 0x610490 + (chid * 0x10))); in gf110_disp_pioc_fini()
628 const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300)); in gf110_disp_main_scanoutpos()
629 const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300)); in gf110_disp_main_scanoutpos()
630 const u32 blanks = nv_rd32(priv, 0x640420 + (head * 0x300)); in gf110_disp_main_scanoutpos()
647 nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff; in gf110_disp_main_scanoutpos()
[all …]
Dnv04.c50 args->v0.vblanks = nv_rd32(priv, 0x680800 + hoff) & 0xffff; in nv04_disp_scanoutpos()
51 args->v0.vtotal = nv_rd32(priv, 0x680804 + hoff) & 0xffff; in nv04_disp_scanoutpos()
54 args->v0.hblanks = nv_rd32(priv, 0x680820 + hoff) & 0xffff; in nv04_disp_scanoutpos()
55 args->v0.htotal = nv_rd32(priv, 0x680824 + hoff) & 0xffff; in nv04_disp_scanoutpos()
67 line = nv_rd32(priv, 0x600868 + hoff); in nv04_disp_scanoutpos()
153 u32 crtc0 = nv_rd32(priv, 0x600100); in nv04_disp_intr()
154 u32 crtc1 = nv_rd32(priv, 0x602100); in nv04_disp_intr()
169 pvideo = nv_rd32(priv, 0x8100); in nv04_disp_intr()
Dnv50.c171 return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr); in nv50_disp_chan_rd32()
282 nv_rd32(priv, 0x610200 + (chid * 0x10))); in nv50_disp_dmac_init()
301 nv_rd32(priv, 0x610200 + (chid * 0x10))); in nv50_disp_dmac_fini()
325 u32 next = nv_rd32(priv, list->data[i].addr + base + 0); in nv50_disp_mthd_list()
326 u32 prev = nv_rd32(priv, list->data[i].addr + base + c); in nv50_disp_mthd_list()
531 if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000) in nv50_disp_core_init()
533 if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000) in nv50_disp_core_init()
546 nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); in nv50_disp_core_init()
563 nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200)); in nv50_disp_core_fini()
817 nv_rd32(priv, 0x610200 + (chid * 0x10))); in nv50_disp_pioc_init()
[all …]
Dsorgf110.c98 data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); in gf110_sor_dp_drv_ctl()
99 data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); in gf110_sor_dp_drv_ctl()
100 data[2] = nv_rd32(priv, 0x61c130 + loff); in gf110_sor_dp_drv_ctl()
106 data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); in gf110_sor_dp_drv_ctl()
Dsorgm204.c113 data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); in gm204_sor_dp_drv_ctl()
114 data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); in gm204_sor_dp_drv_ctl()
115 data[2] = nv_rd32(priv, 0x61c130 + loff); in gm204_sor_dp_drv_ctl()
121 data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); in gm204_sor_dp_drv_ctl()
Dsorg94.c121 data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drv_ctl()
122 data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drv_ctl()
123 data[2] = nv_rd32(priv, 0x61c130 + loff); in g94_sor_dp_drv_ctl()
Dvga.c149 if (!(nv_rd32(obj, 0x001084) & 0x10000000)) in nv_lockvgac()
178 u32 tied = nv_rd32(obj, 0x001084) & 0x10000000; in nv_rdvgaowner()
Dgm107.c58 int heads = nv_rd32(parent, 0x022448); in gm107_disp_ctor()
Dgk110.c58 int heads = nv_rd32(parent, 0x022448); in gk110_disp_ctor()
Dgm204.c59 int heads = nv_rd32(parent, 0x022448); in gm204_disp_ctor()
Dgk104.c223 int heads = nv_rd32(parent, 0x022448); in gk104_disp_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv04.c208 chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; in nv04_fifo_chan_fini()
218 u32 rv = (nv_rd32(priv, c->regp) & rm) >> c->regs; in nv04_fifo_chan_fini()
326 if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
390 engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); in nv04_fifo_swmthd()
423 mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
424 data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
426 mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
427 data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
443 nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1); in nv04_fifo_cache_error()
446 nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1); in nv04_fifo_cache_error()
[all …]
Dgk104.c120 if (wait_event_timeout(engn->wait, !(nv_rd32(priv, 0x002284 + in gk104_fifo_runlist_update()
521 u32 intr = nv_rd32(priv, 0x00252c); in gk104_fifo_intr_bind()
547 u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04)); in gk104_fifo_intr_sched_ctxsw()
570 u32 intr = nv_rd32(priv, 0x00254c); in gk104_fifo_intr_sched()
593 u32 stat = nv_rd32(priv, 0x00256c); in gk104_fifo_intr_chsw()
601 u32 stat = nv_rd32(priv, 0x00259c); in gk104_fifo_intr_dropped_fault()
713 u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); in gk104_fifo_intr_fault()
714 u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); in gk104_fifo_intr_fault()
715 u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); in gk104_fifo_intr_fault()
716 u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); in gk104_fifo_intr_fault()
[all …]
Dgf100.c101 !(nv_rd32(priv, 0x00227c) & 0x00100000), in gf100_fifo_runlist_update()
496 u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04)); in gf100_fifo_intr_sched_ctxsw()
517 u32 intr = nv_rd32(priv, 0x00254c); in gf100_fifo_intr_sched()
599 u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); in gf100_fifo_intr_fault()
600 u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); in gf100_fifo_intr_fault()
601 u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); in gf100_fifo_intr_fault()
602 u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); in gf100_fifo_intr_fault()
683 u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); in gf100_fifo_intr_pbdma()
684 u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); in gf100_fifo_intr_pbdma()
685 u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); in gf100_fifo_intr_pbdma()
[all …]
Dnv40.c131 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) in nv40_fifo_context_attach()
167 if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) in nv40_fifo_context_detach()
Dnv50.c52 if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000) in nv50_fifo_playlist_update_locked()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dnv31.c31 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); in nv31_bus_intr()
32 u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144); in nv31_bus_intr()
41 u32 addr = nv_rd32(pbus, 0x009084); in nv31_bus_intr()
42 u32 data = nv_rd32(pbus, 0x009088); in nv31_bus_intr()
Dgf100.c31 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); in gf100_bus_intr()
34 u32 addr = nv_rd32(pbus, 0x009084); in gf100_bus_intr()
35 u32 data = nv_rd32(pbus, 0x009088); in gf100_bus_intr()
Dnv50.c49 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); in nv50_bus_intr()
52 u32 addr = nv_rd32(pbus, 0x009084); in nv50_bus_intr()
53 u32 data = nv_rd32(pbus, 0x009088); in nv50_bus_intr()
Dnv04.c31 u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); in nv04_bus_intr()
Dhwsq.h89 reg->data = nv_rd32(ram->subdev, reg->addr); in hwsq_rd32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dgk104.c29 u32 intr0 = nv_rd32(gpio, 0x00dc00); in gk104_gpio_intr_stat()
30 u32 intr1 = nv_rd32(gpio, 0x00dc80); in gk104_gpio_intr_stat()
31 u32 stat0 = nv_rd32(gpio, 0x00dc08) & intr0; in gk104_gpio_intr_stat()
32 u32 stat1 = nv_rd32(gpio, 0x00dc88) & intr1; in gk104_gpio_intr_stat()
42 u32 inte0 = nv_rd32(gpio, 0x00dc08); in gk104_gpio_intr_mask()
43 u32 inte1 = nv_rd32(gpio, 0x00dc88); in gk104_gpio_intr_mask()
Dg94.c29 u32 intr0 = nv_rd32(gpio, 0x00e054); in g94_gpio_intr_stat()
30 u32 intr1 = nv_rd32(gpio, 0x00e074); in g94_gpio_intr_stat()
31 u32 stat0 = nv_rd32(gpio, 0x00e050) & intr0; in g94_gpio_intr_stat()
32 u32 stat1 = nv_rd32(gpio, 0x00e070) & intr1; in g94_gpio_intr_stat()
42 u32 inte0 = nv_rd32(gpio, 0x00e050); in g94_gpio_intr_mask()
43 u32 inte1 = nv_rd32(gpio, 0x00e070); in g94_gpio_intr_mask()
Dnv10.c33 line = nv_rd32(gpio, 0x600818) >> line; in nv10_gpio_sense()
38 line = nv_rd32(gpio, 0x60081c) >> line; in nv10_gpio_sense()
43 line = nv_rd32(gpio, 0x600850) >> line; in nv10_gpio_sense()
83 u32 intr = nv_rd32(gpio, 0x001104); in nv10_gpio_intr_stat()
84 u32 stat = nv_rd32(gpio, 0x001144) & intr; in nv10_gpio_intr_stat()
93 u32 inte = nv_rd32(gpio, 0x001144); in nv10_gpio_intr_mask()
Dnv50.c89 return !!(nv_rd32(gpio, reg) & (4 << shift)); in nv50_gpio_sense()
95 u32 intr = nv_rd32(gpio, 0x00e054); in nv50_gpio_intr_stat()
96 u32 stat = nv_rd32(gpio, 0x00e050) & intr; in nv50_gpio_intr_stat()
105 u32 inte = nv_rd32(gpio, 0x00e050); in nv50_gpio_intr_mask()
Dgf110.c66 return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000); in gf110_gpio_sense()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dshadowramin.c38 *(u32 *)&bios->data[i] = nv_rd32(bios, 0x700000 + i); in pramin_read()
66 addr = nv_rd32(bios, 0x021c04); in pramin_init()
69 addr = nv_rd32(bios, 0x022500); in pramin_init()
79 addr = nv_rd32(bios, 0x619f04); in pramin_init()
92 addr = (u64)nv_rd32(bios, 0x001700) << 16; in pramin_init()
103 priv->bar0 = nv_rd32(bios, 0x001700); in pramin_init()
Dshadowrom.c33 *(u32 *)&bios->data[i] = nv_rd32(bios, 0x300000 + i); in prom_read()
Dramcfg.c32 return (nv_rd32(subdev, 0x101000) & 0x0000003c) >> 2; in nvbios_ramcfg_strap()
Dpll.c366 u32 sel_clk = nv_rd32(bios, 0x680524); in nvbios_pll_parse()
Dinit.c186 return nv_rd32(init->subdev, reg); in init_rd32()
203 u32 tmp = nv_rd32(init->subdev, reg); in init_mask()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv44.c70 if (nv_rd32(priv, 0x00b318) == inst) in nv44_mpeg_context_fini()
101 u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff; in nv44_mpeg_intr()
102 u32 stat = nv_rd32(priv, 0x00b100); in nv44_mpeg_intr()
103 u32 type = nv_rd32(priv, 0x00b230); in nv44_mpeg_intr()
104 u32 mthd = nv_rd32(priv, 0x00b234); in nv44_mpeg_intr()
105 u32 data = nv_rd32(priv, 0x00b238); in nv44_mpeg_intr()
146 if ((stat = nv_rd32(priv, 0x00b100))) in nv44_mpeg_me_intr()
149 if ((stat = nv_rd32(priv, 0x00b800))) { in nv44_mpeg_me_intr()
Dnv50.c126 u32 stat = nv_rd32(priv, 0x00b100); in nv50_mpeg_intr()
127 u32 type = nv_rd32(priv, 0x00b230); in nv50_mpeg_intr()
128 u32 mthd = nv_rd32(priv, 0x00b234); in nv50_mpeg_intr()
129 u32 data = nv_rd32(priv, 0x00b238); in nv50_mpeg_intr()
154 if (nv_rd32(priv, 0x00b100)) in nv50_vpe_intr()
157 if (nv_rd32(priv, 0x00b800)) { in nv50_vpe_intr()
158 u32 stat = nv_rd32(priv, 0x00b800); in nv50_vpe_intr()
209 nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); in nv50_mpeg_init()
Dnv31.c200 u32 stat = nv_rd32(priv, 0x00b100); in nv31_mpeg_intr()
201 u32 type = nv_rd32(priv, 0x00b230); in nv31_mpeg_intr()
202 u32 mthd = nv_rd32(priv, 0x00b234); in nv31_mpeg_intr()
203 u32 data = nv_rd32(priv, 0x00b238); in nv31_mpeg_intr()
288 nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); in nv31_mpeg_init()
Dnv40.c95 if ((stat = nv_rd32(priv, 0x00b100))) in nv40_mpeg_intr()
98 if ((stat = nv_rd32(priv, 0x00b800))) { in nv40_mpeg_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv50.c41 return nv_rd32(priv, 0x004700); in read_div()
45 return nv_rd32(priv, 0x004800); in read_div()
56 u32 rsel = nv_rd32(priv, 0x00e18c); in read_pll_src()
72 coef = nv_rd32(priv, 0x00e81c + (id * 0x0c)); in read_pll_src()
81 coef = nv_rd32(priv, 0x00e81c); in read_pll_src()
89 rsel = nv_rd32(priv, 0x00c050); in read_pll_src()
107 coef = nv_rd32(priv, 0x00e81c + (id * 0x28)); in read_pll_src()
108 P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7; in read_pll_src()
127 u32 src, mast = nv_rd32(priv, 0x00c040); in read_pll_ref()
159 u32 mast = nv_rd32(priv, 0x00c040); in read_pll()
[all …]
Dgk20a.c133 val = nv_rd32(priv, GPCPLL_COEFF); in gk20a_pllg_read_mnp()
274 val = nv_rd32(priv, GPCPLL_COEFF); in gk20a_pllg_slide()
291 val = nv_rd32(priv, GPCPLL_COEFF); in gk20a_pllg_slide()
298 val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); in gk20a_pllg_slide()
305 val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); in gk20a_pllg_slide()
314 nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); in gk20a_pllg_slide()
328 nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_enable()
335 nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_disable()
345 val = nv_rd32(priv, GPCPLL_COEFF); in _gk20a_pllg_program_mnp()
350 cfg = nv_rd32(priv, GPCPLL_CFG); in _gk20a_pllg_program_mnp()
[all …]
Dgk104.c52 u32 ssrc = nv_rd32(priv, dsrc); in read_vco()
61 u32 ctrl = nv_rd32(priv, pll + 0x00); in read_pll()
62 u32 coef = nv_rd32(priv, pll + 0x04); in read_pll()
84 fN = nv_rd32(priv, pll + 0x10) >> 16; in read_pll()
106 u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); in read_div()
107 u32 sctl = nv_rd32(priv, dctl + (doff * 4)); in read_div()
132 switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) { in read_mem()
143 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); in read_clk()
147 u32 ssel = nv_rd32(priv, 0x137100); in read_clk()
156 u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04)); in read_clk()
Dgt215.c45 u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); in read_vco()
68 return nv_rd32(priv, 0x00471c) * 1000; in read_clk()
74 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); in read_clk()
108 u32 ctrl = nv_rd32(priv, pll + 0); in read_pll()
113 u32 coef = nv_rd32(priv, pll + 4); in read_pll()
159 hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; in gt215_clk_read()
351 bypass = nv_rd32(priv, ctrl) & 0x00000008; in prog_pll()
390 u32 hsrc = (nv_rd32(priv, 0xc040)); in prog_host()
417 u32 fb_delay = nv_rd32(priv, 0x10002c); in prog_core()
Dmcp77.c44 return nv_rd32(clk, 0x004600); in read_div()
50 u32 ctrl = nv_rd32(clk, base + 0); in read_pll()
51 u32 coef = nv_rd32(clk, base + 4); in read_pll()
59 post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16); in read_pll()
62 post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16; in read_pll()
82 u32 mast = nv_rd32(clk, 0x00c054); in mcp77_clk_read()
103 P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16; in mcp77_clk_read()
126 P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16; in mcp77_clk_read()
Dgf100.c52 u32 ssrc = nv_rd32(priv, dsrc); in read_vco()
62 u32 ctrl = nv_rd32(priv, pll + 0x00); in read_pll()
63 u32 coef = nv_rd32(priv, pll + 0x04); in read_pll()
100 u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); in read_div()
101 u32 sctl = nv_rd32(priv, dctl + (doff * 4)); in read_div()
126 u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); in read_clk()
127 u32 ssel = nv_rd32(priv, 0x137100); in read_clk()
172 if (nv_rd32(priv, 0x1373f0) & 0x00000002) in gf100_clk_read()
Dnv40.c52 u32 ctrl = nv_rd32(priv, reg + 0x00); in read_pll_1()
67 u32 ctrl = nv_rd32(priv, reg + 0x00); in read_pll_2()
68 u32 coef = nv_rd32(priv, reg + 0x04); in read_pll_2()
108 u32 mast = nv_rd32(priv, 0x00c040); in nv40_clk_read()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dnv40.c71 return nv_rd32(therm, 0x15b4) & 0x3fff; in nv40_sensor_setup()
75 return nv_rd32(therm, 0x15b4) & 0xff; in nv40_sensor_setup()
90 core_temp = nv_rd32(therm, 0x15b4) & 0x3fff; in nv40_temp_get()
93 core_temp = nv_rd32(therm, 0x15b4) & 0xff; in nv40_temp_get()
130 u32 reg = nv_rd32(therm, 0x0010f0); in nv40_fan_pwm_get()
138 u32 reg = nv_rd32(therm, 0x0015f4); in nv40_fan_pwm_get()
140 *divs = nv_rd32(therm, 0x0015f8); in nv40_fan_pwm_get()
173 uint32_t stat = nv_rd32(therm, 0x1100); in nv40_therm_intr()
Dgf110.c35 u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04)); in pwm_info()
76 if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) { in gf110_fan_pwm_get()
77 *divs = nv_rd32(therm, 0x00e114 + (indx * 8)); in gf110_fan_pwm_get()
78 *duty = nv_rd32(therm, 0x00e118 + (indx * 8)); in gf110_fan_pwm_get()
82 *divs = nv_rd32(therm, 0x0200d8) & 0x1fff; in gf110_fan_pwm_get()
83 *duty = nv_rd32(therm, 0x0200dc) & 0x1fff; in gf110_fan_pwm_get()
Dnv50.c75 if (nv_rd32(therm, ctrl) & (1 << line)) { in nv50_fan_pwm_get()
76 *divs = nv_rd32(therm, 0x00e114 + (id * 8)); in nv50_fan_pwm_get()
77 *duty = nv_rd32(therm, 0x00e118 + (id * 8)); in nv50_fan_pwm_get()
105 u8 pwm_div = nv_rd32(therm, 0x410c); in nv50_fan_pwm_clock()
106 if (nv_rd32(therm, 0xc040) & 0x800000) { in nv50_fan_pwm_clock()
136 core_temp = nv_rd32(therm, 0x20014) & 0x3fff; in nv50_temp_get()
Dgm107.c42 *divs = nv_rd32(therm, 0x10eb20) & 0x1fff; in gm107_fan_pwm_get()
43 *duty = nv_rd32(therm, 0x10eb24) & 0x1fff; in gm107_fan_pwm_get()
Dgt215.c36 u32 tach = nv_rd32(therm, 0x00e728) & 0x0000ffff; in gt215_therm_fan_sense()
37 u32 ctrl = nv_rd32(therm, 0x00e720); in gt215_therm_fan_sense()
Dg84.c39 return nv_rd32(therm, 0x20400); in g84_temp_get()
105 temp = nv_rd32(therm, thrs_reg); in g84_therm_threshold_hyst_emulation()
148 intr = nv_rd32(therm, 0x20100) & 0x3ff; in g84_therm_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/sec/
Dg98.c82 u32 disp = nv_rd32(priv, 0x08701c); in g98_sec_intr()
83 u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16); in g98_sec_intr()
84 u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff; in g98_sec_intr()
85 u32 ssta = nv_rd32(priv, 0x087040) & 0x0000ffff; in g98_sec_intr()
86 u32 addr = nv_rd32(priv, 0x087040) >> 16; in g98_sec_intr()
89 u32 data = nv_rd32(priv, 0x087044); in g98_sec_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv20.c33 u32 pbus1218 = nv_rd32(pfb, 0x001218); in nv20_ram_create()
47 ram->size = (nv_rd32(pfb, 0x10020c) & 0xff000000); in nv20_ram_create()
48 ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; in nv20_ram_create()
49 ram->tags = nv_rd32(pfb, 0x100320); in nv20_ram_create()
Dramnv49.c33 u32 pfb914 = nv_rd32(pfb, 0x100914); in nv49_ram_create()
48 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv49_ram_create()
49 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; in nv49_ram_create()
50 ram->base.tags = nv_rd32(pfb, 0x100320); in nv49_ram_create()
Dramnv41.c33 u32 pfb474 = nv_rd32(pfb, 0x100474); in nv41_ram_create()
48 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv41_ram_create()
49 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; in nv41_ram_create()
50 ram->base.tags = nv_rd32(pfb, 0x100320); in nv41_ram_create()
Dramnv40.c79 u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000)); in nv40_ram_prog()
82 if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) { in nv40_ram_prog()
178 u32 pbus1218 = nv_rd32(pfb, 0x001218); in nv40_ram_create()
193 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv40_ram_create()
194 ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; in nv40_ram_create()
195 ram->base.tags = nv_rd32(pfb, 0x100320); in nv40_ram_create()
Dramnv50.c321 r0 = nv_rd32(pfb, 0x100200); in nv50_fb_vram_rblock()
322 r4 = nv_rd32(pfb, 0x100204); in nv50_fb_vram_rblock()
323 rt = nv_rd32(pfb, 0x100250); in nv50_fb_vram_rblock()
325 r0, r4, rt, nv_rd32(pfb, 0x001540)); in nv50_fb_vram_rblock()
366 ram->size = nv_rd32(pfb, 0x10020c); in nv50_ram_create_()
369 ram->part_mask = (nv_rd32(pfb, 0x001540) & 0x00ff0000) >> 16; in nv50_ram_create_()
372 switch (nv_rd32(pfb, 0x100714) & 0x00000007) { in nv50_ram_create_()
393 ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1; in nv50_ram_create_()
394 ram->tags = nv_rd32(pfb, 0x100320); in nv50_ram_create_()
Dramnv10.c33 u32 cfg0 = nv_rd32(pfb, 0x100200); in nv10_ram_create()
46 ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv10_ram_create()
Dramnv44.c33 u32 pfb474 = nv_rd32(pfb, 0x100474); in nv44_ram_create()
48 ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv44_ram_create()
Drammcp77.c48 priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12; in mcp77_ram_ctor()
49 priv->base.size = (u64)nv_rd32(pfb, 0x100e14) << 12; in mcp77_ram_ctor()
Dramgf100.c112 u32 part = nv_rd32(pfb, 0x022438), i; in gf100_ram_train()
113 u32 mask = nv_rd32(pfb, 0x022554); in gf100_ram_train()
515 u32 parts = nv_rd32(pfb, 0x022438); in gf100_ram_create_()
516 u32 pmask = nv_rd32(pfb, maskaddr); in gf100_ram_create_()
517 u32 bsize = nv_rd32(pfb, 0x10f20c); in gf100_ram_create_()
527 nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800)); in gf100_ram_create_()
531 ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1; in gf100_ram_create_()
536 u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000)); in gf100_ram_create_()
Dnv30.c71 nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : in calc_bias()
108 int l = nv_rd32(priv, 0x1003d0); in nv30_fb_init()
Dramnv4e.c40 ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000; in nv4e_ram_create()
Dramgt215.c322 r001700 = nv_rd32(pfb, 0x1700); in gt215_link_train_init()
330 train->r_100720 = nv_rd32(pfb, 0x100720); in gt215_link_train_init()
331 train->r_1111e0 = nv_rd32(pfb, 0x1111e0); in gt215_link_train_init()
332 train->r_111400 = nv_rd32(pfb, 0x111400); in gt215_link_train_init()
357 cur2 = nv_rd32(pfb, 0x100228); in gt215_ram_timing_calc()
358 cur3 = nv_rd32(pfb, 0x10022c); in gt215_ram_timing_calc()
359 cur7 = nv_rd32(pfb, 0x10023c); in gt215_ram_timing_calc()
360 cur8 = nv_rd32(pfb, 0x100240); in gt215_ram_timing_calc()
Dramnv04.c34 u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0); in nv04_ram_create()
Dnv41.c34 nv_rd32(pfb, 0x100600 + (i * 0x10)); in nv41_fb_tile_prog()
Dnv10.c52 nv_rd32(pfb, 0x100240 + (i * 0x10)); in nv10_fb_tile_prog()
Dnv44.c44 nv_rd32(pfb, 0x100600 + (i * 0x10)); in nv44_fb_tile_prog()
Dnv50.c157 idx = nv_rd32(priv, 0x100c90); in nv50_fb_intr()
164 trap[i] = nv_rd32(priv, 0x100c94); in nv50_fb_intr()
Dgf100.c41 u32 intr = nv_rd32(priv, 0x000100); in gf100_fb_intr()
Dnv20.c74 nv_rd32(pfb, 0x100240 + (i * 0x10)); in nv20_fb_tile_prog()
Dbase.c32 const u8 ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2; in nvkm_fb_bios_memtype()
Dramfuc.h86 reg->data = nv_rd32(ram->pfb, reg->addr); in ramfuc_rd32()
Dramgk104.c241 u32 prev = nv_rd32(priv, addr); in gk104_ram_nuts()
1339 save = nv_rd32(pfb, 0x10f65c) & 0x000000f0; in gk104_ram_init()
1480 ram->parts = nv_rd32(pfb, 0x022438); in gk104_ram_ctor()
1481 ram->pmask = nv_rd32(pfb, 0x022554); in gk104_ram_ctor()
1485 u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); in gk104_ram_ctor()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dg94.c29 u32 intr = nv_rd32(i2c, 0x00e06c); in g94_aux_stat()
30 u32 stat = nv_rd32(i2c, 0x00e068) & intr, i; in g94_aux_stat()
43 u32 temp = nv_rd32(i2c, 0x00e068), i; in g94_aux_mask()
76 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); in auxch_init()
88 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); in auxch_init()
117 stat = nv_rd32(aux, 0x00e4e8 + (ch * 0x50)); in g94_aux()
132 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); in g94_aux()
151 ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); in g94_aux()
176 xbuf[i / 4] = nv_rd32(aux, 0x00e4d0 + (ch * 0x50) + i); in g94_aux()
Dgm204.c46 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); in auxch_init()
58 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); in auxch_init()
87 stat = nv_rd32(aux, 0x00d958 + (ch * 0x50)); in gm204_aux()
102 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); in gm204_aux()
121 ctrl = nv_rd32(aux, 0x00d954 + (ch * 0x50)); in gm204_aux()
146 xbuf[i / 4] = nv_rd32(aux, 0x00d940 + (ch * 0x50) + i); in gm204_aux()
Dgk104.c29 u32 intr = nv_rd32(i2c, 0x00dc60); in gk104_aux_stat()
30 u32 stat = nv_rd32(i2c, 0x00dc68) & intr, i; in gk104_aux_stat()
43 u32 temp = nv_rd32(i2c, 0x00dc68), i; in gk104_aux_mask()
Dgf110.c31 return !!(nv_rd32(priv, port->addr) & 0x00000010); in gf110_i2c_sense_scl()
39 return !!(nv_rd32(priv, port->addr) & 0x00000020); in gf110_i2c_sense_sda()
Dnv4e.c58 return !!(nv_rd32(priv, port->addr) & 0x00040000); in nv4e_i2c_sense_scl()
66 return !!(nv_rd32(priv, port->addr) & 0x00080000); in nv4e_i2c_sense_sda()
Dnv50.c51 return !!(nv_rd32(priv, port->addr) & 0x00000001); in nv50_i2c_sense_scl()
59 return !!(nv_rd32(priv, port->addr) & 0x00000002); in nv50_i2c_sense_sda()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dgm107.c68 u32 stat = nv_rd32(priv, base + 0x00c); in gm107_ltc_lts_isr()
82 mask = nv_rd32(priv, 0x00017c); in gm107_ltc_intr()
95 u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); in gm107_ltc_init()
123 parts = nv_rd32(priv, 0x022438); in gm107_ltc_ctor()
124 mask = nv_rd32(priv, 0x021c14); in gm107_ltc_ctor()
129 priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28; in gm107_ltc_ctor()
Dgf100.c87 u32 intr = nv_rd32(priv, base + 0x020); in gf100_ltc_lts_intr()
105 mask = nv_rd32(priv, 0x00017c); in gf100_ltc_intr()
118 u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); in gf100_ltc_init()
213 parts = nv_rd32(priv, 0x022438); in gf100_ltc_ctor()
214 mask = nv_rd32(priv, 0x022554); in gf100_ltc_ctor()
219 priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28; in gf100_ltc_ctor()
Dgk104.c30 u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); in gk104_ltc_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c146 uint32_t oldpll = nv_rd32(devinit, reg); in setPLL_single()
156 saved_powerctrl_1 = nv_rd32(devinit, 0x001584); in setPLL_single()
173 nv_rd32(devinit, reg); in setPLL_single()
202 uint32_t oldpll1 = nv_rd32(devinit, reg1); in setPLL_double_highregs()
203 uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0; in setPLL_double_highregs()
218 oldramdac580 = nv_rd32(devinit, 0x680580); in setPLL_double_highregs()
234 saved_powerctrl_1 = nv_rd32(devinit, 0x001584); in setPLL_double_highregs()
254 savedc040 = nv_rd32(devinit, 0xc040); in setPLL_double_highregs()
286 uint32_t oldPval = nv_rd32(devinit, Preg); in setPLL_double_lowregs()
295 if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval) in setPLL_double_lowregs()
[all …]
Dgm204.c64 nv_wr32(priv, 0x10a1c0, nv_rd32(priv, 0x10a1c4) + argi); in pmu_args()
65 return nv_rd32(priv, 0x10a1c4); in pmu_args()
123 nv_rd32(priv, 0x000200); in gm204_devinit_post()
124 while (nv_rd32(priv, 0x10a10c) & 0x00000006) { in gm204_devinit_post()
152 while (!(nv_rd32(priv, 0x10a040) & 0x00002000)) { in gm204_devinit_post()
Dgt215.c69 u32 r001540 = nv_rd32(priv, 0x001540); in gt215_devinit_disable()
70 u32 r00154c = nv_rd32(priv, 0x00154c); in gt215_devinit_disable()
126 priv->r001540 = nv_rd32(priv, 0x001540); in gt215_devinit_mmio()
Dnv05.c62 strap = (nv_rd32(priv, 0x101000) & 0x0000003c) >> 2; in nv05_devinit_meminit()
74 if (nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) in nv05_devinit_meminit()
105 v = nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; in nv05_devinit_meminit()
Dgm107.c33 u32 r021c00 = nv_rd32(priv, 0x021c00); in gm107_devinit_disable()
34 u32 r021c04 = nv_rd32(priv, 0x021c04); in gm107_devinit_disable()
Dmcp89.c33 u32 r001540 = nv_rd32(priv, 0x001540); in mcp89_devinit_disable()
34 u32 r00154c = nv_rd32(priv, 0x00154c); in mcp89_devinit_disable()
Dg84.c33 u32 r001540 = nv_rd32(priv, 0x001540); in g84_devinit_disable()
34 u32 r00154c = nv_rd32(priv, 0x00154c); in g84_devinit_disable()
Dg98.c33 u32 r001540 = nv_rd32(priv, 0x001540); in g98_devinit_disable()
34 u32 r00154c = nv_rd32(priv, 0x00154c); in g98_devinit_disable()
Dnv20.c53 amount = nv_rd32(priv, 0x10020c); in nv20_devinit_meminit()
57 amount = nv_rd32(priv, 0x10020c); in nv20_devinit_meminit()
Dnv10.c78 int off = nv_rd32(priv, 0x10020c) - 0x100000; in nv10_devinit_meminit()
Dgf100.c70 u32 r022500 = nv_rd32(priv, 0x022500); in gf100_devinit_disable()
Dnv50.c83 u32 r001540 = nv_rd32(priv, 0x001540); in nv50_devinit_disable()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
Dnv04.c35 hi = nv_rd32(priv, NV04_PTIMER_TIME_1); in nv04_timer_read()
36 lo = nv_rd32(priv, NV04_PTIMER_TIME_0); in nv04_timer_read()
37 } while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1)); in nv04_timer_read()
115 u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0); in nv04_timer_intr()
177 if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) || in nv04_timer_init()
178 !nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) { in nv04_timer_init()
Dbase.c35 if ((nv_rd32(obj, addr) & mask) == data) in nvkm_timer_wait_eq()
55 if ((nv_rd32(obj, addr) & mask) != data) in nvkm_timer_wait_ne()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c115 u32 stat = nv_rd32(priv, 0x102130); in g84_cipher_intr()
116 u32 mthd = nv_rd32(priv, 0x102190); in g84_cipher_intr()
117 u32 data = nv_rd32(priv, 0x102194); in g84_cipher_intr()
118 u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff; in g84_cipher_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
Dmemx.fuc86 nv_rd32($r7, $r8)
95 nv_rd32($r8, $r6)
100 nv_rd32($r8, $r6)
105 nv_rd32($r8, $r6)
140 nv_rd32($r7, $r8)
147 nv_rd32($r8, $r6)
152 nv_rd32($r8, $r6)
157 nv_rd32($r8, $r6)
281 nv_rd32($r8,$r9)
302 nv_rd32($r8, $r9)
[all …]
Dmacros.fuc227 #define nv_rd32(reg,addr) /*
232 #define nv_rd32(reg,addr) /*
Dkernel.fuc126 nv_rd32($r10, $r14)
519 // used by the nv_rd32/nv_wr32 macros to work
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
Dbase.c40 u32 intr = nv_rd32(pmc, 0x000100); in nvkm_mc_intr_mask()
56 nv_rd32(pmc, 0x000140); in nvkm_mc_intr()
Dnv44.c30 u32 tmp = nv_rd32(priv, 0x10020c); in nv44_mc_init()
/linux-4.1.27/drivers/gpu/drm/nouveau/include/nvkm/core/
Dsubdev.h80 nv_rd32(void *obj, u32 addr) in nv_rd32() function
115 u32 temp = nv_rd32(obj, addr); in nv_mask()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/
Dxtensa.c31 return nv_rd32(xtensa, xtensa->addr + addr); in _nvkm_xtensa_rd32()
150 tmp = nv_rd32(xtensa, 0x0); in _nvkm_xtensa_init()
Dfalcon.c50 return nv_rd32(falcon, falcon->addr + addr); in _nvkm_falcon_rd32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
Dgm107.c34 return nv_rd32(priv, 0x21100 + addr); in gm107_fuse_rd32()
Dnv50.c42 val = nv_rd32(priv, 0x21000 + addr); in nv50_fuse_rd32()
Dgf100.c43 val = nv_rd32(priv, 0x21100 + addr); in gf100_fuse_rd32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dgf100.c179 nv_rd32(priv, 0x100c80), type); in gf100_vm_flush()
188 nv_rd32(priv, 0x100c80), type); in gf100_vm_flush()
Dnv44.c147 nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808)); in nv44_vm_flush()
224 addr = nv_rd32(priv, 0x10020c); in nv44_mmu_init()
Dnv41.c74 nv_rd32(priv, 0x100810)); in nv41_vm_flush()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dhub.fuc121 nv_rd32($r14, 0x409604)
194 call(nv_rd32)
198 call(nv_rd32)
347 nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO)
349 nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR)
355 call(nv_rd32)
392 nv_rd32($r15, 0x404160)
418 nv_rd32($r15, 0x404170)
Dmacros.fuc243 #define nv_rd32(reg,addr) /*
245 */ call(nv_rd32) /*
Dgpc.fuc169 call(nv_rd32)
254 call(nv_rd32)
268 call(nv_rd32)
Dcom.fuc89 // nv_rd32 - read 32-bit value from nv register
94 nv_rd32:
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv40.c78 vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8); in nv40_instmem_ctor()
Dnv50.c58 data = nv_rd32(priv, 0x700000 + addr); in nv50_instobj_rd32()
Dnv04.c112 return nv_rd32(object, 0x700000 + addr); in nv04_instmem_rd32()
Dgk20a.c121 data = nv_rd32(priv, 0x700000 + addr); in gk20a_instobj_rd32()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/ce/
Dgk104.c71 u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); in gk104_ce_intr()
Dgm204.c71 u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); in gm204_ce_intr()
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/device/
Dbase.c179 return nv_rd32(object->engine, addr); in nvkm_devobj_rd32()