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Searched refs:CSR (Results 1 – 48 of 48) sorted by relevance

/linux-4.1.27/arch/arm/mach-prima2/
DKconfig2 bool "CSR SiRF" if ARCH_MULTI_V7
10 Support for CSR SiRFprimaII/Marco/Polo platforms
14 comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
17 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
21 Support for CSR SiRFSoC ARM Cortex A9 Platform
24 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
31 Support for CSR SiRFSoC ARM Cortex A7 Platform
34 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
39 Support for CSR SiRFSoC ARM Cortex A9 Platform
/linux-4.1.27/drivers/scsi/aacraid/
Daacraid.h718 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
719 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
720 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
721 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
780 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
781 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
782 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
783 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
798 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
799 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
/linux-4.1.27/arch/arm/boot/dts/
Dprima2-evb.dts2 * DTS file for CSR SiRFprimaII Evaluation Board
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
14 model = "CSR SiRFprimaII Evaluation Board";
Datlas6-evb.dts2 * DTS file for CSR SiRFatlas6 Evaluation Board
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
14 model = "CSR SiRFatlas6 Evaluation Board";
Datlas7-evb.dts2 * DTS file for CSR SiRFatlas7 Evaluation Board
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
14 model = "CSR SiRFatlas7 Evaluation Board";
Datlas6.dtsi2 * DTS file for CSR SiRFatlas6 SoC
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
Dprima2.dtsi2 * DTS file for CSR SiRFprimaII SoC
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
Datlas7.dtsi2 * DTS file for CSR SiRFatlas7 SoC
4 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/arch/c6x/kernel/
Dentry.S31 MVC .S2 CSR,reg
33 MVC .S2 reg,CSR
37 MVC .S2 CSR,reg
39 MVC .S2 reg,CSR
77 || MVC .S2 CSR,B12
114 STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
130 LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
170 || MVC .S2 B12,CSR
248 MVC .S2 CSR,B1
250 MVC .S2 B1,CSR ; enable ints
Dhead.S45 MVC .S2 CSR,B2
47 MVC .S2 B2,CSR
Dsetup.c117 csr = get_creg(CSR); in get_cpuinfo()
/linux-4.1.27/drivers/dma/
Dtxx9dmac.c299 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
311 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
353 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
374 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
487 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
500 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
526 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
552 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
553 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
Dtxx9dmac.h81 TXX9_DMA_REG32(CSR); /* Channel Status Register */
91 u32 CSR; member
Domap-dma.c257 omap_dma_chan_read(c, CSR); in omap_dma_clear_csr()
259 omap_dma_chan_write(c, CSR, ~0); in omap_dma_clear_csr()
264 unsigned val = omap_dma_chan_read(c, CSR); in omap_dma_get_csr()
267 omap_dma_chan_write(c, CSR, val); in omap_dma_get_csr()
DKconfig231 tristate "CSR SiRFprimaII/SiRFmarco DMA support"
235 Enable support for the CSR SiRFprimaII DMA engine.
/linux-4.1.27/Documentation/devicetree/bindings/clock/
Dxgene.txt24 - reg : shall be a list of address and length pairs describing the CSR
37 - csr-offset : Offset to the CSR reset register from the reset address base.
39 - csr-mask : CSR reset mask bit. Default is 0xF.
42 - enable-mask : CSR enable mask bit. Default is 0xF.
43 - divider-offset : Offset to the divider CSR register from the divider base.
Dprima2-clock.txt1 * Clock bindings for CSR SiRFprimaII
/linux-4.1.27/drivers/net/ethernet/qlogic/qlge/
Dqlge_mpi.c8 tmp = ql_read32(qdev, CSR); in ql_unpause_mpi_risc()
12 ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in ql_unpause_mpi_risc()
22 ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in ql_pause_mpi_risc()
24 tmp = ql_read32(qdev, CSR); in ql_pause_mpi_risc()
39 ql_write32(qdev, CSR, CSR_CMD_SET_RST); in ql_hard_reset_mpi_risc()
41 tmp = ql_read32(qdev, CSR); in ql_hard_reset_mpi_risc()
43 ql_write32(qdev, CSR, CSR_CMD_CLR_RST); in ql_hard_reset_mpi_risc()
174 if (ql_read32(qdev, CSR) & CSR_HRI) in ql_exec_mb_cmd()
193 ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in ql_exec_mb_cmd()
516 ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in ql_mpi_handler()
[all …]
Dqlge.h803 CSR = 0x14, enumerator
Dqlge_dbg.c1489 DUMP_REG(qdev, CSR); in ql_dump_regs()
/linux-4.1.27/arch/arm/plat-omap/
Ddma.c495 p->dma_read(CSR, lch); in omap_enable_channel_irq()
497 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_enable_channel_irq()
509 p->dma_read(CSR, lch); in omap_disable_channel_irq()
511 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_disable_channel_irq()
1095 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
1147 u32 status = p->dma_read(CSR, ch); in omap2_dma_handle_ch()
1183 p->dma_write(status, CSR, ch); in omap2_dma_handle_ch()
1202 status = p->dma_read(CSR, ch); in omap2_dma_handle_ch()
1203 p->dma_write(status, CSR, ch); in omap2_dma_handle_ch()
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dsirf.txt1 CSR SiRFprimaII and SiRFmarco device tree bindings.
/linux-4.1.27/arch/arm/mach-omap1/
Ddma.c62 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
222 l = dma_read(CSR, lch); in omap1_clear_dma()
/linux-4.1.27/Documentation/devicetree/bindings/dma/
Dsirfsoc-dma.txt1 * CSR SiRFSoC DMA controller
/linux-4.1.27/Documentation/devicetree/bindings/reset/
Dsirf,rstc.txt1 CSR SiRFSoC Reset Controller
/linux-4.1.27/Documentation/devicetree/bindings/spi/
Dspi-sirf.txt1 * CSR SiRFprimaII Serial Peripheral Interface
/linux-4.1.27/Documentation/devicetree/bindings/serial/
Dsirf-uart.txt1 * CSR SiRFprimaII/atlasVI Universal Synchronous Asynchronous Receiver/Transmitter *
/linux-4.1.27/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-sirf.txt1 CSR SiRFprimaII pinmux controller
/linux-4.1.27/arch/arm/mach-omap2/
Ddma.c62 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
/linux-4.1.27/Documentation/arm/
DIXP4xx39 require the use of Intel's proprietary CSR software:
140 the CSR or a WiFi card and a ramdisk that BOOTPs and then does
/linux-4.1.27/include/linux/
Domap-dma.h155 CSDP, CCR, CICR, CSR, enumerator
/linux-4.1.27/Documentation/rapidio/
Drapidio.txt248 device by writing into the Host Device ID Lock CSR. It does this to ensure that
254 is written into the device's Base Device ID CSR.
271 into device's Component Tag CSR. That unique value is used by the error
283 in the system, it sets the Discovered bit in the Port General Control CSR
/linux-4.1.27/arch/blackfin/include/asm/
Dbfin_can.h116 #define CSR 0x0040 /* CAN Suspend Mode Request */ macro
/linux-4.1.27/drivers/pinctrl/
DKconfig123 bool "CSR SiRFprimaII pin controller driver"
/linux-4.1.27/drivers/regulator/
Dbcm590xx-regulator.c299 BCM590XX_MATCH(csr, CSR),
/linux-4.1.27/arch/arm/mach-tegra/
Dsleep-tegra30.S195 ldr r3, [r1] @ read CSR
196 str r3, [r1] @ clear CSR
/linux-4.1.27/drivers/mmc/host/
DKconfig219 tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
726 the Cypress Astoria chip with firmware compliant with CSR's
729 CSR boards with this device include: USB<>SDIO (M1985v2),
/linux-4.1.27/drivers/bluetooth/
DKconfig76 USB Bluetooth devices based on CSR BlueCore chip, including PCMCIA and
/linux-4.1.27/drivers/spi/
DKconfig508 tristate "CSR SiRFprimaII SPI controller"
512 SPI driver for CSR SiRFprimaII SoCs
/linux-4.1.27/Documentation/frv/
Dfeatures.txt83 0xFC200000 - 0xFC2FFFFF CS3# MB93493 CSR area (DAV daughter board)
Dmmu-layout.txt52 FC200000 - FC2FFFFF L-BUS CS3# MB93493 CSR area (DAV daughter board)
/linux-4.1.27/Documentation/networking/
Dstmmac.txt160 o clk_csr: fixed CSR Clock range selection.
/linux-4.1.27/drivers/i2c/busses/
DKconfig816 tristate "CSR SiRFprimaII I2C interface"
820 CSR SiRFprimaII I2C interface.
/linux-4.1.27/drivers/input/misc/
DKconfig738 bool "CSR SiRFSoC power on/off/suspend key support"
/linux-4.1.27/drivers/tty/serial/
DKconfig296 Support for the on-chip UART on the CSR SiRFprimaII series,
/linux-4.1.27/drivers/watchdog/
DKconfig470 Support for CSR SiRFprimaII and SiRFatlasVI watchdog. When
/linux-4.1.27/Documentation/virtual/kvm/
Dapi.txt2061 MIPS FPU control registers (see KVM_REG_MIPS_FCR_{IR,CSR} above) have the
2065 MIPS MSA control registers (see KVM_REG_MIPS_MSA_{IR,CSR} above) have the
/linux-4.1.27/
DMAINTAINERS981 ARM/CSR SIRFPRIMA2 MACHINE SUPPORT