Searched refs:CSR (Results 1 - 200 of 231) sorted by relevance

12

/linux-4.1.27/include/linux/rtc/
H A Dsirfsoc_rtciobrg.h2 * RTC I/O Bridge interfaces for CSR SiRFprimaII
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/arch/alpha/kernel/
H A Derr_ev7.c193 "DM CSR PH", "DM CSR PH", "DM CSR PH",
194 "DM CSR PH", "reserved",
197 "DM CSR PH", "DM CSR PH", "DM CSR PH",
198 "DM CSR PH", "reserved",
201 "DM CSR PH", "DM CSR PH", "DM CSR PH",
202 "DM CSR PH", "reserved",
205 "DM CSR PH", "DM CSR PH", "DM CSR PH",
206 "DM CSR PH", "reserved",
H A Derr_marvel.c423 printk("%s Write byte into IO7 CSR\n", err_print_prefix); marvel_print_po7_err_sum()
425 printk("%s PIO to non-existent CSR\n", err_print_prefix); marvel_print_po7_err_sum()
785 printk("%s CSR NXM READ\n", err_print_prefix); marvel_print_pox_err()
787 printk("%s CSR NXM WRITE\n", err_print_prefix); marvel_print_pox_err()
H A Dcore_marvel.c343 * Get the Port 7 CSR pointer. marvel_init_io7()
/linux-4.1.27/arch/arm/mach-prima2/
H A Dhotplug.c2 * CPU hotplug support for CSR Marco dual-core SMP SoCs
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dpm.h4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dcommon.c2 * Defines machines for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dheadsmp.S2 * Entry of the second core for CSR Marco dual-core SMP SoCs
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Drtciobrg.c2 * RTC I/O Bridge interfaces for CSR SiRFprimaII
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
137 MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
H A Dcommon.h4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Drstc.c2 * reset controller for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dsleep.S2 * sleep mode for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dplatsmp.c2 * plat smp support for CSR Marco dual-core SMP SoCs
4 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dpm.c2 * power management entry for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/include/linux/
H A Drio_regs.h105 #define RIO_MBOX_CSR 0x40 /* [II, <= 1.2] Mailbox CSR */
131 #define RIO_WRITE_PORT_CSR 0x44 /* [I, <= 1.2] Write Port CSR */
132 #define RIO_DOORBELL_CSR 0x44 /* [II, <= 1.2] Doorbell CSR */
148 #define RIO_PELL_CTRL_CSR 0x4c /* [I] PE Logical Layer Control CSR */
158 #define RIO_DID_CSR 0x60 /* [III] Base Device ID CSR */
162 #define RIO_HOST_DID_LOCK_CSR 0x68 /* [III] Host Base Device ID Lock CSR */
163 #define RIO_COMPONENT_TAG_CSR 0x6c /* [III] Component Tag CSR */
268 #define RIO_EM_LTL_ERR_DETECT 0x008 /* Logical/Transport Layer Error Detect CSR */
269 #define RIO_EM_LTL_ERR_EN 0x00c /* Logical/Transport Layer Error Enable CSR */
274 #define RIO_EM_LTL_HIADDR_CAP 0x010 /* Logical/Transport Layer High Address Capture CSR */
275 #define RIO_EM_LTL_ADDR_CAP 0x014 /* Logical/Transport Layer Address Capture CSR */
276 #define RIO_EM_LTL_DEVID_CAP 0x018 /* Logical/Transport Layer Device ID Capture CSR */
277 #define RIO_EM_LTL_CTRL_CAP 0x01c /* Logical/Transport Layer Control Capture CSR */
278 #define RIO_EM_PW_TGT_DEVID 0x028 /* Port-write Target deviceID CSR */
279 #define RIO_EM_PKT_TTL 0x02c /* Packet Time-to-live CSR */
283 #define RIO_EM_PN_ERR_DETECT(x) (0x040 + x*0x40) /* Port N Error Detect CSR */
286 #define RIO_EM_PN_ERRRATE_EN(x) (0x044 + x*0x40) /* Port N Error Rate Enable CSR */
287 #define RIO_EM_PN_ATTRIB_CAP(x) (0x048 + x*0x40) /* Port N Attributes Capture CSR */
288 #define RIO_EM_PN_PKT_CAP_0(x) (0x04c + x*0x40) /* Port N Packet/Control Symbol Capture 0 CSR */
289 #define RIO_EM_PN_PKT_CAP_1(x) (0x050 + x*0x40) /* Port N Packet Capture 1 CSR */
290 #define RIO_EM_PN_PKT_CAP_2(x) (0x054 + x*0x40) /* Port N Packet Capture 2 CSR */
291 #define RIO_EM_PN_PKT_CAP_3(x) (0x058 + x*0x40) /* Port N Packet Capture 3 CSR */
292 #define RIO_EM_PN_ERRRATE(x) (0x068 + x*0x40) /* Port N Error Rate CSR */
293 #define RIO_EM_PN_ERRRATE_TR(x) (0x06c + x*0x40) /* Port N Error Rate Threshold CSR */
H A Drio.h76 * A component tag value (stored in the component tag CSR) is used as device's
403 u32 comptag; /* Component Tag CSR */
404 u32 errdetect; /* Port N Error Detect CSR */
406 u32 ltlerrdet; /* LTL Error Detect CSR */
H A Dstmmac.h35 /* Define the macros for CSR clock range parameters to be passed by
H A Domap-dma.h155 CSDP, CCR, CICR, CSR, enumerator in enum:omap_reg_offsets
H A Dfsl_ifc.h260 * Clock Status Register (CSR)
/linux-4.1.27/arch/alpha/include/asm/
H A Dcore_t2.h213 unsigned long elcmc_bcc; /* CSR 0 */
214 unsigned long elcmc_bcce; /* CSR 1 */
215 unsigned long elcmc_bccea; /* CSR 2 */
216 unsigned long elcmc_bcue; /* CSR 3 */
217 unsigned long elcmc_bcuea; /* CSR 4 */
218 unsigned long elcmc_dter; /* CSR 5 */
219 unsigned long elcmc_cbctl; /* CSR 6 */
220 unsigned long elcmc_cbe; /* CSR 7 */
221 unsigned long elcmc_cbeal; /* CSR 8 */
222 unsigned long elcmc_cbeah; /* CSR 9 */
223 unsigned long elcmc_pmbx; /* CSR 10 */
224 unsigned long elcmc_ipir; /* CSR 11 */
225 unsigned long elcmc_sic; /* CSR 12 */
226 unsigned long elcmc_adlk; /* CSR 13 */
227 unsigned long elcmc_madrl; /* CSR 14 */
228 unsigned long elcmc_crrev4; /* CSR 15 */
257 unsigned long elco_bcc; /* CSR 0 */
258 unsigned long elco_bcce; /* CSR 1 */
259 unsigned long elco_bccea; /* CSR 2 */
260 unsigned long elco_bcue; /* CSR 3 */
261 unsigned long elco_bcuea; /* CSR 4 */
262 unsigned long elco_dter; /* CSR 5 */
263 unsigned long elco_cbctl; /* CSR 6 */
264 unsigned long elco_cbe; /* CSR 7 */
265 unsigned long elco_cbeal; /* CSR 8 */
266 unsigned long elco_cbeah; /* CSR 9 */
267 unsigned long elco_pmbx; /* CSR 10 */
268 unsigned long elco_ipir; /* CSR 11 */
269 unsigned long elco_sic; /* CSR 12 */
270 unsigned long elco_adlk; /* CSR 13 */
271 unsigned long elco_madrl; /* CSR 14 */
272 unsigned long elco_crrev4; /* CSR 15 */
410 * and use the HAE_MEM CSR to provide some bits of the address.
432 * HHH = 31:29 HAE_MEM CSR
H A Dcore_mcpcia.h222 * and use the HAE_MEM CSR to provide some bits of the address.
244 * HHH = 31:29 HAE_MEM CSR
H A Dcore_cia.h314 * and use the HAE_MEM CSR to provide some bits of the address.
336 * HHH = 31:29 HAE_MEM CSR
H A Dcore_irongate.h28 * Irongate CSR map. Some of the CSRs are 8 or 16 bits, but all access
H A Dcore_marvel.h50 * EV7 CSR addressing macros
/linux-4.1.27/arch/mips/include/asm/dec/
H A Dkn02.h60 #define KN02_CPU_INR_CASCADE 2 /* CSR cascade */
63 * CSR interrupt bits.
75 #define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */
76 #define KN02_IRQ_LINES 8 /* number of CSR interrupts */
H A Dinterrupts.h25 #define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */
/linux-4.1.27/arch/arm/include/debug/
H A Dsirf.S4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/arch/x86/include/asm/numachip/
H A Dnumachip_csr.h28 /* 32K CSR space, b15 indicates geo/non-geo */
31 /* Global CSR space covers all 4K possible nodes with 64K CSR space per node */
37 * Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
/linux-4.1.27/arch/c6x/include/asm/
H A Dirqflags.h23 asm volatile (" mvc .s2 CSR,%0\n" : "=b"(flags)); arch_local_save_flags()
30 asm volatile (" mvc .s2 %0,CSR\n" : : "b"(flags) : "memory"); arch_local_irq_restore()
/linux-4.1.27/drivers/net/ethernet/sfc/
H A Dio.h103 /* Write a normal 128-bit CSR, locking as appropriate. */ efx_writeo()
149 /* Write a 32-bit CSR or the last dword of a special 128-bit CSR */ efx_writed()
161 /* Read a 128-bit CSR, locking as appropriate. */ efx_reado()
200 /* Read a 32-bit CSR or SRAM */ efx_readd()
210 /* Write a 128-bit CSR forming part of a table */
218 /* Read a 128-bit CSR forming part of a table */ efx_reado_table()
258 /* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
278 /* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
/linux-4.1.27/arch/mips/kernel/
H A Dsignal-common.h27 /* Check and clear pending FPU exceptions in saved CSR */
/linux-4.1.27/drivers/irqchip/
H A Dirq-sirfsoc.c2 * interrupt controller support for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/drivers/pinctrl/sirf/
H A Dpinctrl-sirf.h2 * pinmux driver shared headfile for CSR SiRFsoc
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dpinctrl-atlas6.c2 * pinctrl pads, groups, functions for CSR SiRFatlasVI
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
H A Dpinctrl-prima2.c2 * pinctrl pads, groups, functions for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
H A Dpinctrl-sirf.c2 * pinmux driver for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
/linux-4.1.27/arch/c6x/kernel/
H A Dhead.S45 MVC .S2 CSR,B2
47 MVC .S2 B2,CSR
H A Dprocess.c45 asm volatile (" mvc .s2 CSR,%0\n" arch_cpu_idle()
47 " mvc .s2 %0,CSR\n" arch_cpu_idle()
H A Dentry.S31 MVC .S2 CSR,reg
33 MVC .S2 reg,CSR
37 MVC .S2 CSR,reg
39 MVC .S2 reg,CSR
77 || MVC .S2 CSR,B12
114 STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
130 LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
170 || MVC .S2 B12,CSR
248 MVC .S2 CSR,B1
250 MVC .S2 B1,CSR ; enable ints
H A Dptrace.c80 /* Don't copyin TSR or CSR */ gpr_set()
H A Dsetup.c117 csr = get_creg(CSR); get_cpuinfo()
/linux-4.1.27/drivers/clk/
H A Dclk-xgene.c174 pr_err("Unable to map CSR register for %s\n", np->full_name); xgene_pllclk_init()
200 void __iomem *csr_reg; /* CSR for IP clock */
201 u32 reg_clk_offset; /* Offset to clock enable CSR */
203 u32 reg_csr_offset; /* Offset to CSR reset */
204 u32 reg_csr_mask; /* Mask bit for disable CSR reset */
205 void __iomem *divider_reg; /* CSR for divider */
242 /* Second enable the CSR */ xgene_clk_enable()
248 pr_debug("%s CSR RESET PADDR base 0x%016LX csr offset 0x%08X mask 0x%08X value 0x%08X\n", xgene_clk_enable()
271 /* First put the CSR in reset */ xgene_clk_disable()
/linux-4.1.27/drivers/dma/
H A Dtxx9dmac.c291 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", txx9dmac_dump_regs()
299 channel64_readl(dc, CSR)); txx9dmac_dump_regs()
303 " SAIR: %#x DAIR: %#x CCR: %#x CSR: %#x\n", txx9dmac_dump_regs()
311 channel32_readl(dc, CSR)); txx9dmac_dump_regs()
343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { txx9dmac_dostart()
353 channel64_writel(dc, CSR, 0xffffffff); txx9dmac_dostart()
374 channel32_writel(dc, CSR, 0xffffffff); txx9dmac_dostart()
487 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); txx9dmac_dump_desc()
500 d->SAIR, d->DAIR, d->CCR, d->CSR); txx9dmac_dump_desc()
526 channel_writel(dc, CSR, errors); txx9dmac_handle_error()
552 csr = channel64_readl(dc, CSR); txx9dmac_scan_descriptors()
553 channel64_writel(dc, CSR, csr); txx9dmac_scan_descriptors()
556 csr = channel32_readl(dc, CSR); txx9dmac_scan_descriptors()
557 channel32_writel(dc, CSR, csr); txx9dmac_scan_descriptors()
618 csr = channel_readl(dc, CSR); txx9dmac_chan_tasklet()
636 channel_readl(dc, CSR)); txx9dmac_chan_interrupt()
663 csr = channel_readl(dc, CSR); txx9dmac_tasklet()
961 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) && txx9dmac_chain_dynamic()
1002 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { txx9dmac_alloc_chan_resources()
1064 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT); txx9dmac_free_chan_resources()
H A Dtxx9dmac.h81 TXX9_DMA_REG32(CSR); /* Channel Status Register */
91 u32 CSR; member in struct:txx9dmac_cregs32
H A Domap-dma.c257 omap_dma_chan_read(c, CSR); omap_dma_clear_csr()
259 omap_dma_chan_write(c, CSR, ~0); omap_dma_clear_csr()
264 unsigned val = omap_dma_chan_read(c, CSR); omap_dma_get_csr()
267 omap_dma_chan_write(c, CSR, val); omap_dma_get_csr()
H A Dsirf-dma.c2 * DMA controller driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/drivers/mmc/host/
H A Dsdhci-sirf.c4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
34 * CSR atlas7 and prima2 SD host version is not 3.0 sdhci_sirf_set_bus_width()
35 * 8bit-width enable bit of CSR SD hosts is 3, sdhci_sirf_set_bus_width()
H A Dushc.c552 /* CSR USB SD Host Controller */
/linux-4.1.27/drivers/mtd/devices/
H A Dms02-nv.h21 * 0x400000 - 0x7fffff CSR
53 * The state of the battery as provided by the CSR is reflected on
66 /* MS02-NV CSR status bits. */
/linux-4.1.27/drivers/net/ethernet/altera/
H A Daltera_msgdmahw.h101 /* mSGDMA CSR status register bit definitions
127 /* mSGDMA CSR control register bit definitions
136 /* mSGDMA CSR fill level bits
/linux-4.1.27/drivers/scsi/aacraid/
H A Daacraid.h718 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
719 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR))
720 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR))
721 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR))
780 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR))
781 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR))
782 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR))
783 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR))
798 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR))
799 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR))
800 #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR))
801 #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR))
841 #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR))
842 #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR))
843 #define src_writeb(AEP, CSR, value) writeb(value, \
844 &((AEP)->regs.src.bar0->CSR))
845 #define src_writel(AEP, CSR, value) writel(value, \
846 &((AEP)->regs.src.bar0->CSR))
/linux-4.1.27/drivers/clk/sirf/
H A Dclk-atlas6.c2 * Clock tree for CSR SiRFatlasVI
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
H A Dclk-prima2.c2 * Clock tree for CSR SiRFprimaII
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
H A Dclk-common.c4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
/linux-4.1.27/drivers/block/
H A Dumem.h18 /* CSR register definition */
95 (31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
H A Dumem.c844 "CSR 0x%08lx -> 0x%p (0x%lx)\n", mm_pci_probe()
/linux-4.1.27/arch/mips/dec/
H A Dkn02-irq.c57 .name = "KN02-CSR",
H A Dsetup.c76 * SERIAL0 CPU CPU CSR ASIC ASIC ASIC
78 * SCSI CPU CPU CSR ASIC ASIC ASIC
79 * ETHERNET CPU * CSR ASIC ASIC ASIC
81 * TC2 - - CSR CPU ASIC ASIC
82 * TC1 - - CSR CPU ASIC ASIC
83 * TC0 - - CSR CPU ASIC ASIC
408 /* KN02 CSR IRQ priorities. */ dec_init_kn02()
/linux-4.1.27/arch/powerpc/platforms/82xx/
H A Dpq2ads.h32 /* Things of interest in the CSR.
/linux-4.1.27/sound/soc/sirf/
H A Dsirf-audio-port.c4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dsirf-audio.c4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dsirf-usp.c4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dsirf-usp.h4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/sound/soc/codecs/
H A Dsirf-audio-codec.h4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dsirf-audio-codec.c4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/drivers/net/wireless/iwlegacy/
H A Dcsr.h66 * CSR (control and status registers)
68 * CSR registers are mapped directly into PCI bus space, and are accessible
78 * the CSR registers.
142 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
258 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
306 /* CSR GIO */
/linux-4.1.27/drivers/vme/bridges/
H A Dvme_tsi148.h89 * CR/CSR - Subset of Configuration ROM /
388 * Inbound Translation CR/CSR
525 * CR/CSR
529 * CR/CSR CRG
692 #define TSI148_LCSR_OTAT_AMODE_CRCSR (5<<0) /* CR/CSR Address Space */
938 * CR/CSR Offset Lower Register CRG + $41C
943 * CR/CSR Attribute register CRG + $420
945 #define TSI148_LCSR_CRAT_EN (1<<7) /* Enable access to CR/CSR */
1304 #define TSI148_LCSR_DSAT_AMODE_CRCSR (5<<0) /* CR/CSR */
1384 * CR/CSR Register Group
1388 * CR/CSR Bit Clear Register CRG + $FF4
1397 * CR/CSR Bit Set Register CRG+$FF8
1406 * CR/CSR Base Address Register CRG + FFC
H A Dvme_tsi148.c1408 * own registers as mapped into CR/CSR space. tsi148_master_write()
2251 * Configure CR/CSR space
2253 * Access to the CR/CSR can be configured at power-up. The location of the
2254 * CR/CSR registers in the CR/CSR address space is determined by the boards
2272 /* Allocate mem for CR/CSR image */ tsi148_crcsr_init()
2277 "CR/CSR image\n"); tsi148_crcsr_init()
2286 /* Ensure that the CR/CSR is configured at the correct offset */ tsi148_crcsr_init()
2294 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n"); tsi148_crcsr_init()
2297 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); tsi148_crcsr_init()
2301 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); tsi148_crcsr_init()
2303 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); tsi148_crcsr_init()
2309 * over the CR/CSR registers. We read from here to safely flush tsi148_crcsr_init()
2333 /* Turn off CR/CSR space */ tsi148_crcsr_exit()
2428 * We need to do this safely, thus we read the devices own CR/CSR tsi148_probe()
2429 * register. To do this we must set up a window in CR/CSR space and tsi148_probe()
2584 dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); tsi148_probe()
H A Dvme_ca91cx42.c1528 * Configure CR/CSR space
1530 * Access to the CR/CSR can be configured at power-up. The location of the
1531 * CR/CSR registers in the CR/CSR address space is determined by the boards
1546 /* Write CSR Base Address if slot ID is supplied as a module param */ ca91cx42_crcsr_init()
1550 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot); ca91cx42_crcsr_init()
1553 "CR/CSR space\n"); ca91cx42_crcsr_init()
1557 /* Allocate mem for CR/CSR image */ ca91cx42_crcsr_init()
1561 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " ca91cx42_crcsr_init()
1584 /* Turn off CR/CSR space */ ca91cx42_crcsr_exit()
1799 dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); ca91cx42_probe()
/linux-4.1.27/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac100_dma.c93 pr_debug("DWMAC 100 DMA CSR\n"); dwmac100_dump_dma_regs()
95 pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i, dwmac100_dump_dma_regs()
H A Ddwmac100.h34 /* MAC CSR offset */
H A Ddwmac100_core.c51 "\t DWMAC 100 CSR (base addr = 0x%p)\n" dwmac100_dump_mac_regs()
H A Dcommon.h142 /* CSR Frequency Access Defines*/
H A Dstmmac_main.c158 * this means that the CSR Clock Range selection cannot be
2848 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", stmmac_dvr_probe()
2927 * this means that the CSR Clock Range selection cannot be stmmac_dvr_probe()
/linux-4.1.27/drivers/net/wireless/iwlwifi/
H A Diwl-csr.h68 * CSR (control and status registers)
70 * CSR registers are mapped directly into PCI bus space, and are accessible
80 * the CSR registers.
146 * CSR HW resources monitor registers
153 * CSR Hardware Revision Workaround Register. Indicates hardware rev;
268 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
361 /* CSR GIO */
516 * CSR values
H A Diwl-eeprom-read.c219 * CSR auto clock gate disable bit - iwl_init_otp_access()
/linux-4.1.27/drivers/input/misc/
H A Dsirfsoc-onkey.c4 * Copyright (c) 2013 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
215 MODULE_DESCRIPTION("CSR Prima2 PWRC Driver");
/linux-4.1.27/drivers/clocksource/
H A Dtimer-prima2.c2 * System timer for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dtimer-atlas7.c2 * System timer for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/drivers/watchdog/
H A Dsirfsoc_wdt.c2 * Watchdog driver for CSR SiRFprimaII and SiRFatlasVI
4 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/arch/arm/mach-tegra/
H A Dplatsmp.c68 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ tegra20_boot_secondary()
137 flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ tegra30_boot_secondary()
H A Dsleep-tegra30.S170 add r1, r1, r12 @ virtual CSR address for this CPU
195 ldr r3, [r1] @ read CSR
196 str r3, [r1] @ clear CSR
/linux-4.1.27/arch/ia64/kernel/
H A Dacpi-ext.c23 * describe the location and size of CSR space.
/linux-4.1.27/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h18 * 0xfe000000 0x42000000 1MB CSR
/linux-4.1.27/arch/arm/plat-omap/
H A Ddma.c493 /* Clear CSR */ omap_enable_channel_irq()
495 p->dma_read(CSR, lch); omap_enable_channel_irq()
497 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); omap_enable_channel_irq()
507 /* Clear CSR */ omap_disable_channel_irq()
509 p->dma_read(CSR, lch); omap_disable_channel_irq()
511 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); omap_disable_channel_irq()
1095 csr = p->dma_read(CSR, ch); omap1_dma_handle_ch()
1103 pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n", omap1_dma_handle_ch()
1147 u32 status = p->dma_read(CSR, ch); omap2_dma_handle_ch()
1183 p->dma_write(status, CSR, ch); omap2_dma_handle_ch()
1202 status = p->dma_read(CSR, ch); omap2_dma_handle_ch()
1203 p->dma_write(status, CSR, ch); omap2_dma_handle_ch()
/linux-4.1.27/drivers/usb/gadget/udc/
H A Damd5536udc.h50 /* Global CSR's -------------------------------------------------------------*/
200 /* Endpoint-specific CSR's --------------------------------------------------*/
354 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
380 /* UDC CSR's */
390 /* AHB subsystem CSR registers */
H A Damd5536udc.c354 /* ep ix in UDC CSR register space */ udc_ep_enable()
377 /* ep ix in UDC CSR register space */ udc_ep_enable()
380 /* set max packet size UDC CSR */ udc_ep_enable()
1484 /* enable dynamic CSR programming */ udc_basic_init()
1852 /* set max packet size of EP0 in UDC CSR */ activate_control_endpoints()
2766 /* ep ix in UDC CSR register space */
2772 /* ep ix in UDC CSR register space */
2819 /* ep ix in UDC CSR register space */
2825 /* ep ix in UDC CSR register space */
2829 /* UDC CSR reg */
H A Dpch_udc.c492 * @val: value to be written to CSR register
493 * @addr: address of CSR register
508 * @addr: address of CSR register
510 * Return codes: content of CSR register
783 * CSR done field (bit 13)
1080 /* enable dynamic CSR programmingi, self powered and device speed */ pch_udc_init()
H A Dat91_udc.c286 * Endpoint FIFO CSR bits have a mix of bits, making it unsafe to just write
368 * CSR returns bad RXCOUNT when read too soon after updating read_fifo()
/linux-4.1.27/drivers/net/ethernet/qlogic/qlge/
H A Dqlge_mpi.c8 tmp = ql_read32(qdev, CSR); ql_unpause_mpi_risc()
12 ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); ql_unpause_mpi_risc()
22 ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE); ql_pause_mpi_risc()
24 tmp = ql_read32(qdev, CSR); ql_pause_mpi_risc()
39 ql_write32(qdev, CSR, CSR_CMD_SET_RST); ql_hard_reset_mpi_risc()
41 tmp = ql_read32(qdev, CSR); ql_hard_reset_mpi_risc()
43 ql_write32(qdev, CSR, CSR_CMD_CLR_RST); ql_hard_reset_mpi_risc()
174 if (ql_read32(qdev, CSR) & CSR_HRI) ql_exec_mb_cmd()
193 ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); ql_exec_mb_cmd()
516 ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); ql_mpi_handler()
596 ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); ql_mailbox_command()
H A Dqlge.h197 * Host Command Status Register (CSR) bit definitions.
803 CSR = 0x14, enumerator in enum:__anon7236
H A Dqlge_dbg.c1489 DUMP_REG(qdev, CSR); ql_dump_regs()
/linux-4.1.27/drivers/ata/
H A Dahci_xgene.c39 /* MUX CSR */
43 /* SATA core host controller CSR */
54 /* SATA host AHCI CSR */
77 /* SATA host controller AXI CSR */
80 /* SATA diagnostic CSR */
92 void __iomem *csr_core; /* Core CSR address of IP */
93 void __iomem *csr_diag; /* Diag CSR address of IP */
94 void __iomem *csr_axi; /* AXI CSR address of IP */
95 void __iomem *csr_mux; /* MUX CSR address of IP */
411 /* As hardreset resets these CSR, save it to restore later */ xgene_ahci_hardreset()
/linux-4.1.27/drivers/net/ethernet/dec/tulip/
H A Dpnic2.c23 * CSR 6 (mask = 0xfe3bd1fd of bits not to change)
35 * CSR 14 (mask = 0xfff0ee39 of bits not to change)
48 * CSR 12
H A Dde4x5.h14 ** DC21040 CSR<1..15> Register Address Map
692 #define SICR_CAC 0x00000004 /* CSR Auto Configuration */
H A Dde2104x.c1852 * and if any custom CSR values are provided de21041_get_srom_info()
2040 /* remap CSR registers */ de_init_one()
/linux-4.1.27/drivers/pci/hotplug/
H A Dcpci_hotplug.h35 /* PICMG 2.1 R2.0 HS CSR bits: */
/linux-4.1.27/arch/powerpc/include/asm/
H A Dtsi108.h38 /* Offsets within Tsi108(A) CSR space for individual blocks */
/linux-4.1.27/drivers/crypto/qat/qat_common/
H A Dadf_accel_devices.h169 /* CSR write macro */
173 /* CSR read macro */
H A Dqat_hal.c130 pr_err("QAT: Read CSR timeout\n"); qat_hal_rd_ae_csr()
146 pr_err("QAT: Write CSR Timeout\n"); qat_hal_wr_ae_csr()
/linux-4.1.27/drivers/tty/serial/
H A Dsirfsoc_uart.h2 * Drivers for CSR SiRFprimaII onboard UARTs.
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dsirfsoc_uart.c2 * Driver for CSR SiRFprimaII onboard UARTs.
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
1530 MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
H A Datmel_serial.c1537 /* TODO: All reads to CSR will clear these interrupts! */ atmel_tasklet_func()
1799 /* Save current CSR for comparison in atmel_tasklet_func() */ atmel_startup()
/linux-4.1.27/arch/frv/include/asm/
H A Dmb-regs.h62 #define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
150 #define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
/linux-4.1.27/arch/arm/mach-omap1/
H A Ddma.c62 [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT },
222 l = dma_read(CSR, lch); omap1_clear_dma()
/linux-4.1.27/arch/mips/include/asm/octeon/
H A Dcvmx-pip.h282 /* CSR typedefs have been moved to cvmx-csr-*.h */
302 * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
304 * the preferred upgrade path is to use the CSR directly.
H A Dcvmx-fpa.h96 /* CSR typedefs have been moved to cvmx-csr-*.h */
139 * Enable the FPA for use. Must be performed after any CSR
H A Dcvmx-ipd.h51 /* CSR typedefs have been moved to cvmx-csr-*.h */
H A Dcvmx-spi.h37 /* CSR typedefs have been moved to cvmx-csr-*.h */
H A Docteon.h248 /* R/W If set, the (mem) CSR clock never turns off. */
H A Dcvmx.h407 * is common in code to need to wait for a specific field in a CSR
H A Dcvmx-cmd-queue.h42 * unit specific validation and CSR writes to submit the
H A Dcvmx-pko.h266 /* CSR typedefs have been moved to cvmx-csr-*.h */
H A Dcvmx-pow.h462 * (except CSR reads)
1248 /* CSR typedefs have been moved to cvmx-csr-*.h */
/linux-4.1.27/drivers/i2c/busses/
H A Di2c-sibyte.c29 void *reg_base; /* CSR base */
H A Di2c-sirf.c2 * I2C bus driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Di2c-octeon.c81 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
102 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
/linux-4.1.27/drivers/net/wireless/iwlwifi/dvm/
H A Dtt.h100 * @ct_kill_toggle: used to toggle the CSR bit when checking uCode temperature
/linux-4.1.27/arch/sparc/include/asm/
H A Dobio.h15 /* CSR space (for each XDBUS)
/linux-4.1.27/drivers/gpu/drm/via/
H A Dvia_dmablit.h130 /* CSR */
/linux-4.1.27/drivers/vme/
H A Dvme_bridge.h159 /* CR/CSR space functions */
/linux-4.1.27/arch/m68k/include/asm/
H A Dmcfwdebug.h65 /* And some definitions for the writable sections of the CSR */
/linux-4.1.27/drivers/rapidio/switches/
H A Didt_gen2.c229 /* Set Port-Write info CSR: PRIO=3 and CRF=1 */ idtg2_em_init()
343 /* Clear implementation specific address capture CSR */ idtg2_em_handler()
/linux-4.1.27/drivers/regulator/
H A Dbcm590xx-regulator.c126 /* DCDC group CSR: supported voltages in microvolts */
299 BCM590XX_MATCH(csr, CSR),
/linux-4.1.27/drivers/net/wan/
H A Dwanxlfw.S694 movel #CSRA, %a0 // A0 = CSR address
697 movew (%a0), %d1 // D1 = CSR input bits
737 movew %d1, (%a0) // Write CSR output bits
743 movew (%a0), %d1 // D1 = CSR input bits
748 movew (%a0), %d1 // D1 = CSR input bits
759 addl #2, %a0 // next CSR register
/linux-4.1.27/drivers/scsi/be2iscsi/
H A Dbe_main.h136 * Macros for reading/writing a protection domain or CSR registers
349 u8 __iomem *csr_va; /* CSR */
352 struct be_bus_address csr_pa; /* CSR */
353 struct be_bus_address db_pa; /* CSR */
354 struct be_bus_address pci_pa; /* CSR */
H A Dbe_mgmt.c27 /* UE Status Low CSR */
63 /* UE Status High CSR */
/linux-4.1.27/drivers/rapidio/
H A Drio-scan.c206 * Marks the component tag CSR on each device with the enumeration
500 * Reads the port error status CSR for a particular switch port to
536 * rio_get_host_deviceid_lock- Reads the Host Device ID Lock CSR on a device
540 * Used during enumeration to read the Host Device ID Lock CSR on a
841 * Reads the port error status CSR for the master port to
H A Drio.c995 /* Clear EM Port N Error Detect CSR */ rio_inb_pwrite_handler()
1005 /* Clear EM L/T Layer Error Detect CSR */ rio_inb_pwrite_handler()
/linux-4.1.27/arch/x86/kernel/
H A Dpci-calgary_64.c99 /* CSR (Channel/DMA Status Register) */
841 /* If no error, the agent ID in the CSR is not valid */ calgary_dump_error_regs()
842 pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n", calgary_dump_error_regs()
856 /* dump CSR */ calioc2_dump_error_regs()
871 pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n", calioc2_dump_error_regs()
903 /* If no error, the agent ID in the CSR is not valid */ calgary_watchdog()
/linux-4.1.27/drivers/i2c/algos/
H A Di2c-algo-pcf.c77 "i2c-algo-pcf.o: lost arbitration (CSR 0x%02x)\n", handle_lab()
100 "i2c-algo-pcf.o: reset LAB condition (CSR 0x%02x)\n", handle_lab()
/linux-4.1.27/drivers/phy/
H A Dphy-xgene.c39 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
42 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
43 * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
91 /* SATA Clock/Reset CSR */
104 /* SDS CSR used for PHY Indirect access */
135 /* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */
279 /* PHY lane CSR accessing from SDS indirectly */
547 void __iomem *sds_base; /* PHY CSR base addr */
/linux-4.1.27/drivers/mtd/maps/
H A Dintel_vr_nor.c57 /* Chip Select 0 Timing Register is at offset 0 in CSR */
/linux-4.1.27/drivers/net/wireless/rt2x00/
H A Drt2x00.h813 * csr.base: CSR base register address. (PCI)
814 * csr.cache: CSR cache for usb_control_msg. (USB)
825 * registers require multiple calls to the CSR registers.
827 * field is used for normal CSR access and it cannot support
H A Drt2500usb.h69 * Control/Status Registers(CSR).
H A Drt2x00usb.c88 rt2x00_err(rt2x00dev, "CSR cache not available\n"); rt2x00usb_vendor_req_buff_lock()
H A Drt2400pci.c40 * All access to the CSR registers will go through the methods
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
H A Drt2500usb.c45 * All access to the CSR registers will go through the methods
48 * and use the CSR registers BBPCSR and RFCSR to achieve this.
H A Drt2500pci.c40 * All access to the CSR registers will go through the methods
43 * and use the CSR registers BBPCSR and RFCSR to achieve this.
H A Drt73usb.c46 * All access to the CSR registers will go through the methods
49 * and use the CSR registers BBPCSR and RFCSR to achieve this.
H A Drt2400pci.h58 * Control/Status Registers(CSR).
H A Drt2500pci.h69 * Control/Status Registers(CSR).
H A Drt61pci.h225 * MAC Control/Status Registers(CSR).
H A Drt73usb.h135 * MAC Control/Status Registers(CSR).
/linux-4.1.27/drivers/rtc/
H A Drtc-xgene.c33 /* RTC CSR Registers */
H A Drtc-sirfsoc.c4 * Copyright (c) 2013 Cambridge Silicon Radio Limited, a CSR plc group company.
/linux-4.1.27/drivers/net/wireless/ath/wil6210/
H A Dpcie_bus.c215 dev_info(&pdev->dev, "CSR at %pR -> 0x%p\n", &pdev->resource[0], csr); wil_pcie_probe()
/linux-4.1.27/arch/arm/mach-omap2/
H A Ddma.c62 [CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
/linux-4.1.27/sound/soc/intel/common/
H A Dsst-dsp.h72 /* CSR / CS */
/linux-4.1.27/include/uapi/linux/
H A Dfirewire-cdev.h535 * struct fw_cdev_allocate - Allocate a CSR in an address range
538 * @length: Length of the CSR, in bytes
560 * the start address of the new CSR back in @offset. I.e. @offset is an
561 * in and out parameter. If this automatic placement of a CSR in a bigger
580 * struct fw_cdev_deallocate - Free a CSR address range or isochronous resource
/linux-4.1.27/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x540.c561 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
629 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
/linux-4.1.27/drivers/misc/mei/
H A Dhw-me.c83 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
100 * mei_hcsr_read - Reads 32bit data from the host CSR
/linux-4.1.27/drivers/scsi/lpfc/
H A Dlpfc_sli4.h495 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
501 /* IF type 0, BAR 1 function CSR register memory map */
/linux-4.1.27/drivers/spi/
H A Dspi-sirf.c2 * SPI bus driver for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
H A Dspi-omap-uwire.c71 /* CSR bits */
/linux-4.1.27/arch/mips/cavium-octeon/
H A Docteon-platform.c225 * equipment field in the UPHY CSR octeon2_usb_clocks_start()
234 /* Step 8: Clear the ATE_RESET field in the UPHY CSR. */ octeon2_usb_clocks_start()
H A Dsetup.c551 /* R/W If set, the (mem) CSR clock never turns off. */ octeon_user_io_init()
/linux-4.1.27/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h35 #define SLIPORT_SEMAPHORE_OFFSET_BEx 0xac /* CSR BAR offset */
H A Dbe.h473 u8 __iomem *csr; /* CSR BAR used only for BE2/3 */
/linux-4.1.27/arch/arm/mach-ixp4xx/
H A Dcommon-pci.c377 * Enable CSR window at 64 MiB to allow PCI masters ixp4xx_pci_preinit()
/linux-4.1.27/sound/pci/asihpi/
H A Dhpi6000.c107 /* HPI CSR registers */
108 /* word offsets from CSR base */
481 /* BAR0 - 4K = HPI control and status registers on PCI2040 (HPI CSR) */ create_adapter_obj()
/linux-4.1.27/drivers/net/ethernet/intel/e1000e/
H A Dregs.h66 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */
/linux-4.1.27/drivers/net/wireless/
H A Dadm8211.h13 /* CSR (Host Control and Status Registers) */
/linux-4.1.27/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_common.h29 /* CSR Frequency Access Defines*/
H A Dsxgbe_main.c2180 netdev_warn(ndev, "%s: warning: cannot get CSR clock\n",
2186 * this means that the CSR Clock Range selection cannot be
/linux-4.1.27/drivers/scsi/
H A Dsun3_scsi.c186 // safe bits for the CSR
/linux-4.1.27/drivers/char/agp/
H A Dhp-agp.c490 /* Look for an enclosing IOC scope and find its CSR space */ zx1_gart_probe()
/linux-4.1.27/drivers/hsi/controllers/
H A Domap_ssi.c99 seq_printf(m, "CSR\t\t: 0x%04x\n", ssi_debug_gdd_show()
/linux-4.1.27/arch/arm/mach-pxa/
H A Dcm-x300.c785 /* Libertas and CSR reset */ cm_x300_init_wi2wi()
H A Dstargate2.c162 /* the CSR bluecore chip */
/linux-4.1.27/drivers/net/ethernet/apm/xgene/
H A Dxgene_enet_main.c892 dev_err(dev, "Unable to retrieve ENET Port CSR region\n"); xgene_enet_get_resources()
904 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n"); xgene_enet_get_resources()
/linux-4.1.27/drivers/bluetooth/
H A Dbtusb.c161 /* CSR BlueCore devices */
287 /* CSR BlueCore Bluetooth Sniffer */
1369 * early Bluetooth 1.1 device from CSR. btusb_setup_csr()
1373 /* These fake CSR controllers have all a broken btusb_setup_csr()
3238 /* Fake CSR devices with broken commands */ btusb_probe()
/linux-4.1.27/drivers/net/wireless/iwlwifi/pcie/
H A Dtrans.c392 /* Enable LP XTAL by indirect access through CSR */ iwl_pcie_apm_lp_xtal_enable()
1763 IWL_ERR(trans, "CSR values:\n"); iwl_pcie_dump_csr()
2241 /* CSR registers */ iwl_trans_pcie_dump_data()
/linux-4.1.27/drivers/mmc/core/
H A Dmmc_ops.c321 * The spec states that CSR and CID accesses have a timeout mmc_send_cxd_data()
/linux-4.1.27/drivers/net/can/sja1000/
H A Dpeak_pcmcia.c95 /* CSR bits */
/linux-4.1.27/drivers/net/ethernet/amd/
H A D7990.c114 /* Load the CSR registers. The LANCE has to be STOPped when we do this! */ load_csrs()
H A Da2065.c130 /* Load the CSR registers */ load_csrs()
H A Dsunlance.c298 /* Load the CSR registers */ load_csrs()
1149 /* Read back CSR to invalidate the E-Cache. lance_start_xmit()
H A Ddeclance.c300 /* Load the CSR registers */ load_csrs()
H A Dpcnet32.c1721 /* read PROM address and compare with CSR address */ pcnet32_probe1()
1729 pr_cont(" warning: CSR address invalid,\n"); pcnet32_probe1()
/linux-4.1.27/drivers/net/ethernet/intel/
H A De100.c58 * shared-memory structure, the Control/Status Registers (CSR). All
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
287 /* CSR (Control/Status Registers) */
/linux-4.1.27/arch/x86/include/asm/uv/
H A Duv_hub.h96 * s = bits that are in the SOCKET_ID CSR
/linux-4.1.27/drivers/pnp/pnpacpi/
H A Drsparser.c127 * describe the location and size of CSR space.
/linux-4.1.27/arch/arm/mach-ixp4xx/include/mach/
H A Dixp4xx-regs.h347 /* CSR bit definitions */
/linux-4.1.27/sound/firewire/bebob/
H A Dbebob_stream.c188 * If source of clock is internal CSR, Music Sub Unit Sync Input is snd_bebob_stream_check_internal_clock()
/linux-4.1.27/sound/soc/intel/haswell/
H A Dsst-haswell-dsp.c352 /* Stall and reset core, set CSR */ hsw_set_dsp_D0()
/linux-4.1.27/drivers/net/ethernet/broadcom/
H A Dsb1250-mac.c1095 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) sbdma_rx_process()
1259 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) sbdma_tx_process()
/linux-4.1.27/drivers/usb/musb/
H A Dmusb_gadget.c308 /* setup DMA, then program endpoint CSR */ txstate()
370 /* program endpoint CSR first, then setup DMA */ txstate()
H A Dmusb_host.c550 * when we do, use tx/rx reinit routine and then construct a new CSR
1383 "CSR %04x\n", tx_csr); musb_host_tx()
/linux-4.1.27/drivers/net/ethernet/agere/
H A Det131x.h275 * CSR
/linux-4.1.27/drivers/net/ethernet/intel/igb/
H A De1000_defines.h619 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */
/linux-4.1.27/drivers/net/wireless/iwlwifi/mvm/
H A Dops.c170 * TODO: Bits 7-8 of CSR in 8000 HW family set the ADC sampling, and iwl_mvm_nic_config()
/linux-4.1.27/drivers/sbus/char/
H A Denvctrl.c236 /* CSR 0 means acknowledged. */ envctrl_i2c_read_addr()
/linux-4.1.27/drivers/staging/octeon-usb/
H A Docteon-hcd.c364 * usbcx_hprt: Stored port status so we don't need to read a CSR to
420 * This macro logically sets a single field in a CSR. It does the sequence
550 * Read a USB 32bit CSR. It performs the necessary address swizzle
568 * Write a USB 32bit CSR. It performs the necessary address
H A Docteon-hcd.h691 * * CSR control bits used by the AHB clock domain state
704 * * Clears the interrupts and all the CSR registers except the
/linux-4.1.27/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper.c930 /* Return CSR configs to saved values */ __cvmx_helper_errata_fix_ipd_ptr_alignment()
/linux-4.1.27/include/uapi/scsi/fc/
H A Dfc_els.h147 [ELS_CSR] = "CSR", \
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Datombios.h3020 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default
3021 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback
3022 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications
4926 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
4927 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
4928 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
5152 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default
5153 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback.
5154 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications.
/linux-4.1.27/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c1141 /* Clear the Tx CSR's in case this is a restart */ xemaclite_of_probe()
/linux-4.1.27/drivers/net/fddi/
H A Ddefxx.h1475 /* Define TC PDQ CSR offset and length */

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