1/*
2 * Copyright (C) 2005 - 2014 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.  The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18/********* Mailbox door bell *************/
19/* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
26 * queue entry.
27 */
28#define MPU_MAILBOX_DB_OFFSET	0x160
29#define MPU_MAILBOX_DB_RDY_MASK	0x1 	/* bit 0 */
30#define MPU_MAILBOX_DB_HI_MASK	0x2	/* bit 1 */
31
32#define MPU_EP_CONTROL 		0
33
34/********** MPU semphore: used for SH & BE  *************/
35#define SLIPORT_SEMAPHORE_OFFSET_BEx		0xac  /* CSR BAR offset */
36#define SLIPORT_SEMAPHORE_OFFSET_SH		0x94  /* PCI-CFG offset */
37#define POST_STAGE_MASK				0x0000FFFF
38#define POST_ERR_MASK				0x1
39#define POST_ERR_SHIFT				31
40
41/* MPU semphore POST stage values */
42#define POST_STAGE_AWAITING_HOST_RDY 	0x1 /* FW awaiting goahead from host */
43#define POST_STAGE_HOST_RDY 		0x2 /* Host has given go-ahed to FW */
44#define POST_STAGE_BE_RESET		0x3 /* Host wants to reset chip */
45#define POST_STAGE_ARMFW_RDY		0xc000	/* FW is done with POST */
46
47
48/* Lancer SLIPORT registers */
49#define SLIPORT_STATUS_OFFSET		0x404
50#define SLIPORT_CONTROL_OFFSET		0x408
51#define SLIPORT_ERROR1_OFFSET		0x40C
52#define SLIPORT_ERROR2_OFFSET		0x410
53#define PHYSDEV_CONTROL_OFFSET		0x414
54
55#define SLIPORT_STATUS_ERR_MASK		0x80000000
56#define SLIPORT_STATUS_DIP_MASK		0x02000000
57#define SLIPORT_STATUS_RN_MASK		0x01000000
58#define SLIPORT_STATUS_RDY_MASK		0x00800000
59#define SLI_PORT_CONTROL_IP_MASK	0x08000000
60#define PHYSDEV_CONTROL_FW_RESET_MASK	0x00000002
61#define PHYSDEV_CONTROL_DD_MASK		0x00000004
62#define PHYSDEV_CONTROL_INP_MASK	0x40000000
63
64#define SLIPORT_ERROR_NO_RESOURCE1	0x2
65#define SLIPORT_ERROR_NO_RESOURCE2	0x9
66
67#define SLIPORT_ERROR_FW_RESET1		0x2
68#define SLIPORT_ERROR_FW_RESET2		0x0
69
70/********* Memory BAR register ************/
71#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 	0xfc
72/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
73 * Disable" may still globally block interrupts in addition to individual
74 * interrupt masks; a mechanism for the device driver to block all interrupts
75 * atomically without having to arbitrate for the PCI Interrupt Disable bit
76 * with the OS.
77 */
78#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	BIT(29) /* bit 29 */
79
80/********* PCI Function Capability *********/
81#define BE_FUNCTION_CAPS_RSS			0x2
82#define BE_FUNCTION_CAPS_SUPER_NIC		0x40
83
84/********* Power management (WOL) **********/
85#define PCICFG_PM_CONTROL_OFFSET		0x44
86#define PCICFG_PM_CONTROL_MASK			0x108	/* bits 3 & 8 */
87
88/********* Online Control Registers *******/
89#define PCICFG_ONLINE0				0xB0
90#define PCICFG_ONLINE1				0xB4
91
92/********* UE Status and Mask Registers ***/
93#define PCICFG_UE_STATUS_LOW			0xA0
94#define PCICFG_UE_STATUS_HIGH			0xA4
95#define PCICFG_UE_STATUS_LOW_MASK		0xA8
96#define PCICFG_UE_STATUS_HI_MASK		0xAC
97
98/******** SLI_INTF ***********************/
99#define SLI_INTF_REG_OFFSET			0x58
100#define SLI_INTF_VALID_MASK			0xE0000000
101#define SLI_INTF_VALID				0xC0000000
102#define SLI_INTF_HINT2_MASK			0x1F000000
103#define SLI_INTF_HINT2_SHIFT			24
104#define SLI_INTF_HINT1_MASK			0x00FF0000
105#define SLI_INTF_HINT1_SHIFT			16
106#define SLI_INTF_FAMILY_MASK			0x00000F00
107#define SLI_INTF_FAMILY_SHIFT			8
108#define SLI_INTF_IF_TYPE_MASK			0x0000F000
109#define SLI_INTF_IF_TYPE_SHIFT			12
110#define SLI_INTF_REV_MASK			0x000000F0
111#define SLI_INTF_REV_SHIFT			4
112#define SLI_INTF_FT_MASK			0x00000001
113
114#define SLI_INTF_TYPE_2		2
115#define SLI_INTF_TYPE_3		3
116
117/********* ISR0 Register offset **********/
118#define CEV_ISR0_OFFSET 			0xC18
119#define CEV_ISR_SIZE				4
120
121/********* Event Q door bell *************/
122#define DB_EQ_OFFSET			DB_CQ_OFFSET
123#define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
124#define DB_EQ_RING_ID_EXT_MASK		0x3e00  /* bits 9-13 */
125#define DB_EQ_RING_ID_EXT_MASK_SHIFT	(2) /* qid bits 9-13 placing at 11-15 */
126
127/* Clear the interrupt for this eq */
128#define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
129/* Must be 1 */
130#define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
131/* Number of event entries processed */
132#define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
133/* Rearm bit */
134#define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */
135
136/********* Compl Q door bell *************/
137#define DB_CQ_OFFSET 			0x120
138#define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
139#define DB_CQ_RING_ID_EXT_MASK		0x7C00	/* bits 10-14 */
140#define DB_CQ_RING_ID_EXT_MASK_SHIFT	(1)	/* qid bits 10-14
141						 placing at 11-15 */
142
143/* Number of event entries processed */
144#define DB_CQ_NUM_POPPED_SHIFT		(16) 	/* bits 16 - 28 */
145/* Rearm bit */
146#define DB_CQ_REARM_SHIFT		(29) 	/* bit 29 */
147
148/********** TX ULP door bell *************/
149#define DB_TXULP1_OFFSET		0x60
150#define DB_TXULP_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
151/* Number of tx entries posted */
152#define DB_TXULP_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
153#define DB_TXULP_NUM_POSTED_MASK	0x3FFF	/* bits 16 - 29 */
154
155/********** RQ(erx) door bell ************/
156#define DB_RQ_OFFSET 			0x100
157#define DB_RQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
158/* Number of rx frags posted */
159#define DB_RQ_NUM_POSTED_SHIFT		(24)	/* bits 24 - 31 */
160
161/********** MCC door bell ************/
162#define DB_MCCQ_OFFSET 			0x140
163#define DB_MCCQ_RING_ID_MASK		0x7FF	/* bits 0 - 10 */
164/* Number of entries posted */
165#define DB_MCCQ_NUM_POSTED_SHIFT	(16)	/* bits 16 - 29 */
166
167/********** SRIOV VF PCICFG OFFSET ********/
168#define SRIOV_VF_PCICFG_OFFSET		(4096)
169
170/********** FAT TABLE  ********/
171#define RETRIEVE_FAT	0
172#define QUERY_FAT	1
173
174/************* Rx Packet Type Encoding **************/
175#define BE_UNICAST_PACKET		0
176#define BE_MULTICAST_PACKET		1
177#define BE_BROADCAST_PACKET		2
178#define BE_RSVD_PACKET			3
179
180/*
181 * BE descriptors: host memory data structures whose formats
182 * are hardwired in BE silicon.
183 */
184/* Event Queue Descriptor */
185#define EQ_ENTRY_VALID_MASK 		0x1	/* bit 0 */
186#define EQ_ENTRY_RES_ID_MASK 		0xFFFF	/* bits 16 - 31 */
187#define EQ_ENTRY_RES_ID_SHIFT 		16
188
189struct be_eq_entry {
190	u32 evt;
191};
192
193/* TX Queue Descriptor */
194#define ETH_WRB_FRAG_LEN_MASK		0xFFFF
195struct be_eth_wrb {
196	__le32 frag_pa_hi;		/* dword 0 */
197	__le32 frag_pa_lo;		/* dword 1 */
198	u32 rsvd0;			/* dword 2 */
199	__le32 frag_len;		/* dword 3: bits 0 - 15 */
200} __packed;
201
202/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
203 * actual structure is defined as a byte : used to calculate
204 * offset/shift/mask of each field */
205struct amap_eth_hdr_wrb {
206	u8 rsvd0[32];		/* dword 0 */
207	u8 rsvd1[32];		/* dword 1 */
208	u8 complete;		/* dword 2 */
209	u8 event;
210	u8 crc;
211	u8 forward;
212	u8 lso6;
213	u8 mgmt;
214	u8 ipcs;
215	u8 udpcs;
216	u8 tcpcs;
217	u8 lso;
218	u8 vlan;
219	u8 gso[2];
220	u8 num_wrb[5];
221	u8 lso_mss[14];
222	u8 len[16];		/* dword 3 */
223	u8 vlan_tag[16];
224} __packed;
225
226#define TX_HDR_WRB_COMPL		1		/* word 2 */
227#define TX_HDR_WRB_EVT			BIT(1)		/* word 2 */
228#define TX_HDR_WRB_NUM_SHIFT		13		/* word 2: bits 13:17 */
229#define TX_HDR_WRB_NUM_MASK		0x1F		/* word 2: bits 13:17 */
230
231struct be_eth_hdr_wrb {
232	__le32 dw[4];
233};
234
235/********* Tx Compl Status Encoding *********/
236#define BE_TX_COMP_HDR_PARSE_ERR	0x2
237#define BE_TX_COMP_NDMA_ERR		0x3
238#define BE_TX_COMP_ACL_ERR		0x5
239
240#define LANCER_TX_COMP_LSO_ERR			0x1
241#define LANCER_TX_COMP_HSW_DROP_MAC_ERR		0x3
242#define LANCER_TX_COMP_HSW_DROP_VLAN_ERR	0x5
243#define LANCER_TX_COMP_QINQ_ERR			0x7
244#define LANCER_TX_COMP_PARITY_ERR		0xb
245#define LANCER_TX_COMP_DMA_ERR			0xd
246
247/* TX Compl Queue Descriptor */
248
249/* Pseudo amap definition for eth_tx_compl in which each bit of the
250 * actual structure is defined as a byte: used to calculate
251 * offset/shift/mask of each field */
252struct amap_eth_tx_compl {
253	u8 wrb_index[16];	/* dword 0 */
254	u8 ct[2]; 		/* dword 0 */
255	u8 port[2];		/* dword 0 */
256	u8 rsvd0[8];		/* dword 0 */
257	u8 status[4];		/* dword 0 */
258	u8 user_bytes[16];	/* dword 1 */
259	u8 nwh_bytes[8];	/* dword 1 */
260	u8 lso;			/* dword 1 */
261	u8 cast_enc[2];		/* dword 1 */
262	u8 rsvd1[5];		/* dword 1 */
263	u8 rsvd2[32];		/* dword 2 */
264	u8 pkts[16];		/* dword 3 */
265	u8 ringid[11];		/* dword 3 */
266	u8 hash_val[4];		/* dword 3 */
267	u8 valid;		/* dword 3 */
268} __packed;
269
270struct be_eth_tx_compl {
271	u32 dw[4];
272};
273
274/* RX Queue Descriptor */
275struct be_eth_rx_d {
276	u32 fragpa_hi;
277	u32 fragpa_lo;
278};
279
280/* RX Compl Queue Descriptor */
281
282/* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
283 * each bit of the actual structure is defined as a byte: used to calculate
284 * offset/shift/mask of each field */
285struct amap_eth_rx_compl_v0 {
286	u8 vlan_tag[16];	/* dword 0 */
287	u8 pktsize[14];		/* dword 0 */
288	u8 port;		/* dword 0 */
289	u8 ip_opt;		/* dword 0 */
290	u8 err;			/* dword 1 */
291	u8 rsshp;		/* dword 1 */
292	u8 ipf;			/* dword 1 */
293	u8 tcpf;		/* dword 1 */
294	u8 udpf;		/* dword 1 */
295	u8 ipcksm;		/* dword 1 */
296	u8 l4_cksm;		/* dword 1 */
297	u8 ip_version;		/* dword 1 */
298	u8 macdst[6];		/* dword 1 */
299	u8 vtp;			/* dword 1 */
300	u8 ip_frag;		/* dword 1 */
301	u8 fragndx[10];		/* dword 1 */
302	u8 ct[2];		/* dword 1 */
303	u8 sw;			/* dword 1 */
304	u8 numfrags[3];		/* dword 1 */
305	u8 rss_flush;		/* dword 2 */
306	u8 cast_enc[2];		/* dword 2 */
307	u8 qnq;			/* dword 2 */
308	u8 rss_bank;		/* dword 2 */
309	u8 rsvd1[23];		/* dword 2 */
310	u8 lro_pkt;		/* dword 2 */
311	u8 rsvd2[2];		/* dword 2 */
312	u8 valid;		/* dword 2 */
313	u8 rsshash[32];		/* dword 3 */
314} __packed;
315
316/* Pseudo amap definition for BE3 native mode eth_rx_compl in which
317 * each bit of the actual structure is defined as a byte: used to calculate
318 * offset/shift/mask of each field */
319struct amap_eth_rx_compl_v1 {
320	u8 vlan_tag[16];	/* dword 0 */
321	u8 pktsize[14];		/* dword 0 */
322	u8 vtp;			/* dword 0 */
323	u8 ip_opt;		/* dword 0 */
324	u8 err;			/* dword 1 */
325	u8 rsshp;		/* dword 1 */
326	u8 ipf;			/* dword 1 */
327	u8 tcpf;		/* dword 1 */
328	u8 udpf;		/* dword 1 */
329	u8 ipcksm;		/* dword 1 */
330	u8 l4_cksm;		/* dword 1 */
331	u8 ip_version;		/* dword 1 */
332	u8 macdst[7];		/* dword 1 */
333	u8 rsvd0;		/* dword 1 */
334	u8 fragndx[10];		/* dword 1 */
335	u8 ct[2];		/* dword 1 */
336	u8 sw;			/* dword 1 */
337	u8 numfrags[3];		/* dword 1 */
338	u8 rss_flush;		/* dword 2 */
339	u8 cast_enc[2];		/* dword 2 */
340	u8 qnq;			/* dword 2 */
341	u8 rss_bank;		/* dword 2 */
342	u8 port[2];		/* dword 2 */
343	u8 vntagp;		/* dword 2 */
344	u8 header_len[8];	/* dword 2 */
345	u8 header_split[2];	/* dword 2 */
346	u8 rsvd1[12];		/* dword 2 */
347	u8 tunneled;
348	u8 valid;		/* dword 2 */
349	u8 rsshash[32];		/* dword 3 */
350} __packed;
351
352struct be_eth_rx_compl {
353	u32 dw[4];
354};
355