Searched refs:ldr (Results 1 - 200 of 218) sorted by relevance

12

/linux-4.4.14/arch/arm/mach-imx/
H A Dsuspend-imx53.S50 ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
55 ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
58 ldr r5, [r2], #12 /* IOMUXC register offset */
59 ldr r6, [r3, r5] /* current value */
66 ldr r1, [r0, #SUSPEND_INFO_MX53_M4IF_V_OFFSET]
67 ldr r2,[r1, #M4IF_MCR0_OFFSET]
73 ldr r2,[r1, #M4IF_MCR0_OFFSET]
78 ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
83 ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
86 ldr r5, [r2], #4 /* IOMUXC register offset */
87 ldr r6, [r2], #4 /* clear */
88 ldr r7, [r3, r5]
90 ldr r6, [r2], #8 /* set */
105 ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
110 ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
113 ldr r5, [r2], #12 /* IOMUXC register offset */
114 ldr r6, [r2], #4 /* saved value */
121 ldr r1, [r0, #SUSPEND_INFO_MX53_M4IF_V_OFFSET]
122 ldr r2,[r1, #M4IF_MCR0_OFFSET]
128 ldr r2,[r1, #M4IF_MCR0_OFFSET]
H A Dsuspend-imx6.S81 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
87 ldr r6, [r11, #L2X0_CACHE_SYNC]
102 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
103 ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
106 ldr r8, [r7], #0x4
107 ldr r9, [r7], #0x4
120 ldr r7, =MX6Q_MMDC_MPDGCTRL0
121 ldr r6, [r11, r7]
125 ldr r6, [r11, r7]
130 ldr r6, [r11, r7]
134 ldr r6, [r11, r7]
139 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
143 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
148 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
155 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
156 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
157 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
158 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
164 ldr r6, =imx6_suspend
165 ldr r7, =resume
175 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
176 ldr r6, [r11, #0x0]
177 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
178 ldr r6, [r11, #0x0]
179 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
180 ldr r6, [r11, #0x0]
183 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
191 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
196 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
201 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
206 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
210 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
211 ldr r6, =0x0
212 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
213 ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
219 ldr r9, [r8], #0x8
226 ldr r6, =0x1000
227 ldr r9, [r8], #0x8
229 ldr r9, [r8], #0x8
231 ldr r6, =0x80000
232 ldr r9, [r8]
243 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
244 ldr r6, [r11, #MX6Q_GPC_IMR1]
245 ldr r7, [r11, #MX6Q_GPC_IMR2]
246 ldr r8, [r11, #MX6Q_GPC_IMR3]
247 ldr r9, [r11, #MX6Q_GPC_IMR4]
249 ldr r10, =0xffffffff
261 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
262 ldr r10, [r11, #MX6Q_CCM_CCR]
268 ldr r10, [r11, #MX6Q_CCM_CCR]
273 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
289 ldr r6, =2000
323 ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
325 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
330 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
H A Dssi-fiq.S45 ldr r12, .L_imx_ssi_fiq_base
48 ldr r13, .L_imx_ssi_fiq_tx_buffer
51 ldr r11, [r12, #SSI_SIER]
56 ldr r11, [r12, #SSI_SISR]
87 ldr r11, [r12, #SSI_SIER]
92 ldr r11, [r12, #SSI_SISR]
96 ldr r13, .L_imx_ssi_fiq_rx_buffer
104 ldr r11, [r12, #SSI_SACNT]
107 ldr r11, [r12, #SSI_SRX0]
110 ldr r11, [r12, #SSI_SRX0]
116 ldr r11, [r12, #SSI_SRX0]
119 ldr r11, [r12, #SSI_SRX0]
H A Dheadsmp.S21 ldr r1, [r0]
23 ldr r0, [r1]
/linux-4.4.14/arch/arm/mach-exynos/
H A Dsleep.S46 ldr r1, =CPU_MASK
48 ldr r1, =CPU_CORTEX_A9
59 ldr r1, =CPU_MASK
61 ldr r1, =CPU_CORTEX_A9
66 ldr r1, [r0]
67 ldr r1, [r0, r1]
69 ldr r2, [r0]
70 ldr r2, [r0, r2]
76 ldr r2, [r0]
80 ldr r1, [r0, #L2X0_R_PHY_BASE]
85 ldr r2, [r1, #L2X0_CTRL]
89 ldr r1, [r0, #L2X0_R_TAG_LATENCY]
90 ldr r2, [r0, #L2X0_R_DATA_LATENCY]
91 ldr r3, [r0, #L2X0_R_PREFETCH_CTRL]
97 ldr r2, [r0]
100 ldr r1, [r0, #L2X0_R_PWR_CTRL]
101 ldr r2, [r0, #L2X0_R_AUX_CTRL]
H A Dheadsmp.S27 pen: ldr r7, [r6]
H A Dmcpm-exynos.c53 "ldr r4, [%0]\n\t" \
222 __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ exynos_mcpm_setup_entry_point()
/linux-4.4.14/arch/arm/include/debug/
H A Dsirf.S22 ldr \rp, =CONFIG_DEBUG_UART_PHYS @ physical
23 ldr \rv, =CONFIG_DEBUG_UART_VIRT @ virtual
34 1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
H A Dmeson.S17 ldr \rp, =(CONFIG_DEBUG_UART_PHYS) @ physical
18 ldr \rv, =(CONFIG_DEBUG_UART_VIRT) @ virtual
26 1002: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS]
H A Dnetx.S18 ldr \rp, =CONFIG_DEBUG_UART_PHYS
19 ldr \rv, =CONFIG_DEBUG_UART_VIRT
27 1002: ldr \rd, [\rx, #UART_FLAG]
33 1001: ldr \rd, [\rx, #UART_FLAG]
H A Dsamsung.S17 ldr \rd, [\rx, # S3C2410_UFSTAT]
22 ldr \rd, [\rx, # S3C2410_UFSTAT]
30 ldr \rd, [\rx, # S3C2410_UFSTAT]
39 ldr \rd, [\rx, # S3C2410_UFSTAT]
52 ldr \rd, [\rx, # S3C2410_UFCON]
63 ldr \rd, [\rx, # S3C2410_UTRSTAT]
71 ldr \rd, [\rx, # S3C2410_UFCON]
82 ldr \rd, [\rx, # S3C2410_UTRSTAT]
H A Dat91.S26 ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
27 ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
35 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
41 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
H A Defm32.S20 ldr \rx, =(CONFIG_DEBUG_UART_PHYS)
27 ldr \tmp, =(UARTn_CMD_TXEN)
36 1001: ldr \rd, [\rx, #UARTn_STATUS]
42 1001: ldr \rd, [\rx, UARTn_STATUS]
H A Dks8695.S22 ldr \rp, =KS8695_UART_PA @ physical base address
23 ldr \rv, =KS8695_UART_VA @ virtual base address
31 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
37 1001: ldr \rd, [\rx, #KS8695_URLS] @ Read Line Status Register
H A Dpl01x.S24 ldr \rp, =CONFIG_DEBUG_UART_PHYS
25 ldr \rv, =CONFIG_DEBUG_UART_VIRT
34 1001: ldr \rd, [\rx, #UART01x_FR]
41 1001: ldr \rd, [\rx, #UART01x_FR]
H A Ds3c24xx.S20 ldr \rp, = CONFIG_DEBUG_UART_PHYS
21 ldr \rv, = CONFIG_DEBUG_UART_VIRT
25 ldr \rd, [\rx, # S3C2410_UFSTAT]
30 ldr \rd, [\rx, # S3C2410_UFSTAT]
H A Dsti.S43 ldr \rp, =DEBUG_LL_UART_BASE @ physical base
44 ldr \rv, =VIRT_ADDRESS(DEBUG_LL_UART_BASE) @ virt base
52 1001: ldr \rd, [\rx, #ASC_STA_OFF]
58 1001: ldr \rd, [\rx, #ASC_STA_OFF]
H A D8250.S13 ldr \rp, =CONFIG_DEBUG_UART_PHYS
14 ldr \rv, =CONFIG_DEBUG_UART_VIRT
25 ldr \rd, \rx
H A Dclps711x.S23 ldr \rv, =CLPS711X_UART_VADDR
24 ldr \rp, =CLPS711X_UART_PADDR
35 1001: ldr \rd, [\rx, #SYSFLG]
H A Dimx.S32 ldr \rp, =UART_PADDR @ physical
33 ldr \rv, =UART_VADDR @ virtual
44 1002: ldr \rd, [\rx, #0x98] @ SR2
H A Ddigicolor.S19 ldr \rp, =CONFIG_DEBUG_UART_PHYS
20 ldr \rv, =CONFIG_DEBUG_UART_VIRT
H A Dzynq.S36 ldr \rp, =LL_UART_PADDR @ physical
37 ldr \rv, =LL_UART_VADDR @ virtual
45 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
52 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
H A Domap2plus.S71 ldr \rv, [\rp] @ get absolute addr of 99f
73 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
75 ldr \rp, [\tmp, #0] @ omap_uart_phys
76 ldr \rv, [\tmp, #4] @ omap_uart_virt
127 ldr \rp, =AM33XX_UART1_BASE
132 ldr \rp, =ZOOM_UART_BASE
134 ldr \rp, =ZOOM_UART_VIRT
169 ldr \tmp, [\tmp, #8] @ omap_uart_lsr
H A Drenesas-scif.S31 ldr \rp, =SCIF_PHYS
32 ldr \rv, =SCIF_VIRT
H A Ds5pv210.S23 ldr \rp, =S5PV210_PA_UART
24 ldr \rv, =S3C_VA_UART
H A Dux500.S44 ldr \rp, =UART_PHYS_BASE @ no, physical address
45 ldr \rv, =UART_VIRT_BASE @ yes, virtual address
H A Dsa1100.S33 ldr \rv, [\rp, #UTCR3]
59 1001: ldr \rd, [\rx, #UTSR1]
65 1001: ldr \rd, [\rx, #UTSR1]
H A Dtegra.S56 ldr rp, =TEGRA_CLK_RST_DEVICES_##lhu ; \
58 ldr rp, [rp, #0] ; \
64 ldr rp, =TEGRA_CLK_OUT_ENB_##lhu ; \
66 ldr rp, [rp, #0] ; \
72 ldr rp, =TEGRA_UART##uart##_BASE ; \
78 ldr \rv, [\rp] @ linked addr is stored there
80 ldr \rp, [\rp, #4] @ linked tegra_uart_config
82 ldr \rp, [\tmp] @ Load tegra_uart_config
90 10: ldr \rp, =TEGRA_PMC_SCRATCH20
91 ldr \rp, [\rp, #0] @ Load PMC_SCRATCH20
165 100: ldr \rp, [\tmp, #4] @ Load tegra_uart_phys
166 ldr \rv, [\tmp, #8] @ Load tegra_uart_virt
H A Dvt8500.S29 1001: ldr \rd, [\rx, #0x1c]
H A Dexynos.S29 ldr \rv, =S3C_VA_UART
H A Dvf.S21 ldr \rp, =VF_UART_PHYSICAL_BASE @ physical
/linux-4.4.14/arch/arm/mach-prima2/
H A Dsleep.S22 ldr r0, =sirfsoc_memc_base
23 ldr r5, [r0]
25 ldr r0, =sirfsoc_pwrc_base
26 ldr r6, [r0]
28 ldr r0, =sirfsoc_rtciobrg_base
29 ldr r7, [r0]
43 ldr r2, [r5, #DENALI_CTL_22_OFF]
52 ldr r4, [r5, #DENALI_CTL_112_OFF]
61 ldr r3, [r7]
H A Dheadsmp.S24 pen: ldr r7, [r6]
/linux-4.4.14/arch/arm/mach-pxa/
H A Dstandby.S22 ldr r0, =PSSR
26 ldr ip, [r3]
62 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
69 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
72 1: ldr r0, [r1, #PXA3_DDR_HCAL]
76 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
83 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
87 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
92 1: ldr r0, [r1, #PXA3_DMCISR]
96 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
99 1: ldr r0, [r1, #PXA3_MDCNFG]
103 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
107 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
H A Dsleep.S55 ldr r4, =MDREFR
56 ldr r5, [r4]
62 ldr r6, =MDREFR_KDIV
69 ldr r6, =CCCR
70 ldr r8, [r6] @ keep original value for resume
72 ldr r7, =CCCR_SLEEP @ prepare CCCR sleep value
96 ldr r4, =MDREFR
97 ldr r5, [r4]
112 ldr r6, =CCCR
113 ldr r8, [r6] @ keep original value for resume
163 ldr r3, [r2]
H A Dpalm27x.c73 0xe590f008, /* ldr pc, [r0, #0x08] */ palm27x_pm_init()
/linux-4.4.14/arch/arm/mach-sa1100/
H A Dsleep.S36 ldr r6, =MDREFR
37 ldr r4, [r6]
39 ldr r5, =PPCR
81 ldr r0, =MSC0
82 ldr r1, =MSC1
83 ldr r2, =MSC2
85 ldr r3, [r0]
89 ldr r4, [r1]
93 ldr r5, [r2]
97 ldr r7, [r6]
102 ldr r9, =MDCNFG
103 ldr r10, [r9]
110 ldr r12, =PMCR
/linux-4.4.14/arch/arm64/kvm/
H A Dvgic-v2-switch.S40 ldr x2, [x0, #VCPU_KVM]
42 ldr x2, [x2, #KVM_VGIC_VCTRL]
50 ldr w5, [x2, #GICH_VMCR]
51 ldr w6, [x2, #GICH_MISR]
52 ldr w7, [x2, #GICH_EISR0]
53 ldr w8, [x2, #GICH_EISR1]
54 ldr w9, [x2, #GICH_ELRSR0]
55 ldr w10, [x2, #GICH_ELRSR1]
56 ldr w11, [x2, #GICH_APR]
82 ldr w4, [x3, #VGIC_CPU_NR_LR]
84 1: ldr w5, [x2], #4
100 ldr x2, [x0, #VCPU_KVM]
102 ldr x2, [x2, #KVM_VGIC_VCTRL]
110 ldr w4, [x3, #VGIC_V2_CPU_HCR]
111 ldr w5, [x3, #VGIC_V2_CPU_VMCR]
112 ldr w6, [x3, #VGIC_V2_CPU_APR]
123 ldr w4, [x3, #VGIC_CPU_NR_LR]
125 1: ldr w5, [x3], #4
H A Dvgic-v3-switch.S153 ldr w4, [x3, #VGIC_V3_CPU_HCR]
154 ldr w5, [x3, #VGIC_V3_CPU_VMCR]
155 ldr w25, [x3, #VGIC_V3_CPU_SRE]
170 ldr w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
172 ldr w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
174 6: ldr w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
176 5: ldr w17, [x3, #VGIC_V3_CPU_AP1R]
182 ldr w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
184 ldr w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
186 6: ldr w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
188 5: ldr w17, [x3, #VGIC_V3_CPU_AP0R]
200 ldr x20, [x3, #LR_OFFSET(15)]
201 ldr x19, [x3, #LR_OFFSET(14)]
202 ldr x18, [x3, #LR_OFFSET(13)]
203 ldr x17, [x3, #LR_OFFSET(12)]
204 ldr x16, [x3, #LR_OFFSET(11)]
205 ldr x15, [x3, #LR_OFFSET(10)]
206 ldr x14, [x3, #LR_OFFSET(9)]
207 ldr x13, [x3, #LR_OFFSET(8)]
208 ldr x12, [x3, #LR_OFFSET(7)]
209 ldr x11, [x3, #LR_OFFSET(6)]
210 ldr x10, [x3, #LR_OFFSET(5)]
211 ldr x9, [x3, #LR_OFFSET(4)]
212 ldr x8, [x3, #LR_OFFSET(3)]
213 ldr x7, [x3, #LR_OFFSET(2)]
214 ldr x6, [x3, #LR_OFFSET(1)]
215 ldr x5, [x3, #LR_OFFSET(0)]
H A Dhyp.S74 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
75 ldr x23, [x2, #CPU_GP_REG_OFFSET(CPU_ELR_EL1)]
76 ldr x24, [x2, #CPU_SPSR_OFFSET(KVM_SPSR_EL1)]
84 ldr x21, [x3, #16]
169 ldr x18, [x3, #144]
332 ldr x21, [x4, #(15 * 8)]
333 ldr x20, [x4, #(14 * 8)]
334 ldr x19, [x4, #(13 * 8)]
335 ldr x18, [x4, #(12 * 8)]
336 ldr x17, [x4, #(11 * 8)]
337 ldr x16, [x4, #(10 * 8)]
338 ldr x15, [x4, #(9 * 8)]
339 ldr x14, [x4, #(8 * 8)]
340 ldr x13, [x4, #(7 * 8)]
341 ldr x12, [x4, #(6 * 8)]
342 ldr x11, [x4, #(5 * 8)]
343 ldr x10, [x4, #(4 * 8)]
344 ldr x9, [x4, #(3 * 8)]
345 ldr x8, [x4, #(2 * 8)]
346 ldr x7, [x4, #(1 * 8)]
347 ldr x6, [x4, #(0 * 8)]
384 ldr \tmp, [x0, #VCPU_DEBUG_FLAGS]
402 ldr x25, [x25, #CPU_SYSREG_OFFSET(MDSCR_EL1)]
463 ldr x7, [x3, #24]
469 ldr x2, [x0, #VCPU_HCR_EL2]
492 ldr x2, [x0, #VCPU_MDCR_EL2]
507 ldr x1, [x0, #VCPU_KVM]
509 ldr x2, [x1, #KVM_VTTBR]
538 ldr x25, [x0, #VCPU_IRQ_LINES]
551 ldr x2, [x0, #VCPU_KVM]
553 ldr w3, [x2, #KVM_TIMER_ENABLED]
587 ldr x2, [x0, #VCPU_KVM]
589 ldr w3, [x2, #KVM_TIMER_ENABLED]
592 ldr x3, [x2, #KVM_TIMER_CNTVOFF]
594 ldr x2, [x0, #VCPU_TIMER_CNTV_CVAL]
598 ldr w2, [x0, #VCPU_TIMER_CNTV_CTL]
666 ldr x21, [x2, #CPU_SYSREG_OFFSET(MDCCINT_EL1)]
691 ldr x2, [x0, #VCPU_HOST_CONTEXT]
699 ldr x4, [x2, #CPU_SYSREG_OFFSET(FPEXC32_EL2)]
724 ldr x2, [x0, #VCPU_HOST_CONTEXT]
749 ldr x3, [x0, #VCPU_DEBUG_PTR]
770 ldr x3, [x0, #VCPU_DEBUG_PTR]
783 ldr x2, [x0, #VCPU_HOST_CONTEXT]
810 ldr x2, [x0, #KVM_VTTBR]
846 ldr x2, [x0, #KVM_VTTBR]
882 ldr x2, [x0, #VCPU_HOST_CONTEXT]
891 ldr x22, [x2, #CPU_GP_REG_OFFSET(CPU_SP_EL1)]
911 ldr lr, =panic
H A Dhyp-init.S65 ldr x5, =TCR_EL2_MASK
67 ldr x5, =TCR_EL2_FLAGS
90 ldr x4, =VTCR_EL2_FLAGS
109 ldr x5, =SCTLR_EL2_FLAGS
119 ldr x4, =TRAMPOLINE_VA
/linux-4.4.14/arch/arm/crypto/
H A Dsha512-armv4.pl95 ldr $t2,[sp,#$Hoff+0] @ h.lo
97 ldr $t3,[sp,#$Hoff+4] @ h.hi
107 ldr $t0,[sp,#$Foff+0] @ f.lo
109 ldr $t1,[sp,#$Foff+4] @ f.hi
111 ldr $t2,[sp,#$Goff+0] @ g.lo
113 ldr $t3,[sp,#$Goff+4] @ g.hi
124 ldr $t2,[$Ktbl,#$lo] @ K[i].lo
126 ldr $t3,[$Ktbl,#$hi] @ K[i].hi
129 ldr $Elo,[sp,#$Doff+0] @ d.lo
131 ldr $Ehi,[sp,#$Doff+4] @ d.hi
136 ldr $t2,[sp,#$Boff+0] @ b.lo
140 ldr $t3,[sp,#$Coff+0] @ c.lo
164 ldr $t1,[sp,#$Boff+4] @ b.hi
166 ldr $t2,[sp,#$Coff+4] @ c.hi
276 ldr r12,.LOPENSSL_armcap
277 ldr r12,[r3,r12] @ OPENSSL_armcap_P
286 ldr $Elo,[$ctx,#$Eoff+$lo]
287 ldr $Ehi,[$ctx,#$Eoff+$hi]
288 ldr $t0, [$ctx,#$Goff+$lo]
289 ldr $t1, [$ctx,#$Goff+$hi]
290 ldr $t2, [$ctx,#$Hoff+$lo]
291 ldr $t3, [$ctx,#$Hoff+$hi]
297 ldr $Alo,[$ctx,#$Aoff+$lo]
298 ldr $Ahi,[$ctx,#$Aoff+$hi]
299 ldr $Tlo,[$ctx,#$Boff+$lo]
300 ldr $Thi,[$ctx,#$Boff+$hi]
301 ldr $t0, [$ctx,#$Coff+$lo]
302 ldr $t1, [$ctx,#$Coff+$hi]
303 ldr $t2, [$ctx,#$Doff+$lo]
304 ldr $t3, [$ctx,#$Doff+$hi]
311 ldr $Tlo,[$ctx,#$Foff+$lo]
312 ldr $Thi,[$ctx,#$Foff+$hi]
333 ldr $Tlo,[$inp,#4]
334 ldr $Thi,[$inp],#8
345 ldr $t0,[sp,#`$Xoff+8*(16-1)`+0]
346 ldr $t1,[sp,#`$Xoff+8*(16-1)`+4]
353 ldr $t2,[sp,#`$Xoff+8*(16-14)`+0]
355 ldr $t3,[sp,#`$Xoff+8*(16-14)`+4]
379 ldr $t2,[sp,#`$Xoff+8*(16-9)`+0]
382 ldr $t3,[sp,#`$Xoff+8*(16-9)`+4]
384 ldr $t0,[sp,#`$Xoff+8*16`+0]
387 ldr $t1,[sp,#`$Xoff+8*16`+4]
403 ldr $Tlo,[sp,#$Boff+0]
404 ldr $Thi,[sp,#$Boff+4]
405 ldr $t0, [$ctx,#$Aoff+$lo]
406 ldr $t1, [$ctx,#$Aoff+$hi]
407 ldr $t2, [$ctx,#$Boff+$lo]
408 ldr $t3, [$ctx,#$Boff+$hi]
418 ldr $Alo,[sp,#$Coff+0]
419 ldr $Ahi,[sp,#$Coff+4]
420 ldr $Tlo,[sp,#$Doff+0]
421 ldr $Thi,[sp,#$Doff+4]
422 ldr $t0, [$ctx,#$Coff+$lo]
423 ldr $t1, [$ctx,#$Coff+$hi]
424 ldr $t2, [$ctx,#$Doff+$lo]
425 ldr $t3, [$ctx,#$Doff+$hi]
435 ldr $Tlo,[sp,#$Foff+0]
436 ldr $Thi,[sp,#$Foff+4]
437 ldr $t0, [$ctx,#$Eoff+$lo]
438 ldr $t1, [$ctx,#$Eoff+$hi]
439 ldr $t2, [$ctx,#$Foff+$lo]
440 ldr $t3, [$ctx,#$Foff+$hi]
450 ldr $Alo,[sp,#$Goff+0]
451 ldr $Ahi,[sp,#$Goff+4]
452 ldr $Tlo,[sp,#$Hoff+0]
453 ldr $Thi,[sp,#$Hoff+4]
454 ldr $t0, [$ctx,#$Goff+$lo]
455 ldr $t1, [$ctx,#$Goff+$hi]
456 ldr $t2, [$ctx,#$Hoff+$lo]
457 ldr $t3, [$ctx,#$Hoff+$hi]
H A Dsha1-armv4-large.S64 ldr r8,.LK_00_19
83 ldr r9,[r1],#4 @ handles unaligned
108 ldr r9,[r1],#4 @ handles unaligned
133 ldr r9,[r1],#4 @ handles unaligned
158 ldr r9,[r1],#4 @ handles unaligned
183 ldr r9,[r1],#4 @ handles unaligned
211 ldr r9,[r1],#4 @ handles unaligned
224 ldr r9,[r14,#15*4]
225 ldr r10,[r14,#13*4]
226 ldr r11,[r14,#7*4]
228 ldr r12,[r14,#2*4]
241 ldr r9,[r14,#15*4]
242 ldr r10,[r14,#13*4]
243 ldr r11,[r14,#7*4]
245 ldr r12,[r14,#2*4]
258 ldr r9,[r14,#15*4]
259 ldr r10,[r14,#13*4]
260 ldr r11,[r14,#7*4]
262 ldr r12,[r14,#2*4]
275 ldr r9,[r14,#15*4]
276 ldr r10,[r14,#13*4]
277 ldr r11,[r14,#7*4]
279 ldr r12,[r14,#2*4]
293 ldr r8,.LK_20_39 @ [+15+16*4]
296 ldr r9,[r14,#15*4]
297 ldr r10,[r14,#13*4]
298 ldr r11,[r14,#7*4]
300 ldr r12,[r14,#2*4]
312 ldr r9,[r14,#15*4]
313 ldr r10,[r14,#13*4]
314 ldr r11,[r14,#7*4]
316 ldr r12,[r14,#2*4]
328 ldr r9,[r14,#15*4]
329 ldr r10,[r14,#13*4]
330 ldr r11,[r14,#7*4]
332 ldr r12,[r14,#2*4]
344 ldr r9,[r14,#15*4]
345 ldr r10,[r14,#13*4]
346 ldr r11,[r14,#7*4]
348 ldr r12,[r14,#2*4]
360 ldr r9,[r14,#15*4]
361 ldr r10,[r14,#13*4]
362 ldr r11,[r14,#7*4]
364 ldr r12,[r14,#2*4]
382 ldr r8,.LK_40_59
385 ldr r9,[r14,#15*4]
386 ldr r10,[r14,#13*4]
387 ldr r11,[r14,#7*4]
389 ldr r12,[r14,#2*4]
402 ldr r9,[r14,#15*4]
403 ldr r10,[r14,#13*4]
404 ldr r11,[r14,#7*4]
406 ldr r12,[r14,#2*4]
419 ldr r9,[r14,#15*4]
420 ldr r10,[r14,#13*4]
421 ldr r11,[r14,#7*4]
423 ldr r12,[r14,#2*4]
436 ldr r9,[r14,#15*4]
437 ldr r10,[r14,#13*4]
438 ldr r11,[r14,#7*4]
440 ldr r12,[r14,#2*4]
453 ldr r9,[r14,#15*4]
454 ldr r10,[r14,#13*4]
455 ldr r11,[r14,#7*4]
457 ldr r12,[r14,#2*4]
473 ldr r8,.LK_60_79
H A Daes-armv4.S187 ldr r0,[r12,#0]
188 ldr r1,[r12,#4]
189 ldr r2,[r12,#8]
190 ldr r3,[r12,#12]
200 ldr r12,[sp],#4 @ pop out
251 ldr r12,[r11,#240-16]
263 ldr r4,[r10,r7,lsl#2] @ Te3[s0>>0]
265 ldr r5,[r10,r8,lsl#2] @ Te2[s0>>8]
267 ldr r6,[r10,r9,lsl#2] @ Te1[s0>>16]
269 ldr r0,[r10,r0,lsl#2] @ Te0[s0>>24]
272 ldr r7,[r10,r7,lsl#2] @ Te1[s1>>16]
273 ldr r8,[r10,r8,lsl#2] @ Te3[s1>>0]
274 ldr r9,[r10,r9,lsl#2] @ Te2[s1>>8]
276 ldr r1,[r10,r1,lsl#2] @ Te0[s1>>24]
282 ldr r7,[r10,r7,lsl#2] @ Te2[s2>>8]
284 ldr r8,[r10,r8,lsl#2] @ Te1[s2>>16]
287 ldr r9,[r10,r9,lsl#2] @ Te3[s2>>0]
289 ldr r2,[r10,r2,lsl#2] @ Te0[s2>>24]
295 ldr r7,[r10,r7,lsl#2] @ Te3[s3>>0]
297 ldr r8,[r10,r8,lsl#2] @ Te2[s3>>8]
300 ldr r9,[r10,r9,lsl#2] @ Te1[s3>>16]
302 ldr r7,[r11],#16
304 ldr r3,[r10,r3,lsl#2] @ Te0[s3>>24]
306 ldr r4,[r11,#-12]
309 ldr r5,[r11,#-8]
311 ldr r6,[r11,#-4]
364 ldr r7,[r11,#0]
367 ldr r4,[r11,#4]
369 ldr r5,[r11,#8]
371 ldr r6,[r11,#12]
379 ldr pc,[sp],#4 @ pop and return
442 ldr r0,[r12,#0]
443 ldr r1,[r12,#4]
444 ldr r2,[r12,#8]
445 ldr r3,[r12,#12]
476 ldr r4,[r6],#4 @ rcon[i++]
511 ldr r8,[r12,#16]
512 ldr r9,[r12,#20]
540 ldr r4,[r6],#4 @ rcon[i++]
555 ldr r7,[r11,#-32]
556 ldr r8,[r11,#-28]
582 ldr r8,[r12,#24]
583 ldr r9,[r12,#28]
609 ldr r4,[r6],#4 @ rcon[i++]
634 ldr r4,[r11,#-48]
637 ldr r7,[r11,#-44]
638 ldr r8,[r11,#-40]
640 ldr r9,[r11,#-36]
671 ldr r12,[r2,#240] @ AES_set_encrypt_key preserves r2,
676 .Linv: ldr r0,[r7]
677 ldr r1,[r7,#4]
678 ldr r2,[r7,#8]
679 ldr r3,[r7,#12]
680 ldr r4,[r8]
681 ldr r5,[r8,#4]
682 ldr r6,[r8,#8]
683 ldr r9,[r8,#12]
694 ldr r0,[r11,#16]! @ prefetch tp1
732 ldr r0,[r11,#4] @ prefetch tp1
882 ldr r0,[r12,#0]
883 ldr r1,[r12,#4]
884 ldr r2,[r12,#8]
885 ldr r3,[r12,#12]
895 ldr r12,[sp],#4 @ pop out
946 ldr r12,[r11,#240-16]
958 ldr r4,[r10,r7,lsl#2] @ Td1[s0>>16]
960 ldr r5,[r10,r8,lsl#2] @ Td2[s0>>8]
962 ldr r6,[r10,r9,lsl#2] @ Td3[s0>>0]
964 ldr r0,[r10,r0,lsl#2] @ Td0[s0>>24]
967 ldr r7,[r10,r7,lsl#2] @ Td3[s1>>0]
968 ldr r8,[r10,r8,lsl#2] @ Td1[s1>>16]
969 ldr r9,[r10,r9,lsl#2] @ Td2[s1>>8]
971 ldr r1,[r10,r1,lsl#2] @ Td0[s1>>24]
977 ldr r7,[r10,r7,lsl#2] @ Td2[s2>>8]
979 ldr r8,[r10,r8,lsl#2] @ Td3[s2>>0]
982 ldr r9,[r10,r9,lsl#2] @ Td1[s2>>16]
984 ldr r2,[r10,r2,lsl#2] @ Td0[s2>>24]
990 ldr r7,[r10,r7,lsl#2] @ Td1[s3>>16]
992 ldr r8,[r10,r8,lsl#2] @ Td2[s3>>8]
995 ldr r9,[r10,r9,lsl#2] @ Td3[s3>>0]
997 ldr r7,[r11],#16
999 ldr r3,[r10,r3,lsl#2] @ Td0[s3>>24]
1002 ldr r4,[r11,#-12]
1004 ldr r5,[r11,#-8]
1006 ldr r6,[r11,#-4]
1020 ldr r5,[r10,#0] @ prefetch Td4
1021 ldr r6,[r10,#32]
1022 ldr r4,[r10,#64]
1023 ldr r5,[r10,#96]
1024 ldr r6,[r10,#128]
1025 ldr r4,[r10,#160]
1026 ldr r5,[r10,#192]
1027 ldr r6,[r10,#224]
1072 ldr r7,[r11,#0]
1074 ldr r4,[r11,#4]
1076 ldr r5,[r11,#8]
1078 ldr r6,[r11,#12]
1086 ldr pc,[sp],#4 @ pop and return
H A Dsha256-armv4.pl69 @ ldr $t1,[$inp],#4 @ $i
96 ldr $t2,[$Ktbl],#4 @ *K256++
112 ldr $t1,[$inp],#4 @ prefetch
118 ldr $t1,[sp,#`($i+2)%16`*4] @ from future BODY_16_xx
120 ldr $t4,[sp,#`($i+15)%16`*4] @ from future BODY_16_xx
136 @ ldr $t1,[sp,#`($i+1)%16`*4] @ $i
137 @ ldr $t4,[sp,#`($i+14)%16`*4]
144 ldr $t1,[sp,#`($i+0)%16`*4]
146 ldr $t4,[sp,#`($i+9)%16`*4]
214 ldr r12,.LOPENSSL_armcap
215 ldr r12,[r3,r12] @ OPENSSL_armcap_P
228 ldr $t1,[$inp],#4
246 ldr $t0,[$t3,#0]
247 ldr $t1,[$t3,#4]
248 ldr $t2,[$t3,#8]
250 ldr $t0,[$t3,#12]
252 ldr $t1,[$t3,#16]
254 ldr $t2,[$t3,#20]
256 ldr $t0,[$t3,#24]
258 ldr $t1,[$t3,#28]
260 ldr $inp,[sp,#17*4] @ pull inp
261 ldr $t2,[sp,#18*4] @ pull inp+len
442 '&ldr ($t1,sprintf "[sp,#%d]",4*(($j+1)&15)) if (($j&15)!=15);'.
443 '&ldr ($t1,"[$Ktbl]") if ($j==15);'.
444 '&ldr ($t1,"[sp,#64]") if ($j==31)',
500 ldr $t1,[sp,#0]
514 ldr $t1,[sp,#0]
518 ldr $inp,[sp,#68]
519 ldr $t0,[sp,#72]
537 ldr $t0,[$t1,#0]
539 ldr $t2,[$t1,#4]
540 ldr $t3,[$t1,#8]
541 ldr $t4,[$t1,#12]
543 ldr $t0,[$t1,#16]
545 ldr $t2,[$t1,#20]
547 ldr $t3,[$t1,#24]
549 ldr $t4,[$t1,#28]
H A Dbsaes-armv7.pl991 ldr r5,[$inp,#240] @ pass rounds
1039 ldr r5,[$inp,#240] @ pass rounds
1111 ldr $ivp, [ip] @ IV is 1st arg on the stack
1116 ldr $rounds, [$key, #240] @ get # of rounds
1132 ldr r12, [$key, #244]
1376 ldr $ctr, [ip] @ ctr is 1st arg on the stack
1380 ldr $rounds, [$key, #240] @ get # of rounds
1398 ldr r12, [$key, #244]
1540 ldr ip, [sp] @ ctr pointer is passed on stack
1547 ldr r8, [ip, #12] @ load counter LSW
1616 ldr r0, [ip] @ pointer to input tweak
1619 ldr r0, [ip, #4] @ iv[]
1621 ldr r2, [ip, #0] @ key2
1626 ldr $rounds, [$key, #240] @ get # of rounds
1643 ldr r12, [$key, #244]
1995 ldr r1, [$fp, #0x20+VFP_ABI_FRAME] @ chain tweak
2030 ldr r0, [ip] @ pointer to input tweak
2033 ldr r0, [ip, #4] @ iv[]
2035 ldr r2, [ip, #0] @ key2
2040 ldr $rounds, [$key, #240] @ get # of rounds
2060 ldr r12, [$key, #244]
2438 ldr r1, [$fp, #0x20+VFP_ABI_FRAME] @ chain tweak
H A Daes-ce-core.S167 ldr r4, [sp, #8]
193 ldr r4, [sp, #8]
380 ldr r6, [sp, #28]
387 ldr r6, [sp, #24] @ load AES key 2
H A Dsha1-armv7-neon.S94 ldr RT3, [sp, WK_offs(i)]; \
108 ldr RT3, [sp, WK_offs(i)]; \
121 ldr RT3, [sp, WK_offs(i)]; \
594 ldr RT0, [RSTATE, #state_h4];
627 ldr RT0, [RSTATE, #state_h4];
/linux-4.4.14/arch/arm/mach-at91/
H A Dpm_suspend.S29 1: ldr tmp1, [pmc, #AT91_PMC_SR]
38 1: ldr tmp1, [pmc, #AT91_PMC_SR]
47 1: ldr tmp1, [pmc, #AT91_PMC_SR]
108 ldr r0, .pm_mode
112 ldr pmc, .pmc_base
115 ldr tmp1, [pmc, #AT91_PMC_MCKR]
127 ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
135 ldr tmp1, [pmc, #AT91_CKGR_MOR]
141 ldr pmc, .pmc_base
146 ldr r0, .pm_mode
150 ldr pmc, .pmc_base
153 ldr tmp1, [pmc, #AT91_CKGR_MOR]
161 ldr tmp1, .saved_pllar
175 ldr tmp1, .saved_mckr
201 ldr r1, .memtype
202 ldr r2, .sramc_base
234 ldr r3, [r2, #AT91_DDRSDRC_MDR]
244 ldr r3, [r2, #AT91_DDRSDRC_LPR]
251 ldr r2, .sramc1_base
255 ldr r3, [r2, #AT91_DDRSDRC_MDR]
265 ldr r3, [r2, #AT91_DDRSDRC_LPR]
276 ldr r3, .saved_sam9_mdr
279 ldr r3, .saved_sam9_lpr
283 ldr r2, .sramc1_base
300 ldr r3, [r2, #AT91_SDRAMC_LPR]
307 ldr r3, .saved_sam9_lpr
/linux-4.4.14/arch/arm/kernel/
H A Drelocate_kernel.S13 ldr r0,kexec_indirection_page
14 ldr r1,kexec_start_address
24 ldr r3, [r0],#4
51 ldr r5,[r3],#4
61 ldr r1,kexec_mach_type
62 ldr r2,kexec_boot_atags
H A Dentry-v7m.S46 ldr r1, =V7M_xPSR_EXCEPTIONNO
58 ldr r1, =BASEADDR_V7M_SCB
59 ldr r0, [r1, V7M_SCB_ICSR]
64 ldr r2, [tsk, #TI_FLAGS]
84 ldr r1, =BASEADDR_V7M_SCB
108 ldr r0, =thread_notify_head
114 ldr sp, [ip]
115 ldr pc, [ip, #4]!
H A Dhead-nommu.S60 ldr r9, =BASEADDR_V7M_SCB
61 ldr r9, [r9, V7M_SCB_CPUID]
63 ldr r9, =CONFIG_PROCESSOR_ID
71 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET
72 ldr r6, =(_end) @ Cover whole kernel
82 ldr r12, [r10, #PROCINFO_INITFUNC]
101 ldr r9, =CONFIG_PROCESSOR_ID
109 ldr r7, __secondary_data
113 ldr r6, [r7] @ get secondary_data.mpu_szr
118 ldr r12, [r10, #PROCINFO_INITFUNC]
122 ldr sp, [r7, #12] @ set up the stack pointer
211 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET
212 ldr r5,=(MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL)
224 ldr r5,=(MPU_ACR_XN | MPU_RGN_STRONGLY_ORDERED | MPU_AP_PL1RW_PL0NA)
237 ldr r5,=(MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL)
H A Dentry-ftrace.S67 ldr r0, =ftrace_trace_function
68 ldr r2, [r0]
74 ldr r1, =ftrace_graph_return
75 ldr r2, [r1]
79 ldr r1, =ftrace_graph_entry
80 ldr r2, [r1]
81 ldr r0, =ftrace_graph_entry_stub
118 ldr r1, [sp, #16] @ instrumented routine (func)
139 ldr \reg, [fp, #-4]
143 ldr lr, [fp, #-4]
150 ldr lr, [fp, #-4]
189 ldr \reg, [sp, #20]
H A Dsleep.S63 ldr r10, =processor
64 ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
66 ldr r4, =cpu_suspend_size
71 ldr r3, =sleep_save_sp
73 ldr r3, [r3, #SLEEP_SAVE_SP_VIRT]
74 ALT_SMP(ldr r0, =mpidr_hash)
103 ldr r3, =cpu_resume_after_mmu
141 ldr r3, [r2]
151 ldr r2, [r0]
153 ldr r0, [r0, #SLEEP_SAVE_SP_PHYS]
154 ldr r0, [r0, r1, lsl #2]
H A Diwmmxt.S88 ldr r3, =concan_owner
90 ldr r2, [sp, #60] @ current task pc value
91 ldr r1, [r3] @ get current Concan owner
203 ldr r3, =concan_owner
205 ldr r1, [r3] @ get current Concan owner
255 ldr r3, =concan_owner
257 ldr r3, [r3] @ get current Concan owner
293 ldr r3, =concan_owner
295 ldr r3, [r3] @ get current Concan owner
332 ldr r2, =concan_owner
334 ldr r2, [r2] @ get current Concan owner
359 ldr r3, =concan_owner
361 ldr r1, [r3] @ get current Concan owner
H A Dentry-armv.S43 ldr r1, =handle_arch_irq
46 ldr pc, [r1]
56 ldr ip, .LCprocfns
58 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
77 ldr ip, .LCprocfns
79 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
160 SPFIX( ldr r0, [sp] ) @ restored
205 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
217 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
218 ldr r0, [tsk, #TI_FLAGS] @ get flags
235 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
248 ldr r2, [r0, #S_PC]
272 ldr r0, [r4, #-4]
293 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
384 ATRAP( ldr r8, .LCcralign)
393 ATRAP( ldr r8, [r8, #0])
517 ldr r5, .LCcpu_architecture
518 ldr r5, [r5]
611 2: ldr r5, [r6], #4 @ mask value
612 ldr r7, [r6], #4 @ opcode bits matching in mask
635 ldr r5, [r10, #TI_FLAGS]
704 ldr r4, .LCfp
706 ldr pc, [r4] @ Call FP module USR entry point
783 ldr r4, [r2, #TI_TP_VALUE]
784 ldr r5, [r2, #TI_TP_VALUE + 4]
788 ldr r6, [r2, #TI_CPU_DOMAIN]
792 ldr r7, [r2, #TI_TASK]
793 ldr r8, =__stack_chk_guard
794 ldr r7, [r7, #TSK_STACK_CANARY]
801 ldr r0, =thread_notify_head
811 THUMB( ldr sp, [ip], #4 )
812 THUMB( ldr pc, [ip] )
950 1: ldr r3, [r2] @ load current val
996 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1018 * vectors, rather than ldr's. Note that this code must not exceed
1055 THUMB( ldr lr, [r0, lr, lsl #2] )
1057 ARM( ldr lr, [pc, lr, lsl #2] )
1212 W(ldr) pc, __vectors_start + 0x1000
H A Dentry-header.S49 ldr \rtmp1, \label
50 ldr \rtmp1, [\rtmp1]
129 ldr lr, =EXC_RET_THREADMODE_PROCESSSTACK
192 ldr sp, [\rd, #\offset] @ load sp_usr
193 ldr lr, [\rd, #\offset + 4] @ load lr_usr
231 ldr lr, [sp, #S_SP] @ top of the stack
240 ldr lr, [sp], #4
270 ldr r9, [r0, #S_PSR]
272 ldr r0, [r0, #S_R0]
277 ldr lr, [sp, #S_LR]
278 ldr sp, [sp, #S_SP] @ abort is deadly from here onward (it will
296 ldr r1, [r2, #\offset + S_PSR] @ get calling cpsr
297 ldr lr, [r2, #\offset + S_PC]! @ get pc
324 ldr r1, [sp, #\offset + S_PSR] @ get calling cpsr
325 ldr lr, [sp, #\offset + S_PC] @ get pc
H A Dhead-common.S51 ldr r5, [r2, #0]
53 ldr r6, =OF_DT_MAGIC @ is it a DTB?
60 ldr r5, [r2, #4]
61 ldr r6, =ATAG_CORE
98 THUMB( ldr sp, [r3, #16] )
H A Dmodule-plts.c29 u32 ldr[PLT_ENT_COUNT]; member in struct:plt_entries
64 return (u32)plt->ldr; get_module_plt()
72 return (u32)&plt->ldr[i]; get_module_plt()
H A Dentry-common.S38 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
64 ldr r1, [tsk, #TI_FLAGS] @ re-check for syscall tracing
96 ldr r1, [tsk, #TI_FLAGS]
180 USER( ldr r10, [lr, #-4] ) @ get SWI instruction
197 USER( ldr scno, [lr, #-4] ) @ get SWI instruction
220 ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing
H A Dhead.S114 ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case
149 ldr r13, =__mmap_switched @ address to jump to after
158 ldr r12, [r10, #PROCINFO_INITFUNC]
224 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
248 ldr r6, =(_end - 1)
266 ldr r6, =(_edata_loc - 1)
308 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
326 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
405 ldr r8, [r3, #8] @ get secondary_data.swapper_pg_dir
408 ldr r12, [r10, #PROCINFO_INITFUNC]
419 ldr sp, [r7, #12] @ get secondary_data.stack
538 ldr r0, [r0, #4] @ read SCU Config
637 ldr r6, [r0]
639 ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
640 ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
683 1: ldr ip, [r7, r3]
H A Dhyp-stub.S44 ldr \reg3, [\reg2]
56 ldr \reg3, [\reg2]
57 ldr \reg1, [\reg2, \reg3]
/linux-4.4.14/arch/arm/mach-omap2/
H A Dsleep34xx.S90 ldr r2, [r3] @ value for offset
106 ldr r12, high_mask
108 ldr r12, sram_phy_addr_mask
175 ldr r4, omap3_do_wfi_sram_addr
176 ldr r5, [r4]
192 ldr r1, kernel_flush
211 ldr r1, kernel_flush
236 ldr r4, sdrc_power @ read the SDRC_POWER register
237 ldr r5, [r4] @ read the contents of SDRC_POWER
282 ldr r4, cm_idlest_ckgen
284 ldr r5, [r4]
288 ldr r4, cm_idlest1_core
290 ldr r5, [r4]
294 ldr r4, sdrc_power
295 ldr r5, [r4]
301 ldr r4, sdrc_dlla_ctrl
302 ldr r5, [r4]
307 ldr r4, sdrc_dlla_status
313 ldr r5, [r4]
321 ldr r4, sdrc_dlla_ctrl
322 ldr r5, [r4]
381 ldr r5, pm_prepwstst_core_p
382 ldr r4, [r5]
387 ldr r1, sram_base
388 ldr r2, es3_sdrc_fix_sz
395 ldr r1, sram_base
401 ldr r1, pm_prepwstst_core_p
402 ldr r2, [r1]
407 ldr r1, control_mem_rta
419 ldr r1, pm_pwstctrl_mpu
420 ldr r2, [r1]
426 ldr r0, [r1] @ value for offset
427 ldr r0, [r1, r0] @ value at l2dis_3630
434 ldr r0, control_stat
435 ldr r1, [r0]
440 ldr r3, [r0]
456 ldr r4, scratchpad_base
457 ldr r3, [r4, #0xBC] @ r3 points to parameters
470 ldr r4, scratchpad_base
471 ldr r3, [r4, #0xBC]
487 ldr r4, scratchpad_base
488 ldr r3, [r4,#0xBC]
489 ldr r0, [r3,#4]
492 ldr r4, scratchpad_base
493 ldr r3, [r4,#0xBC]
494 ldr r0, [r3,#12]
499 ldr r1, [r0] @ value for offset
500 ldr r1, [r0, r1] @ value at l2dis_3630
551 ldr r4, sdrc_syscfg @ get config addr
552 ldr r5, [r4] @ get value
557 ldr r4, sdrc_mr_0 @ get config addr
558 ldr r5, [r4] @ get value
560 ldr r4, sdrc_emr2_0 @ get config addr
561 ldr r5, [r4] @ get value
563 ldr r4, sdrc_manual_0 @ get config addr
566 ldr r4, sdrc_mr_1 @ get config addr
567 ldr r5, [r4] @ get value
569 ldr r4, sdrc_emr2_1 @ get config addr
570 ldr r5, [r4] @ get value
572 ldr r4, sdrc_manual_1 @ get config addr
H A Dsram242x.S51 ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
60 ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
61 ldr r10, [r11] @ get current val
73 ldr r10, [r11] @ get locked value
111 ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
112 ldr r5, [r4] @ get value.
113 ldr r6, prcm_mask_val @ get value of mask
121 ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
122 ldr r5, [r3] @ get value
125 ldr r7, [r3] @ get timer value
155 ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
156 ldr r5, [r6] @ get value
169 ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
170 ldr r3, [r4] @ get curr value
190 ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
206 ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
207 ldr r8, [r10] @ get value
208 ldr r7, ddr_prcm_mask_val @ get value of mask
216 ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
217 ldr r8, [r10] @ get value
220 ldr r7, [r10] @ get timer value
252 ldr r8, omap242x_ssp_pll_ctl @ get addr
253 ldr r5, [r8] @ get val
258 ldr r4, omap242x_ssp_pll_stat @ addr of stat
261 ldr r8, [r4] @ stat value
267 ldr r4, omap242x_ssp_pll_div @ get addr
270 ldr r4, omap242x_ssp_set_config @ get addr
284 ldr r5, omap242x_ssp_pll_stat @ get addr
285 ldr r4, omap242x_ssp_pll_ctl @ get addr
293 ldr r8, [r5] @ get lock val
299 ldr r4, omap242x_ssp_sdrc_rfr @ get addr
301 ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
302 ldr r10, [r11] @ get current val
H A Dsram243x.S51 ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
60 ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
61 ldr r10, [r11] @ get current val
73 ldr r10, [r11] @ get locked value
111 ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
112 ldr r5, [r4] @ get value.
113 ldr r6, prcm_mask_val @ get value of mask
121 ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
122 ldr r5, [r3] @ get value
125 ldr r7, [r3] @ get timer value
155 ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
156 ldr r5, [r6] @ get value
169 ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
170 ldr r3, [r4] @ get curr value
190 ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
206 ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
207 ldr r8, [r10] @ get value
208 ldr r7, ddr_prcm_mask_val @ get value of mask
216 ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
217 ldr r8, [r10] @ get value
220 ldr r7, [r10] @ get timer value
252 ldr r8, omap243x_ssp_pll_ctl @ get addr
253 ldr r5, [r8] @ get val
258 ldr r4, omap243x_ssp_pll_stat @ addr of stat
261 ldr r8, [r4] @ stat value
267 ldr r4, omap243x_ssp_pll_div @ get addr
270 ldr r4, omap243x_ssp_set_config @ get addr
284 ldr r5, omap243x_ssp_pll_stat @ get addr
285 ldr r4, omap243x_ssp_pll_ctl @ get addr
293 ldr r8, [r5] @ get lock val
299 ldr r4, omap243x_ssp_sdrc_rfr @ get addr
301 ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
302 ldr r10, [r11] @ get current val
H A Dsleep44xx.S71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
77 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
110 ldr r9, [r8, #OMAP_TYPE_OFFSET]
119 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
164 ldr r0, =0xffff
167 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
168 ldr r1, =0xffff
182 ldr r0, [r2, #L2X0_CACHE_SYNC]
213 ldr r9, [r8, #OMAP_TYPE_OFFSET]
219 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
254 ldr r8, =OMAP44XX_SAR_RAM_BASE
255 ldr r9, [r8, #OMAP_TYPE_OFFSET]
264 ldr r3, [r1]
290 ldr r2, =OMAP44XX_L2CACHE_BASE
291 ldr r0, [r2, #L2X0_CTRL]
295 ldr r3, =OMAP44XX_SAR_RAM_BASE
296 ldr r1, [r3, #OMAP_TYPE_OFFSET]
299 ldr r0, =OMAP4_PPA_L2_POR_INDEX
300 ldr r1, =OMAP44XX_SAR_RAM_BASE
301 ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
303 ldr r3, [r1]
313 ldr r1, =OMAP44XX_SAR_RAM_BASE
314 ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
315 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
318 ldr r1, =OMAP44XX_SAR_RAM_BASE
319 ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
320 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
323 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
H A Domap-headsmp.S35 wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
36 ldr r0, [r2]
51 wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
52 ldr r0, [r2]
58 ldr r12, =API_HYP_ENTRY
72 hold: ldr r12,=0x103
89 hold_2: ldr r12,=0x103
113 ldr r1, =OMAP44XX_GIC_DIST_BASE
114 ldr r0, [r1]
H A Dsleep24xx.S72 ldr r4, [r2] @ read SDRC_POWER
86 ldr r4, A_SDRC0 @ make a clock happen
87 ldr r4, [r4] @ read A_SDRC0
/linux-4.4.14/arch/arm/kvm/
H A Dinterrupts_head.S179 ldr r2, [vcpu, #VCPU_PC]
180 ldr r3, [vcpu, #VCPU_CPSR]
185 ldr r2, [vcpu, #VCPU_USR_SP]
186 ldr r3, [vcpu, #VCPU_USR_LR]
332 ldr r2, [vcpu, #CP15_OFFSET(c14_CNTKCTL)]
335 ldr r6, [vcpu, #CP15_OFFSET(c10_AMAIR0)]
336 ldr r7, [vcpu, #CP15_OFFSET(c10_AMAIR1)]
347 ldr r2, [vcpu, #CP15_OFFSET(c13_CID)]
348 ldr r3, [vcpu, #CP15_OFFSET(c13_TID_URW)]
349 ldr r4, [vcpu, #CP15_OFFSET(c13_TID_URO)]
350 ldr r5, [vcpu, #CP15_OFFSET(c13_TID_PRIV)]
351 ldr r6, [vcpu, #CP15_OFFSET(c5_DFSR)]
352 ldr r7, [vcpu, #CP15_OFFSET(c5_IFSR)]
353 ldr r8, [vcpu, #CP15_OFFSET(c5_ADFSR)]
354 ldr r9, [vcpu, #CP15_OFFSET(c5_AIFSR)]
355 ldr r10, [vcpu, #CP15_OFFSET(c6_DFAR)]
356 ldr r11, [vcpu, #CP15_OFFSET(c6_IFAR)]
357 ldr r12, [vcpu, #CP15_OFFSET(c12_VBAR)]
375 ldr r2, [vcpu, #CP15_OFFSET(c1_SCTLR)]
376 ldr r3, [vcpu, #CP15_OFFSET(c1_CPACR)]
377 ldr r4, [vcpu, #CP15_OFFSET(c2_TTBCR)]
378 ldr r5, [vcpu, #CP15_OFFSET(c3_DACR)]
383 ldr r10, [vcpu, #CP15_OFFSET(c10_PRRR)]
384 ldr r11, [vcpu, #CP15_OFFSET(c10_NMRR)]
385 ldr r12, [vcpu, #CP15_OFFSET(c0_CSSELR)]
406 ldr r2, [vcpu, #VCPU_KVM]
407 ldr r2, [r2, #KVM_VGIC_VCTRL]
415 ldr r4, [r2, #GICH_VMCR]
416 ldr r5, [r2, #GICH_MISR]
417 ldr r6, [r2, #GICH_EISR0]
418 ldr r7, [r2, #GICH_EISR1]
419 ldr r8, [r2, #GICH_ELRSR0]
420 ldr r9, [r2, #GICH_ELRSR1]
421 ldr r10, [r2, #GICH_APR]
452 ldr r4, [r11, #VGIC_CPU_NR_LR]
453 1: ldr r6, [r2], #4
468 ldr r2, [vcpu, #VCPU_KVM]
469 ldr r2, [r2, #KVM_VGIC_VCTRL]
477 ldr r3, [r11, #VGIC_V2_CPU_HCR]
478 ldr r4, [r11, #VGIC_V2_CPU_VMCR]
479 ldr r8, [r11, #VGIC_V2_CPU_APR]
491 ldr r4, [r11, #VGIC_CPU_NR_LR]
492 1: ldr r6, [r3], #4
511 ldr r4, [vcpu, #VCPU_KVM]
512 ldr r2, [r4, #KVM_TIMER_ENABLED]
522 ldr r4, =VCPU_TIMER_CNTV_CVAL
555 ldr r4, [vcpu, #VCPU_KVM]
556 ldr r2, [r4, #KVM_TIMER_ENABLED]
560 ldr r2, [r4, #KVM_TIMER_CNTVOFF]
561 ldr r3, [r4, #(KVM_TIMER_CNTVOFF + 4)]
564 ldr r4, =VCPU_TIMER_CNTV_CVAL
570 ldr r2, [vcpu, #VCPU_TIMER_CNTV_CTL]
583 ldr r3, =HSTR_T(15)
601 ldr r3, =\mask
625 ldr r3, =(HDCR_TPM|HDCR_TPMCR)
637 ldr r2, [vcpu, #VCPU_HCR]
638 ldr r3, [vcpu, #VCPU_IRQ_LINES]
H A Dinit.S80 ldr r2, =HTCR_MASK
88 ldr r2, =VTCR_MASK
116 ldr r2, =HSCTLR_MASK
119 ldr r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
121 ARM( ldr r2, =(HSCTLR_M | HSCTLR_A) )
122 THUMB( ldr r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE) )
139 ldr r0, =TRAMPOLINE_VA
H A Dinterrupts.S138 ldr r1, [vcpu, #VCPU_MIDR]
142 ldr r1, [vcpu, #CP15_OFFSET(c0_MPIDR)]
146 ldr r1, [vcpu, #VCPU_KVM]
180 ldr r7, [r7]
310 ldr r2, =panic
312 ldr r0, =\panic_str
490 ldr r7, [r7]
/linux-4.4.14/arch/arm/boot/compressed/
H A Dhead-sharpsl.S27 ldr r7, .TOSAID
37 ldr r3, .PXA270ID
42 ldr r1, .W100ADDR @ Base address of w100 chip + regs offset
53 ldr r6, [r1, #0] @ Load Chip ID
54 ldr r3, .W100ID
55 ldr r7, .POODLEID
60 ldr r7, .CORGIID
61 ldr r3, .PXA255ID
67 ldr r7, .SHEPHERDID
72 ldr r7, .HUSKYID @ Must be Husky
78 ldr r7, .SPITZID
83 ldr r1, .SCOOP2ADDR
84 ldr r7, .BORZOIID
92 ldr r7, .AKITAID
H A Dll_char_wr.S52 ldr r4, [r4, ip]
53 ldr r5, [r5, ip]
68 ldr r7, [lr, r7, lsl #2]
73 ldr r7, [lr, r7, lsl #2]
87 ldr ip, [lr, ip, lsl #2]
90 ldr ip, [lr, ip, lsl #2] @ avoid r4
97 ldr ip, [lr, ip, lsl #2]
100 ldr ip, [lr, ip, lsl #2] @ avoid r4
H A Ddebug.S22 ldr r1, [r2, r3]
H A Dhead-xscale.S23 1: ldr r0, [r2], #32
H A Dhead-sa1100.S37 1: ldr r0, [r2], #32
H A Dhead.S203 ldr r4, =zreladdr
222 ldr sp, [r0, #28]
279 ldr lr, [r6, #0]
281 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
283 ldr r1, =0xd00dfeed
299 ldr r5, [r6, #4]
351 ldr r5, =_kernel_bss_size
358 ldr r5, [r6, #4]
487 1: ldr r1, [r11, #0] @ relocate entries in the GOT
506 1: ldr r1, [r11, #0] @ relocate entries in the GOT
556 ldr r0, [r12]
585 params: ldr r0, =0x10000100 @ params_phys for RPC
851 ldr r9, =CONFIG_PROCESSOR_ID
853 1: ldr r1, [r12, #0] @ get value
854 ldr r2, [r12, #4] @ get mask
1171 ldr r4, =0x3ff
1174 ldr r7, =0x7fff
1237 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
1238 THUMB( ldr r3, [r1] ) @ s/w flush D cache
1315 ldr r0, [r12, r11, lsl #2]
/linux-4.4.14/arch/arm/mach-tegra/
H A Dsleep-tegra30.S84 ldr \rd, [\base, #EMC_ADR_CFG]
94 ldr \rd, [\base, #EMC_EMC_STATUS]
100 ldr \rd, [\r_car_base, #\pll_base]
106 ldr \rd, [\r_car_base, #\pll_misc]
109 ldr \rd, [\r_car_base, #\pll_misc]
110 ldr \rd, [\r_car_base, #\pll_misc]
118 ldr \rd, [\r_car_base, #\pll_base]
124 ldr \rd, [\car, #\iddq]
130 ldr \rd, [\car, #\iddq]
168 ldr r12, =TEGRA_FLOW_CTRL_VIRT
195 ldr r3, [r1] @ read CSR
214 ldr r0, [r2]
345 ldr r1, [r7]
351 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
364 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
383 ldr r1, [r7]
389 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
392 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
403 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
420 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
422 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
424 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
428 ldr r1, [r0, #EMC_CFG_DIG_DLL]
439 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
445 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
449 ldr r1, [r0, #EMC_CFG]
464 ldr r2, [r0, #EMC_EMC_STATUS]
471 ldr r2, [r0, #EMC_FBIO_CFG5]
480 ldr r2, [r7]
490 ldr r2, [r7]
499 ldr r2, [r7]
509 ldr r2, [r7]
516 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
518 ldr r1, [r5, #0x0] @ restore EMC_CFG
532 ldr r0, [r0, #PMC_SCRATCH41]
617 ldr r1, [r7]
626 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
631 ldr r1, [r7]
636 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
641 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
644 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
647 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
650 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
677 ldr r0, [r6, r2]
691 ldr r0, [r6, r2] /* memory barrier */
729 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
731 ldr r1, [r0]
753 ldr r1, [r0, #EMC_CFG]
760 ldr r1, [r7]
765 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
773 ldr r1, [r0, #EMC_EMC_STATUS]
783 ldr r2, [r0, #EMC_EMC_STATUS]
789 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
793 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
810 ldr r1, [r4, #PMC_CTRL]
H A Dsleep-tegra20.S57 ldr \rd, [\r_car_base, #\pll_base]
64 ldr \rd, [\base, #EMC_ADR_CFG]
101 ldr r2, =__tegra20_cpu1_resettable_status_offset
106 ldr r3, =TEGRA_FLOW_CTRL_VIRT
109 ldr r2, [r3, r1]
114 ldr r3, =TEGRA_CLK_RESET_VIRT
162 ldr r12, [r3]
191 ldr r2, =__tegra20_cpu1_resettable_status_offset
205 ldr r2, =__tegra20_cpu1_resettable_status_offset
219 ldr r2, =__tegra20_cpu1_resettable_status_offset
264 ldr r4, =__tegra20_cpu1_resettable_status_offset
283 ldr r4, =__tegra20_cpu1_resettable_status_offset
362 ldr r6, tegra20_sdram_pad_size
364 ldr r7, [r2, r5] @ r7 is the addr in the pad_address
366 ldr r1, [r4, r5]
376 ldr r1, [r7]
381 ldr r4, [r4]
387 ldr r1, [r0, #EMC_CFG]
401 ldr r2, [r0, #EMC_EMC_STATUS]
409 ldr r0, [r0, #PMC_SCRATCH41]
444 ldr r1, [r7]
449 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
452 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
455 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
481 ldr r0, [r6, r1] /* memory barrier */
503 ldr r2, [r1, #EMC_EMC_STATUS]
513 ldr r3, [r1, #EMC_EMC_STATUS]
523 ldr r6, tegra20_sdram_pad_size
525 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
527 ldr r1, [r0]
530 ldr r1, [r3, r5]
539 ldr r0, [r5, #CLK_RESET_SCLK_BURST]
H A Dreset-handler.S61 ldr r1, [r2, r1]
77 ldr r1, [r0]
162 ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
180 ldr r8, [r12, #RESET_DATA(MASK_LP1)]
185 ldr lr, [r12, #RESET_DATA(STARTUP_LP1)]
193 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
196 ldr lr, [r12, #RESET_DATA(STARTUP_LP2)]
213 ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
253 ldr r0, [r6, +r2]
261 ldr r0, [r6, +r1] @ memory barrier
H A Dsleep.h56 1001: ldr \tmp, [\base]
122 ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
H A Dsleep.S107 ldr r1, [r6]
/linux-4.4.14/arch/arm/mach-omap1/
H A Dams-delta-fiq-handler.S100 ldr r12, omap_ih1_base @ set pointer to level1 handler
102 ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
104 ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
108 ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
126 ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank
128 ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
130 ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
149 ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
151 ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
172 data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
189 ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
194 ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count
195 ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size
202 ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset
207 ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address
209 ldr r8, [r9, #BUF_KEY] @ get last keycode
215 ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter
232 ldr r10, [r9, #BUF_CNT_INT_HSW]
247 ldr r10, [r9, #BUF_CNT_INT_MDM]
254 ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler
258 ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank
H A Dsleep.S82 ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
88 ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
158 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
167 ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
173 ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
237 ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
243 ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
/linux-4.4.14/arch/arm/mach-shmobile/
H A Dheadsmp.S27 ldr r0, 2f
28 ldr r1, 1f
58 ldr r8, [r5, r1, lsl #2]
62 ldr r9, [r6, r1, lsl #2]
74 ldr r0, [r7, r1, lsl #2]
H A Dheadsmp-scu.S33 ldr r2, [r0, #8] @ SCU Power Status Register
/linux-4.4.14/arch/arm/mach-davinci/
H A Dsleep.S55 ldr ip, CACHE_FLUSH
65 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
70 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
85 ldr ip, [r3, #PLLDIV1]
90 ldr ip, [r3, #PLLCTL]
101 ldr ip, [r3, #PLLCTL]
106 ldr ip, [r4]
114 ldr ip, [r4]
121 ldr ip, [r3, #PLLCTL]
126 ldr ip, [r3, #PLLCTL]
135 ldr ip, [r3, #PLLCTL]
145 ldr ip, [r3, #PLLCTL]
152 ldr ip, [r3, #PLLDIV1]
166 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
170 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
190 ldr ip, [r1, r6]
196 ldr ip, [r1, #PTCMD]
202 ldr ip, [r1, #PTSTAT]
211 ldr ip, [r1, r6]
/linux-4.4.14/arch/arm/lib/
H A Dcsumpartialcopy.S38 ldr \reg1, [r0], #4
42 ldr \reg1, [r0], #4
43 ldr \reg2, [r0], #4
H A Dbacktrace.S42 ldr r0, [sp], #4 @ by stmfd for this CPU
64 1001: ldr sv_pc, [frame, #0] @ get saved pc
65 1002: ldr sv_fp, [frame, #-12] @ get saved fp
70 1003: ldr r2, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
71 ldr r3, .Ldsi+4 @ adjust saved 'pc' back one
76 ldr r1, [frame, #-4] @ get saved lr
81 ldr r1, [sv_pc, #-4] @ if stmfd sp!, {args} exists,
82 ldr r3, .Ldsi+4
88 1004: ldr r1, [sv_pc, #0] @ if stmfd sp!, {..., fp, ip, lr, pc}
89 ldr r3, .Ldsi @ instruction exists,
134 ldr r2, [stack], #-4
H A Dio-writesw-armv4.S61 ldr r3, [r1], #4
78 ARM( ldr r3, [r1, -r3]! )
80 THUMB( ldr r3, [r1, r3] )
90 ldr r3, [r1, #4]!
H A Dgetuser.S64 4: TUSER(ldr) r2, [r0]
72 5: TUSER(ldr) r2, [r0]
73 6: TUSER(ldr) r3, [r0, #4]
75 5: TUSER(ldr) r2, [r0], #4
76 6: TUSER(ldr) r3, [r0]
89 7: ldr r2, [r0, #4]
120 11: TUSER(ldr) r3, [r0]
H A Dcsumpartial.S31 ldr pc, [sp], #4
75 ldr td0, [sp], #4
78 ldr pc, [sp], #4 @ return
136 4: ldr td0, [buf], #4
H A Dmemcpy.S21 W(ldr) \reg, [\ptr], #4
33 ldr\cond\()b \reg, [\ptr], #1
H A Dbitops.h70 ldr r2, [r1, r0, lsl #2]
95 ldr r2, [r1, r0, lsl #2]!
H A Dcopy_to_user.S45 W(ldr) \reg, [\ptr], #4
57 ldr\cond\()b \reg, [\ptr], #1
H A Dcopy_from_user.S106 ldr r0, [sp], #4
H A Dcsumpartialcopyuser.S88 ldr r5, [sp, #8*4] @ *err_ptr
H A Ddiv64.S209 ldr pc, [sp], #8
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A Dsleep-s3c2410.S46 ldr r4, =S3C2410_REFRESH
47 ldr r5, =S3C24XX_MISCCR
48 ldr r6, =S3C2410_CLKCON
49 ldr r7, [r4] @ get REFRESH (and ensure in TLB)
50 ldr r8, [r5] @ get MISCCR (and ensure in TLB)
51 ldr r9, [r6] @ get CLKCON (and ensure in TLB)
H A Dsleep-s3c2412.S36 ldr r1, =S3C2410_INTPND
37 ldr r2, =S3C2410_SRCPND
38 ldr r3, =S3C2410_EINTPEND
H A Dpm-h1940.S33 ldr pc, [r0, #S3C2410_GSTATUS3 - S3C24XX_VA_GPIO]
/linux-4.4.14/arch/arm/mach-gemini/include/mach/
H A Dentry-macro.S19 ldr \irqstat, =IO_ADDRESS(GEMINI_INTERRUPT_BASE + IRQ_STATUS)
20 ldr \irqnr, [\irqstat]
/linux-4.4.14/arch/arm/vfp/
H A Dentry.S29 ldr r4, .LCvfp
30 ldr r11, [r10, #TI_CPU] @ CPU number
32 ldr pc, [r4] @ call VFP entry point
50 ldr r0, VFP_arch_address
H A Dvfphw.S28 ldr r0, =1f
43 ldr r0, =1f
60 ldr r0, =1f
84 ldr r3, [sp, #S_PSR] @ Neither lazy restore nor FP exceptions
95 ldr r3, vfp_current_hw_state_address
97 ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer
141 ldr ip, [r10, #VFP_CPU]
/linux-4.4.14/arch/arm/mach-rockchip/
H A Dsleep.S39 ldr r3, rkpm_bootdata_l2ctlr_f
42 ldr r3, rkpm_bootdata_l2ctlr
45 ldr sp, rkpm_bootdata_cpusp
46 ldr r1, rkpm_bootdata_cpu_code
H A Dheadsmp.S19 ldr pc, 1f
/linux-4.4.14/firmware/av7110/
H A DBoot.S55 reset: ldr r13, buffer
56 ldr r4, flag
61 ldr r1, wait_address
62 ldr r2, flag_address
63 ldr r3, sram
70 ldr pc, sram // jump to the copied code
77 ldr r3, [r4,#4] // destaddr
/linux-4.4.14/arch/arm/mach-lpc32xx/
H A Dsuspend.S46 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
47 ldr EMCBASE_REG, [WORK1_REG, #4]
49 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
56 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
61 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
76 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
87 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
93 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
112 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
134 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
/linux-4.4.14/arch/arm/mach-lpc32xx/include/mach/
H A Dentry-macro.S25 ldr \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
33 ldr \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
/linux-4.4.14/arch/arm/mach-s3c64xx/
H A Dsleep.S44 ldr r2, =LL_UART /* for debug */
59 ldr r3, =S3C64XX_PA_GPIO
60 ldr r0, [ r3, #S3C64XX_GPNCON ]
67 ldr r0, [ r3, #S3C64XX_GPNDAT ]
/linux-4.4.14/arch/arm/mach-zynq/
H A Dheadsmp.S15 ldr r0, zynq_secondary_trampoline_jump
/linux-4.4.14/arch/arm/include/asm/
H A Dvfpmacros.h28 ldr \tmp, =elf_hwcap @ may not have MVFR regs
29 ldr \tmp, [\tmp, #0]
52 ldr \tmp, =elf_hwcap @ may not have MVFR regs
53 ldr \tmp, [\tmp, #0]
H A Dchecksum.h66 "ldr %0, [%1], #4 @ ip_fast_csum \n\ ip_fast_csum()
67 ldr %3, [%1], #4 \n\ ip_fast_csum()
70 ldr %3, [%1], #4 \n\ ip_fast_csum()
72 ldr %3, [%1], #4 \n\ ip_fast_csum()
74 ldr %3, [%1], #4 \n\ ip_fast_csum()
H A Dword-at-a-time.h72 "1: ldr %0, [%2]\n" load_unaligned_zeropad()
78 " ldr %0, [%2]\n" load_unaligned_zeropad()
H A Dfutex.h87 "1: " TUSER(ldr) " %1, [%3]\n" \
112 "1: " TUSER(ldr) " %1, [%4]\n" futex_atomic_cmpxchg_inatomic()
H A Dtls.h20 ldr \tmp1, =elf_hwcap
21 ldr \tmp1, [\tmp1, #0]
H A Dassembler.h214 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
220 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
433 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
489 ldr r0, [sp, #S_FRAME_SIZE]
/linux-4.4.14/arch/arm/mach-berlin/
H A Dheadsmp.S22 ldr pc, [pc, #140]
/linux-4.4.14/arch/arm/mach-ep93xx/
H A Dcrunch-bits.S71 ldr r8, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
73 ldr r1, [r8, #0x80]
81 ldr r3, =crunch_owner
83 ldr r2, [sp, #60] @ current task pc value
84 ldr r1, [r3] @ get current crunch owner
89 ldr r2, [r8, #0x80]
216 ldr r4, =(EP93XX_APB_VIRT_BASE + 0x00130000) @ syscon addr
218 ldr r3, =crunch_owner
220 ldr r1, [r3] @ get current crunch owner
227 ldr r5, [r4, #0x80] @ enable access to crunch
235 ldr r2, [r4, #0x80] @ flush out enable (@@@)
243 ldr r5, [r4, #0x80] @ flush out enable (@@@)
262 ldr r3, =crunch_owner
264 ldr r3, [r3] @ get current crunch owner
295 ldr r3, =crunch_owner
297 ldr r3, [r3] @ get current crunch owner
/linux-4.4.14/tools/perf/arch/arm64/tests/
H A Dregs_load.S6 #define LDR_REG(r) ldr x##r, [x0, 8 * r]
/linux-4.4.14/arch/arm/mach-uniphier/
H A Dheadsmp.S23 ldr r1, uniphier_smp_trampoline_jump
24 ldr r3, uniphier_smp_trampoline_poll_addr
31 1: ldr r0, [r3]
/linux-4.4.14/arch/arm/mm/
H A Dabort-lv4t.S28 ldr r8, [r4] @ read arm instruction
40 /* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
41 /* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
42 /* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
43 /* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
48 /* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
73 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
91 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
105 ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
117 ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
202 ldr r7, [r2, #13 << 2]
218 ldr r7, [r2, r9, lsr #6]
H A Dproc-v7m.S85 ldr r0, =BASEADDR_V7M_SCB
86 ldr r12, =vector_table
90 ldr r5, [r0, #V7M_SCB_SHCSR]
102 ldr r5, [r12, #11 * 4] @ read the SVC vector entry
106 ldr sp, =__v7m_setup_stack_top
120 ldr r12, [r0, V7M_SCB_CCR] @ system control register
H A Dproc-arm740.S77 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
78 ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
87 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
88 ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
H A Dproc-sa110.S96 ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc
97 ldr r1, [r1, #0] @ force switch to MCLK
142 ldr pc, [sp], #4
H A Dcache-v4wb.S82 ldr r3, =flush_base
83 ldr r1, [r3, #0]
87 1: ldr r3, [r1], #32
93 1: ldr r3, [r1], #32
H A Dproc-arm940.S299 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
300 ldr r7, =CONFIG_DRAM_SIZE >> 12 @ size of RAM (must be >= 4KB)
305 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
306 ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
H A Dproc-arm946.S345 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
346 ldr r7, =CONFIG_DRAM_SIZE @ size of RAM (must be >= 4KB)
350 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
351 ldr r7, =CONFIG_FLASH_SIZE @ size of FLASH (must be >= 4KB)
H A Dpv-fixup-asm.S32 ldr r6, =(_end - 1)
H A Dproc-sa1100.S109 ldr r1, =UNCACHEABLE_ADDR @ ptr to uncacheable address
112 ldr r1, [r1, #0] @ force switch to MCLK
153 ldr pc, [sp], #4
H A Dproc-v7.S139 ldr r4, =PRRR @ PRRR
140 ldr r5, =NMRR @ NMRR
433 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
438 ldr r10, =0x00000c09 @ Cortex-A9 primary part number
443 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
453 ldr r3, =PRRR @ PRRR
454 ldr r6, =NMRR @ NMRR
H A Dproc-arm720.S127 ldr r5, arm710_cr1_clear
129 ldr r5, arm710_cr1_set
H A Dproc-fa526.S161 ldr r5, fa526_cr1_clear
163 ldr r5, fa526_cr1_set
H A Dproc-v7-3level.S130 ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address
H A Dproc-xscale.S89 ldr \rs, =clean_addr
90 ldr \rd, [\rs]
519 ldr ip, [ip, r1]
H A Dcache-v6.S253 ldr r2, [r0] @ read for ownership
H A Dproc-feroceon.S61 ldr r1, __cache_params
159 ldr r1, __cache_params
/linux-4.4.14/arch/arm64/lib/
H A Dmemcmp.S75 ldr data1, [src1], #8
76 ldr data2, [src2], #8
111 ldr data1, [src1], #8
112 ldr data2, [src2], #8
178 ldr data1, [src1], #8
179 ldr data2, [src2], #8
199 ldr data1, [src1,pos]
200 ldr data2, [src2,pos]
205 ldr data1, [src1], #8
206 ldr data2, [src2], #8
H A Dstrcmp.S77 ldr data1, [src1], #8
78 ldr data2, [src2], #8
97 ldr data1, [src1], #8
99 ldr data2, [src2], #8
145 ldr data1, [src1], #8
146 ldr data2, [src2], #8
168 ldr data1, [src1,pos]
169 ldr data2, [src2,pos]
178 ldr data1, [src1], #8
179 ldr data2, [src2], #8
H A Dstrncmp.S89 ldr data1, [src1], #8
90 ldr data2, [src2], #8
132 ldr data1, [src1], #8
134 ldr data2, [src2], #8
194 ldr data1, [src1], #8
195 ldr data2, [src2], #8
222 ldr data1, [src1,pos]
223 ldr data2, [src2,pos]
232 ldr data1, [src1], #8
233 ldr data2, [src2], #8
H A Dmemmove.S91 ldr tmp1w, [src, #-4]!
95 ldr tmp1, [src, #-8]!
127 ldr tmp1, [src, #-8]!
131 ldr tmp1w, [src, #-4]!
/linux-4.4.14/arch/arm64/kernel/vdso/
H A Dgettimeofday.S33 9999: ldr seqcnt, [vdso_data, #VDSO_TB_SEQ_COUNT]
36 ldr use_syscall, [vdso_data, #VDSO_USE_SYSCALL]
41 ldr \cnt, [vdso_data, #VDSO_TB_SEQ_COUNT]
181 ldr x2, 5f
187 ldr x2, 6f
220 ldr x10, [vdso_data, #VDSO_CS_CYCLE_LAST]
/linux-4.4.14/sound/oss/
H A Dvidc_fill.S36 ldr r4, [r0], #2
62 ldr r4, [r0], #2
77 ldr r5, [r0], #2
95 ldr r4, [r0], #4
138 ldr r8, =dma_start
176 ldr lr, [ip, #IOMD_SD0ST]
/linux-4.4.14/arch/arm64/kernel/
H A Dentry-ftrace.S64 ldr \reg, [x29]
65 ldr \reg, [\reg]
74 ldr \reg, [x29, #8]
79 ldr \reg, [x29]
80 ldr \reg, [\reg, #8]
85 ldr \reg, [x29]
102 ldr x2, [x0, #:lo12:ftrace_trace_function]
119 ldr x2, [x1, #:lo12:ftrace_graph_return]
125 ldr x2, [x1, #:lo12:ftrace_graph_entry]
H A Dsleep.S83 ldr x1, =sleep_save_sp
84 ldr x1, [x1, #SLEEP_SAVE_SP_VIRT]
86 ldr x9, =mpidr_hash
87 ldr x10, [x9, #MPIDR_HASH_MASK]
133 ldr x3, =cpu_resume_after_mmu
164 ldr x2, [x8, #MPIDR_HASH_MASK]
170 ldr x0, [x0, x7, lsl #3]
172 ldr x2, [x0, #CPU_CTX_SP]
H A Dentry.S92 ldr x19, [tsk, #TI_FLAGS] // since we can unmask debug
123 ldr x23, [sp, #S_SP] // load return stack pointer
161 ldr lr, [sp, #S_LR]
187 ldr x1, [x1, #:lo12:handle_arch_irq]
365 ldr w24, [tsk, #TI_PREEMPT] // get preempt count
367 ldr x0, [tsk, #TI_FLAGS] // get flags
382 ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
600 ldr lr, [x8]
612 ldr x1, [tsk, #TI_FLAGS] // re-check for syscall tracing
629 ldr x2, [sp, #S_PSTATE]
644 ldr x1, [tsk, #TI_FLAGS]
677 ldr x16, [tsk, #TI_FLAGS] // check for syscall hooks
682 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
713 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
H A Defi-entry.S63 ldr x0, [sp, #16] // relocated _text address
64 ldr x21, =stext_offset
H A Dhead.S222 ldr x27, =__mmap_switched // address to jump to after
336 ldr x7, =SWAPPER_MM_MMUFLAGS
394 ldr x6, =KERNEL_END // __va(KERNEL_END)
578 ldr x1, =MPIDR_HWID_BITMASK
581 pen: ldr x4, [x3]
606 ldr x21, =secondary_data
607 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
612 ldr x0, [x21] // get secondary_data.stack
635 ldr x5, =vectors
/linux-4.4.14/arch/arm/mach-socfpga/
H A Dself-refresh.S65 ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
72 ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
101 ldr r2, [r0, #SDR_CTRLGRP_LOWPWREQ_ADDR]
108 ldr r2, [r0, #SDR_CTRLGRP_LOWPWRACK_ADDR]
/linux-4.4.14/arch/arm/mach-mvebu/
H A Dcoherency_ll.S42 ldr r1, =coherency_base
46 ldr r3, [r1]
47 ldr r1, [r1, r3]
54 ldr r1, =coherency_base
55 ldr r1, [r1]
H A Dpmsu_ll.S62 ldr r0, [r0] @ load the address of the
64 ldr r0, [r0] @ load the value in the
/linux-4.4.14/arch/arm/probes/kprobes/
H A Dtest-thumb.c159 TEST_X( "ldr r0, 3f", kprobe_thumb16_test_cases()
162 TEST_X( "ldr r7, 3f", kprobe_thumb16_test_cases()
177 TEST_PR( "ldr r0, [r",1, 24,", r",2, 48,"]") kprobe_thumb16_test_cases()
178 TEST_PR( "ldr r7, [r",6, 24,", r",5, 48,"]") kprobe_thumb16_test_cases()
188 TEST_P( "ldr r0, [r",1, 24,", #120]") kprobe_thumb16_test_cases()
189 TEST_P( "ldr r7, [r",6, 24,", #120]") kprobe_thumb16_test_cases()
201 TEST( "ldr r0, [sp, #0]") kprobe_thumb16_test_cases()
202 TEST( "ldr r7, [sp, #160]") kprobe_thumb16_test_cases()
205 TEST_P( "ldr r0, [r",0, 24,"]") kprobe_thumb16_test_cases()
858 TEST_P( "ldr"size" r0, [r",11,-1024, ", #1024]") \ kprobe_thumb32_test_cases()
859 TEST_P( "ldr"size" r14, [r",1, -1024,", #1080]") \ kprobe_thumb32_test_cases()
860 TEST_P( "ldr"size" r0, [r",11,256, ", #-120]") \ kprobe_thumb32_test_cases()
861 TEST_P( "ldr"size" r14, [r",1, 256, ", #-128]") \ kprobe_thumb32_test_cases()
862 TEST_P( "ldr"size" r0, [r",11,24, "], #120") \ kprobe_thumb32_test_cases()
863 TEST_P( "ldr"size" r14, [r",1, 24, "], #128") \ kprobe_thumb32_test_cases()
864 TEST_P( "ldr"size" r0, [r",11,24, "], #-120") \ kprobe_thumb32_test_cases()
865 TEST_P( "ldr"size" r14, [r",1,24, "], #-128") \ kprobe_thumb32_test_cases()
866 TEST_P( "ldr"size" r0, [r",11,24, ", #120]!") \ kprobe_thumb32_test_cases()
867 TEST_P( "ldr"size" r14, [r",1, 24, ", #128]!") \ kprobe_thumb32_test_cases()
868 TEST_P( "ldr"size" r0, [r",11,256, ", #-120]!") \ kprobe_thumb32_test_cases()
869 TEST_P( "ldr"size" r14, [r",1, 256, ", #-128]!") \ kprobe_thumb32_test_cases()
870 TEST_PR("ldr"size".w r0, [r",1, 0,", r",2, 4,"]") \ kprobe_thumb32_test_cases()
871 TEST_PR("ldr"size" r14, [r",10,0,", r",11,4,", lsl #1]") \ kprobe_thumb32_test_cases()
872 TEST_X( "ldr"size".w r0, 3f", \ kprobe_thumb32_test_cases()
875 TEST_X( "ldr"size".w r14, 3f", \ kprobe_thumb32_test_cases()
878 TEST( "ldr"size".w r7, 3b") \ kprobe_thumb32_test_cases()
879 TEST( "ldr"size".w r7, [sp, #24]") \ kprobe_thumb32_test_cases()
880 TEST_P( "ldr"size".w r0, [r",0,0, "]") \ kprobe_thumb32_test_cases()
881 TEST_UNSUPPORTED("ldr"size"t r0, [r1, #4]") kprobe_thumb32_test_cases()
889 TEST_BF_P("ldr pc, [r",14, 15*4,"]") kprobe_thumb32_test_cases()
890 TEST_P( "ldr sp, [r",14, 13*4,"]") kprobe_thumb32_test_cases()
891 TEST_BF_R("ldr pc, [sp, r",14, 15*4,"]") kprobe_thumb32_test_cases()
892 TEST_R( "ldr sp, [sp, r",14, 13*4,"]") kprobe_thumb32_test_cases()
893 TEST_THUMB_TO_ARM_INTERWORK_P("ldr pc, [r",0,0,", #15*4]") kprobe_thumb32_test_cases()
894 TEST_SUPPORTED("ldr sp, 99f") kprobe_thumb32_test_cases()
895 TEST_SUPPORTED("ldr pc, 99f") kprobe_thumb32_test_cases()
897 TEST_UNSUPPORTED(__inst_thumb32(0xf854700d) " @ ldr r7, [r4, sp]") kprobe_thumb32_test_cases()
898 TEST_UNSUPPORTED(__inst_thumb32(0xf854700f) " @ ldr r7, [r4, pc]") kprobe_thumb32_test_cases()
H A Dactions-common.c97 "ldr pc, [sp], #4 \n\t" emulate_generic_r0_12_noflags()
100 "ldr lr, [sp], #4 \n\t" /* lr = regs */ emulate_generic_r0_12_noflags()
102 "ldr r11, [sp], #4 \n\t" emulate_generic_r0_12_noflags()
H A Dtest-arm.c670 TEST_P( "ldr"byte" r0, [r",0, 24,", #-2]") \ kprobe_arm_test_cases()
671 TEST_P( "ldr"byte" r14, [r",13,0, ", #2]") \ kprobe_arm_test_cases()
672 TEST_P( "ldr"byte" r1, [r",2, 24,", #4]!") \ kprobe_arm_test_cases()
673 TEST_P( "ldr"byte" r12, [r",11,24,", #-4]!") \ kprobe_arm_test_cases()
674 TEST_P( "ldr"byte" r2, [r",3, 24,"], #48") \ kprobe_arm_test_cases()
675 TEST_P( "ldr"byte" r10, [r",9, 64,"], #-48") \ kprobe_arm_test_cases()
676 TEST_PR( "ldr"byte" r0, [r",0, 48,", -r",2, 24,"]") \ kprobe_arm_test_cases()
677 TEST_PR( "ldr"byte" r14, [r",13,0, ", r",12, 48,"]") \ kprobe_arm_test_cases()
678 TEST_PR( "ldr"byte" r1, [r",2, 24,", r",3, 48,"]!") \ kprobe_arm_test_cases()
679 TEST_PR( "ldr"byte" r12, [r",11,48,", -r",10,24,"]!") \ kprobe_arm_test_cases()
680 TEST_PR( "ldr"byte" r2, [r",3, 24,"], r",4, 48,"") \ kprobe_arm_test_cases()
681 TEST_PR( "ldr"byte" r10, [r",9, 48,"], -r",11,24,"") \ kprobe_arm_test_cases()
682 TEST_PR( "ldr"byte" r0, [r",0, 24,", r",2, 32,", asl #1]") \ kprobe_arm_test_cases()
683 TEST_PR( "ldr"byte" r14, [r",13,0, ", r",12, 32,", lsr #2]") \ kprobe_arm_test_cases()
684 TEST_PR( "ldr"byte" r1, [r",2, 24,", r",3, 32,", asr #3]!") \ kprobe_arm_test_cases()
685 TEST_PR( "ldr"byte" r12, [r",11,24,", r",10, 4,", ror #31]!") \ kprobe_arm_test_cases()
686 TEST( "ldr"byte" r0, [pc, #0]") \ kprobe_arm_test_cases()
687 TEST_R( "ldr"byte" r12, [pc, r",14,0,"]") kprobe_arm_test_cases()
692 TEST_BF( "ldr pc, [sp, #15*4]") kprobe_arm_test_cases()
693 TEST_BF_R("ldr pc, [sp, r",2,15*4,"]") kprobe_arm_test_cases()
697 TEST_BF( "ldr sp, [sp, #13*4]") kprobe_arm_test_cases()
698 TEST_BF_R("ldr sp, [sp, r",2,13*4,"]") kprobe_arm_test_cases()
701 TEST_ARM_TO_THUMB_INTERWORK_P("ldr pc, [r",0,0,", #15*4]") kprobe_arm_test_cases()
705 TEST_UNSUPPORTED(__inst_arm(0xe5bf6008) " @ ldr r6, [pc, #8]!") kprobe_arm_test_cases()
706 TEST_UNSUPPORTED(__inst_arm(0xe7bf6008) " @ ldr r6, [pc, r8]!") kprobe_arm_test_cases()
708 TEST_UNSUPPORTED(__inst_arm(0xe798600f) " @ ldr r6, [r8, pc]") kprobe_arm_test_cases()
H A Dopt-arm.c60 " ldr r0, 1f\n"
61 " ldr r2, 2f\n"
76 " ldr r1, [sp, #64]\n"
H A Dcheckers-thumb.c32 * First, filter out all ldr insns to make our life easier. t32_check_stack()
H A Dcore.c545 "ldr r0, ="__stringify(JPROBE_MAGIC_ADDR)"\n\t" jprobe_return()
556 "ldr lr, [sp, %2] \n\t" /* lr = saved sp */ jprobe_return()
558 "ldr r2, [sp, %4] \n\t" /* r2 = saved psr */ jprobe_return()
563 "ldr lr, [sp], #4 \n\t" jprobe_return()
566 "ldr r0, [sp, %4] \n\t" jprobe_return()
H A Dactions-thumb.c530 "ldr r9, [%[regs], #13*4] \n\t" t16_emulate_push()
531 "ldr r8, [%[regs], #14*4] \n\t" t16_emulate_push()
564 "ldr r9, [%[regs], #13*4] \n\t" t16_emulate_pop_nopc()
583 "ldr r9, [%[regs], #13*4] \n\t" t16_emulate_pop_pc()
/linux-4.4.14/drivers/spi/
H A Dspi-s3c24xx-fiq.S43 ldr fiq_rtmp, fiq_rx_irq_ack
73 ldr fiq_rtmp, fiq_txrx_irq_ack
98 ldr fiq_rtmp, fiq_tx_irq_ack
/linux-4.4.14/arch/arm/plat-versatile/
H A Dheadsmp.S28 pen: ldr r7, [r6]
/linux-4.4.14/arch/arm/mach-spear/
H A Dheadsmp.S30 pen: ldr r7, [r6]
/linux-4.4.14/arch/arm/mach-sti/
H A Dheadsmp.S31 pen: ldr r7, [r6]
/linux-4.4.14/drivers/media/rc/img-ir/
H A Dimg-ir-sanyo.c92 .ldr = {
117 .ldr = {
H A Dimg-ir-nec.c121 .ldr = {
146 .ldr = {
H A Dimg-ir-hw.h93 * @ldr: Leader symbol timing data
101 struct img_ir_symbol_timing ldr, s00, s01, s10, s11; member in struct:img_ir_timings
121 * @ldr: Leader symbol timing register value
129 u32 ldr, s00, s01, s10, s11, ft; member in struct:img_ir_timing_regvals
H A Dimg-ir-jvc.c64 .ldr = {
H A Dimg-ir-rc6.c92 .ldr = {
H A Dimg-ir-sony.c130 .ldr = {
H A Dimg-ir-hw.c91 img_ir_symbol_timing_preprocess(&timings->ldr, unit); img_ir_timings_preprocess()
123 img_ir_symbol_timing_defaults(&timings->ldr, &defaults->ldr); img_ir_timings_defaults()
300 regs->ldr = img_ir_symbol_timing(&timings->ldr, tolerance, clock_hz, img_ir_timings_convert()
387 img_ir_write(priv, IMG_IR_LEAD_SYMB_TIMING, regs->ldr); img_ir_write_timings()
393 dev_dbg(priv->dev, "timings: ldr=%#x, s=[%#x, %#x, %#x, %#x], ft=%#x\n", img_ir_write_timings()
394 regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft); img_ir_write_timings()
/linux-4.4.14/arch/unicore32/kernel/
H A Ddebug-macro.S78 1001: ldr \rd, [\rx, #UART_LSR_OFFSET]
84 1001: ldr \rd, [\rx, #UART_LSR_OFFSET]
/linux-4.4.14/arch/arm64/include/asm/
H A Dword-at-a-time.h69 "1: ldr %0, %3\n" load_unaligned_zeropad()
75 " ldr %0, [%2]\n" load_unaligned_zeropad()
H A Dassembler.h149 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where
178 ldr \dst, [\dst, :lo12:\sym]
181 ldr \dst, [\tmp, :lo12:\sym]
H A Dfpsimdmacros.h73 ldr w\tmpnr, [\state, #16 * 2]
75 ldr w\tmpnr, [\state, #16 * 2 + 4]
112 ldr w\tmpnr2, [\state, #8]
H A Dio.h91 asm volatile(ALTERNATIVE("ldr %w0, [%1]", __raw_readl()
102 asm volatile(ALTERNATIVE("ldr %0, [%1]", __raw_readq()
H A Dspinlock.h92 " ldr %w0, %2\n" arch_spin_trylock()
291 " ldr %w0, %2\n" arch_read_trylock()
H A Duaccess.h147 __get_user_asm("ldr", "%w", __gu_val, (ptr), (err)); \
150 __get_user_asm("ldr", "%", __gu_val, (ptr), (err)); \
/linux-4.4.14/drivers/scsi/arm/
H A Dacornscsi-io.S67 ldr r3, [r0], #4
123 ldr r4, [r1], #4
133 ldr r3, [r1], #2
/linux-4.4.14/arch/arm/xen/
H A Dhypercall.S73 ldr r4, [sp, #4] \
100 ldr r3, [sp, #8]
108 ldr r4, [sp, #4]
/linux-4.4.14/arch/arm/mach-s3c24xx/include/mach/
H A Dio.h58 "ldr" instr " %1, [%0, #0 ] @ in" #fnsuffix \
184 "ldr %0, [%1, %2] @ inlc" \
188 "ldr %0, [%1, #0] @ inlc" \
/linux-4.4.14/arch/arm/boot/bootp/
H A Dinit.S40 ldr r10, [r9, #4] @ get first tag
54 taglist: ldr r10, [r9, #0] @ tag length
/linux-4.4.14/arch/arm/common/
H A Dvlock.S78 MANY( ldr r2, [r0, r3] )
79 FEW( ldr r2, [r0, #VLOCK_VOTING_OFFSET] )
H A Dmcpm_head.S79 ldr r7, [r5, r7] @ r7 = mcpm_power_up_setup_phys
196 ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
/linux-4.4.14/arch/arm/nwfpe/
H A Dentry.S37 ldr r4, .LC2
38 ldr pc, [r4] @ Call FP emulator entry point
82 ldr r5, [sp, #S_PC] @ get contents of PC;
85 ldr r1, [sp, #S_PSR] @ fetch the PSR
/linux-4.4.14/arch/unicore32/mm/
H A Dalignment.c385 case 0x60000000: /* ldr or str immediate */ do_alignment()
386 case 0x60000100: /* ldr or str immediate */ do_alignment()
387 case 0x60000020: /* ldr or str immediate */ do_alignment()
388 case 0x60000120: /* ldr or str immediate */ do_alignment()
393 case 0x40000000: /* ldr or str register */ do_alignment()
/linux-4.4.14/drivers/net/ethernet/amd/
H A Dam79c961a.c64 "ldr%?h %0, [%2, #-4] @ NET_RDP" read_rreg()
84 "ldr%?h %0, [%2, #8] @ NET_IDP\n\t" read_ireg()
135 "ldr%?h %2, [%0], #4\n\t" am_readbuffer()
145 "ldr%?h %2, [%0], #4\n\t" am_readbuffer()
146 "ldr%?h %4, [%0], #4\n\t" am_readbuffer()
147 "ldr%?h %3, [%0], #4\n\t" am_readbuffer()
149 "ldr%?h %4, [%0], #4\n\t" am_readbuffer()
159 "ldr%?h %2, [%0], #4\n\t" am_readbuffer()
/linux-4.4.14/arch/arm/include/asm/hardware/
H A Dentry-macro-iomd.S16 ldr \tmp, =irq_prio_h
/linux-4.4.14/arch/arm64/mm/
H A Dproc.S103 ldr x12, [x0, #80]
172 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
191 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
/linux-4.4.14/arch/arm64/crypto/
H A Daes-modes.S307 ldr q8, =0x30000000200000001 /* addends 1,2,3[,0] */
399 ldr q7, .Lxts_mul_x
403 ldr q7, .Lxts_mul_x
471 ldr q7, .Lxts_mul_x
475 ldr q7, .Lxts_mul_x
H A Daes-neon.S28 ldr q13, \shiftrows
245 ldr q13, .LForward_ShiftRows
248 ldr q13, .LReverse_ShiftRows
275 ldr q13, .LForward_ShiftRows
278 ldr q13, .LReverse_ShiftRows
/linux-4.4.14/arch/arm/mach-hisi/
H A Dplatsmp.c112 writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */ hix5hd2_set_scu_boot_addr()
/linux-4.4.14/drivers/net/wireless/
H A Datmel.c4348 ldr r0, =SPI_CGEN_BASE
4353 ldr r1, [r0, #28]
4359 ldr r0, =MRBASE
4372 ldr r0, =MRBASE
4373 ldr r1, =MAC_ADDRESS_MIB
4375 ldr r1, =NVRAM_IMAGE
4386 ldr r0, =NVRAM_IMAGE
4398 ldr r0, =MAC_ADDRESS_MIB
4418 ldr r0, =SP_BASE
4427 ldr r3, =SPI_CGEN_BASE
4428 ldr r1, [r3, #28]
4432 ldr r1, =0x2000c01
4434 ldr r1, =0x2000201
4438 ldr r1, [r0, #SP_SR]
4439 ldr r0, [r0, #SP_RDR]
4444 ldr r1, =SP_BASE
4445 ldr r0, [r1, #SP_RDR]
4449 ldr r0, [r1, #SP_SR]
4456 ldr r0, [r1, #SP_SR]
4460 ldr r0, [r1, #SP_RDR]
4462 ldr r0, [r1, #SP_SR]
4466 ldr r0, [r1, #SP_RDR]
4483 ldr r1, =NVRAM_SCRATCH
4503 ldr r4, =SP_BASE
4507 ldr r5, =NVRAM_SCRATCH
4512 ldr r6, [r4, #SP_SR]
4521 ldr r0, [r4, #SP_RDR]
4523 ldr r0, [r4, #SP_SR]
4526 ldr r0, [r4, #SP_RDR] /* what's this byte? It's the byte read while writing the TDR -- nonsense, because the NVRAM doesn't read and write at the same time */
4531 ldr r5, [r4, #SP_SR]
4536 ldr r5, [r4, #SP_SR]
4539 ldr r5, [r4, #SP_RDR] /* but didn't we read this byte above? */
/linux-4.4.14/drivers/net/ethernet/i825xx/
H A Dether1.c151 1: ldr %0, [%1], #2\n\ ether1_writebuffer()
157 ldr %0, [%1], #2\n\ ether1_writebuffer()
163 ldr %0, [%1], #2\n\ ether1_writebuffer()
169 ldr %0, [%1], #2\n\ ether1_writebuffer()
214 1: ldr %0, [%2], #4\n\ ether1_readbuffer()
220 ldr %0, [%2], #4\n\ ether1_readbuffer()
226 ldr %0, [%2], #4\n\ ether1_readbuffer()
232 ldr %0, [%2], #4\n\ ether1_readbuffer()
/linux-4.4.14/drivers/power/reset/
H A Dat91-reset.c98 "ldr r0, [%1]\n\t" at91sam9g45_restart()
/linux-4.4.14/arch/x86/kvm/
H A Dlapic.c174 u32 ldr, aid; kvm_for_each_vcpu() local
180 ldr = kvm_apic_get_reg(apic, APIC_LDR); kvm_for_each_vcpu()
187 } else if (ldr) { kvm_for_each_vcpu()
188 ldr = GET_APIC_LOGICAL_ID(ldr); kvm_for_each_vcpu()
198 apic_logical_id(new, ldr, &cid, &lid); kvm_for_each_vcpu()
245 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); kvm_apic_set_x2apic_id() local
248 apic_set_reg(apic, APIC_LDR, ldr); kvm_apic_set_x2apic_id()
/linux-4.4.14/drivers/bus/
H A Darm-cci.c1825 " ldr r2, [r1] \n" cci_enable_port_for_self()
1830 "1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n" cci_enable_port_for_self()
1835 " ldr r3, [r1, %[offsetof_cpu_port_port]] \n" cci_enable_port_for_self()
1855 " ldr r0, [r0, r2] @ *(&ports) \n" cci_enable_port_for_self()
1861 " ldr r0, [r0, %[offsetof_port_phys]] \n" cci_enable_port_for_self()
1867 " ldr r0, [r1] \n" cci_enable_port_for_self()
1868 " ldr r0, [r0, r1] @ cci_ctrl_base \n" cci_enable_port_for_self()
1869 "4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n" cci_enable_port_for_self()
/linux-4.4.14/drivers/cpufreq/
H A Dsa1110-cpufreq.c288 ldr %0, [%1, #0] \n\ sa1110_target()
H A Dpxa2xx-cpufreq.c326 ldr r4, [%1] /* load MDREFR */ \n\ pxa_set_target()
/linux-4.4.14/arch/x86/include/asm/
H A Dapicdef.h239 } ldr; member in struct:local_apic
/linux-4.4.14/arch/arm/plat-iop/
H A Dpci.c97 "ldr %0, [%3]\n\t" iop3xx_read()
/linux-4.4.14/arch/arm/mach-footbridge/
H A Ddc21285.c80 asm("ldr %0, [%1, %2]" dc21285_read_config()

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