Lines Matching refs:ldr
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
77 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
110 ldr r9, [r8, #OMAP_TYPE_OFFSET]
119 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
164 ldr r0, =0xffff
167 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
168 ldr r1, =0xffff
182 ldr r0, [r2, #L2X0_CACHE_SYNC]
213 ldr r9, [r8, #OMAP_TYPE_OFFSET]
219 ldr r12, =OMAP4_MON_SCU_PWR_INDEX
254 ldr r8, =OMAP44XX_SAR_RAM_BASE
255 ldr r9, [r8, #OMAP_TYPE_OFFSET]
264 ldr r3, [r1]
290 ldr r2, =OMAP44XX_L2CACHE_BASE
291 ldr r0, [r2, #L2X0_CTRL]
295 ldr r3, =OMAP44XX_SAR_RAM_BASE
296 ldr r1, [r3, #OMAP_TYPE_OFFSET]
299 ldr r0, =OMAP4_PPA_L2_POR_INDEX
300 ldr r1, =OMAP44XX_SAR_RAM_BASE
301 ldr r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
303 ldr r3, [r1]
313 ldr r1, =OMAP44XX_SAR_RAM_BASE
314 ldr r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
315 ldr r12, =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
318 ldr r1, =OMAP44XX_SAR_RAM_BASE
319 ldr r0, [r1, #L2X0_AUXCTRL_OFFSET]
320 ldr r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
323 ldr r12, =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache