Lines Matching refs:ldr

40 	ldr	x2, [x0, #VCPU_KVM]
42 	ldr	x2, [x2, #KVM_VGIC_VCTRL]
50 	ldr	w5, [x2, #GICH_VMCR]
51 	ldr	w6, [x2, #GICH_MISR]
52 	ldr	w7, [x2, #GICH_EISR0]
53 	ldr	w8, [x2, #GICH_EISR1]
54 	ldr	w9, [x2, #GICH_ELRSR0]
55 	ldr	w10, [x2, #GICH_ELRSR1]
56 	ldr	w11, [x2, #GICH_APR]
82 	ldr	w4, [x3, #VGIC_CPU_NR_LR]
84 1:	ldr	w5, [x2], #4
100 	ldr	x2, [x0, #VCPU_KVM]
102 	ldr	x2, [x2, #KVM_VGIC_VCTRL]
110 	ldr	w4, [x3, #VGIC_V2_CPU_HCR]
111 	ldr	w5, [x3, #VGIC_V2_CPU_VMCR]
112 	ldr	w6, [x3, #VGIC_V2_CPU_APR]
123 	ldr	w4, [x3, #VGIC_CPU_NR_LR]
125 1:	ldr	w5, [x3], #4