Lines Matching refs:ldr
57 ldr \rd, [\r_car_base, #\pll_base]
64 ldr \rd, [\base, #EMC_ADR_CFG]
101 ldr r2, =__tegra20_cpu1_resettable_status_offset
106 ldr r3, =TEGRA_FLOW_CTRL_VIRT
109 ldr r2, [r3, r1]
114 ldr r3, =TEGRA_CLK_RESET_VIRT
162 ldr r12, [r3]
191 ldr r2, =__tegra20_cpu1_resettable_status_offset
205 ldr r2, =__tegra20_cpu1_resettable_status_offset
219 ldr r2, =__tegra20_cpu1_resettable_status_offset
264 ldr r4, =__tegra20_cpu1_resettable_status_offset
283 ldr r4, =__tegra20_cpu1_resettable_status_offset
362 ldr r6, tegra20_sdram_pad_size
364 ldr r7, [r2, r5] @ r7 is the addr in the pad_address
366 ldr r1, [r4, r5]
376 ldr r1, [r7]
381 ldr r4, [r4]
387 ldr r1, [r0, #EMC_CFG]
401 ldr r2, [r0, #EMC_EMC_STATUS]
409 ldr r0, [r0, #PMC_SCRATCH41]
444 ldr r1, [r7]
449 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
452 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
455 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
481 ldr r0, [r6, r1] /* memory barrier */
503 ldr r2, [r1, #EMC_EMC_STATUS]
513 ldr r3, [r1, #EMC_EMC_STATUS]
523 ldr r6, tegra20_sdram_pad_size
525 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
527 ldr r1, [r0]
530 ldr r1, [r3, r5]
539 ldr r0, [r5, #CLK_RESET_SCLK_BURST]