Lines Matching refs:ldr
84 ldr \rd, [\base, #EMC_ADR_CFG]
94 ldr \rd, [\base, #EMC_EMC_STATUS]
100 ldr \rd, [\r_car_base, #\pll_base]
106 ldr \rd, [\r_car_base, #\pll_misc]
109 ldr \rd, [\r_car_base, #\pll_misc]
110 ldr \rd, [\r_car_base, #\pll_misc]
118 ldr \rd, [\r_car_base, #\pll_base]
124 ldr \rd, [\car, #\iddq]
130 ldr \rd, [\car, #\iddq]
195 ldr r3, [r1] @ read CSR
214 ldr r0, [r2]
345 ldr r1, [r7]
351 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
364 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
383 ldr r1, [r7]
389 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
392 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
403 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
420 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
422 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
424 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
428 ldr r1, [r0, #EMC_CFG_DIG_DLL]
439 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
445 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
449 ldr r1, [r0, #EMC_CFG]
464 ldr r2, [r0, #EMC_EMC_STATUS]
471 ldr r2, [r0, #EMC_FBIO_CFG5]
480 ldr r2, [r7]
490 ldr r2, [r7]
499 ldr r2, [r7]
509 ldr r2, [r7]
516 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
518 ldr r1, [r5, #0x0] @ restore EMC_CFG
532 ldr r0, [r0, #PMC_SCRATCH41]
617 ldr r1, [r7]
626 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
631 ldr r1, [r7]
636 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
641 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
644 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
647 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
650 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
677 ldr r0, [r6, r2]
691 ldr r0, [r6, r2] /* memory barrier */
729 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
731 ldr r1, [r0]
753 ldr r1, [r0, #EMC_CFG]
760 ldr r1, [r7]
765 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
773 ldr r1, [r0, #EMC_EMC_STATUS]
783 ldr r2, [r0, #EMC_EMC_STATUS]
789 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
793 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
810 ldr r1, [r4, #PMC_CTRL]