Lines Matching refs:ldr
153 ldr w4, [x3, #VGIC_V3_CPU_HCR]
154 ldr w5, [x3, #VGIC_V3_CPU_VMCR]
155 ldr w25, [x3, #VGIC_V3_CPU_SRE]
170 ldr w20, [x3, #(VGIC_V3_CPU_AP1R + 3*4)]
172 ldr w19, [x3, #(VGIC_V3_CPU_AP1R + 2*4)]
174 6: ldr w18, [x3, #(VGIC_V3_CPU_AP1R + 1*4)]
176 5: ldr w17, [x3, #VGIC_V3_CPU_AP1R]
182 ldr w20, [x3, #(VGIC_V3_CPU_AP0R + 3*4)]
184 ldr w19, [x3, #(VGIC_V3_CPU_AP0R + 2*4)]
186 6: ldr w18, [x3, #(VGIC_V3_CPU_AP0R + 1*4)]
188 5: ldr w17, [x3, #VGIC_V3_CPU_AP0R]
200 ldr x20, [x3, #LR_OFFSET(15)]
201 ldr x19, [x3, #LR_OFFSET(14)]
202 ldr x18, [x3, #LR_OFFSET(13)]
203 ldr x17, [x3, #LR_OFFSET(12)]
204 ldr x16, [x3, #LR_OFFSET(11)]
205 ldr x15, [x3, #LR_OFFSET(10)]
206 ldr x14, [x3, #LR_OFFSET(9)]
207 ldr x13, [x3, #LR_OFFSET(8)]
208 ldr x12, [x3, #LR_OFFSET(7)]
209 ldr x11, [x3, #LR_OFFSET(6)]
210 ldr x10, [x3, #LR_OFFSET(5)]
211 ldr x9, [x3, #LR_OFFSET(4)]
212 ldr x8, [x3, #LR_OFFSET(3)]
213 ldr x7, [x3, #LR_OFFSET(2)]
214 ldr x6, [x3, #LR_OFFSET(1)]
215 ldr x5, [x3, #LR_OFFSET(0)]