Lines Matching refs:ldr
81 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
87 ldr r6, [r11, #L2X0_CACHE_SYNC]
102 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
103 ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
106 ldr r8, [r7], #0x4
107 ldr r9, [r7], #0x4
120 ldr r7, =MX6Q_MMDC_MPDGCTRL0
121 ldr r6, [r11, r7]
125 ldr r6, [r11, r7]
130 ldr r6, [r11, r7]
134 ldr r6, [r11, r7]
139 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
143 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
148 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
155 ldr r1, [r0, #PM_INFO_PBASE_OFFSET]
156 ldr r2, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
157 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]
158 ldr r4, [r0, #PM_INFO_PM_INFO_SIZE_OFFSET]
164 ldr r6, =imx6_suspend
165 ldr r7, =resume
175 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
176 ldr r6, [r11, #0x0]
177 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
178 ldr r6, [r11, #0x0]
179 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
180 ldr r6, [r11, #0x0]
183 ldr r11, [r0, #PM_INFO_MX6Q_SRC_V_OFFSET]
191 ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
196 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
201 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
206 ldr r7, [r11, #MX6Q_MMDC_MAPSR]
210 ldr r11, [r0, #PM_INFO_MX6Q_IOMUXC_V_OFFSET]
211 ldr r6, =0x0
212 ldr r7, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
213 ldr r8, =PM_INFO_MMDC_IO_VAL_OFFSET
219 ldr r9, [r8], #0x8
226 ldr r6, =0x1000
227 ldr r9, [r8], #0x8
229 ldr r9, [r8], #0x8
231 ldr r6, =0x80000
232 ldr r9, [r8]
243 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
244 ldr r6, [r11, #MX6Q_GPC_IMR1]
245 ldr r7, [r11, #MX6Q_GPC_IMR2]
246 ldr r8, [r11, #MX6Q_GPC_IMR3]
247 ldr r9, [r11, #MX6Q_GPC_IMR4]
249 ldr r10, =0xffffffff
261 ldr r11, [r0, #PM_INFO_MX6Q_CCM_V_OFFSET]
262 ldr r10, [r11, #MX6Q_CCM_CCR]
268 ldr r10, [r11, #MX6Q_CCM_CCR]
273 ldr r11, [r0, #PM_INFO_MX6Q_GPC_V_OFFSET]
289 ldr r6, =2000
323 ldr lr, [r0, #PM_INFO_RESUME_ADDR_OFFSET]
325 ldr r11, [r0, #PM_INFO_MX6Q_SRC_P_OFFSET]
330 ldr r3, [r0, #PM_INFO_DDR_TYPE_OFFSET]